Display substrate and display device

Abstract

FIELD: display devices.SUBSTANCE: invention relates to display devices consisting of a display substrate and an optical element located thereon. The substrate of the display device has a display area and a connection area, which is located on one side of the display area in the first direction. The display substrate includes a base, a plurality of signal lines and a light-protecting layer, wherein the plurality of signal lines are located on the base, the signal lines are located at least in the display zone, and the plurality of signal lines include a plurality of signal lines of the first type and a plurality of branching lines of the first type, wherein the signal lines of the first type receive electrical signals of direct voltage; the light-protecting layer is located on the side of the plurality of signal lines remote from the base and is located in the display zone, and the light-protecting layer includes a plurality of first openings; the display zone includes a main display zone and an additional display zone, which are located on one side of the main display zone, wherein the light transmittance of the additional display zone is greater than the light transmittance of the main display zone, and the plurality of first openings are located in the additional display zone; the orthogonal projections of the plurality of signal lines of the first type and the plurality of branching lines of the first type onto the base do not overlap the orthogonal projections of the plurality of first openings onto the base; and each branching line of the first type is located between two adjacent signal lines of the first type.EFFECT: reduction in external light loss, which increases the light transmittance of the display area of the display substrate and increases the amount of light collected by the optical element.20 cl, 17 dwg

Description

[0001] Field of technology to which the invention relates

[0002] This application claims priority from Chinese Patent Application No. 202410175990.6, filed on February 7, 2024, which is incorporated herein by reference in its entirety.

[0003] Field of technology to which the invention relates

[0004] The present disclosure relates generally to the field of display technologies, and in particular to a display substrate and a display device.

[0005] Technology Level

[0006] Organic LED (OLED) display technology is a technology that uses luminescent materials to emit light under the influence of a current to achieve display. OLED displays have the advantages of being ultra-light, ultra-thin, high brightness, wide viewing angle, low voltage, low power consumption, fast response time, high resolution, vibration resistance, flexibility, low cost, simple manufacturing process, limited raw materials, high luminous efficiency, and a wide temperature range.

[0007] Essence of the invention

[0008] In one aspect, a display substrate is provided. The display substrate has a display area and a connection area, wherein the connection area is located on the display area side in a first direction. The display substrate includes a substrate, a plurality of signal lines, and a light-shielding layer. A plurality of signal lines are located on the substrate. The signal lines are located at least in the display area. The plurality of signal lines include a plurality of first-type signal lines and a plurality of first-type branching lines. The first-type signal lines are configured to receive a DC electrical signal. The light-shielding layer is located on the side of the plurality of signal lines remote from the substrate and located in the display area. The light-shielding layer includes a plurality of first openings. The display area includes a main display area and a secondary display area located on the side of the main display area.The light transmittance of the additional display zone is greater than the light transmittance of the main display zone. A plurality of first apertures are located in the additional display zone. The orthogonal projections of the plurality of first-type signal lines and the plurality of first-type branching lines onto the substrate and the orthogonal projections of the plurality of first apertures onto the substrate do not overlap. A first-type branching line is located between two adjacent first-type signal lines.

[0009] In some embodiments, the first type signal lines extend in a first direction, and the first type branch lines extend in a first direction. The first type branch lines located between two adjacent first type signal lines and the two adjacent first type signal lines have substantially equal or equal distances.

[0010] In some embodiments, two adjacent signal lines of the first type, located on opposite sides of the branching line of the first type, are located substantially symmetrically or symmetrically with respect to the branching line of the first type.

[0011] In some embodiments, the display substrate further includes a plurality of pixel circuits. The plurality of pixel circuits are arranged in multiple rows and multiple columns. Each row of the pixel circuits is arranged in a second direction, and each column of the pixel circuits is arranged in a first direction, wherein the second direction intersects the first direction. Two adjacent signal lines of the first type are arranged on both sides of a branching line of the first type and form a group of signal lines of the first type, and two signal lines of the first type in the group of signal lines of the first type are connected to each other. The signal line of the first type is electrically connected to a column of the pixel circuits.

[0012] In some embodiments, the plurality of signal lines further include a plurality of first connecting lines. The first connecting lines extend in a second direction. The first connecting line connects two signal lines of the first type in a group of signal lines of the first type.

[0013] In some embodiments, the first type signal lines include a first voltage signal line.

[0014] In some embodiments, the plurality of signal lines further include a plurality of signal lines of a second type. The signal lines of the second type and the signal lines of the first type are configured to receive the same electrical signal. The signal lines of the second type have the same or substantially the same extension directions as the signal lines of the first type. Compared to the signal lines of the second type, the signal lines of the first type are located closer to the center line of the display area extending in the first direction.

[0015] In some embodiments, the plurality of signal lines further include a plurality of second-type branch lines and a plurality of data signal lines. The data signal lines extend in a first direction, the second-type branch lines extend in a second direction, and the second-type branch lines are located in the display area. The second-type branch line is connected to the first-type branch line. The data signal line is connected to the second-type branch line.

[0016] In some embodiments, the display substrate further includes a plurality of pixel circuits. The plurality of pixel circuits are arranged in multiple rows and multiple columns. Each row of the pixel circuits is arranged in a second direction, and each column of the pixel circuits is arranged in a first direction, wherein the second direction intersects the first direction. The plurality of signal lines further includes a plurality of signal lines of a third type. The signal lines of the third type are intended to receive an initiation signal; and the signal lines of the third type extend in the second direction. Two adjacent rows of pixel circuits are connected to the same signal line of the third type.

[0017] In some embodiments, two adjacent rows of pixel circuits are located on opposite sides of the same signal line of the third type.

[0018] In some embodiments, two adjacent rows of pixel circuits and the same signal line of the third type have equal or substantially equal distances between them.

[0019] In some embodiments, the plurality of signal lines of the third type includes a plurality of first initiating signal lines, a plurality of second initiating signal lines, and a plurality of third initiating signal lines.

[0020] In some embodiments, the plurality of signal lines further includes a plurality of second connecting lines. The second connecting lines extend in a first direction; and the second connecting line is connected to a signal line of a third type.

[0021] In some embodiments, the plurality of signal lines further include a plurality of second connecting lines. The second connecting lines extend in a first direction. The second connecting line includes at least one gap and a plurality of sublines. The gap is located directly opposite the first opening, and the size of the gap in the first direction is greater than or equal to the size of the first opening in the first direction. Each gap is provided with two of the plurality of sublines on opposite sides thereof; and the subline is connected to a signal line of a third type.

[0022] In some embodiments, the plurality of signal lines further includes a plurality of data signal lines, and the second connecting line is located between two adjacent data signal lines.

[0023] In some embodiments, the display substrate includes a first source-drain conductive layer and a second source-drain conductive layer, which are arranged sequentially on the side of the substrate. The display substrate further includes a plurality of second-type branching lines and a plurality of data signal lines. The plurality of second-type branching lines are arranged in the first source-drain conductive layer; and the plurality of first-type data signal lines, the plurality of first-type branching lines, and the plurality of data signal lines are arranged in the second source-drain conductive layer.

[0024] In some embodiments, the display substrate further includes a first gate conductive layer and a second gate conductive layer, which are arranged sequentially between the substrate and the first source-drain conductive layer. The first gate conductive layer is arranged between the substrate and the second gate conductive layer. The display substrate further includes a plurality of first connecting lines, a plurality of second connecting lines, and a plurality of signal lines of a third type. The plurality of signal lines of the third type include a plurality of first trigger signal lines, a plurality of second trigger signal lines, and a plurality of third trigger signal lines. The plurality of second connecting lines are arranged in the second source-drain conductive layer. The plurality of first trigger signal lines are arranged in the first source-drain conductive layer.A plurality of second initiating signal lines and a plurality of first connecting lines are located in the first gate conductive layer, and a plurality of third initiating signal lines are located in the second gate conductive layer.

[0025] In some embodiments, the display substrate further includes a plurality of filtering sections. The light-shielding layer further includes a plurality of second openings. The plurality of second openings are located in the main display region, and the filtering section is located in the second opening.

[0026] In some embodiments, the display substrate further includes a plurality of light-emitting devices and an encapsulating layer. The plurality of light-emitting devices are located on the side of the plurality of signal lines remote from the substrate. The encapsulating layer is located between the light-protective layer and the plurality of light-emitting devices.

[0027] In another aspect, a display device is provided. The display device includes a display substrate as described in any of the above-mentioned embodiments and an optical element. The optical element is located on the side of the display substrate not intended for light output and is located in a secondary display area of ​​the display substrate.

[0028] Brief description of drawings

[0029] To more clearly describe the technical solutions provided in the present disclosure, the accompanying drawings used in some embodiments of the present disclosure will be briefly presented below. It is obvious that the accompanying drawings, which will be described below, are only accompanying drawings of some embodiments of the present disclosure, and a person skilled in the art can derive other drawings based on these drawings. In addition, the accompanying drawings, which will be described below, can be regarded as a schematic representation, but they do not limit the actual size of the product to which the embodiments of the present disclosure relate.

[0030] Fig. 1 is a schematic diagram of a display device in accordance with some embodiments of the present disclosure;

[0031] Fig. 2 is a schematic diagram of another display device in accordance with some embodiments of the present disclosure;

[0032] Fig. 3 is a block diagram of another display device in accordance with some embodiments of the present disclosure;

[0033] Fig. 4 is a block diagram of a display substrate in accordance with some embodiments of the present disclosure;

[0034] Fig. 5 is a structural diagram of some film layers in a display substrate in accordance with an embodiment of the present disclosure;

[0035] Fig. 6 is a structural diagram of some film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0036] Fig. 7 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0037] Fig. 8 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0038] Fig. 9 is a structural diagram of third type signal lines and second connection lines in a display substrate in accordance with some embodiments of the present disclosure;

[0039] Fig. 10 is an equivalent circuit diagram of a pixel driver and a light-emitting device in accordance with some embodiments of the present disclosure;

[0040] Fig. 11 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0041] Fig. 12 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0042] Fig. 13 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0043] Fig. 14 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0044] Fig. 15 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure;

[0045] Fig. 16 is a block diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure; and

[0046] Fig. 17 is a structural diagram of certain other film layers in a display substrate in accordance with some embodiments of the present disclosure.

[0047] Detailed description of the invention

[0048] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments represent only some, but not all, embodiments of the present disclosure. All other embodiments obtained by a person skilled in the art based on the embodiments of the present disclosure shall be included within the scope of legal protection of the present disclosure.

[0049] Unless the context otherwise requires, throughout the description and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are construed as open and inclusive, that is, "including but not limited to". In the description of the specification, terms such as "one embodiment", "some embodiments", "exemplary embodiments", "example", "a specific example", or "some examples" are intended to indicate that particular features, structures, materials, or characteristics that refer to an embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s).In addition, specific features, structures, materials, or characteristics described herein may be included in any one or more embodiments or examples in any suitable manner.

[0050] The terms "first" and "second" are used hereinafter for descriptive purposes only and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of technical features specified. Thus, features defined using the terms "first" or "second" may explicitly or implicitly include one or more features. In the description of embodiments of the present disclosure, the terms "plurality" or "numerous" mean two or more, unless otherwise specified.

[0051] The phrase "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, the terms "about," "essentially," or "approximately" include a specified value and an average value within an acceptable range of deviation from a specified value. The acceptable range of deviation is determined by one skilled in the art, taking into account the measurement in question and the errors associated with measuring the specified quantity (i.e., the limitations of the measuring system).

[0053] The terms "perpendicular" or "equal" as used herein include the stated condition and a condition similar to the stated condition. The range of the similar condition is within the allowable deviation range. The allowable deviation range is determined by a person skilled in the art, taking into account the measurement in question and the errors associated with the measurement of a specific quantity (i.e., the limitations of the measuring system). For example, the term "perpendicular" includes absolute perpendicularity and approximate perpendicularity, and the allowable deviation range of approximate perpendicularity may also be a deviation within 5°; and the term "equal" includes absolute equality and approximate equality, and the allowable deviation range of approximate equality may be the difference between two equal quantities, less than or equal to 5% of either of the two equal quantities.

[0054] It should be understood that when a layer or element is on another layer or substrate, that layer or element may be directly on the other layer or substrate, or there may be intermediate layers between the layer or element and the other layer or substrate.

[0055] This document describes exemplary embodiments with reference to sectional views and / or plan views as idealized exemplary drawings. In the accompanying drawings, the thickness of layers and the sizes of zones / regions are exaggerated for clarity. Variations in shapes compared to the accompanying drawings are possible, due to, for example, manufacturing technologies and / or tolerances. Therefore, the exemplary embodiments should not be considered as limited to the shapes of the zones / regions shown in this document and as including deviations in shapes due to, for example, manufacturing. For example, an etched zone / region shown as a rectangle typically has a curved shape. Therefore, the zones / regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to represent the actual shapes of the zones / regions in the device and are not intended to limit the scope of the exemplary embodiments.

[0056] As shown in Fig. 1, some embodiments of the present disclosure provide a display device 1000. The display device 1000 may be any display device 1000 that displays images both in motion (e.g., video) and in a static state (e.g., a still image), regardless of whether they are text or an image. More specifically, it is contemplated that the display device 1000 in the embodiments may be implemented in various electronic devices or associated with various electronic devices.Various electronic devices may include, but are not limited to, mobile phones, wireless devices, personal digital assistants (PDAs), portable computers, global positioning system (GPS) receivers / navigators, cameras, MPEG-4 Part 14 (MP4) video players, camcorders, game consoles, watches, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays), navigators, controllers and / or displays in the driver's cabin, camera displays of various types (e.g., a rear-view camera display in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays for displaying an image of a piece of jewelry), etc.

[0057] In some examples, as shown in Fig. 1, the display device 1000 includes a display substrate 100 and a frame. The display substrate 100 is embedded in the frame.

[0058] In some embodiments, as shown in Fig. 2, the display device 1000 further includes a driver circuit board 300. The driver circuit board 300 may include, for example, a timing controller (TCON), a DC-DC converter chip for power management, a voltage divider circuit with an adjustable resistor (for generating Vcom), and other driver circuits. The driver circuit board 300 may further include other circuit structures that are not listed individually in this document. The driver circuit board 300 is electrically connected to the display substrate 100 and is used to transmit control signals to the display substrate 100, thereby controlling the display substrate 100 to produce an image.

[0059] As shown in Fig. 2, the display substrate 100 has a display area A and a peripheral area N located on at least one side of the display area A in the second direction X.

[0060] In some embodiments, as shown in Fig. 2, a peripheral zone N is located around the display zone A. The peripheral zone N may be provided with gate driver circuits (e.g., gate drivers on array, GOA), control signal lines (e.g., clock signal lines and supply voltage signal lines), and a driver chip for connection (e.g., a source driver chip, a source driver chip). For example, the gate driver circuits are located in the peripheral zone N and on opposite sides of the display zone A. The functions of the peripheral zone N include, but are not limited to, the following.

[0061] For example, as shown in Figs. 2 and 4, the peripheral region N includes a connection region B, and the connection region B is located on the side of the display region A in the first direction Y. The connection region B is adjacent to the side edge of the display region A. For example, the connection region B is adjacent to the lower side edge of the display region A. The display substrate 100 is connected to the external driver in the connection region B.

[0062] For example, connection area B is configured to output signal lines (for example, data signal lines, the first VDD voltage signal line, and the common voltage line mentioned below) and connect the signal lines to the driver circuit board 300. Connection area B is located on the side of the display substrate 100 intended for connection with the driver circuit board 300. The aforementioned driver chip can be located in connection area B.

[0063] For example, the display substrate 100 includes a plurality of pixels arranged in the display zone A, and each pixel includes at least three subpixels P(x).

[0064] For example, a plurality of pixels P are arranged in the form of a plurality of rows and a plurality of columns.

[0065] For example, as shown in Fig. 2, the display area A is an area of ​​the display substrate 100 for displaying images, the subpixel P(x) is the smallest light-emitting unit in the display substrate 100, and the subpixel P(x) is used for displaying images.

[0066] In some examples, a plurality of subpixels P(x) emit light of the same color. For example, a plurality of subpixels P(x) emit light of white, red, green, blue, or another color. In this case, the color of the light emitted by the subpixel P(x) after passing through the color filter layer either maintains the same color at the output or is converted to a different color at the output. Thus, in the case where a plurality of subpixels P(x) emit light of the same color, the display substrate 100 can achieve multi-color light output.

[0067] In some other examples, the plurality of subpixels P(x) emit light of different colors. For example, the plurality of subpixels P(x) includes a red subpixel for emitting red light, a green subpixel for emitting green light, and a blue subpixel for emitting blue light, thereby enabling multi-color light output from the display substrate 100.

[0068] It should be noted that each pixel includes at least three sub-pixels P(x), that is, each pixel may include three, four, or more sub-pixels P(x). The plurality of sub-pixels P(x) included in each pixel may be a row of sub-pixels P(x), a column of sub-pixels P(x), or a group of sub-pixels P(x), where the group of sub-pixels P(x) may consist of multiple adjacent sub-pixels P(x), and the multiple adjacent sub-pixels P(x) are arranged in a row, a column, an L-shape, a rectangle, a diamond, or the like.

[0069] Furthermore, multiple subpixels P(x) included in each pixel may have identical or different light-emitting areas. The above description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure. Adaptive designs may be specifically developed depending on actual needs.

[0070] As shown in Fig. 3, the display substrate 100 may further include an encapsulation layer 60 located on the light exit side of the plurality of subpixels P(x), and a functional multilayer layer 70 located on the encapsulation layer 60.

[0071] For example, the functional multilayer layer 70 may include a color filter layer 71, that is, the display substrate 100 has a color filter on encapsulation (CF on encapsulation, COE) structure. The functional multilayer layer 70 may further include one or more layers of a sensor function, an antireflective layer, a reinforcing layer, and an anti-fingerprint layer so that the display substrate 100 can perform the corresponding functions. Embodiments of the present disclosure do not specifically limit the type and number of functional multilayer layers.

[0072] The display substrate 100 including the COE structure has the advantages of high contrast, low power consumption, and a wide color gamut, and can have a reduced thickness, which is conducive to realizing a lightweight and thin structure of the display substrate 100. In addition, the display substrate 100 has good bending properties, which makes it possible for the display substrate 100 and the display device 1000 to be used to construct flexible displays.

[0073] In some embodiments, as shown in Fig. 3, the display device 1000 may further include an optical element 200. The optical element 200 is located on the non-light-outputting side of the display substrate 100. The light-outputting side of the display substrate 100 refers to the side of the display substrate 100 where images can be displayed. The non-light-outputting side of the display substrate 100 refers to the side of the display substrate 100 opposite the light-outputting side.

[0074] Display area A refers to an area of ​​the display substrate 100 for displaying images.

[0075] Display area A can be in the shape of a rectangle, rounded rectangle, etc. A rounded rectangle is a rectangle with four rounded corners.

[0076] As shown in Fig. 4, the display region A includes a main display region A1 and a sub-display region A2, wherein the sub-display region A2 is located on at least one side of the main display region A1. In the proposed solution, the sub-display region A2 is located at the side of the main display region A1, which may mean that the sub-display region A2 is located at the side of the main body of the main display region A1, and the sub-display region A2 may be surrounded or half-surrounded by the main display region A1.

[0077] For example, the additional display area A2 can be in the shape of a circle, ellipse, or rectangle.

[0078] For example, the additional display area A2 can be located on one or more sides of the main display area A1.

[0079] For example, in the case where the display area A is in the shape of a rectangle, the additional display area A2 may be located at any point in the middle of the rectangle, and the additional display area A2 may alternatively be located near any corner of the rectangle, and the additional display area A2 may alternatively be located near any side of the rectangle.

[0080] The following description will be given using an example where the additional display area A2 is located close to or facing the center line CL of the display area A in the first direction Y.

[0081] For example, portions of the display substrate 100 located in both the main display region A1 and the sub-display region A2 can be used to display an image.

[0082] For example, the light transmittance of the sub-display region A2 is greater than the light transmittance of the main display region A1. For example, the pixel density of a plurality of sub-pixels P(x) located in the main display region A1 of the display substrate 100 is greater than the pixel density of a plurality of sub-pixels P(x) located in the sub-display region A2 of the display substrate 100.

[0083] As shown in Fig. 3, the optical element 200 is disposed in the additional display region A2 of the display substrate 100. Since the light transmittance of the additional display region A2 is greater than the light transmittance of the main display region A1, external light has less loss when passing through the additional display region A2, so the optical element 200 can receive sufficient light, thereby avoiding affecting the operation of the optical element 200.

[0084] For example, as shown in Fig. 3, the optical elements 200 may be a camera, a fingerprint recognition sensor, an infrared sensor, etc.

[0085] When the optical elements 200 operate, external light must pass through the additional display region A2 and hit the optical elements 200 to activate the corresponding functions. Embodiments of the present disclosure are described using an example in which the optical element 200 is a camera.

[0086] For example, during camera operation, external light may pass through a portion of the display substrate located in the sub-display area A2. The camera can thus collect light to perform photo-taking or image recording. For example, when the camera is in operation (e.g., the user takes a selfie), the sub-display area A2 may display a black image, and the main display area A1 may display the user's selfie image, more clearly revealing the camera's location. Alternatively, the entire sub-display area A2 and the main display area A1 may display the user's selfie image without revealing the camera's location.

[0087] For example, when the camera is not operating, portions of the display substrate located in both the sub-display area A2 and the main display area A1 can display images, so that images can be displayed on both the entire display substrate and the entire display device 1000.

[0088] In some examples, the above-mentioned color filter layer 71 includes a light-shading layer 50.

[0089] For example, the light shading layer 50 is a black matrix. The material of the black matrix includes an opaque material. The light shading layer 50 includes a plurality of first openings 51 and a plurality of second openings. A top view of the light shading layer 50 may have the form of a mesh structure, wherein the first openings 51 and the second openings form a mesh of this mesh structure. The first openings 51 are located in the additional display region A2 of the display substrate 100. Since the optical elements 200 are located in the additional display region A2, and the plurality of first openings 51 correspond to the optical elements 200, external light can pass through the display substrate 100 through the first openings 51 and hit the optical elements 200, so the optical elements 200 can capture external light.

[0090] For example, a plurality of first holes 51 are arranged in an array, and a plurality of second holes are also arranged in an array.

[0091] In some examples, the first opening 51 and the second opening may have the same or substantially the same shape.

[0092] For example, the first hole 51 has the shape of a rectangle, trapezoid, circle, rounded rectangle, ellipse, or the like.

[0093] In some other examples, the first hole 51 and the second hole may have different shapes.

[0094] The area ratio between the first opening 51 and the second opening can be set depending on actual needs, and is not limited in the embodiments of the present disclosure.

[0095] For example, the area of ​​the first hole 51 is greater than or equal to the area of ​​the second hole.

[0096] As another example, the area of ​​the first hole 51 is smaller than the area of ​​the second hole.

[0097] For example, the color filter layer 71 further includes a plurality of filter sections. The filter section is located in the second opening. The plurality of second openings are located in the main display region A1 of the display substrate 100. Thus, the filter sections are also located in the main display region A1 of the display substrate 100.

[0098] The filter portion can transmit light in a certain wavelength range, and the filter portion is provided for the light emitting device 30.

[0099] The plurality of filter sections may include at least a plurality of first filter sections, a plurality of second filter sections, and a plurality of third filter sections. The first filter section may transmit red light, the second filter section may transmit green light, and the third filter section may transmit blue light.

[0100] For example, light emitted from the light-emitting device 30 passes through the encapsulating layer 60 and falls on the corresponding filter portion in the light-shading layer 50, and then passes through the filter portion and exits the display substrate 100.

[0101] In some embodiments, as shown in Fig. 3, the display substrate 100 includes a substrate 10, a plurality of pixel circuits 20 and a plurality of light-emitting devices 30.

[0102] The substrate type 10 varies and can be installed according to actual needs.

[0103] For example, the substrate 10 may be a rigid substrate 10. The rigid substrate 10 may be a glass substrate, a polymethyl methacrylate (PMMA) substrate, or the like.

[0104] For example, the substrate 10 may be a flexible substrate 10. The flexible substrate 10 may be a polyethylene terephthalate (PET) substrate 10, a polyethylene naphthalate (PEN) substrate 10, a polyimide (PI) substrate 10, or the like. In this case, the display substrate 100 may, for example, provide a flexible display.

[0105] As shown in Fig. 2, a plurality of pixel circuits 20 are arranged on the side of the substrate 10. The plurality of pixel circuits 20 are arranged in a plurality of rows and a plurality of columns. Each row of the pixel circuits 20 is arranged in a second direction X, and each column of the pixel circuits 20 is arranged in a first direction Y. Each row of the pixel circuits 20 includes a plurality of pixel circuits 20 arranged at intervals in the second direction X, and each column of the pixel circuits 20 includes a plurality of pixel circuits 20 arranged at intervals in the first direction Y. That is, the first direction Y is a column direction in which the plurality of pixel circuits 20 are arranged, and the second direction X is a row direction in which the plurality of pixel circuits 20 are arranged. The first direction Y and the second direction X intersect.

[0106] For example, the angle between the first Y direction and the second X direction is 75°, 80°, 90°, 95°, 105° or 120°.

[0107] In addition, in Fig. 2, Z represents a third direction, and the third direction Z is perpendicular to the plane in which the substrate 10 is located. For example, the third direction Z is perpendicular to both the first direction Y and the second direction X.

[0108] The light-emitting device 30 includes, but is not limited to, an organic light-emitting diode (OLED), a miniature light-emitting diode (mini LED), a microscopic light-emitting diode (micro LED), and the like.

[0109] This will now be illustrated using an example where the light-emitting device 30 includes an OLED.

[0110] The light-emitting device 30 includes a first electrode, a light-emitting functional layer, and a second electrode, which are sequentially arranged one above the other. The light-emitting functional layer may include a light-emitting layer. If necessary, the light-emitting functional layer may further include at least one of the following layers: a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0111] For example, the first electrode is an anode and a cathode, and the second electrode is another anode and a cathode, which is not limited to the embodiments of the present disclosure.

[0112] For convenience of description, embodiments of the present disclosure will be given by way of example, where the first electrode is an anode and the second electrode is a cathode.

[0113] The pixel circuit 20 is connected to the light-emitting device 30; alternatively, the pixel circuit 20 is connected to multiple light-emitting devices 30. The pixel circuit 20 and the light-emitting device 30 connected thereto form the above-mentioned subpixel P(x). The pixel circuit 20 can generate a control signal (for example, a drive current). Each light-emitting device 30 can emit light under the action of a control signal generated by the pixel circuit 20 connected thereto. The light emitted by all the light-emitting devices 30, after passing through the filter sections of the color filter layer 71, forms a plurality of light rays of different colors. The plurality of light rays of different colors interact with each other, so that the display substrate 100 and the display device 1000 can realize a display function.

[0114] In some examples, as shown in Figs. 2 and 3, the display substrate 100 has a display region A and a connection region B. The connection region B is located on the side of the display region A in the first direction Y. The display substrate 100 further includes a plurality of signal lines 40.

[0115] A plurality of signal lines 40 are arranged on the substrate 10. The plurality of signal lines 40 are arranged on the side of the pixel circuits 20 remote from the substrate 10, and between a plurality of light-emitting devices 30 and the pixel circuits 20. The light-emitting devices 30 are arranged on the side of the plurality of signal lines 40 remote from the substrate 10.

[0116] As shown in Figs. 5 and 6, the plurality of signal lines 40 includes a plurality of first-type signal lines 41 and a plurality of first-type branch lines 44. The first-type signal line 41 receives a DC voltage electrical signal. For example, the first-type signal lines 41 and the first-type branch lines 44 are arranged in the same layer.

[0117] As shown in Fig. 2, the signal lines 40 are located at least in the display area A. For example, both the first type signal lines 41 and the first type branch lines 44 extend from the display area A to the connection area B and are connected to the driver circuit board 300 near the connection area B.

[0118] As shown in Fig. 3 and 6, the light shading layer 50 is located on the side of the plurality of signal lines 40 that is distant from the substrate 10. The light shading layer 50 forms a portion of the color filter layer 71. The light shading layer 50 includes a plurality of first openings 51. The plurality of first openings 51 are arranged at intervals and are located in the additional display region A2.

[0119] The orthogonal projections of the plurality of signal lines 41 of the first type and the plurality of branching lines 44 of the first type onto the substrate 10 and the orthogonal projections of the plurality of first openings 51 onto the substrate 10 do not overlap. For example, there is no intersection between the orthogonal projections of the plurality of signal lines 41 of the first type and the plurality of branching lines 44 of the first type onto the substrate 10 and the edges of the orthogonal projections of the first openings 51 onto the substrate 10, and the orthogonal projections of the plurality of signal lines 41 of the first type and the plurality of branching lines 44 of the first type onto the substrate 10 are located outside the edges of the orthogonal projections of the first openings 51 onto the substrate 10.

[0120] For example, external light may pass through the plurality of first openings 51 in the light-shading layer 50 and enter the display substrate 100, and then pass through the display substrate 100 and enter the optical elements 200.

[0121] Therefore, when external light enters the optical element 200 through the first opening 51 in the additional display region A2, it can avoid being blocked by the light-shading layer 50, and the external light is not easily blocked or not blocked at all by the first-type signal lines 41 and the first-type branching lines 44. As a result, the external light has a relatively small loss, which improves the light transmittance of the additional display region A2 of the display substrate 100 and increases the amount of light collected by the optical element 200. Therefore, this is advantageous for optimizing the performance of the optical element 200, for example, improving the fingerprint recognition accuracy of the fingerprint recognition sensor and improving the photography quality of the camera.

[0122] In the embodiment shown in Fig. 5, the first type branching line 44 is located between two adjacent data signal lines, and the first type branching line 44 and the two data signal lines are located in the same layer. The first type branching line 44 and the two data signal lines form parasitic capacitors. During the surge of the data signal transmitted through the data signal line, the electrical signal transmitted by the first type branching line 44 will be affected by surges due to the influence of the parasitic capacitor, which will lead to fluctuations in the electrical signal transmitted by the first type branching line 44. Thus, this may adversely affect the image display quality on the display substrate and in the display device.

[0123] In this regard, as shown in Fig. 6, in the display substrate 100 provided in some embodiments of the present disclosure, a first type branching line 44 is located between two adjacent first type signal lines 41. No other signal lines 40 are provided between the first type branching line 44 and the two adjacent first type signal lines 41.

[0124] The first type line 44 receives an electrical signal (for example, a data signal) from the driver circuit board or the driver chip and transmits the electrical signal to the pixel circuits 20. The first type signal line 41 receives a DC voltage signal from the driver circuit board or the driver chip and transmits the DC voltage signal to the pixel circuits 20.

[0125] The first signal line 41 transmitting a DC signal has a certain shielding effect and can separate the first type branching line 44 from the other signal lines 40. As a result, the first branching line 44 and any of the signal lines 40 (for example, the aforementioned Data line of data signals), except the first signal line 41, are at a relatively large distance from each other. Therefore, the first type branching line 44 is less susceptible to the influence of the other signal lines 40, and the influence of the electrical signal surges on the adjacent signal line 40 (for example, on the aforementioned Data line of data signals) on the first type branching line 44 is reduced or even completely eliminated.Thus, it is possible to achieve higher stability and accuracy of the electrical signal transmitted along the first type branching line 44, while the driving efficiency of the pixel circuits 20 can increase, thereby improving the quality of image display on the display substrate 100 and in the display device 1000.

[0126] The display substrate 100 provided in the embodiments of the present disclosure includes a substrate 10, a plurality of signal lines 40, and a light-shielding layer 50. The light transmittance of the additional display region A2 is greater than the light transmittance of the main display region A1. The signal lines 40 are located at least in the display zone A. The light-shielding layer 50 includes a plurality of first openings 51 located in the additional display region A2. A plurality of first type signal lines 41 in the plurality of signal lines 40 receive a DC electrical signal. The orthogonal projections of the plurality of first type signal lines 41 and the plurality of first type branching lines 44 onto the plane where the substrate is located, and the orthogonal projections of the plurality of first openings 51 onto the plane where the substrate is located do not overlap.Thus, when external light passes through display substrate 100 through first opening 51, the external light is not blocked or even obstructed by first-type signal lines 41 and first-type branching lines 44. The external light has relatively small losses, which improves the light transmittance of the additional display area A2 of display substrate 100 and increases the amount of light collected by optical element 200. This thereby contributes to the optimization of the characteristics of optical element 200, such as improving the accuracy of fingerprint recognition by the fingerprint recognition sensor and improving the quality of photography by the camera.Moreover, the first type branching line 44 is located between two adjacent signal lines 41 of the first type, so that the first type branching line 44 is less susceptible to the influence of other signal lines 40, and the influence on the first type branching line 44 of surges in the electrical signal on the adjacent signal line 40 (for example, on the aforementioned Data line of data signals) is reduced or even completely eliminated. Thus, this makes it possible to achieve higher stability and accuracy of the electrical signal transmitted along the first type branching line 44, and the driving efficiency of the pixel circuits 20 can increase, thereby improving the quality of image display on the display substrate 100 and in the display device 1000.

[0127] In some examples, as shown in Fig. 6, the first type signal lines 41 continue in the first direction Y, and the first type branch lines 44 continue in the first direction Y.

[0128] For example, as shown in Fig. 6, the first type signal line 41 has the shape of a long strip, and this long strip continues in the first direction Y. As another example, as shown in Fig. 7, the first type signal line 41 has a zigzag shape, and the general direction of continuation of the zigzag shape basically coincides with the first direction Y.

[0129] For example, the first type branching line 44 has essentially the shape of a long strip, and this long strip continues in the first Y direction.

[0130] For example, two adjacent signal lines 41 of the first type and the branch line 44 of the first type are parallel or substantially parallel.

[0131] For example, in the second X direction, the distance between the entire first type signal line 41 and the entire first type branching line 44 is the same. For example, the first type branching line 44 includes multiple connected subsections, wherein the multiple subsections include the first and second subsections, and the corresponding first type signal line 41 includes multiple connected subsections, wherein the multiple connected subsections include the third subsection and the fourth subsection. In the second X direction, the first subsection is located opposite the third subsection, and the size of the first subsection in the first Y direction is approximately equal to the size of the third subsection in the first Y direction. In the second X direction, the second subsection is located opposite the fourth subsection, and the size of the second subsection in the first Y direction is approximately equal to the size of the fourth subsection in the first Y direction.The distance between the first subsection and the third subsection is equal to or approximately equal to the distance between the second subsection and the fourth subsection.

[0132] As another example, in the second X direction, the first type signal line 41 and the first type branching line 44 have an uneven distance between them. For example, the first type branching line 44 includes multiple connected subsections, wherein the multiple connected subsections include the first and second subsections, and the corresponding first type signal line 41 includes multiple connected subsections, wherein the multiple connected subsections include the third subsection and the fourth subsection. The first subsection corresponds to the third subsection. In this case, the correspondence means that in the second X direction, the first subsection is located opposite the third subsection, and the size of the first subsection in the first Y direction is approximately equal to the size of the third subsection in the first Y direction. The second subsection corresponds to the fourth subsection.In this case, the correspondence means that in the second X-direction, the second subsection is located opposite the fourth subsection, and the size of the second subsection in the first Y-direction is approximately equal to the size of the fourth subsection in the first Y-direction. The distance between the first subsection and the third subsection is not equal to the distance between the second subsection and the fourth subsection.

[0133] For example, as shown in Fig. 6 and 7, the first type branch line 44 located between the two adjacent first type signal lines 41 and the two adjacent first type signal lines 41 has equal or substantially equal distances.

[0134] For example, the distance between each subsection of the first type branch line 44 and the corresponding subsection of the first type signal line 41 on one side thereof is equal to or substantially equal to the distance between the subsection of the first type branch line 44 and the corresponding subsection of the other first type signal line 41 on the other side thereof.

[0135] Thus, the two signal lines 41 of the first type can have the same or approximately the same shielding effect on the opposite sides of the first branching line, which can further reduce the influence on the branching line 44 of the first type of electrical signal surges on any other signal line 40, thereby effectively improving the stability and accuracy of the electrical signal transmitted along the branching line 44 of the first type, improving the driving ability of the pixel circuits 20 and, thus, improving the image display quality on the display substrate 100.

[0136] If necessary, two adjacent signal lines 41 of the first type, located on opposite sides of the same branching line 44 of the first type, are located substantially symmetrically or symmetrically with respect to the same branching line 44 of the first type.

[0137] For example, the first type branching line 44 is an axis of symmetry, and the shapes of the two first type signal lines 41 are symmetrical with respect to the same first type branching line 44.

[0138] Thus, two opposite sides of each subsection of the first type branching line 44 can be subjected to the same or approximately the same shielding effect, which further reduces the influence on the first type branching line 44 of surges in the electrical signal on any other signal line 40 and improves the stability and accuracy of the electrical signal transmitted along the first type branching line 44.

[0139] In some examples, as shown in Fig. 2, the display substrate 100 further includes a plurality of pixel circuits 20.

[0140] The structure of the pixel circuit 20 varies and can be set depending on actual needs. For example, the pixel circuit 20 may have a structure of "6T1C," "7T1C," "8T1C," or "7T2C." In this document, "T" denotes a transistor, and the number before "T" denotes the number of transistors. "C" denotes a storage capacitor, and the number before "C" denotes the number of storage capacitors.

[0141] For example, embodiments of the present disclosure will be described using an example where the structure of the pixel circuit 20 is an "8T1C" structure. Fig. 10 shows an equivalent circuit of a subpixel.

[0142] In the pixel circuit provided in the embodiments of the present disclosure, the first electrode of each transistor represents one of the source and the drain, and the second electrode of each transistor represents the other of the source and the drain. Since the source and the drain of the transistor may be symmetrical in structure, the source and the drain may be structurally indistinguishable. That is, the first electrode and the second electrode of the transistor provided in the embodiments of the present disclosure may be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode of the transistor is the source, and the second electrode of the transistor is the drain. For example, in the case of an N-type transistor, the first electrode of the transistor is the drain, and the second electrode of the transistor is the source.In the pixel circuit presented in the embodiments of the present disclosure, the first node, second node, and other nodes do not represent actual components, but rather represent connections of corresponding electrical contacts in the circuit diagram. That is, these nodes are nodes equivalent to the connections of corresponding electrical circuits in the circuit diagram.

[0143] For example, as shown in Fig. 10, the pixel circuit 20 includes a first reset transistor T1, a compensation transistor T2, a control transistor T3, a switching transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst.

[0144] For example, as shown in Fig. 10, the control electrode of the first reset transistor T1 is electrically connected to the first terminal RN1 of the reset signal, the first electrode of the first reset transistor T1 is electrically connected to the first terminal VN1 of the trigger signal, and the second electrode of the first reset transistor T1 is electrically connected to the first node N1 (that is, electrically connected to the first electrode of the compensation transistor T2). The first reset transistor T1 is configured to be turned on, under the control of the first reset signal supplied from the first terminal RN1 of the reset signal, to transmit the first trigger signal received at the first terminal VN1 of the trigger signal to the first node N1 in order to reset the first node N1.

[0145] For example, as shown in Fig. 10, the control electrode of the second reset transistor T7 is electrically connected to the second reset signal terminal RN2, the first electrode of the second reset transistor T7 is electrically connected to the second terminal VN2 of the trigger signal, and the second electrode of the second reset transistor T7 is electrically connected to the second node N2. The second reset transistor T7 is configured to turn on, under the control of the second reset signal supplied from the second reset signal terminal RN2, to transmit the second trigger signal received at the second terminal VN2 of the trigger signal to the second node N2, to reset the second node N2.

[0146] For example, as shown in Fig. 10, the control electrode of the switching transistor T4 is electrically connected to the first scanning signal terminal SN1, the first electrode of the switching transistor T4 is electrically connected to the data signal terminal DN, and the second electrode of the switching transistor T4 is electrically connected to the third node N3. The switching transistor T4 is configured to be turned on under the control of the first scanning signal supplied from the first scanning signal terminal SN1 to transmit the data signal transmitted from the data signal terminal DN to the third node N3.

[0147] For example, as shown in Fig. 10, the control electrode of the transistor T3 is electrically connected to the fourth node N4, the first electrode of the transistor T3 is electrically connected to the third node N3, and the second electrode of the transistor T3 is electrically connected to the first node N1. The transistor T3 is configured to be turned on under the control of the voltage at the fourth node N4 to transmit a signal (for example, a data signal) from the third node N3 to the first node N1.

[0148] For example, as shown in Fig. 10, the control electrode of the compensation transistor T2 is electrically connected to the second terminal SN2 of the scanning signal, the first electrode of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode of the compensation transistor T2 is electrically connected to the fourth node N4. The compensation transistor T2 is configured to be turned on under the control of the second scanning signal supplied from the second terminal SN2 of the scanning signal, to transmit an electrical signal (for example, a data signal) from the first node N1 to the fourth node N4.

[0149] For example, as shown in Fig. 10, the control electrode of the first light-emitting transistor T5 is electrically connected to the enable signal terminal EM, the first electrode of the first light-emitting transistor T5 is electrically connected to the first voltage signal terminal VDDN, and the second electrode of the first light-emitting transistor T5 is electrically connected to the third node N3. The first light-emitting transistor T5 is configured to be turned on under the control of the enable signal supplied from the enable signal terminal EM, to transmit the voltage signal received at the first signal terminal VDDN of the voltage signal to the third node N3.

[0150] For example, as shown in Fig. 10, the control electrode of the second light-emitting transistor T6 is electrically connected to the enable signal terminal EM, the first electrode of the second light-emitting transistor T6 is electrically connected to the first node N1, and the second electrode of the second light-emitting transistor T6 is electrically connected to the second node N2. The second light-emitting transistor T6 is configured to be turned on under the control of the enable signal supplied from the enable signal terminal EM, to transfer the voltage from the first node N1 to the second node N2.

[0151] For example, as shown in Fig. 10, the control electrode of the third reset transistor T8 is electrically connected to the second terminal RN2 of the reset signal, the first electrode of the third reset transistor T8 is electrically connected to the third terminal VN3 of the trigger signal, and the second electrode of the third reset transistor T8 is electrically connected to the third node N3. The third reset transistor T8 is configured to be turned on under the control of the second reset signal supplied from the second terminal RN2 of the reset signal, to transmit the third trigger signal received at the third terminal VN3 of the trigger signal, to the third node N3.

[0152] For example, as shown in Fig. 10, the first electrode of the storage capacitor Cst is electrically connected to the fourth node N4, and the second electrode of the storage capacitor Cst is electrically connected to the first terminal VDDN of the voltage signal.

[0153] One end of the light emitting device 30 is electrically connected to the second node N2, and the other end of the light emitting device 30 is electrically connected to the common voltage signal terminal VSS.

[0154] The light-emitting device 30 emits light under the action of an electric signal supplied to the second node N2 and a common voltage supplied to the common voltage signal terminal VSS.

[0155] The compensation transistor T2 in the above pixel circuit 20 may be a low-temperature polycrystalline oxide (LTPO) transistor, and the other transistors may be low-temperature polycrystalline silicon (LTPS) transistors.

[0156] For example, an LTPO transistor has a relatively low leakage current. Therefore, by using the compensation transistor T2 as an oxide transistor, the leakage current of the compensation transistor T2 can be reduced, preventing the electrical leakage of the fourth node N4 through the compensation transistor T2 and the first reset transistor T1. Furthermore, the compensation effect of the control transistor T3 and the stability of the electrical signal at the fourth node N4 can be ensured, thereby improving the display quality on the display substrate 100. Furthermore, the LTPS transistor has a relatively high charge carrier mobility. Therefore, by using the control transistor T3 and other transistors as low-temperature polycrystalline silicon transistors, the charging speed of the storage capacitor Cst can be accelerated, further improving the display quality on the display substrate 100.

[0157] In the implementation as shown in Fig. 5, the signal line 41 of the first type is connected to two adjacent columns of pixel circuits.

[0158] In some embodiments of the present disclosure, as shown in Figs. 6 and 7, two adjacent signal lines 41 of the first type, located on both sides of the branch line 44 of the first type, form a group 410 of signal lines of the first type. The two signal lines 41 of the first type in the group 410 of signal lines of the first type are connected to each other. The signal line 41 of the first type is electrically connected to a column of pixel circuits 20.

[0159] Thus, based on the relative positions of the pixel circuits 20 in display area A, the position of the corresponding first-type signal line 41 can be determined. As a result, the relative positions of the first-type signal line 41 and the pixel circuits 20 connected thereto can be appropriately adjusted, thereby increasing the design flexibility of the first-type signal line 41 and reducing the design complexity of the display substrate 100.

[0160] In some examples, as shown in Fig. 6, the plurality of signal lines 40 further includes a plurality of first connecting lines 46. The first connecting lines 46 extend in the second direction X. The first connecting line 46 connects two signal lines 41 of the first type in the group 410 of the first type signal lines.

[0161] For example, the first connecting line 46 and the corresponding signal lines 41 of the first type are located in different layers.

[0162] Two first-type signal lines 41 in the first-type signal line group 410 diverge in different directions from the first connecting line 46, so that a plurality of first-type signal lines 41 and a plurality of first connecting lines 46 intersect with each other to form a mesh structure. Therefore, when an electrical signal is transmitted along the first-type signal line 41, the electrical signals transmitted to all the pixel circuits 20 in different rows of the same column have a small difference. Therefore, the voltage drop of the electrical signal transmitted along the first-type signal line 41 can be reduced, and therefore, the difference between the light emitted by the subpixel and the target light can be reduced, which improves the image display quality on the display substrate 100 and in the display device 1000.

[0163] In some examples, as shown in Figs. 6 and 7, the first type signal line 41 includes a first voltage signal line VDD. The first voltage signal line VDD transmits a first voltage signal to the pixel circuits 20 connected thereto.

[0164] In the embodiment shown in Fig. 5, the first voltage signal line VDD in the display substrate 100 provides an electrical signal for two adjacent columns of pixel circuits. The first voltage signal line VDD has a relatively large dimension in the second X direction, that is, the first voltage signal line VDD has a width.

[0165] In the embodiments of the present disclosure, the first voltage signal line VDD in the above-mentioned implementation is divided into two first VDD voltage signal lines. The two first VDD voltage signal lines respectively provide or transmit the first voltage signals for two adjacent columns of the pixel circuits 20, and a first branch line 44 is provided between the two first VDD voltage signal lines. Thus, the two first VDD voltage signal lines can be used to shield and protect the first branch line 44. Moreover, the distance between the first VDD voltage signal line and the column of the pixel circuits 20 connected to it can be flexibly adjusted without affecting the positions of other columns of the pixel circuits 20, thereby simplifying the design of the display substrate 100.

[0166] In some examples, as shown in Fig. 2, the plurality of signal lines 40 further includes a plurality of signal lines 42 of the second type. The signal lines 42 of the second type and the signal lines 41 of the first type are used to receive the same electrical signal. The plurality of signal lines 42 of the second type have the same or substantially the same extension directions as the plurality of data lines DL.

[0167] For example, the second type signal line 42 also includes the first voltage signal line VDD. The second type signal line 42 is connected to one or two columns of the pixel circuits 20 and provides the first voltage signal for the pixel circuits 20.

[0168] Compared with the second signal line 42, the first signal line 41 is closer to the center line CL of the display area A extending in the first direction Y.

[0169] Therefore, the first type branching line 44 located between two adjacent first type signal lines 41 can be made close to the center line CL of the display area A in order to reduce the distance between the first type branching line 44 and the connection area B in the second X direction, which helps to ensure that the first type branching line 44 continues to the connection area B.

[0170] In some examples, as shown in Fig. 2 and 6, the plurality of signal lines 40 further includes a plurality of second-type branching lines 45 and a plurality of data signal lines. The data signal lines 45 extend in the first Y direction, and the second-type branching lines 45 extend in the second X direction. The second-type branching lines 45 are located in the display zone A. The second-type branching line 45 is connected to the first-type branching line 44. The data signal line 45 is connected to the second-type branching line.

[0171] For example, the second type branch line 45 and the first type branch line 44 are connected via the via hole(s), and the data signal line Data and the second type branch line 45 are connected via the via hole(s).

[0172] In Fig. 6, a top view, in the second direction X, the arrangement order of the plurality of signal lines 40 and the first holes 51 is as follows: the first type signal line 41 (or the first type voltage signal line VDD), the first type branch line 44, the first type signal line 41 (or the first type voltage signal line VDD), the data signal line Data, the first holes 51, the data signal line Data, the first type signal line 41 (or the first type voltage signal line VDD).

[0173] For example, in a plurality of data signal lines, the data signal line located away from the center line CL of display area A and extending in the first direction Y is connected to the second type branching line 45. The data signal line is connected to the first type branching line 44 via the second type branching line 45 in such a way that the data signal line extends outward, thereby facilitating the data signal line to receive an electrical signal from the connection area B.

[0174] The data signal lines D, connected to the second branching line 45, are signal lines in the display substrate 100 that are to be sequentially output to the connection region B via the second branching line 45 and the first branching line 44. This solution can be called "fanout in pixel" (FIP). The data signal line D is located at a relatively large distance from the center line CL of the display area A in the first direction Y and is close to the boundary line between the display area A and the peripheral area N.

[0175] By routing the data signal line DA to the connection area B using the second-type branching line 45 and the first-type branching line 44, it is possible to reduce the area in the peripheral area N occupied by the data signal line DA and the corresponding second-type branching line 45 and the first-type branching line 44. Therefore, the area of ​​the peripheral area N of the display substrate 100 can be designed to be small, which contributes to the realization of a narrow-frame design of the display substrate 100 and the display device 1000.

[0176] At least one subsection in the plural subsections of the first type branching line 44 is connected to the second type branching line 45. For example, the plural subsections of the first type branching line 44 can be interconnected and not interrupted. As another example, as shown in Fig. 6, in the plural subsections 441 of the first type branching line 44, at least two adjacent subsections 441 of the plurality of adjacent subsections 441 are not connected to each other. The subsection 441 of the first type branching line 44 connected to the second type branching line 45 is an acceptable subsection of the first type branching line 44, and the subsection 441 of the first type branching line 44 not connected to the second type branching line 45 is a reserve subsection of the first type branching line 44. The backup subsection can receive a DC voltage signal, such as a common voltage signal.

[0177] It can be understood that the display substrate 100 is further provided with data signal lines that are not connected to the second type branching lines 45 and the first type branching lines 44. These data signal lines extend in the first direction Y and have a relatively small distance from the connection region B in the second direction X, or these data signal lines extend directly opposite the connection region B in the first direction Y. Thus, these data signal lines extend directly to the connection region B without using the first type branching lines 44 and the second type branching lines 45 for output.

[0178] In some examples, as shown in Fig. 2, the plurality of signal lines 40 further includes a plurality of signal lines 43 of a third type. The signal line 43 of the third type receives the trigger signal and transmits the trigger signal. The signal lines 43 of the third type extend in the second direction X.

[0179] Two adjacent rows of pixel circuits 20 are connected to the same type-3 signal line 43. Therefore, two adjacent rows of pixel circuits 20 share a single type-3 signal line 43, which reduces the number of type-3 signal lines 43. As a result, the area occupied by the type-3 signal lines 43 in the film layer where they are located can be reduced, thereby reducing the complexity of the film layer layout and reducing the manufacturing cost of the display substrate 100.

[0180] For example, two adjacent rows of pixel circuits 20 are arranged on opposite sides of the same type-3 signal line 43. Therefore, the distance between the type-3 signal line 43 and the two rows of pixel circuits 20 can be reduced to a certain extent, which reduces the complexity of wiring the type-3 signal lines 43 and, therefore, simplifies the manufacture of the display substrate 100.

[0181] In some examples, two adjacent rows of pixel circuits 20 and the same signal line 43 of the third type have equal or substantially equal distances between them.

[0182] Two adjacent rows of pixel circuits 20 may be symmetrically arranged relative to the signal line 43 of the third type.

[0183] Thus, the third type signal line 43 can be electrically connected to two adjacent rows of the pixel circuits 20 along the same or approximately the same paths, so that the electrical signals transmitted through the third type signal line 43 to the two rows of the pixel circuits 20 have a relatively small difference or even no difference. As a result, at the same set luminance, the two rows of subpixels can emit light with little or no difference, which is conducive to improving the image display quality of the display substrate 100 and the display device 1000. Moreover, a plurality of pixel circuits 20 can be regularly arranged, which contributes to rational planning of the relative positions of the first openings 51, thereby increasing the area of ​​the first opening 51, increasing the amount of light collected by the optical element 200, and improving the performance of the optical element 200 and the display device 1000.

[0184] In some examples, as shown in Fig. 2 and 9, the plurality of signal lines 43 of the third type includes a plurality of first trigger signal lines Vinit1, a plurality of second trigger signal lines Vinit2, and a plurality of third trigger signal lines Vinit3.

[0185] For example, the first trigger signal line Vinit1 and the second trigger signal line Vinit2 are located on opposite sides of the row of pixel circuits 20, and the second trigger signal line Vinit2 and the third trigger signal line Vinit3 are located on the same side of the same row of pixel circuits 20.

[0186] For example, the plurality of rows of pixel circuits 20 includes a first row of pixel circuits 20, a second row of pixel circuits 20, a third row of pixel circuits 20, a fourth row of pixel circuits 20 and a fifth row of pixel circuits 20, which are arranged sequentially in the first Y direction. The first line Vinit1 of the trigger signal is located between the first row of pixel circuits 20 and the second row of pixel circuits 20, and the first row of pixel circuits 20 and the second row of pixel circuits 20 are symmetrically arranged relative to the first line Vinit1 of the trigger signal. The second line Vinit2 of the initiating signal and the third line Vinit3 of the initiating signal are located between the second row and the third row of the pixel circuits 20, wherein the second row of the pixel circuits 20 and the third row of the pixel circuits 20 are symmetrically located relative to the second line Vinit2 of the initiating signal (or the third line Vinit3 of the initiating signal).Another first line Vinit1 of the initiating signal is located between the third row and the fourth row of the pixel circuits 20, wherein the third row of the pixel circuits 20 and the fourth row of the pixel circuits 20 are symmetrically located relative to the other first line Vinit1 of the initiating signal. The second line Vinit2 of the initiating signal and the third line Vinit3 of the initiating signal are located between the fourth row and the fifth row of the pixel circuits 20, wherein the fourth row of the pixel circuits 20 and the fifth row of the pixel circuits 20 are symmetrically located relative to the second line Vinit2 of the initiating signal (or the third line Vinit3 of the initiating signal).

[0187] As shown in Figs. 8 and 9, the plurality of signal lines 40 further includes a plurality of second connecting lines 47. The plurality of second connecting lines 47 extend in the first direction Y.

[0188] For example, as shown in Fig. 17, two adjacent columns of pixel circuits 20 located on opposite sides of the second connecting line 47 are symmetrically arranged with respect to the second connecting line 47. Two adjacent columns of pixel circuits 20 located on opposite sides of the first type branching line 44 are symmetrically arranged with respect to the first type branching line 44. In this way, a plurality of signal lines 40 and a plurality of pixel circuits 20 can be regularly arranged, which makes it possible to rationally plan the relative position of the first openings 51. In this way, relatively large areas can be reserved for the areas corresponding to the first openings 51, which contributes to the creation of relatively large areas of the first openings 51.In addition, it is preferable for increasing the light transmittance of the additional display area A2, improving the light transmittance of the layer 50 (the opening ratio in this document refers to the ratio of the area of ​​the plurality of first openings 51 to the entire area of ​​the light-shading layer 50), increasing the amount of light collected by the optical elements 200, and therefore improving the characteristics of the optical elements 200.

[0189] The second connecting line 47 is connected to at least one of the signal lines 43 of the third type. The structure of the second connecting line 47 varies and can be set depending on actual needs and cannot be limited to the embodiments of the present disclosure.

[0190] In some examples, the second connecting line 47 is connected to the signal line 43 of the third type.

[0191] For example, the second connecting line 47 has a continuous and uninterrupted pattern.

[0192] The second connection line 47 and the third-type signal line 43 have different extension directions and are connected to each other, so they can form a mesh structure in a local small area. Therefore, when the electrical signal transmitted through the third-type signal line 43 is transmitted to each pixel circuit 20, the voltage drop is small, and the electrical signals transmitted through the third-type signal line 43 to each pair of adjacent rows of the pixel circuits 20 have a relatively small difference or even no difference. Furthermore, the stability and accuracy of the electrical signals transmitted through the third-type signal line 43 to each pair of adjacent rows of the pixel circuits 20 are ensured, allowing the display substrate 100 to achieve a good image display effect.

[0193] In some other examples, as shown in Figs. 8 and 9, the second connecting line 47 includes at least one gap 471 and a plurality of sublines 472.

[0194] For example, the second connecting line 47 includes a gap 471 and two sublines 472 located on both sides of the gap 471.

[0195] As another example, the second connecting line 47 includes two gaps 471 and three sublines 472, where the subline 472 is located between the two gaps 471, and the remaining two sublines 472 are located on both sides of the two gaps 471.

[0196] For example, the gap 471 is located directly opposite the first opening 51, and the connecting line between two sublines 472 on both sides of the gap 471 passes through the first opening 51. In addition, the size of the gap 471 in the first direction Y is larger than the size of the first opening 51 in the first direction Y. In this way, it is possible to ensure that there are no overlapping regions between the orthogonal projections of the plurality of sublines 472 of the second connecting line 47 onto the plane where the substrate 10 is located and the orthogonal projections of the first opening 51 onto the plane where the substrate 10 is located. In the process of external light passing through the display substrate 100 through the first opening 51, the loss caused by the blocking of external light by the plurality of sublines 472 can be reduced or even prevented, thereby increasing the amount of light collected by the optical element 200 and improving the characteristics of the optical element 200.

[0197] For example, each gap 471 is equipped with two of the plurality of sublines 472 on opposite sides of it. Subline 472 is connected to signal line 43 of the third type.

[0198] As shown in Fig. 9, it can be understood that a plurality of sublines 472 of the same second connecting line 47 are connected to the third type signal lines 43 of the same type in a plurality of third type signal lines 43. In this document, the third type signal lines 43 of the same type refer to the third type signal lines 43 that transmit the same electrical signal. For example, the first trigger signal line Vinit1 and the second trigger signal line Vinit2 are different types of third type signal lines. The first trigger signal line Vinit1 and the third trigger signal line Vinit3 are different types of third type signal lines. The third trigger signal line Vinit3 and the second trigger signal line Vinit2 are different types of third type signal lines.

[0199] For example, the plurality of connecting lines 47 of the second type includes the plurality of connecting lines 473 of the first type, the plurality of connecting lines 474 of the second type, and the plurality of connecting lines 475 of the third type.

[0200] A plurality of sub-lines 472 of the first type connecting line 473 are respectively connected to a plurality of first Vinit1 trigger signal lines. A plurality of sub-lines 472 of the second type connecting line 474 are respectively connected to a plurality of second Vinit2 trigger signal lines. A plurality of sub-lines 472 of the third type connecting line 475 are respectively connected to a plurality of third Vinit3 trigger signal lines.

[0201] Therefore, the second connection line 47 is connected to a plurality of third-type signal lines 43, so that the plurality of second connection lines 47 and the plurality of third-type signal lines 43 form a mesh structure. As a result, when transmitting an electrical signal transmitted through the third-type signal line 43 to each pixel circuit 20, the voltage drop is small, which ensures the stability and accuracy of the electrical signals transmitted through the third-type signal line 43 to each pair of adjacent rows of the pixel circuits 20, thereby enabling the display substrate 100 to have a good image display effect.

[0202] In Fig. 9, the dotted line BL1 illustrates the transmission path of the first trigger signal transmitted along the first trigger signal line Vinit1, the dotted line BL2 illustrates the transmission path of the second trigger signal transmitted along the second trigger signal line Vinit2, and the dotted line BL3 illustrates the transmission path of the third trigger signal transmitted along the third trigger signal line Vinit3.

[0203] In some examples, as shown in Fig. 8 and 17, the second connecting line 47 is located between two adjacent Data lines of data signals.

[0204] In the plan view shown in Fig. 8, in the second direction X, the arrangement order of the plurality of signal lines 40 and the first openings 51 is as follows: the first type signal line 41 (or the first type voltage signal line VDD), the first type branch line 44, the first type signal line 41 (or the first type voltage signal line VDD), the data signal line Data, the first opening 51 and the second connecting line 47, the data signal line Data and the first type signal line 41 (or the first type voltage signal line VDD).

[0205] For example, the second connecting line 47 is located in the same layer as two adjacent Data signal lines.

[0206] Because the second connection line 47 is connected to the third type signal line 43, the second connection line 47 transmits a DC voltage electrical signal. Therefore, the second connection line 47 can be used to shield two adjacent data signal lines to avoid mutual interference between the data signals transmitted by the two adjacent data signal lines and to improve the stability and accuracy of the data signals transmitted by the two adjacent data signal lines. As a result, the light emitted by the subpixel and the target light can have a small difference, improving the image display quality of the display substrate 100 and the display device 100.

[0207] In some embodiments, as shown in Figs. 11-17 and 8, the display substrate 100 includes: a shielding layer BSM, a first active layer PL, a third gate conductive layer Gate3, a first gate conductive layer Gate1, a second active layer ZL, a second gate conductive layer Gate2, a first source-drain conductive layer SD1 and a second source-drain conductive layer SD2, which are sequentially arranged on the side of the substrate 10.

[0208] Fig. 11 is a top view of the structure of the shielding layer BSM. Fig. 12 is a top view of the structure of the first active layer PL. Fig. 13 is a top view of the multilayer structure of the first active layer PL and the third gate conductive layer Gate3. Fig. 14 is a top view of the structure of the first gate conductive layer Gate1. Fig. 15 is a top view of the structure of the second gate conductive layer Gate2. Fig. 16 is a top view of the multilayer structure of the first gate conductive layer Gate1, the second active layer ZL and the second gate conductive layer Gate2. Fig. 8 is a top view of the multilayer structure of the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2. In Fig.17 shows a top view of a multilayer structure consisting of a shielding layer BSM, a first active layer PL, a third gate conductive layer Gate3, a first gate conductive layer Gate1, a second active layer ZL, a second gate conductive layer Gate2, a first source-drain conductive layer SD1 and a second source-drain conductive layer SD2.

[0209] It can be understood that Fig. 6 shows a top view of another multilayer structure consisting of a first source-drain conductive layer SD1, a second source-drain conductive layer SD2 and a light-shielding layer 50. Fig. 7 shows a top view of another multilayer structure consisting of a first source-drain conductive layer SD1 and a second source-drain conductive layer SD2.

[0210] The BSM shield layer material may include a conductive material. The BSM shield layer may be connected to a signal line transmitting a DC voltage electrical signal (for example, a first voltage signal line VDD, a common voltage signal line, a first trigger signal line Vinit1, a second trigger signal line Vinit2, or a third trigger signal line Vinit3) to improve the stability of the electrical signal of the film layer (for example, the film layer where the gate of the drive transistor T4 is located) located on the side of the BSM shield layer remote from the substrate 10, thereby preventing interference in the signal of the film layer.

[0211] For example, the material of the first active layer PL may include a semiconductor material such as amorphous silicon, single-crystal silicon, and polycrystalline silicon.

[0212] For example, the material of the second active layer ZL may include a metal oxide-based semiconductor material such as indium gallium zinc oxide (IGZO).

[0213] For example, the materials of the first gate conductive layer Gate1, the second gate conductive layer Gate2, the third gate conductive layer Gate3, the first source-drain conductive layer SD1, and the second source-drain conductive layer SD2 are conductive materials. For example, the materials of the first gate conductive layer Gate1, the second gate conductive layer Gate2, and the third gate conductive layer Gate3 may be the same, and the materials of the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 may be the same.

[0214] For example, the conductive material can be a metal such as aluminum (Al), silver (Ag), copper (Cu) and chromium (Cr).

[0215] It should be noted that the orthogonal projection of the first active layer PL onto the substrate 10 overlaps the orthogonal projections of the third gate conductive layer Gate3 onto the substrate 10. After the first gate conductive layer Gate1 is formed on the side of the first active layer PL remote from the substrate 10, doping is performed on the first active layer PL using the third gate conductive layer Gate3 as a mask. As a result, the portions of the first active layer PL covered by the third gate conductive layer Gate3 form active structures of some transistors, and the portions of the first active layer PL not covered by the third gate conductive layer Gate3 form conductors that can serve as the first electrodes or second electrodes of some transistors. The portions of the third gate conductive layer Gate3 overlapping with the first active layer PL form gate structures of some transistors.

[0216] In addition, the orthogonal projection of the second active layer ZL onto the substrate 10 and the orthogonal projections of the second gate conductive layer Gate2 onto the substrate 10 have the same overlapping structures as the orthogonal projection of the second active layer ZL onto the substrate 10 and the orthogonal projections of the first gate conductive layer Gate1 onto the substrate 10. The portions of the second gate conductive layer Gate2 located within the same overlapping patterns and the portions of the first gate conductive layer Gate1 located within the same overlapping patterns form gate patterns of some transistors, and the portions of the second active layer ZL connected to the same overlapping patterns form the first electrodes or the second electrodes of some transistors.

[0217] It can be understood that in the multiple film layers as mentioned above, an insulating layer (not shown in the drawings) may be provided between any two adjacent film layers. The drawings only show the positions of some through holes in the insulating layer. Each insulating layer can insulate conductive film layers (in this document, conductive film layers refer to the shield layer BSM, the first active layer PL, the third gate conductive layer Gate3, the first gate conductive layer Gate1, the second active layer ZL, the second gate conductive layer Gate2, the first source-drain conductive layer SD1, and the second source-drain conductive layer SD2) located on opposite sides of it, so as to prevent short circuits between the conductive film layers located on opposite sides of each insulating layer. Conductive film layers can be connected via through holes passing through the insulating layers.For example, the materials of the insulating layers can be silicon oxide, silicon nitride or silicon oxynitride.

[0218] In the embodiment, a plurality of signal lines (hereinafter referred to as a plurality of second type lines 45, a plurality of first type signal lines 41, a plurality of first type lines 44, a plurality of data signal lines, a plurality of second type lines 47, and a plurality of second type signal lines 42) are arranged in three different film layers (for example, a first source-drain conductive layer SD1, a second source-drain conductive layer SD2, and a third source-drain conductive layer) of the display substrate 100. Therefore, the number of film layers in the display substrate 100 is relatively large, and the total thickness of the display substrate 100 is also relatively large, which is not conducive to achieving a light and thin structure of the display substrate 100. Moreover, the masks used to form the three film layers have a relatively high cost, which is not conducive to reducing the production cost of the display substrate 100.

[0219] In some examples of the present disclosure, as shown in Figs. 8 and 17, a plurality of second-type branch lines 45 are located in the first source-drain conductive layer SD1. A plurality of first-type signal lines 41, a plurality of first-type branch lines 44, and a plurality of data signal lines Data are located in the second source-drain conductive layer SD2.

[0220] Therefore, the plurality of first type signal lines 41, the plurality of first type branch lines 44, and the plurality of data signal lines Data can be arranged in one layer, which contributes to improving the shielding performance of the first type signal lines 41 from the first type branch lines 44.

[0221] As shown in Fig. 8, a plurality of second connecting lines 47 are located in the second source-drain conducting layer SD2. A plurality of first initiation signal lines Vinit1 are located in the first source-drain conducting layer SD1. As shown in Fig. 14, a plurality of second initiation signal lines Vinit2 and the first connecting lines 46 are located in the first gate conducting layer Gate1. As shown in Fig. 15, a plurality of third initiation signal lines Vinit3 are located in the second gate conducting layer Gate2.

[0222] The first Vinit1 trigger signal lines, the second Vinit2 trigger signal lines, and the third Vinit3 trigger signal lines are arranged in different film layers, and thus the conductor density in each film layer can be reduced to a certain extent. The first Vinit1 trigger signal lines, the second Vinit2 trigger signal lines, and the third Vinit3 trigger signal lines are arranged in different film layers relative to the second connecting lines 47, so that the first Vinit1 trigger signal lines and the second connecting lines 47, the second Vinit2 trigger signal lines and the second connecting lines 47, and the third Vinit3 trigger signal lines and the second connecting lines 47 do not interfere with each other.

[0223] A plurality of data signal lines and a plurality of second connecting lines 47 are located in the second source-drain conductive layer SD2. The second connecting line 47 is located between two adjacent data signal lines, so the second connecting line 47 can be used to shield and protect two adjacent data signal lines.

[0224] Thus, a plurality of signal lines 40 can be arranged in the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 of the display substrate 100, which can reduce the number of film layers in the display substrate 100 and reduce the thickness of the display substrate 100, thereby achieving a light and thin structure of the display substrate 100 and the display device 1000. Moreover, it is possible to further save on the mask, thereby reducing the production cost of the display substrate 100 and the display device 1000.

[0225] In some other examples, as shown in Fig. 6, a plurality of first connecting lines 46 are arranged in the first source-drain conductive layer SD1. Thus, the conductor density of the first gate conductive layer Gate1 can be reduced to a certain extent.

[0226] In some examples, as shown in Fig. 13 and 17, the plurality of signal lines 40 further includes: a plurality of enable signal lines EML, a plurality of first scanning signal lines ScanP, a plurality of second scanning signal lines ScanN, a plurality of first reset signal lines ResetP, and a plurality of second reset signal lines ResetN.

[0227] Each of the EML enable signal lines, the first ScanP scanning signal line, the second ScanN scanning signal line, the first ResetP reset signal line, and the second ResetN reset signal line are continued in the second X direction.

[0228] The first scanning signal lines ScanP, the second scanning signal lines ScanN, the first reset signal lines ResetP and the second reset signal lines ResetN can be connected to the gate driver circuit(s) to receive electrical signals of their gate driver circuit(s).

[0229] The EML enable signal line can be connected to an enable driver circuit (EM GOA) located in the peripheral area N of the display substrate 100 to receive an enable signal from the enable driver circuit.

[0230] For example, as shown in Fig. 13, a plurality of enable signal lines EML, a plurality of first scanning signal lines ScanP, a plurality of first reset signal lines ResetP, and a plurality of second reset signal lines ResetN are disposed in the third gate conductive layer Gate3.

[0231] As shown in Fig. 16, a plurality of second scanning signal lines ScanN are arranged in the first gate conductive layer Gate1 and in the second gate conductive layer Gate2.

[0232] For example, the data signal line Data is connected to the data signal terminal DN in the pixel circuit 20 and is used to transmit the data signals Data to the switching transistor T4 in the pixel circuit 20. The first voltage signal line VDD is connected to the first voltage signal terminal VDDN in the pixel circuit 20 and is used to transmit the first voltage signal to the first light-emitting control transistor T5 and the storage capacitor Cst in the pixel circuit 20.

[0233] The enable signal line EML is connected to the enable signal terminal EM in the pixel circuit 20 and is used to transmit the enable signal to the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the pixel circuit 20. The first scanning signal line ScanP is connected to the first scanning signal terminal SN1 in the pixel circuit 20 and is used to transmit the first scanning signal to the switching transistor T4 in the pixel circuit 20. The second scanning signal line ScanN is connected to the second scanning signal terminal SN2 in the pixel circuit 20 and is used to transmit the second scanning signal to the compensation transistor T2 in the pixel circuit 20.

[0234] The first trigger signal line Vinit1 is connected to the first trigger signal terminal VN1 in the pixel circuit 20 and is used to transmit the first trigger signal to the first reset transistor T1 in the pixel circuit 20. The second trigger signal line Vinit2 is connected to the second trigger signal terminal VN2 in the pixel circuit 20 and is used to transmit the second trigger signal to the second reset transistor T7 in the pixel circuit 20. The third trigger signal line Vinit3 is connected to the third trigger signal terminal VN3 in the pixel circuit 20 and is used to transmit the third trigger signal to the third reset transistor T8 in the pixel circuit 20.

[0235] As shown in Fig. 3, the display substrate 100 further includes an encapsulating layer 60 located on the side of the light-emitting devices 30 remote from the substrate 10 and located between the light-shading layer 50 and the plurality of light-emitting devices 30.

[0236] For example, the encapsulation layer 60 may be a thin-film encapsulation layer that can encapsulate the aforementioned subpixels. As a result, the pixel circuits 20 and the light-emitting devices 30 are isolated from external moisture penetration, which improves the luminous performance and service life of the light-emitting devices 30 and prevents oxidation of the pixel circuits 20 and the light-emitting devices 30 due to moisture penetration.

[0237] The encapsulating layer 60 has a certain light transmittance, so that the light emitted from the light-emitting device 30 can pass through the encapsulating layer 60 and be released to the outside.

[0238] The encapsulating layer 60 includes inorganic encapsulating layer(s) and organic encapsulating layer(s), which are disposed on top of each other. The inorganic encapsulating layer(s) may include a first inorganic encapsulating layer and a second inorganic encapsulating layer. The organic encapsulating layer may be located between the first inorganic encapsulating layer and the second inorganic encapsulating layer.

[0239] For example, the inorganic encapsulating layer material is an inorganic material, and the inorganic encapsulating layer can be formed by vapor deposition. The organic encapsulating layer material is an organic material, and the organic encapsulating layer can be formed by inkjet printing. The inorganic encapsulating layer material can be an optically transparent (OC) adhesive.

[0240] It can be understood that the organic encapsulating layer is mainly used for leveling and relieving stress, and the first inorganic encapsulating layer and the second inorganic encapsulating layer in the inorganic encapsulating layer(s) mainly serve to protect against moisture and oxygen penetration and seal the organic encapsulating layer located between the first inorganic encapsulating layer and the second inorganic encapsulating layer.

[0241] The above descriptions represent only specific implementations of the present disclosure, but the scope of protection of the present disclosure is not limited to them. Changes or substitutions that anyone skilled in the art could conceive within the technical scope of the present disclosure should be included within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should correspond to the protection scope of the patent claims.

Claims

1. A display substrate having a display area and a connection area, wherein the connection area is located on the side of the display area in a first direction; wherein the display substrate comprises: substrate; a plurality of signal lines located on the substrate, wherein the signal lines are located at least in the display zone; the plurality of signal lines includes a plurality of signal lines of the first type and a plurality of branching lines of the first type; and the signal lines of the first type are configured to receive a DC electrical signal; and a light-shading layer located on the side of the plurality of signal lines remote from the substrate and located in the display area; the light-shading layer includes a plurality of first openings, wherein The display area includes a main display area and an additional display area located at the side of the main display area; the light transmittance of the additional display area is greater than the light transmittance of the main display area; a plurality of first openings are located in the additional display area; orthogonal projections of a plurality of first type signal lines and a plurality of first type branching lines onto the substrate and orthogonal projections of a plurality of first openings onto the substrate do not overlap; and a first type branching line is located between two adjacent first type signal lines.

2. The display substrate of claim 1, wherein the first type signal lines extend in a first direction, and the first type branch lines extend in a first direction; and a branch line of the first type located between two adjacent signal lines of the first type, and the two adjacent signal lines of the first type have substantially equal or equal distances.

3. The display substrate of claim 2, wherein two adjacent signal lines of the first type, located on opposite sides of the branching line of the first type, are located substantially symmetrically or symmetrically with respect to the branching line of the first type.

4. The display substrate according to claim 2 or 3, further comprising a plurality of pixel circuits, wherein the plurality of pixel circuits are arranged in multiple rows and multiple columns; each row of the pixel circuits is arranged in a second direction, and each column of the pixel circuits is arranged in a first direction, wherein the second direction intersects the first direction; and two adjacent signal lines of the first type, located on both sides of the branching line of the first type, form a group of signal lines of the first type, and two signal lines of the first type in this group are connected; wherein the signal line of the first type is electrically connected to the column of pixel circuits.

5. The display substrate of claim 4, wherein the plurality of signal lines further includes a plurality of first connecting lines; wherein the first connecting lines extend in a second direction; and the first connecting line connects two signal lines of the first type in a group of signal lines of the first type.

6. The display substrate of claim 1, wherein the signal lines of the first type include a first voltage line.

7. The display substrate of claim 1, wherein the plurality of signal lines further includes a plurality of signal lines of a second type; the signal lines of the second type and the signal lines of the first type are configured to be enabled for receiving the same electrical signal; and the signal lines of the second type have the same or substantially the same directions of extension as the signal lines of the first type; and compared to the signal lines of the second type, the signal lines of the first type are located closer to the center line of the display area, continuing in the first direction.

8. The display substrate of claim 1, wherein the plurality of signal lines further includes a plurality of second type branch lines and a plurality of data signal lines; the data signal lines extend in a first direction, the second type branch lines extend in a second direction, and the second type branch lines are located in the display area; the second type branch line is connected to the first type branch line; and The data signal line is connected to the second branch line.

9. The display substrate of claim 1, further comprising a plurality of pixel circuits, wherein the plurality of pixel circuits are arranged in multiple rows and multiple columns; each row of the pixel circuits is arranged in a second direction, and each column of the pixel circuits is arranged in a first direction, wherein the second direction intersects the first direction; the plurality of signal lines further includes a plurality of signal lines of a third type; the signal lines of the third type are configured to receive an initiating signal; and the signal lines of the third type extend in a second direction; and Two adjacent rows of pixel circuits are connected to the same signal line of the third type.

10. The display substrate of claim 9, wherein two adjacent rows of pixel circuits are located on opposite sides of the same signal line of the third type.

11. The display substrate of claim 9, wherein two adjacent rows of pixel circuits and the same signal line of the third type are located at the same or substantially the same distance from each other.

12. The display substrate of claim 9, wherein the plurality of signal lines of the third type includes a plurality of first trigger signal lines, a plurality of second trigger signal lines, and a plurality of third trigger signal lines.

13. The display substrate of claim 9, wherein the plurality of signal lines further includes a plurality of second connecting lines; the second connecting lines extend in a first direction; and the second connecting line is connected to a signal line of a third type.

14. The display substrate of claim 9, wherein the plurality of signal lines further includes a plurality of second connecting lines; and the second connecting lines extend in a first direction; the second connecting line includes at least one break and a plurality of sublines; and the gap is located directly opposite the first opening, and the size of the gap in the first direction is greater than or equal to the size of the first opening in the first direction; each gap is provided with two of a plurality of auxiliary lines on opposite sides from it; and the auxiliary line is connected to a signal line of the third type.

15. The display substrate of claim 13, wherein the plurality of signal lines further includes a plurality of data signal lines, and the second connecting line is located between two adjacent data signal lines.

16. The display substrate of claim 1, wherein the display substrate comprises a first source-drain conductive layer and a second source-drain conductive layer arranged sequentially on a side of the substrate; the display substrate further comprises a plurality of second type branching lines and a plurality of data signal lines, wherein a plurality of branching lines of the second type are located in the first source-drain conducting layer, a plurality of signal lines of the first type, a plurality of branching lines of the first type and a plurality of data signal lines are located in the second source-drain conducting layer.

17. The display substrate of claim 16, further comprising a first gate conductive layer and a second gate conductive layer arranged sequentially between the substrate and the first source-drain conductive layer, wherein the first gate conductive layer is arranged between the substrate and the second gate conductive layer; the display substrate further comprises a plurality of first connection lines, a plurality of second connection lines and a plurality of signal lines of a third type; wherein the plurality of signal lines of the third type includes a plurality of first trigger signal lines, a plurality of second trigger signal lines and a plurality of third trigger signal lines, wherein a plurality of second connecting lines are located in the second source-drain conductive layer; a plurality of first initiation signal lines are located in the first source-drain conductive layer; and a plurality of second initiating signal lines and a plurality of first connecting lines are located in the first gate conductive layer, and a plurality of third initiating signal lines are located in the second gate conductive layer.

18. The display substrate of claim 1, further comprising a plurality of filtering portions, wherein the light-shading layer further includes a plurality of second openings; the plurality of second openings are located in the main display area, and the filtering portion is located in the second opening.

19. A display substrate according to any one of paragraphs 1-18, further comprising: a plurality of light-emitting devices located on the side of the plurality of signal lines remote from the substrate; and a protective layer located between the light-shielding layer and the plurality of light-emitting devices.

20. A display device comprising a display substrate according to any one of paragraphs 1-19; and an optical element located on the side of the display substrate that does not provide light output and located in an additional display zone of the display substrate.

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