Gallium arsenide operational amplifier with nonlinear correction
The GaAs operational amplifier circuit addresses the low slew rate issue by integrating novel connections and a correction capacitor, achieving enhanced slew rates of 2927 V/μs and 3000 V/μs, overcoming limitations in traditional GaAs amplifiers.
Patent Information
- Authority / Receiving Office
- RU · RU
- Patent Type
- Patents
- Current Assignee / Owner
- FEDERALNOE GOSUDARSTVENNOE BYUDZHETNOE OBRAZOVATELNOE UCHREZHDENIE VYSSHEGO OBRAZOVANIYA DONSKOJ GOSUDARSTVENNYJ TEKHNICHESKIJ UNIV DGTU
- Filing Date
- 2025-10-06
- Publication Date
- 2026-07-09
AI Technical Summary
Existing gallium arsenide (GaAs) operational amplifiers face limitations in achieving high maximum slew rate (SR) with low static current consumption, particularly due to the lack of n-p-n transistors and the inefficiencies in classic junction field-effect transistor (JFET) input differential stages.
The proposed GaAs operational amplifier circuit incorporates novel connections and elements, including connecting the drain of input field-effect transistors to a current mirror, integrating a correction capacitor, and using additional transistors to enhance the slew rate, specifically by allowing faster recharge of the correction capacitor.
The solution achieves significantly higher maximum slew rates of 2927 V/μs on the leading edge and 3000 V/μs on the trailing edge, outperforming traditional designs.
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Abstract
Description
[0001] The proposed invention relates to the microelectronic element base of communication systems, computing technology, instrument making and automation, including those operating at high temperatures.
[0002] In Russian and foreign microelectronics, increased attention is paid to gallium arsenide (GaAs) integrated circuits [1]. However, the specifics of gallium arsenide technological processes impose significant limitations on the types of transistors implemented and their characteristics [2, 3]. The promising gallium arsenide technological process, mastered by the Minsk Research Institute of Radio Materials (https: / / mniirm.by / ) in the interests of the Union State, ensures the creation of only pnp BJT and nJFet transistors. The lack of n-p-n transistors creates problems in the construction of high-temperature GaAs op amps, which are in demand in a number of important fields of science and technology - space instrumentation, oil and gas, automotive and aviation industries.
[0003] Input differential stages (IDCs) based on junction field-effect transistors (JFETs) are widely used in analog microelectronics [4-11]. The proposed invention pertains to this class of IDCs. Practical application of classic JFET IDCs in GaAs operational amplifiers (OPA) with low static current consumption does not allow achieving increased values of the maximum output voltage slew rate (SR).
[0004] The closest prototype of the claimed device is the operational amplifier according to the Burr-Brown patent US 4.901.031, 1990, Fig. 5. It contains (Fig. 1) first 1 and second 2 differential inputs, first 3 and second 4 input field-effect transistors, the gates of which are connected to the corresponding first 1 and second 2 differential inputs, the first 5 bipolar transistor, the emitter of which is connected to the source of the first 3 input field-effect transistor, the second 6 bipolar transistor, the emitter of which is connected to the source of the second 4 input field-effect transistor, the first 7 auxiliary bipolar transistor, the base of which is connected to its collector, the second 8 auxiliary bipolar transistor, the base of which is connected to its collector, the main 9 reference current source connected to the first 10 power supply bus, a current mirror 11, the output of which is connected to the input of a buffer amplifier 12, the output of which 13 is the potential output of the device, the second 14 power supply bus.
[0005] A significant drawback of the prototype operational amplifier is that it does not provide increased values of the maximum rate of rise of the output voltage in large signal mode with low static current consumption.
[0006] The main objective of the proposed invention is to develop a gallium arsenide operational amplifier circuit that is implemented within the framework of a combined GaAs technological process that allows the creation of only pn-p bipolar and nJFet field-effect transistors, and has increased values of the maximum slew rate (SR).
[0007] The stated problem is achieved in that in the operational amplifier of Fig. 1, containing the first 1 and second 2 differential inputs, the first 3 and second 4 input field-effect transistors, the gates of which are connected to the corresponding first 1 and second 2 differential inputs, the first 5 bipolar transistor, the emitter of which is connected to the source of the first 3 input field-effect transistor, the second 6 bipolar transistor, the emitter of which is connected to the source of the second 4 input field-effect transistor, the first 7 auxiliary bipolar transistor, the base of which is connected to its collector, the second 8 auxiliary bipolar transistor, the base of which is connected to its collector, the main 9 reference current source connected to the first 10 power supply bus, a current mirror 11, the output of which is connected to the input of a buffer amplifier 12, the output of which 13 is the potential output of the device, the second 14 power supply bus,new elements and connections are provided - the drain of the first 3 input field-effect transistor is connected to the input of the current mirror 11 matched with the second 14 power supply bus, the drain of the second 4 input field-effect transistor is connected to the output of the current mirror 11, the emitter of the first 7 auxiliary bipolar transistor is connected to the source of the first 3 input field-effect transistor, the emitter of the second 8 auxiliary bipolar transistor is connected to the source of the second 4 input field-effect transistor, the collectors of the first 5 and second 6 bipolar transistors are connected to the first 10 power supply bus, the main 9 reference current source is connected between the base of the second 6 bipolar transistor and the first 10 power supply bus, the base of the first 5 bipolar transistor is connected to the first 10 power supply bus through the first 15 additional reference current source, the first 1 differential input of the device is connected to the base of the first 16 additional transistor,the emitter of which is connected to the base of the second 6 bipolar transistor, the second 2 differential input of the device is connected to the base of the second 17 additional transistor, the emitter of which is connected to the base of the first 5 bipolar transistor, the collectors of the first 16 and second 17 additional transistors are connected to the first 10 bus of the power supply, the drain of the second 4 input field-effect transistor is connected to the base of the output transistor 18, the emitter of which is connected to the second 14 bus of the power supply, and the collector is connected to the input of the buffer amplifier 12 and through the second 19 additional source of reference current and is connected to the first 10 bus of the power supply, wherein between the base of the output transistor 18 and the output of the buffer amplifier 12 an integrating correction capacitor 20 is included.
[0008] The drawing in Fig. 1 shows the circuit diagram of the prototype op-amp.
[0009] The drawing in Fig. 2 shows a circuit diagram of a GaAs op-amp with nonlinear correction based on the first 5 and second 6 bipolar transistors.
[0010] The drawing in Fig. 3 shows the static mode of the op-amp circuit in the drawing in Fig. 2 with a real current mirror on transistors VT10, VT11 in the LTspice environment at t=27°C, I1=I2=100 μA, I3=400 μA, Vcc=-Vee=5V.
[0011] The drawing in Fig. 4 shows the logarithmic amplitude-frequency characteristic of the op-amp in the drawing in Fig. 3 in the LTspice environment at t=27°C, I1=I2=100 μA, I3=400 μA, integrating correction capacitance Ck=1 pF, Vcc=-Vee=5V.
[0012] The drawing in Fig. 5 shows the leading edge of the transient process of the op-amp in the drawing in Fig. 3 in the LTspice environment at t=27°C, I1=I2=100 μA, I3=400 μA, Ck=1 pF, Vcc=-Vee=5V.
[0013] The drawing in Fig. 6 shows the trailing edge of the transient process of the op-amp in the drawing in Fig. 3 in the LTspice environment at t=27°C, I1=I2=100 μA, I3=400 μA, Ck=1 pF, Vcc=-Vee=5V.
[0014] The gallium arsenide operational amplifier with nonlinear correction of Fig. 2 comprises first 1 and second 2 differential inputs, first 3 and second 4 input field-effect transistors, the gates of which are connected to the corresponding first 1 and second 2 differential inputs, a first 5 bipolar transistor, the emitter of which is connected to the source of the first 3 input field-effect transistor, a second 6 bipolar transistor, the emitter of which is connected to the source of the second 4 input field-effect transistor, a first 7 auxiliary bipolar transistor, the base of which is connected to its collector, a second 8 auxiliary bipolar transistor, the base of which is connected to its collector, a main 9 reference current source connected to the first 10 power supply bus, a current mirror 11, the output of which is connected to the input of a buffer amplifier 12, the output of which 13 is the potential output of the device,the second 14 power supply bus. The drain of the first 3 input field-effect transistor is connected to the input of the current mirror 11 matched with the second 14 power supply bus, the drain of the second 4 input field-effect transistor is connected to the output of the current mirror 11, the emitter of the first 7 auxiliary bipolar transistor is connected to the source of the first 3 input field-effect transistor, the emitter of the second 8 auxiliary bipolar transistor is connected to the source of the second 4 input field-effect transistor, the collectors of the first 5 and second 6 bipolar transistors are connected to the first 10 power supply bus, the main 9 reference current source is connected between the base of the second 6 bipolar transistor and the first 10 power supply bus, the base of the first 5 bipolar transistor is connected to the first 10 power supply bus through the first 15 additional reference current source, the first 1 differential input of the device is connected to the base of the first 16 additional transistor,the emitter of which is connected to the base of the second 6 bipolar transistor, the second 2 differential input of the device is connected to the base of the second 17 additional transistor, the emitter of which is connected to the base of the first 5 bipolar transistor, the collectors of the first 16 and second 17 additional transistors are connected to the first 10 bus of the power supply, the drain of the second 4 input field-effect transistor is connected to the base of the output transistor 18, the emitter of which is connected to the second 14 bus of the power supply, and the collector is connected to the input of the buffer amplifier 12 and through the second 19 additional source of reference current and is connected to the first 10 bus of the power supply, wherein between the base of the output transistor 18 and the output of the buffer amplifier 12 an integrating correction capacitor 20 is included.
[0015] Let us consider the operation of the claimed GaAs operational amplifier with nonlinear correction (Fig. 2).
[0016] The static mode of the op-amp input stage transistors is set by the main 9 reference current source, the first 15, and the second 19 additional reference current sources. With identical emitter-base junctions of the second 6 bipolar and first 7 auxiliary bipolar transistors, as well as the first 5 bipolar and second 8 auxiliary bipolar transistors, the drain currents of the first 3 and second 4 input field-effect transistors are equal to 2I0. In practical circuits, it is recommended to use reference current sources on field-effect transistors with a control p-n junction as the main 9 reference current source, the first 15, and the second 19 additional reference current sources.
[0017] The feature of the control unit in the drawing in Fig. 2 is that with a positive increment of the voltage at input 2 relative to input 1, the drain current of the second 4 input field-effect transistor takes on greater values, which contributes to a faster recharge of the integrating correction capacitor 20 and, as a consequence, an increase in SR.
[0018] Computer simulation of the op-amp circuit in Fig. 2 shows that with an ideal current mirror 11, the maximum rate of rise of the output voltage along the leading edge is 3380 V / μs (Fig. 5), and along the trailing edge – 1644 V / μs (Fig. 6).
[0019] If the op-amp circuit uses a real current mirror on transistors VT10, VT11 (Fig. 3), then the leading edge response speed SR (+) =2927 V / μs, and on the rear SR (-) =3000 V / μs.
[0020] Thus, the proposed operational amplifier has significant advantages in comparison with the prototype op-amp - increased values of the maximum rate of rise of the output voltage.
[0021] BIBLIOGRAPHICAL LIST
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[0023] 2. W. Liu, D. Hill, D. Costa and J. S. Harris, "High-performance microwave AlGaAs-InGaAs Pnp HBT with high-DC current gain," in IEEE Microwave and Guided Wave Letters, vol. 2, no. 8, pp. 331-333, Aug. 1992, doi: 10.1109 / 75.153604.
[0024] 3. KW Kobayashi, DK Umemoto, JR Velebir, DC Streit and AK Oki, "Integrated complementary HBT microwave push-pull and Darlington amplifiers with PNP active loads," GaAs IC Symposium Technical Digest 1992, 1992, pp. 313-316, doi: 10.1109 / GAAS. 1992.247281.
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Claims
A gallium arsenide operational amplifier with nonlinear correction, comprising first (1) and second (2) differential inputs, first (3) and second (4) input field-effect transistors, the gates of which are connected to the corresponding first (1) and second (2) differential inputs, a first (5) bipolar transistor, the emitter of which is connected to the source of the first (3) input field-effect transistor, a second (6) bipolar transistor, the emitter of which is connected to the source of the second (4) input field-effect transistor, a first (7) auxiliary bipolar transistor, the base of which is connected to its collector, a second (8) auxiliary bipolar transistor, the base of which is connected to its collector, a main (9) reference current source connected to the first (10) power supply bus, a current mirror (11), the output of which is connected to the input of a buffer amplifier (12), the output of which (13) is the potential output of the device, a second (14) power supply bus, characterized in that,that the drain of the first (3) input field-effect transistor is connected to the input of a current mirror (11) matched with the second (14) power supply bus, the drain of the second (4) input field-effect transistor is connected to the output of the current mirror (11), the emitter of the first (7) auxiliary bipolar transistor is connected to the source of the first (3) input field-effect transistor, the emitter of the second (8) auxiliary bipolar transistor is connected to the source of the second (4) input field-effect transistor, the collectors of the first (5) and second (6) bipolar transistors are connected to the first (10) power supply bus, the main (9) reference current source is connected between the base of the second (6) bipolar transistor and the first (10) power supply bus, the base of the first (5) bipolar transistor is connected to the first (10) power supply bus through the first (15) additional reference current source, the first (1) differential input of the device is connected to the base of the first (16) additional transistor,the emitter of which is connected to the base of the second (6) bipolar transistor, the second (2) differential input of the device is connected to the base of the second (17) additional transistor, the emitter of which is connected to the base of the first (5) bipolar transistor, the collectors of the first (16) and second (17) additional transistors are connected to the first (10) power supply bus, the drain of the second (4) input field-effect transistor is connected to the base of the output transistor (18), the emitter of which is connected to the second (14) power supply bus, and the collector is connected to the input of the buffer amplifier (12) and through the second (19) additional reference current source is connected to the first (10) power supply bus, wherein between the base of the output transistor (18) and the output of the buffer amplifier (12) an integrating correction capacitor (20) is connected.,