Device tolerant to input signal exceeding supply voltage of input / output cell

Abstract

FIELD: input-output cell devices.SUBSTANCE: input-output cell device, comprising an input circuit that maintains the operability of the input when a signal exceeds the supply voltage, a pass NMOS transistor, a pull-up PMOS transistor, the source of which is connected to the supply voltage Vdd, a drain to the input-output cell input circuit, and an inverter connected to the input-output cell input circuit, wherein it contains an additional inverter consisting of two transistors, the gates of which are connected to the input-output cell input circuit, wherein the source of the first transistor is connected to the supply bus Vdd, and the source of the second transistor is connected to the supply bus Vss, wherein a buffer consisting of two pairs of transistors is added to the feedback circuit, the output of the feedback inverter on the first and second transistors is connected to the gates of the pair of transistors of the first inverter of the added buffer, the output of the first inverter of the added buffer is connected to the gates of the pair of transistors of the second inverter of the feedback buffer.EFFECT: maintaining operability at reduced supply voltage and improving the time characteristics in the normal range of supply voltages Vnom±010%.2 cl, 4 dwg, 5 tbl

Description

[0001] Technical field

[0002] The invention relates to the design and construction of microcircuits (integrated circuit design), and is specifically intended for the design of input / output cells with an input tolerant to a signal exceeding the nominal supply voltage (Vnom). Such cells are required for the safe interfacing of the microcircuit with external electrical circuits generating signals with an amplitude up to 2 times the nominal supply voltage of the microcircuit.

[0003] Technology Level

[0004] Various solutions are known for improving the immunity of I / O cells to voltage signals, such as those in patent documents US 5852375, US 6150843, and US 5852375. A circuit for a device tolerant of I / O cells to voltage signals is also known, as described in US Patent US 531259 (FIG. 9), and has been chosen as a prototype. This circuit is shown in Fig. 1. To simplify the circuit, the PAD contact pad and the I / O cell ESD protection circuit are not shown. The circuit is powered by voltage sources Vss=0V and Vdd=3.0V…3.3V. The nominal supply voltage of the NMOS / PMOS transistors is 3.3V. The patent solution comprises a circuit 1 of a 5V-tolerant input / output cell input after an ESD protection circuit, and a circuit 2 of an input / output cell input after a pass NMOS transistor 3 that limits the input voltage.Pass transistor 3 is connected by its drain to circuit 1, by its source to circuit 2, and by its gate to Vdd, which limits the input voltage in circuit 2 to the level Vdd-Vtn, where Vdd is the supply voltage, Vtn is the threshold voltage of NMOS transistor 3. Pull-up PMOS transistor 5 with a long channel length pulls circuit 2, to which the gates of input inverter 7 are connected, to the Vdd bus, compensating for the voltage drop Vtn on pass transistor 3 when a logical "1" is applied to input 1. Gate 6 of transistor 5 is controlled from output 4 of inverter 7, forming feedback.

[0005] This circuit operates reliably in the voltage range of Vdd=3.0V…3.6V. However, due to the voltage drop of Vtn~0.7V…0.8V across transistor 3, as the supply voltage drops below 3.0V, the timing characteristics significantly deteriorate, and the input signal switching thresholds shift and exceed the permissible values. When the supply voltage drops to the range of 1.8V (1.62V…1.98V), under certain manufacturing process variations and at the minimum and maximum permissible temperatures, the circuit described in the patent ceases to function.

[0006] Disclosure of invention

[0007] The technical problem, which the claimed invention is aimed at solving, is to improve the known circuit in order to maintain its functionality with all permissible variations in the parameters of the production process over the entire temperature range with a significant reduction in the supply voltage, going beyond Vnom - 10%.

[0008] The technical result of the declared solution is maintaining operability at reduced supply voltage, and improving the time characteristics in the normal range of supply voltages Vnom±10%.

[0009] In order to achieve the stated result, a device is proposed that is tolerant to an input signal of an input / output cell exceeding the supply voltage, containing a circuit tolerant to the input signal, located after protection against electrostatic discharges, a pass NMOS transistor, the source of which is connected to the input / output cell input circuit, and the gate is connected through a resistor to the Vdd power supply bus, a pull-up PMOS transistor, the source of which is connected to the Vdd power supply, and an inverter connected to the input / output cell input circuit, characterized in that it contains an inverter on transistors, the gates of which are connected to the input / output cell input circuit, the sources to Vdd and Vss, and the drains to the gate of the pull-up pull-up PMOS transistor, connected by the source to Vdd, and by the drain to the input / output cell input circuit, respectively.

[0010] Preferred options are possible when:

[0011] A buffer consisting of two pairs of transistors is added to the feedback circuit, the sources of which are connected to Vdd and Vss respectively, the output of the feedback inverter on the transistors is connected to the gates of the first inverter of the added buffer, the output of the first inverter of the added buffer is connected to the gates of the second inverter of the feedback buffer, whose output is connected to the gate of the pull-up PMOS transistor;

[0012] The device includes a PMOS transistor connected by its source to the drain of the pull-up PMOS transistor, by its drain to the input circuit of the I / O cell, and by its gate to the output of the first inverter in the feedback circuit.

[0013] The combination of the above essential features leads to the fact that:

[0014] maintains operability even with a significant reduction in supply voltage, going beyond Vnom - 10%;

[0015] The device has improved timing characteristics in the standard supply voltage range Vnom ± 10%.

[0016] Brief description of drawings

[0017] The essence of the invention is explained by figures.

[0018] Fig. 1 shows a circuit diagram of an analogue of the one known from US patent No. US 00531359

[0019] Fig. 2 shows a diagram of the claimed device with a separate feedback circuit independent of the input inverter.

[0020] Fig. 3 shows a circuit with an additional buffer in a separate feedback circuit independent of the input inverter.

[0021] Fig. 4 shows a circuit with an additional buffer in a separate feedback circuit independent of the input inverter, and with an additional transistor in the pull-up circuit.

[0022] The positions on the diagrams indicate:

[0023] 1 - I / O cell input voltage tolerance circuit after ESD protection to signal exceeding supply voltage

[0024] 2 - a circuit tolerant to a signal exceeding the supply voltage, the input of the I / O cell after the input voltage limiting pass transistor 3

[0025] 3 - pass NMOS transistor

[0026] 4 - inverter output 7 input cell I / O

[0027] 5 - PMOS pull-up transistor

[0028] 6 - ​​gate of pull-up PMOS transistor 5

[0029] 7 - Input inverter

[0030] 8, 11, 14 - PMOS feedback transistors

[0031] 9, 12, 15 - NMOS feedback transistors

[0032] 10 - drain circuit of transistors 8 and 9

[0033] 13 - drain circuit of transistors 11 and 12

[0034] 16 - PMOS transistor

[0035] Implementation and implementation examples

[0036] The circuit diagram of the claimed device in a simple implementation is shown in Fig. 2, and, like the circuit diagram of the analog in Fig. 1, includes an input 1 circuit, tolerant to an input 1 signal exceeding the rated supply voltage, located after electrostatic discharge protection (ESD) and connected to the drain of a pass NMOS transistor 3, which limits the input voltage, connected by its source to circuit 2 of the input-output cell input. The gate of transistor 3 is connected through a resistor (not shown in the diagram) to the Vdd power supply bus. The signal in circuit 2 is fed to the input of inverter 7, which determines the input signal switching thresholds: these can be CMOS or TTL levels, and a Schmitt trigger can be used instead of inverter 7.

[0037] These switching levels are determined by the requirements of "DC characteristics)) for I / O cells:

[0038] - CMOS: Vil=0.3Vdd, Vih - 0.7Vdd

[0039] - TTL: Vil=0.8V, Vih=2.0V

[0040] The Schimitt trigger has hysteresis, which shifts the switching thresholds to the maximum permissible values: during "rise" switching, to Vih, during "fall" switching, to Vil. This slows the opening / closing process of the pull-up PMOS transistor 5, and, with a significant drop in supply voltage, the voltage Vdd - Vtn at the input of inverter 7 during "rise" switching does not reach its switching threshold. For reliable and faster operation, it is necessary to lower the input switching threshold of the circuit controlling pull-up transistor 5. If such optimization is performed with input inverter 7, its switching thresholds will exceed the "DC characteristics" requirements. For this reason, the feedback controlling pull-up transistor 5 is separated from input inverter 7.

[0041] From output 4 of input inverter 7, the signal is fed to the subsequent circuits of the input / output cell, with a swing from Vss to Vdd. In this circuit, output 4 of inverter 7 is not the input of pull-up PMOS transistor 5, which compensates for the Vtn voltage drop across pass transistor 3 when a logical "1" is applied to input 1. For feedback, an inverter was added on transistors 8-9, whose gates are connected to circuit 2, sources to Vdd and Vss, respectively, and drains 10 of these transistors are connected to gate 6 of pull-up transistor 5, connected by its source to Vdd and by its drain to circuit 2, respectively. This solution allowed us to separate the input circuit of inverter 7 from the feedback circuit designed on transistors 8-9, and optimize each of them for its intended purpose:

[0042] - Input inverter 7 is optimized to ensure that the input signal switching thresholds meet the required DC characteristics levels

[0043] - the feedback circuit on transistors 8-9 is optimized to speed up the switching of pull-up transistor 5.

[0044] This solution had a positive impact on the input characteristics, accelerating switching and maintaining the required switching thresholds at a supply voltage of Vdd << (Vnom - 10%). However, it did not achieve the intended goal of operability within all permissible variations in manufacturing process parameters over the entire temperature range with a significant reduction in supply voltage. This is due to the incomplete closing of transistor 8 during "rise" switching at low supply voltage Vdd due to the voltage limitation in circuit 2 at Vdd - Vtn, where Vtn is the threshold voltage of NMOS transistor 3, which is approximately 50% of Vdd. The incompletely closed transistor 8 prevents pull-up transistor 5 from opening, which should have pulled the voltage in circuit 2 up to Vdd.

[0045] This problem was solved in the circuit shown in Fig. 3. For this purpose, a buffer consisting of transistors 11-12-14-15 was added to the feedback circuit of the circuit shown in Fig. 2 and described above. The sources of these transistors are connected to Vdd and Vss respectively. Output 10 of the feedback inverter on transistors 8-9 is connected to the gates of the first inverter of the added buffer, consisting of transistors 11-12. Output 13 of the first inverter of the added buffer on transistors 11-12 is connected to the gates of the second inverter of the feedback buffer, consisting of transistors 14-15, whose output in turn is connected to gate 6 of pull-up transistor 5. Thus, the feedback circuit now consists of transistors 8-9-11-12-14-15. The inverter, consisting of transistors 11-12, is optimized in such a way that the voltage at output 10 is sufficient for more complete switching at output 13, which in turn fully switches the inverter from transistors 14-15.

[0046] Thus, if the inverter output 10 on transistors 8-9 has a gentle falling edge that doesn't reach the VSS level, then the output 6 of the added buffer produces a steep falling edge that reaches the VSS level. This allows pull-up transistor 5 to quickly and fully open during the "rise" input switching, ensuring reliable and fast switching at reduced supply voltage.

[0047] This solution ensures the input is tolerant to signals exceeding the supply voltage, with voltages ranging from Vdd to 2 × Vtn. The drawback is an increased signal delay, with a typical supply voltage of Vdd=Vnom±10%, introduced by the additional buffer of transistors 11-12-14-15 in the feedback circuit.

[0048] This drawback was eliminated by adding a PMOS transistor 16 between pull-up transistor 5 and input circuit 2 to the circuit shown in Fig. 3 and described above. This transistor is controlled directly by inverter 8-9, bypassing the additional buffer on transistors 11-12-14-15. This solution is shown in Fig. 4. Transistor 16 has a standard channel length. It is connected by its source to the drain of pull-up transistor 5, by its drain to circuit 2, and by its gate to output 10 of the first inverter on transistors 8-9 in the feedback circuit. Transistor 16 provides the initial pulse to pull circuit 2 up to Vdd, bypassing the buffer on transistors 11-12-14-15. This accelerates the start of the switching process, compensating for the delay time on the additional buffer on transistors 11-12-14-15. This buffer then fully opens pull-up transistor 5 and ensures reliable switching.This dynamic solution, due to the voltage drop on transistor 5, reduces the voltage at the source of transistor 16 below Vdd, which lowers its opening threshold and generally speeds up the switching process of the entire pull-up circuit, consisting of transistors 5 and 16.

[0049] This circuit design is used to design I / O libraries for cells with inputs tolerant to signals exceeding the nominal supply voltage. Simulations demonstrated the operability of these cells in the voltage range up to Vnom - 50% and improved timing characteristics in the typical voltage range of Vnom ±10%. The simulation results are presented in Tables 1-5.

[0050] Brief description of tables with simulation results.

[0051] The results for different simulation angles are shown in the tables:

[0052] Table 1 Simulation results of the angle Vdd=3.0V, Vcore=1.35V, T=125C

[0053] Table 2 Simulation results of the angle Vdd=3.3V, Vcore=1.5V, T=25C

[0054] Table 3 Simulation results of the angle Vdd=3.6V, Vcore=1.65V, T=-60C

[0055] Table 4 Simulation results of the angle Vdd=1.62V, Vcore=1.35V, T=-60C

[0056] Table 5 Simulation results of the angle Vdd=1.62V, Vcore=1.35V, T=125C

[0057] The circuit simulation was carried out using NM-TECH c130g technology with the following models:

[0058] tt - typical models

[0059] ff - fast models

[0060] ss - slow models

[0061]

[0062]

[0063]

[0064]

[0065]

[0066] The input / output cells were simulated, differing from each other only in the input circuit, tolerant to a signal exceeding the nominal supply voltage:

[0067] Classic scheme - the scheme from patent US00531359, shown in Fig. 1

[0068] Improved scheme - improved scheme shown in Fig. 4

[0069] The results of the timing characteristics in the operating mode of the standard input and the Schmitt trigger were compared:

[0070] Sch_Delay_rise - input signal rise delay, input with Schmitt trigger

[0071] Sch_Delay_fall - input signal fall delay, Schmitt trigger input

[0072] Sch_Slope_rise - input signal rise time, input with Schmitt trigger

[0073] Sch_Slope_fall - input signal fall time, Schmitt trigger input

[0074] Delay_rise - input signal rise time delay, standard input

[0075] Delay_fall - input signal fall delay, standard input

[0076] Slope_rise - input signal rise time, standard input

[0077] Slope_fall - input signal rise time, standard input

[0078] Simulation frequency - 10 MHz

[0079] The load capacity of the cell output to the core is 0.1L pF

[0080] Based on the simulation results, we can draw conclusions about the improved circuit presented in the description:

[0081] 1. The cell functionality is maintained at a supply voltage of 1.62V.

[0082] 2. With the standard voltage range of 3.0V…3.6V, there was a significant improvement in the timing characteristics of the I / O cell:

[0083] - Input signal rise time decreased by 20-34%

[0084] - Input signal fall delay decreased by 16-20%

Claims

1. An input / output cell device comprising an input circuit that maintains the operability of the input when a signal exceeds the supply voltage, located after protection against electrostatic discharges, a pass NMOS transistor whose source is connected to the input circuit of the input / output cell, and whose gate is connected through a resistor to the power supply bus Vdd, a pull-up PMOS transistor whose source is connected to the power supply Vdd, the drain is connected to the input circuit of the input / output cell, and an inverter connected to the input circuit of the input / output cell, characterized in that it contains an additional inverter consisting of two transistors whose gates are connected to the input circuit of the input / output cell, wherein the source of the first transistor is connected to the power supply bus Vdd, and the source of the second transistor is connected to the power supply bus Vss, and a buffer consisting of two pairs of transistors whose sources are connected to Vdd and Vss, respectively, is added to the feedback circuit,the output of the feedback inverter on the first and second transistors is connected to the gates of a pair of transistors of the first inverter of the added buffer, the output of the first inverter of the added buffer is connected to the gates of a pair of transistors of the second inverter of the feedback buffer, whose output is connected to the gate of the pull-up PMOS transistor, connected by its source to Vdd, and by its drain to the input circuit of the input-output cell., 2. The device according to claim 1, characterized in that it includes a PMOS transistor connected between the drain of the pull-up PMOS transistor and the input of the input-output cell, connected by its source to the drain of the pull-up PMOS transistor, by its drain to the input circuit of the input-output cell, and by its gate to the output of the first inverter in the feedback circuit.

Images