Energy-efficient channel of interprocessor exchange system

Abstract

FIELD: communication systems.SUBSTANCE: invention relates in particular to high-speed serial data input / output mechanisms. The invention comprises input buffers of virtual channels, a channel operating mode control unit, the inputs of which are the inputs of the device. The Send_check error detection unit, the virtual channel switch on the transmitting side, identical blocks for controlling the transmission and reception of data over one communication line, the power consumption control unit, the virtual channel switch on the receiving side, the Recv_check error detection unit, the virtual channel output buffers, the outputs of which are the outputs of the energy-efficient channel of the interprocessor exchange system. Each data transmission and reception control unit for one communication line contains a buffer for sending data, a data transmission control unit, a data encoding unit, a transceiver, a data decoding unit, a data synchronization unit, a data reception control unit and a buffer for receiving data.EFFECT: reduction in the energy consumption of the channel in some operating modes, provision of the possibility of dividing the channel into two independent ones, the expansion of its functional capabilities, increase in the reliability of receiving and transmitting data, and increase in the channel capacity.1 cl, 1 dwg

Description

[0001] Field of technology to which the invention relates

[0002] The invention relates to the field of communication systems, in particular to high-speed serial data input / output mechanisms.

[0003] Technology Level

[0004] A known device is a fault-tolerant channel of an interprocessor exchange system with programmable and adaptive selection of data transmission lines (RU patent No. 2768535, published on March 24, 2022), comprising virtual channel input buffers, a channel operating mode control unit, a virtual channel switch on the transmitting side, data transmission and reception control units over a single communication line, a virtual channel switch on the receiving side, and virtual channel output buffers. Each data transmission and reception control unit over a single communication line includes a data synchronization unit, a series-connected data sending buffer, a packet transmission control unit, a data encoding unit, a transceiver, a data decoding unit, a packet reception control unit, and a data receiving buffer.

[0005] An interprocessor communication system channel is a set of technical means that ensures data transmission over a communication line between adjacent nodes of a communications network. A communication line is a technical means that ensures the simultaneous bidirectional transmission of a serial data stream. To transmit a data packet (a set of data symbols of a given format), it is written into one of the virtual channel input buffers as an ordered sequence of data symbols (data words). All six buffers are identical and form a first-in-first-out (FIFO) queue. Data is read from the input buffers by a virtual channel switch on the transmitting side, which performs the following functions. The virtual channel switch on the transmitting side determines which virtual channel buffer to read data from. Packets are read from each virtual channel buffer in turn.The virtual channel switch on the transmitting side supports the following operating modes:.

[0006] - x12 mode - data transmission and reception is carried out simultaneously via 12 independent communication lines;

[0007] - x8 mode - data transmission and reception is carried out simultaneously via eight independent communication lines;

[0008] - x4 mode - data transmission and reception is carried out simultaneously via four independent communication lines.

[0009] - x1 mode - data transmission and reception is carried out via one communication line.

[0010] The channel contains twelve identical and independent data transmission and reception control units (DCUs) over a single communication line. Each DCU operates at its own clock frequency for transmitting and receiving data. Each DCU converts data from the sender's clock frequency to the DCU's clock frequency via a send data buffer. The packet transmission control unit generates service indicators for the beginning and end of a packet, as well as two-bit frame synchronization headers (preambles). In the data encoding unit, data scrambling first occurs, i.e., the input data is converted into a pseudo-random sequence. This is necessary to ensure a balance of "0" and "1" in the serial data stream.The 66-bit output bus, accompanied by a true signal, is then converted to the 64-bit input bus of the transceiver (64B / 66B encoding is used). The transceiver converts data from parallel code to a serial stream of symbols and transmits it over the communication network. Upon reception, it reverses the serial data stream to parallel code. The data is then fed to the decoding block. First, frames and their preambles are formed from the received serial data stream. The data synchronization block analyzes the frame synchronization headers and signals the data decoding block to shift the word boundary by one bit.After receiving the start-of-packet symbol, the packet reception control block adds three service flags to each received word and writes the words to the data reception buffer, which is necessary for translating data from the link clock to the receiver clock. The virtual channel switch reads data from the asynchronous receive buffers and determines which virtual channel output buffer to write it to. The virtual channel switch on the receiving side supports x12, x8, x4, and x1 operating modes. The channel mode control block is responsible for switching between x12, x8, x4, and x1 modes. Switching between modes is performed both automatically upon loss of synchronization on the communication lines and manually upon receiving a command.

[0011] The known device is the closest in technical essence to the claimed device and is therefore selected as the closest analogue.

[0012] The disadvantages of the known device are constant power consumption by all channel blocks in all operating modes, transmission of only one data packet at a time over the channel to one recipient, detection of only symbolic errors when receiving data, and the same priority of virtual channel buffers.

[0013] Disclosure of the essence of the invention

[0014] The technical problem being solved is the creation of an energy-efficient channel for an interprocessor exchange system (hereinafter referred to as the channel) with the ability to turn off the power consumption of channel blocks that are not involved in transmitting and receiving data, increased reliability and throughput, the ability to transmit two packets simultaneously over the channel to two recipients, as well as providing support for technology for providing different types of data packets with different service priorities.

[0015] The technical result that the invention is aimed at achieving is a reduction in the energy consumption of the channel in the x8, x4 and x1 operating modes, the provision of the possibility of dividing the channel into two independent ones, the expansion of its functional capabilities, an increase in the reliability of receiving and transmitting data, and an increase in the channel throughput.

[0016] In order to achieve the technical result in the device of the energy-efficient channel of the interprocessor exchange system, containing input buffers of virtual channels, the inputs of which are the corresponding inputs of the device, output buffers of virtual channels, the outputs of which are the corresponding outputs of the device, a channel operation mode control unit, the first output of which is connected to the first inputs of virtual channel switches on the transmitting side and on the receiving side, each output of the virtual channel switch on the transmitting side is connected to the first input of the corresponding control unit for the transmission and reception of data over one communication line, every second input of the virtual channel switch on the receiving side is connected to the first output of the corresponding control unit for the transmission and reception of data over one communication line, wherein each control unit for the transmission and reception of data over one communication line includes a series-connected buffer for sending data,a data transmission control unit, a data encoding unit, a transmitter / receiver, a data decoding unit, a data reception control unit and a buffer for receiving data, the output of which is the first output of the data transmission and reception control unit over one communication line, the input of the buffer for sending data is the first input of the data transmission and reception control unit over one communication line, and the second output of the data decoding unit is connected to the input of the data synchronization unit, what is new is that the virtual channel switches on the transmitting side and on the receiving side are designed with the function of dividing the channel into two independent transmission channels, and the virtual channel switch on the transmitting side is designed with the function of providing different types of data packets with different service priorities, Send_check and Recv_check error detection units, a power consumption management unit are introduced,each output of which is connected to the second input of the corresponding control unit for transmitting and receiving data over one communication line, and the input is connected to the second output of the control unit for channel operating modes, the first input of which is the corresponding input of the device, and each second input is connected to the second output of the corresponding control unit for transmitting and receiving data over one communication line, each input of the Send_check error detection unit is connected to the output of the corresponding input buffer of the virtual channel, and the output is connected to the input of the virtual channel switch on the transmitting side, each output of the Recv_check error detection unit is connected to the input of the corresponding output buffer of the virtual channel, and the input is connected to the output of the virtual channel switch on the receiving side.,

[0017] The new set of essential features allows for a reduction in channel energy consumption, an increase in reliability and throughput, the ability to transmit two packets simultaneously over a channel, and mechanisms to support the technology of providing different types of data packets with different service priorities.

[0018] Providing the ability to turn off the power consumption of channel blocks that are not involved in the current operating mode by using a power consumption management unit reduces the power consumption of the channel.

[0019] Carrying out checks of the checksum and size of transmitted packets on both the transmitting and receiving sides using the introduced Send_check and Recv_check error detection blocks increases the reliability of the channel.

[0020] Providing different types of data packets with different service priorities is achieved by implementing a virtual channel switch on the transmitting side with the function of providing different types of data packets with different service priorities, which increases the channel throughput.

[0021] The ability to transmit two packets simultaneously to two recipients over a channel is achieved by introducing an additional 2x4 channel operating mode, which is supported by virtual channel switches on the transmitting and receiving sides, capable of dividing the channel into two independent transmission channels. This expands the channel's functionality.

[0022] Brief description of drawings

[0023] The figure shows a block diagram of the claimed energy-efficient channel of the interprocessor exchange system.

[0024] The energy-efficient channel of the interprocessor exchange system contains input buffers of virtual channels 1.0, 1.1-1.5, the inputs of which are the corresponding inputs of the energy-efficient channel of the interprocessor exchange system, output buffers of virtual channels 15.0, 15.1-15.5, the outputs of which are the corresponding outputs of the device, error detection units Send_check 2 and Recv_check 14, virtual channel switches on the transmitting side 3 and on the receiving side 13, channel operating mode control unit 16, power consumption control unit 17.

[0025] The first output of the channel operation mode control unit 16 is connected to the first inputs of the virtual channel switches on the transmitting side 3 and on the receiving side 13. Each output of the virtual channel switch on the transmitting side 3 is connected to the first input of the corresponding data transmission and reception control unit over one communication line 4.0 (4.1-4.11). Every second input of the virtual channel switch on the receiving side 13 is connected to the first output of the corresponding data transmission and reception control unit over one communication line 4.0 (4.1-4.11).

[0026] Each single link data transmission and reception control unit 4.0 (4.1-4.11) includes a 5.0 (5.1-5.11) data sending buffer, a 6.0 (6.1-6.11) data transmission control unit, a 7.0 (7.1-7.11) data encoding unit, an 8.0 (8.1-8.11) transmitter / receiver, a 9.0 (9.1-9.11) data decoding unit, a 11.0 (11.1-11.11) data reception control unit and a 12.0 (12.1-12.11) data receiving buffer, the output of which is the first output of the single link data transmission and reception control unit 4.0 (4.1-4.11). The input of the data sending buffer 5 is the first input of the control unit for transmitting and receiving data over one communication line 4.0 (4.1-4.11), and the second output of the data decoding unit 9 is connected to the input of the data synchronization unit 10.0 (10.1-10.11).

[0027] Each output of the power consumption management unit 17 is connected to the second input of the corresponding data transmission and reception control unit over one communication line 4.0 (4.1-4.11), and the input is connected to the second output of the channel operation mode control unit 16, the first input of which is the corresponding input of the device. Each second input of the channel operation mode control unit 16 is connected to the second output of the corresponding data transmission and reception control unit over one communication line 4.0 (4.1-4.11). Each input of the Send_check error detection unit 2 is connected to the output of the corresponding input buffer of the virtual channel 1.0 (1.1-1.5), and the output is connected to the input of the virtual channel switch 3 on the transmitting side. Each output of the Recv_check error detection block 14 is connected to the input of the corresponding output buffer of the virtual channel 15.0 (15.1-15.5), and the input is connected to the output of the virtual channel switch 13 on the receiving side.

[0028] Including, the input buffers of virtual channels 1.0, 1.1-1.5 are intended for temporary storage of data packets for their subsequent transmission over the channel. The Send_check error detection block 2 records the arrival of a packet in the channel for transmission, and also calculates and compares the checksum and packet size. The switch 3 of virtual channels on the transmitting side reads packets from the input buffers of virtual channels 1.0, 1.1-1.5 and writes them to asynchronous buffers for sending data 5.0-5.11, corresponding to the channel operating mode. Also, the switch 3 of virtual channels on the transmitting side is designed with the functions of dividing the channel into two independent channels and providing different types of data packets with different service priorities. The energy-efficient channel of the interprocessor exchange system contains twelve identical and independent blocks 4.0, 4.1-4.11 for controlling the transmission and reception of data over one communication line. Each control block 4.0 (4.1-4.11) operates at its own clock frequencies for transmitting and receiving data. Each control unit for transmitting and receiving data over one communication line 4.0 (4.1-4.11) includes a buffer 5.0 (5.1-5.11) for sending data, which is necessary for transferring data from the clock frequency of the sender to the clock frequency of the control unit for transmitting and receiving data over one communication line 4.0 (4.1-4.11). The data transmission control unit 6.0 (6.1-6.11) is designed to read packets from the buffer 5.0 (5.1-5.11) for sending data and adding a header to each transmitted frame. The data encoding unit 7.0 (7.1-7.11) converts data into a pseudo-random sequence. The transmitter / receiver 8.0 (8.1-8.11) converts data from a parallel code into a serial stream of symbols and transmits it over the communication network. Upon reception, it performs the reverse transformation of the serial data stream into parallel code. Block 9.0 (9.1-9.11) data decoding is designed to convert the input scrambled code into the original data format. Data synchronization block 10.0 (10.1-10.11) analyzes frame headers and word-by-word alignment of received data. Data reception control block 11.0 (11.1-11.11) is designed to analyze the received data, set the operability signal of block 4.0 (4.1-4.11) for controlling the transmission and reception of data over one communication line and write packets into buffer 12.0 (12.1-12.11) for receiving data. Data reception buffer 12.0 (12.1-12.11) is designed to translate words from the clock frequency of block 4.0 (4.1-4.11) for controlling the transmission and reception of data over one communication line to the clock frequency of the receiver. Switch 13 of virtual channels on the receiving side reads packets from buffers 12.0 (12.0-12.11) to receive data corresponding to the channel operating mode, and writes them into output buffers 15.0, 15.1-15.5 of virtual channels.Switch 13 of the virtual channels on the receiving side is also configured to split the channel into two independent channels. Error detection unit 14, Recv_check, records packet reception from the channel and calculates and compares the checksum and size of the received packet. Output buffers of virtual channels 15.0, 15.1-15.5 are designed for temporary storage of received data packets. Channel mode control unit 16 is designed to select and switch channel operating modes. Power consumption control unit 17 is designed to reduce channel power consumption.

[0029] Implementation of the invention

[0030] The energy-efficient channel of the interprocessor communication system operates as follows.

[0031] The energy-efficient channel of the interprocessor exchange system ensures data transmission over several serial communication lines, aggregating their bandwidth, and also allows multiplexing data streams from several virtual channels into one physical channel, dynamically adjusting its power consumption.

[0032] To transmit a data packet on the transmitting side, the data packet is written into one of the input buffers of virtual channels 1.0 (1.1-1.5) in 515-bit data words, where 512 bits are useful data and three bits are service flags for the beginning of the packet, the end of the packet, and an error. All six buffers 1.0, 1.1-1.5 represent a queue with the "first in - first out" (FIFO) organization, have the same parameters of the data bus width and buffer depth, but differ in purpose. Input buffers 1.0-1.1 are used to transmit packets with useful data, 1.2-1.3 - for transmitting service packets, and 1.4-1.5 - for multicast broadcasts. The buffer of each virtual channel 1.0 (1.1-1.5) has a signal that is set to "1" when there is room left in it for only one data packet. This signal is intended to prevent buffer overflows 1.0 (1.1-1.5).

[0033] Data is read from buffers 1.0 (1.1-1.5) by the switch of 3 virtual channels on the transmit side. During the reading process, the data passes through error detection unit 2 (Send_check), which detects the arrival of a packet on the transmission channel and also performs the following functions:

[0034] —packet checksum calculation and comparison. This data integrity checking algorithm detects all single errors, double errors, and odd-bit errors. The checksum calculation is implemented using a linear-feedback shift register with serial data input.

[0035] - Counts the number of words in a packet and compares it with the packet size specified in the header.

[0036] If the packet checksum specified in it does not match the calculated one, or the packet size specified in its header does not match the size of the received data, a corresponding error is raised, which is processed at a higher level.

[0037] The 3 virtual channel switch on the transmitting side performs the following functions:

[0038] - switching of data coming from the input buffers of virtual channels 1.0 (1.1-1.5);

[0039] - formatting data words depending on the channel operating mode;

[0040] - writing to asynchronous buffers 5.0 (5.0-5.11) to send data corresponding to the channel operating mode;

[0041] - processing information about the state of the output buffers of virtual channels 15.0, 15.1-15.5, received via the reverse data transmission path.

[0042] The switch of 3 virtual channels on the transmitting side determines from which buffer of virtual channels 1.0 (1.1-1.5) to read the data. Buffers of virtual channels 1.0, 1.1-1.5 have different priorities for reading data. The highest priority is given to input buffers 1.2-1.3, since they transmit service packets of short length. The next highest priority is given to buffers 1.4-1.5, since they are used for multicast transmissions. After transmitting three consecutive packets, the priority is reset. Thus, the technology of providing different types of data packets with different service priorities is supported. If the data is located in only one buffer of virtual channels 1.0 (1.1-1.5), they will be read from it out of turn. The data packet begins to be read if the corresponding output buffer of virtual channel 15.0 (15.0-15.5) of the receiver is not full. When receiving information about filling the required buffer of virtual channels 15.0 (15.0-15.5) The 3rd virtual channel switch on the transmitting side stops the process of transmitting data packets over this virtual channel. Data transmission is resumed when the corresponding buffer 15.0 (15.0-15.5) is released. The 3rd virtual channel switch on the transmitting side supports the following operating modes:

[0043] - x12 mode - data transmission and reception is carried out simultaneously via 12 independent communication lines;

[0044] - x8 mode - data transmission and reception is carried out simultaneously via eight independent communication lines;

[0045] - x4 mode - data transmission and reception is carried out simultaneously via four independent communication lines.

[0046] - x1 mode - data transmission and reception is carried out via one communication line.

[0047] - 2x4 mode - dividing the channel into two independent channels, in each of which data transmission and reception is carried out simultaneously by four communication lines.

[0048] In the x12 channel mode, data is transmitted simultaneously over twelve communication lines. To transmit data in the x12 mode, the 3 virtual channel switch on the transmitting side first reads the first word of the data packet. Since the size of the payload of the read word is 512 bits, and the total size of the payload of the twelve communication lines is 768 bits, then at this clock cycle, no writing to buffers 5.0, 5.1-5.11 for sending data occurs, and the second word of the data packet is read. Then the first data word and the lower 256 bits of the second data word are written to buffers 5.0, 5.1-5.11. The upper 256 bits of the second data word are stored in a special register of the 3 virtual channel switch on the transmitting side. At the next clock cycle, the third word of the data packet is read, and the upper 256 bits of the second data word and the third word of the packet are written to buffers 5.0, 5.1-5.11. Then the process is repeated.If the number of words in a data packet is not a multiple of three, additional data is transmitted over the remaining communication lines and discarded at the receiving end. The prepared data is written to twelve asynchronous buffers 5.0, 5.1-5.11 as 70-bit words. The payload data is appended to the virtual channel number from which the data packet was read and three service flags. The payload data occupies bits 0 through 63. Bit 64 is the start-of-packet flag, bit 65 is the end-of-packet flag, bit 66 is the error flag, and bits 69-67 are the virtual channel number from which the data packet was read.

[0049] In x8 channel mode, data is transmitted simultaneously over eight communication lines. These eight communication lines can be selected either automatically, depending on the presence of synchronization on them, or forced upon receipt of a command by channel mode control unit 16. To transmit data in x8 mode, the 3 virtual channel switch first reads the first word of the data packet. Since the payload size of the read word is 512 bits, and the total payload size of the eight communication lines is also 512 bits, the read word is immediately written to eight data transmission buffers. The process is then repeated until the last word of the data packet. The prepared data is written to eight asynchronous data transmission buffers in 70-bit words. The payload data is accompanied by the number of the virtual channel from which the data packet was read and three service flags. The payload data occupies bits 0 through 63.Bit 64 of the word is the packet start flag, 65 is the packet end flag, 66 is the error flag, 69-67 are the number of the virtual channel from which the packet was read.

[0050] In x4 channel mode, data is transmitted simultaneously over four communication lines. The selection of these four communication lines can be performed either automatically, depending on the presence of synchronization on them, or forced upon receipt of a command by the channel mode control unit 16. To transmit a packet in x4 mode, the switch of 3 virtual channels first reads the first word of the data packet. Since the size of the payload of the read word is 512 bits, and the total size of the payload of the four communication lines is 256 bits, the lower 256 bits of the word are written first, then the upper 256 bits. Then the second word of the data packet is read. The process is then repeated until the last word of the data packet. The prepared data is written to four asynchronous data transmission buffers in 70-bit words. The number of the virtual channel from which the data packet was read and three service flags are appended to the payload. The payload occupies bits 0 through 63.Bit 64 of the word is the packet start flag, 65 is the packet end flag, 66 is the error flag, 69-67 are the number of the virtual channel from which the packet was read.

[0051] In channel x1 mode, data is transmitted over a single communication line. This communication line can be selected either automatically, depending on the presence of synchronization on it, or forced upon receipt of a command by channel mode control unit 16. To transmit a packet in the x1 mode, the switch of 3 virtual channels first reads the first word of the data packet. Since the size of the payload of the read word is 512 bits, and the total size of the payload of one communication line is 64 bits, the read word is written in eight clock cycles. Then the second word of the data packet is read. The process is then repeated until the last word of the packet. The prepared data is written to a single asynchronous buffer for sending data in 70-bit words. The number of the virtual channel from which the data packet was read and three service flags are appended to the payload. The payload occupies bits 0 through 63.Bit 64 of the word is the packet start flag, 65 is the packet end flag, 66 is the error flag, 69-67 are the number of the virtual channel from which the packet was read.

[0052] In 2x4 mode, the channel is divided into two independent channels, each operating in x4 mode. The first channel is considered ready for operation when all 8.0-8.3 transmitters / receivers have successfully synchronized. Then, data is transmitted via this channel only to the data transmission and reception control units over a single 4.0-4.3 communication line. The second channel is considered ready for operation when all 8.4-8.7 transmitters / receivers have successfully synchronized. Then, data is transmitted via this channel only to the data transmission and reception control units over a single 4.4-4.7 communication line. If all 8.0-8.3 transmitters / receivers have not synchronized, the first channel is considered inoperative. If all 8.4-8.7 transmitters / receivers have not synchronized, the second channel is considered inoperative. The first and second channels can operate either individually or simultaneously, independently of each other.Data transmission and reception control units for single communication lines 4.8-4.11 do not participate in the data transmission and reception process in this operating mode and are in the off state. The first channel receives data for transmission only from the buffers of virtual channels 1.0-1.2, and the second channel receives data only from the buffers of virtual channels 1.3-1.5. Data transmission in each channel is identical to the x4 operating mode described above.

[0053] Each data transmission and reception control unit for one communication line 4.0 (4.1-4.11) operates as follows. An asynchronous data sending buffer 5.0 (5.1-5.11) is used to transfer data from the clock frequency of the data sender to the clock frequency of the data transmission and reception control unit for one communication line 4.0 (4.1-4.11). Data is written to the buffer 5.0 (5.1-5.11) by the switch of 3 virtual channels on the transmitting side at the operating frequency of the data sender, and is read by the data transmission control unit 6.0 (6.1-6.11) when the communication line is clear.

[0054] When the first word of a data packet appears in buffer 5.0 (5.1-5.11), data transmission control block 6.0 (6.1-6.11) transmits a packet start service character. Along with this character, the number of the virtual channel from which the packet was read is transmitted. The packet is then transmitted, and each word is checked for the end-of-packet indicator. After the last word of the packet is read from buffer 5.0 (5.1-5.11), a check is made for errors in the packet. If there are no errors, and no errors occurred during packet transmission, then the end-of-packet indicator is transmitted to the channel without errors. Otherwise, the end-of-packet indicator with errors is transmitted.

[0055] A header is transmitted with each data word (frame). The frame header (preamble) defines the type of data being transmitted. There are two frame types: a data frame (preamble = "01") and a control information / data frame (preamble = "10"). Preambles "00" and "11" are considered erroneous, and upon receipt of such a preamble, a frame synchronization error is detected by data synchronization unit 10.

[0056] Data transmission is stopped upon receiving information via the reverse channel about the fullness of the buffers used in the current operating mode for receiving data 12.0, 12.0-12.11. Data transmission is resumed upon receiving information about the emptying of the buffers used in the current operating mode for receiving data 12.0, 12.0-12.11. During data transmission, the state of the buffers for receiving data 12.0, 12.0-12.11 is constantly analyzed. If the state of the buffers 12.0, 12.0-12.11 changes, the corresponding information is transmitted via the channel.

[0057] Data transmission control block 6.0 (6.1-6.11) passes words to the input of data encoding block 7.0 (7.1-7.11). First, the data is scrambled, i.e. the input data is converted into a pseudo-random sequence. This is necessary to ensure a balance of "0" and "1" in the serial data stream. Frame preambles are not scrambled and are used by data synchronization block 10.0 (10.1-10.11) to determine frame boundaries in the received serial data stream. The use of a scrambler does not guarantee a uniform distribution of "0" and "1" in the serial stream, but the selection of "01" and "10" as allowed frame preambles guarantees that at least one transition from "0" to "1" or from "1" to "0" occurs no less than every 66 bit intervals. The 66-bit scrambler output bus, accompanied by a truth signal, is then converted into the 64-bit 8.0 (8.1-8.11) transmitter / receiver input bus.Since a two-bit preamble is transmitted along with 64-bit frames, a pause of one clock cycle is made every 32 cycles to avoid data loss.

[0058] The 7.0 (7.1-7.11) encoding unit transmits data to the 8.0 (8.1-8.11) transmitter / receiver input. The 8.0 (8.1-8.11) transmitter / receiver converts data from parallel code into a serial character stream and transmits it over the communication network. Upon reception, it reverses the serial data stream into parallel code.

[0059] Next, the data is fed to the input of data decoding block 9.0 (9.1-9.11). First, frames and their preambles are formed from the received serial data stream. Based on the signal established by data synchronization block 10.0 (10.1-10.11), the frame boundary is shifted by one bit. Then, the input scrambled code is converted to the original data format. The data preamble does not require descrambling and is used by data synchronization block 10.0 (10.1-10.11) to determine frame boundaries.

[0060] Data Sync Block 10.0 (10.1-10.11) analyzes frame sync headers and sets a signal to Data Decoding Block 9.0 (9.1-9.11) to shift the word boundary by one bit. Valid headers are "01" and "10", invalid headers are "00" or "11".

[0061] Data reception control block 11.0 (11.1-11.11) receives data from data decoding block 9.0 (9.1-9.11). After receiving the service symbol of the beginning of the packet, control block 11.0 (11.1-11.11) switches to the packet reception mode, adds three service flags to each received word and writes the words to the asynchronous buffer 12.0 (12.1-12.11) for data reception. The virtual channel number is added to each word, indicating which virtual channel buffer 15.0 (15.0-15.5) to write the received packet. To align the data, the switch block 13 of virtual channels on the receiving side adds its number in the data packet and the packet number to each word. If errors occurred during packet reception or an end-of-packet indicator with errors was received, an error flag is added to the last word of the packet along with the end-of-packet service flag. After establishing synchronization of the communication line and receiving the receiver's synchronization information from the channel, block 11.0 (11.1-11.11) data reception control sets the readiness indicator of the communication line for data transmission and reception.

[0062] Asynchronous buffer 12.0 (12.1-12.11) for data reception is used to transfer data from the clock frequency of block 4.0 (4.1-4.11) for data transmission and reception control over one communication line to the clock frequency of the data receiver. Data is written to buffer 12.0 (12.1-12.11) by block 11.0 (11.1-11.11) for data reception control at the frequency of the communication line, and is read by switch 13 of virtual channels on the receiving side at the frequency of the data receiver.

[0063] The 13 virtual channel switch on the receiving side performs the following functions:

[0064] - switching of data coming from asynchronous buffers 12.0, 12.1-12.11;

[0065] - formatting data words depending on the channel operating mode;

[0066] - writing data to the output buffers of virtual channels 15.0, (15.1-15.5);

[0067] - word-by-word alignment of received data from asynchronous buffers 12.0, 12.1-12.11;

[0068] Virtual channel switch 13 reads data from asynchronous receive buffers 12.0, 12.1-12.11 and determines which output buffer of virtual channels 15.0, 15.1-15.5 should receive it. Reading of a data packet begins when data with the start-of-packet indicator appears in all buffers 12.0, 12.1-12.11 corresponding to the operating mode. The number of each word and the packet number are checked. If the data words have different numbers during reading, virtual channel switch 13 sets a signal that will reset the channel unit, since a hardware error has occurred in the channel. If a symbol error occurs on one of the communication lines during data reception, the end-of-packet indicator with an error will be written to the corresponding output buffer of virtual channels 15.0 (15.1-15.5). The 13 virtual channel switch on the receiving side supports the operating modes x12, x8, x4, x1 and 2x4.

[0069] To receive data in the x12 channel mode, the 13 virtual channel switch first reads words simultaneously from twelve data reception buffers 12.0, 12.1-12.11. Since the size of the useful read data is 768 bits, and the size of the input bus of the virtual channel buffer is 512 bits, the lower 512 bits of the word are written first, and the upper 256 bits of the word are stored in a special register of the 13 virtual channel switch on the receiving side. Then the second word of the packet is read and the upper 256 bits of the first word and the lower 256 bits of the second word are written to the buffer, and the upper 512 bits of the second word are stored in a special register of the 13 virtual channel switch on the receiving side. Then no reading occurs, and 512 bits of the second word are written. Then the process is repeated until the last word of the packet. The prepared data are written to the synchronous buffers of virtual channels 15.0, 15.1-15.5 data words of 515 bits in length, where 512 bits are useful data and three bits are service flags for the beginning of the packet, the end of the packet, and errors.

[0070] To receive a packet in x8 channel mode, virtual channel switch 13 first reads the first word of the packet from eight data reception buffers 12.0, 12.1-12.11. Since the size of the useful read data is 512 bits, and the size of the virtual channel buffer input bus is also 512 bits, the read word is immediately written to the virtual channel buffer. The process is then repeated until the last word of the packet. The prepared data is written to synchronous buffers of virtual channels 15.0, 15.1-15.5 as 515-bit data words, where 512 bits are the useful data and three bits are the service flags for the beginning of the packet, the end of the packet, and the error.

[0071] To receive a packet in the x4 channel mode, the switch of 13 virtual channels first reads the first word of the packet from the corresponding four buffers 12.0 (12.1-12.11) for receiving data. Since the size of the useful data of the read word is 256 bits, and the size of the data bus of the output buffers of virtual channels 15.0, 15.1-15.5 is 512 bits, the writing does not occur immediately and the second word of the packet is read. Then the first and second words are written to the virtual channel buffer. Then the process is repeated. The prepared data is written to the corresponding synchronous buffers 15.0, 15.1-15.5 of the virtual channel in data words of 515 bits, where 512 bits are the useful data and three bits are the service flags of the beginning of the packet, the end of the packet and the error.

[0072] To receive a packet in the x1 operating mode, the switch of 13 virtual channels first reads the first word of the packet from buffer 12.0 (12.1-12.11) for receiving data of the corresponding control block 4.0 (4.1-4.11). Since the size of the useful data of the read word is 64 bits, and the size of the input bus of the virtual channel buffer is 512 bits, the writing does not occur immediately, and seven more words of the packet are read. Then the first word is written to the output buffer of virtual channels 15.0 (15.1-15.5). Then the process is repeated. The prepared data is written to the synchronous buffers of virtual channels 15.0, 15.1-15.5 in data words of 515 bits, where 512 bits are useful data and three bits are service flags of the beginning of the packet, the end of the packet and the error.

[0073] In 2x4 mode, the channel is divided into two independent channels, each operating in x4 mode. The first channel is considered ready for operation when all 8.0-8.3 transceivers have successfully synchronized. Then, data is received from this channel only from the data transmission and reception control units over one 4.0-4.3 communication line. The second channel is considered ready for operation when all 8.4-8.7 transceivers have successfully synchronized. Then, data is received from this channel only from the data transmission and reception control units over one 4.4-4.7 communication line. If all 8.0-8.3 transceivers have not synchronized, the first channel is considered inoperative. If all 8.4-8.7 transceivers have not synchronized, the second channel is considered inoperative. The first and second channels can operate either individually or together, independently of each other. Control units for transmission and reception of data over one communication line 4.8-4.11 do not participate in the data transmission and reception process in this operating mode and are in the off state. The first channel writes received data only to the output buffers of virtual channels 1.0-1.2, and the second channel only to the output buffers of virtual channels 1.3-1.5. Data reception in each channel is identical to the x4 operating mode described above.

[0074] The selection of the output buffer of virtual channel 15.0 (15.1-15.5) for writing data on the receiving side is performed in the switch block of 13 virtual channels. Therefore, the number of the virtual channel from which the packet was read is transmitted along with each packet. On the receiving side, according to this number, each packet is written to the corresponding buffer of virtual channel 15.0 (15.1-15.5). All six buffers 15.0, 15.1-15.5 represent a first-in-first-out (FIFO) queue and have the same data bus width and buffer depth.

[0075] During the process of writing to the output buffers of virtual channels 15.0, 15.1-15.5, the data passes through the Recv_check error detection block 14, which records the receipt of a packet from the channel and also performs the following functions:

[0076] —packet checksum calculation and comparison. This data integrity checking algorithm detects all single errors, double errors, and odd-bit errors. The checksum calculation is implemented using a linear-feedback shift register with serial data input.

[0077] - Counts the number of words in a packet and compares it with the packet size specified in the header.

[0078] If the packet checksum specified in it does not match the calculated one, or the packet size specified in its header does not match the size of the received data, a corresponding error is raised, which is processed at a higher level.

[0079] Information about the status of virtual channel buffers 15.0, 15.1-15.5 is transmitted after each packet, and if it changes, directly during packet transmission. If the space in buffer 15.0 (15.1-15.5) is exhausted, data transmission over this virtual channel is stopped until this buffer 15.0 (15.1-15.5) is freed. This protects against possible data loss due to insufficient space in the virtual channel buffers on the receiving side 15.0 (15.1-15.5).

[0080] Block 16 of the channel operating mode control is responsible for switching between the x12, x8, x4, x1, or 2x4 modes. By default and after the reset procedure, the channel is set to the x12 mode. If the number of synchronized (active) communication lines is less than twelve, but greater than or equal to eight, then a transition to the x8 mode is performed. If the number of active communication lines is less than eight, but greater than or equal to four, then a transition to the x4 mode is performed. If the number of active communication lines is less than four, but there is at least one active communication line, then a transition to the x1 mode is performed. Switching between modes is performed both automatically when synchronization on the communication lines is lost, and forcedly, upon receiving a command by block 16. Any combination of communication lines corresponding in number to the required operating mode can be used, provided that these communication lines are active. Transition to a mode with a larger number of communication lines can only be performed after the reset procedure.Switching to 2x4 mode is carried out only upon receiving a command.

[0081] The power consumption management unit 17 receives information from the channel operation mode control unit 16 about the current operation mode and the single link data transmission and reception control units 4.0, 4.1-4.11 used in this mode. After that, the power consumption management unit 17 sets a power consumption shutdown signal to the single link data transmission and reception control units 4.0, 4.1-4.11, which are not used in this operation mode. Since almost all the channel power consumption is performed by these units 4.0, 4.1-4.11, then in the x8 and 2x4 operation modes, the channel power consumption is reduced by 34%, in the x4 mode - by 67%, in the x1 mode - by 92%.

[0082] The energy-efficient channel of the interprocessor communication system has been tested and demonstrated its operability on breadboards with integrated programmable logic integrated circuits, as well as on hardware modules of the interprocessor communication system with very large-scale integrated circuits.

[0083] Using this device as part of an interprocessor communication system increases throughput by introducing a mechanism to support technology that provides different service priorities for different types of data packets. System reliability has also been increased by introducing the Send_check and Recv_check error detection blocks. The introduction of a power management block has reduced channel power consumption. The introduction of a 2x4 channel mode allows it to be split into two independent channels, allowing two packets to be transmitted simultaneously to two recipients.

Claims

An energy-efficient channel of an interprocessor exchange system comprising input buffers of virtual channels, the inputs of which are the corresponding inputs of the device, output buffers of virtual channels, the outputs of which are the corresponding outputs of the device, a channel operating mode control unit, the first output of which is connected to the first inputs of virtual channel switches on the transmitting side and on the receiving side, each output of the virtual channel switch on the transmitting side is connected to the first input of the corresponding control unit for the transmission and reception of data over one communication line, every second input of the virtual channel switch on the receiving side is connected to the first output of the corresponding control unit for the transmission and reception of data over one communication line, wherein each control unit for the transmission and reception of data over one communication line includes a series-connected buffer for sending data, a data transmission control unit, a data encoding unit,a transmitter / receiver, a data decoding unit, a data reception control unit and a data reception buffer, the output of which is the first output of the data transmission and reception control unit over one communication line, the input of the buffer for sending data is the first input of the data transmission and reception control unit over one communication line, and the second output of the data decoding unit is connected to the input of the data synchronization unit, characterized in that the virtual channel switches on the transmitting side and on the receiving side are configured to divide the channel into two independent transmission channels, and the virtual channel switch on the transmitting side is configured to provide different types of data packets with different service priorities, additionally introduced are Send_check and Recv_check error detection units, a power consumption control unit, each output of which is connected to the second input of the corresponding data transmission and reception control unit over one communication line,and the input is connected to the second output of the channel operating mode control unit, the first input of which is the corresponding input of the device, and each second input is connected to the second output of the corresponding data transmission and reception control unit over one communication line, each input of the Send_check error detection unit is connected to the output of the corresponding input buffer of the virtual channel, and the output is connected to the input of the virtual channel switch on the transmitting side, each output of the Recv_check error detection unit is connected to the input of the corresponding output buffer of the virtual channel, and the input is connected to the output of the virtual channel switch on the receiving side.

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