Device for squaring binary matrix

Abstract

FIELD: computing technology.SUBSTANCE: invention which can be used to square a binary matrix of size n × n elements. The claimed device contains first, second and third AND elements, first, second and third shift registers, a block of matrix coefficients, a trigger, the block of matrix coefficients consists of n × n storage blocks, groups of OR elements, each of the storage blocks contains an AND element, a first group of AND elements, a trigger, a fourth AND element, a NOT element, an OR element, a second group of OR elements, implemented in a pyramidal pattern.EFFECT: reducing the time costs when squaring a binary matrix of size n × n elements.1 cl, 3 dwg, 1 tbl

Description

[0001] The invention relates to computing technology and can be used to square a binary matrix of n × n elements.

[0002] A device for squaring a binary matrix is ​​known (RU Patent No. 2744239. Device for squaring a binary matrix, filed 07 / 05 / 2020, published 03 / 04 / 2021, Bulletin No. 7), comprising a first and second inverter, a first, second and third shift registers, a first, second and third delay elements, a first, second, third and fourth AND elements, a first, second and third switches; a first, second and third OR element, a two-stage trigger, the matrix coefficient block contains n × n storage blocks and a group of OR output elements, each of the storage blocks contains an AND element, a group of AND elements, a group of OR elements, a trigger [1].

[0003] The disadvantage of this device is the large time required to perform the operation of squaring the matrix.

[0004] The closest in technical essence to the claimed invention is a device for multiplying binary matrices (Patent of the Russian Federation for Utility Model No. 193927, class G06F 15 / 00, filed on June 26, 2019, published on November 21, 2019, Bulletin No. 33), containing a matrix of n × n operational blocks (where n is the size of the square matrices being multiplied), first and second blocks of matrix coefficients, a shift register, a group of n two-stage registers, each of the blocks of matrix coefficients contains n × n storage blocks and a group of n output OR elements, each of the storage blocks contains an AND element, a group of n AND elements, a group of n OR elements, each operational block includes the first, second, third trigger, the first, second, third AND elements, the first, second OR elements, inverter, each storage block contains a trigger, a group of AND elements, and a group of OR elements [2].

[0005] The disadvantage of this device is its high hardware complexity.

[0006] The technical objective of the proposed device is to reduce the time costs when implementing the operation of squaring a binary matrix of n × n elements.

[0007] The technical problem is solved in that in a device containing first, second and third AND elements, first, second and third shift registers, a block of matrix coefficients, a trigger, the block of matrix coefficients consists of n × n storage blocks, a group of OR elements, each of the storage blocks contains an AND element, the first group of AND elements, a trigger, wherein the first synchronization input is connected to the synchronization input of the first shift register, the output of which is connected to the first input of the row address when reading the block of matrix coefficients, to the third input of the row address when reading the block of matrix coefficients, to the seventh input of the row address when writing the block of matrix coefficients, and the n-th digit of the output of the first shift register is connected to the first input of the first AND element, a unit value is supplied to the least significant digit of the information input of the first shift register, zero values ​​are supplied to the remaining (n - 1) digits,the load input of the first shift register is connected to the second synchronization input, the first synchronization input is connected to the second input of the first AND element, the output of which is connected to the synchronization input of the second shift register, the output of which is connected to the second input of the column address when reading the block of matrix coefficients, to the sixth input of the column address when reading the block of matrix coefficients and to the eighth input of addresses when writing the block of matrix coefficients, a value of one is supplied to the least significant bit of the information input of the second shift register, zero values ​​are supplied to the remaining (n - 1) bits, the load input of the second shift register is connected to the second synchronization input, the third synchronization input is connected to the synchronization input of the third shift register, the output of which is connected to the fourth input of the column addresses when reading the block of matrix coefficients, to the fifth input of the row addresses when reading the block of matrix coefficients,a value of one is supplied to the least significant bit of the information input of the third shift register, zero values ​​are supplied to the remaining (n - 1) bits, the load input of the third shift register is connected to the fourth synchronization input, the fifth synchronization input is connected to the first input of the second AND element, the output of which is connected to the tenth input of the write synchronization input of the matrix coefficient block, the second input of the second AND element is connected to the output of the trigger, the first output of the matrix coefficient block is connected to the results unloading output, the second output of the matrix coefficient block is connected to the first input of the third AND element, the second input of which is connected to the third output of the matrix coefficient block, the output of the third AND element is connected to the information input of the trigger, the reset input of the trigger is connected to the sixth synchronization input, the set input of the trigger is connected to the seventh synchronization input, and the synchronization input of the trigger is connected to the eighth synchronization input,the sync input of the matrix coefficient block is connected to the sync input of the write of each of the n × n storage blocks, the k-th input (where, ) as part of the group of read line addresses of the matrix coefficient block is connected to the input of the read line addresses of the (i, k)-th storage block (where ), the k-th input (where ) as part of the group of read column addresses of the matrix coefficient block is connected to the input of the read column addresses of the (k, i)-th storage block (where , ), the k-th input (where ) as part of the group of addresses of recording rows of the matrix coefficient block 9 is connected to the input of the addresses of recording rows of the (i, k)-th storage block (where ), the k-th input (where ) as part of the group of column addresses of the recording block of matrix coefficients is connected to the input of the column addresses of the recording block of the (k, i)-th storage block (where , ), the data input of the matrix coefficient block record is connected to the data input of the record of each of the n × n storage blocks, the k-th output (where ) as part of the data output group for the next row of the (n, p)-th storage block (where ) is connected to the p-th input of the k-th element of the first group of elements of the OR block of matrix coefficients, the output of the k-th (where ) of the element of the group of OR elements of the matrix coefficient block is connected to the k-th output as part of the group of outputs of the matrix coefficient block, as part of each of the storage blocks, the first input of the AND element of the storage block is connected to the input of the column address of the record of the storage block, the write clock signal is supplied to the second input of the AND element of the storage block, the third input of the AND element of the storage block is connected to the input of the row address of the record of the storage block, the information input of the trigger is connected to the input of the record data of the storage block, and the clock input of the trigger is connected to the output of the AND element, the output of the trigger is connected to the first input of each of the elements of the group of AND elements, the output of each k-th (where ) of the element of the group of AND elements is connected to the k-th digit of the data output, the second input of each k-th (where ) of the element of the group of elements AND is connected to the i-th digit of the input of the read line address of the storage block, and the third input of each k-th (where ) of the AND element is connected to the i-th digit of the input of the read column address of the storage block, a fourth AND element, a NOT element, an OR element, a second group of OR elements are additionally introduced in the matrix coefficient block, wherein the data recording input is connected to the first input of the fourth AND element, the output of which is connected to the first input of the OR element, the output of which is connected to the ninth input of the data recording of the matrix coefficient block, the second input of the OR element is connected to the output of the NOT element, the input of which is connected to the initialization input, the second input of the fourth AND element is connected to the initialization input, signals with (i, j)-x outputs storage block, (where , ) are fed to the j-th input of the n-input (i, k)-th element of the second group of OR elements of the matrix coefficient block, the outputs of the (i, k)-th elements of the second group of OR elements (where , ) are fed to the i-th input of the n-input k-th element of the first group of OR elements, the output of the k-th (where ) of the element of the first group of elements OR of the matrix coefficient block is connected to the k-th output as part of the group of outputs of the matrix coefficient block.

[0008] Fig. 1 shows the functional diagram of the device; Fig. 2 shows the diagram of the matrix coefficient block; Fig. 3 shows the diagram of the storage block.

[0009] The device for squaring a binary matrix (Fig. 1) contains the first 1, the second 2 AND elements, the NOT element 3, the first 4, the second 5 and the third 6 shift registers, the OR element 7, the third AND element 8, the matrix coefficient block 9, the fourth AND element 10, the trigger 11, the data write enable input 12, the initialization input 13, the first synchronization input 14, the second synchronization input 15, the third synchronization input 16, the fourth synchronization input 17, the fifth synchronization input 18, the sixth synchronization input 19, the seventh synchronization input 20, the eighth synchronization input 21, the output 22 for unloading the results of multiplication (matrix elements), the matrix coefficient block 9 (Fig. 2) contains a group of inputs 23 as row addresses when reading from the matrix coefficient block, a group of inputs 24 as column addresses when reading from the coefficient block matrices, the same input 25 as the row address when writing to the matrix coefficient block,the same-named input 26 as a column address when writing to the block of matrix coefficients, input 27 of data for writing the block of matrix coefficients, input 28 is a synchronization input for writing the block of matrix coefficients, a group of outputs 29, n × n storage blocks 40, each of which (Fig. 3) contains an AND element 30, a trigger 31, a block of AND elements 32, a group of inputs 33 of read column addresses, an input 34 of a write column address, a group of inputs 35 of read row addresses, an input 36 of write data, an input 37 of write synchronization, an input 38 of a write row address, a group of outputs 39 of data for the next row, the block of matrix coefficients 9 also includes the first group of OR elements 41 and the second group of OR elements 42, wherein the data write input 12 is connected to the first input of the fourth AND element 10, the output of which is connected to the first input of the OR element 7, the output of which is connected to the ninth input 27 of the data write of the block of matrix coefficients 9, the second input of the OR element 7 is connected to the output of the NOT element 3,the input of which is connected to the initialization input 13, the second input of the fourth AND element 10 is connected to the initialization input 13, the first synchronization input 14 is connected to the synchronization input of the first shift register 4, the output of which is connected to the first input 231 of the row address when reading the block of matrix coefficients 9, to the third input 232 of the row address when reading the block of matrix coefficients 9, to the seventh input of the address 25 of the rows when writing the block of matrix coefficients 9, and the n-th digit of the output of the first shift register 4 is connected to the first input of the first AND element 1, a one-digit value is supplied to the least significant digit of the information input of the first shift register 4, zero values ​​are supplied to the remaining (n - 1) digits, the load input of the first shift register 4 is connected to the second synchronization input 15, the first synchronization input 14 is connected to the second input of the first AND element 1, the output of which is connected to the synchronization input of the second shift register 5,the output of which is connected to the second input 241 of the column address when reading the block of coefficients of the matrix 9, to the sixth input 243 of the column address when reading the block of coefficients of the matrix 9 and to the eighth input 26 of the address when writing the block of coefficients of the matrix 9, a one value is supplied to the least significant digit of the information input of the second shift register 5, zero values ​​are supplied to the remaining (n - 1) digits, the load input of the second shift register 5 is connected to the second synchronization input 15, the third synchronization input 16 is connected to the synchronization input of the third shift register 6, the output of which is connected to the fourth input 242 of the column addresses when reading the block of coefficients of the matrix 9, to the fifth input 233 of the row addresses when reading the block of coefficients of the matrix 9, a one value is supplied to the least significant digit of the information input of the third shift register 6, zero values ​​are supplied to the remaining (n - 1) digits,the load input of the third shift register 6 is connected to the fourth synchronization input 17, the fifth synchronization input 18 is connected to the first input of the second AND element 2, the output of which is connected to the tenth input 28 of the write synchronization input of the matrix coefficient block 9, the second input of the second AND element 2 is connected to the output of the trigger 11, the first output 291 of the matrix coefficient block 9 is connected to the results upload output 22, the second output 292 of the matrix coefficient block 9 is connected to the first input of the third AND element 8, the second input of which is connected to the third output 293 of the matrix coefficient block 9, the output of the third AND element 8 is connected to the information input of the trigger 11, the reset input of the trigger 11 is connected to the sixth synchronization input 19, the set input of the trigger 11 is connected to the seventh synchronization input 20, and the synchronization input of the trigger 11 is connected to the eighth synchronization input 21, the synchronization input 28 blocks of matrix coefficients 9 are connected to the sync input 37 of the recording of each of the n × n storage blocks 40,k-th input (where, ) as part of the group of addresses of reading lines 23 of the matrix coefficient block 9 is connected to the input 35 of the addresses of reading lines (i, k) of the storage block (where ), the k-th input (where ) as part of the group of read column addresses, 24 matrix coefficient blocks are connected to the input 33 of the read column addresses of the (k, i)-th storage block (where , ), the k-th input (where ) as part of the group of addresses of recording lines 25 of the matrix coefficient block 9 is connected to the input 38 of the addresses of recording lines (i, k) of the storage block (where ), the k-th input (where ) as part of the group of record column addresses 26 of the matrix coefficient block 9 is connected to the input 34 of the record column addresses of the (k, i)-th storage block (where , ), input 27 of the recording data of the block of coefficients of matrix 9 is connected to input 36 of the recording data of each of the n × n storage blocks, signals from outputs 39 k storage block 40 ij , (Where ) are fed to the j-th input of the n-input element of the second group of OR elements 42 ik block of matrix coefficients 9, outputs of elements of the second group of OR elements 42 ik (Where ) are fed to the i-th input of the n-input element of the first group of OR elements 41 k , the output of the k-th (where ) of the element of the first group of OR elements 41 of the matrix coefficient block 9 is connected to the k-th output 29 as part of the group of outputs of the matrix coefficient block 9, as part of each of the storage blocks, the first input of the AND element 30 of the storage block is connected to the input 34 of the record column address of the storage block, the recording clock signal 37 is fed to the second input of the AND element 30 of the storage block, the third input of the AND element 30 of the storage block is connected to the input 38 of the record row address of the storage block, the information input of the trigger 31 is connected to the input 36 of the record data of the storage block, and the clock input of the trigger 31 is connected to the output of the AND element 30, the output of the trigger 31 is connected to the first input of each of the elements of the group of AND elements 321-323, the output of each k-th (where ) of the element of the group of elements AND 321-323 is connected to the k-th digit of the output 391–393 data, the second input of each k-th (where ) of the element of the group of elements AND 321–323 is connected to the i-th digit of the input 351–353 of the address of the read line of the storage block, and the third input of each k-th (where ) of the element of the group AND 321–323 is connected to the i-th digit of the input 331–333 of the read column address of the storage block.

[0010] The AND element 1 is used to pass the clock pulse from the synchronization input 14 to the clock input of the shift register 5 and is controlled by the value from the most significant bit of the shift register 4. The AND element 2 is used to transfer the clock pulses from the fifth synchronization input 18 to the write clock input 28 of the matrix coefficient block 9 at the data recording stage and is activated by the value one coming from the output of the trigger 11. The NOT element 3 is used to ensure the transfer of the values ​​of the matrix coefficients a ijfrom the output of AND element 10 through OR element 7 to the input of record data 27 of the matrix coefficient block 9 with a unit value at input 12 during the data loading stage. Shift registers 4 and 5 are used to store the addresses of the i and j row and column of the binary matrix, respectively, and shift register 6 is used to store the address k for accessing elements a ik and a kj binary matrix. The OR element 7 is used to transfer the values ​​of the coefficients of the matrix a ij at the data loading stage and the supply of a single value from the NOT element 3 at the matrix multiplication stage to write a single value into a cell of the resulting matrix. Element AND 8 receives input values ​​from outputs 292 and 293 of the matrix coefficient block 9 and calculates the conjunction value. which is fed to the information input of trigger 11. The matrix coefficient block 9 is designed to store elements a ijbinary matrix. The AND element 10 is used to transfer the values ​​of the coefficients of the binary matrix a ijfrom an external device via data input 12 to the first input of OR element 7, enables transmission upon receipt of a one value at initialization input 13 during the data loading stage and interrupts transmission upon receipt of a zero value at initialization input 13 during the initialization stage. Trigger 11 is intended to store the current value of the conjunction during multiplication of the i-th row and the j-th column. Input 12 is intended to receive data from an external device and transmit it to the first input of AND element 10. Control signal g1 is supplied to input 13, switching the device between the initial data loading mode and the operating mode. Synchronization input 14 receives synchronization pulses arriving at the second input of AND element 1, at the synchronization input of shift register 4 and activating the shift of register data towards the most significant digits, which is equivalent to the increment of values ​​in the unitary code.A single sync pulse is fed to synchronization input 15, arriving at the load inputs of shift registers 4 and 5 for writing the initial single values ​​"00...01" into them. Synchronization input 16 receives sync pulses arriving at the clock input of shift register 6, shifting its data toward the most significant bits, which is equivalent to an increment of the value k in the unitary code. Synchronization input 17 receives a sync pulse arriving at the load input of shift register 6, intended for writing the initial single values ​​"00...01" into it. Synchronization input 18 receives sync pulses arriving at the first input of AND element 2 and responsible for writing the updated single value of matrix a. ijA synchronization pulse is fed to synchronization input 19, arriving at the reset input of flip-flop 11, ensuring that a zero value is written to it. A synchronization pulse is fed to synchronization input 20, arriving at the set input of flip-flop 11, ensuring that a one value is written to it. Synchronization input 21 receives synchronization pulses arriving at the synchronization input of flip-flop 11, ensuring that the value received at the data input from the output of AND element 8 is written to it. Output 22 is intended for unloading the multiplication results (matrix elements) and the corresponding output of a one value indicating readiness to interrupt the current multiplication operation. The group of inputs 231, 232, 233 of read row addresses in combination with the group of inputs 241, 242, 243 of read column addresses are used for obtaining by the block the coefficients of the matrix of row and column addresses of the required elements for the purpose of selecting them from the triggers 31 of the storage blocks 40 and outputting them to the outputs 291–293.Input 25 of the write row address in combination with input 26 of the write column address are used for obtaining by the matrix coefficient block the values ​​of the i-th row and the j-th column for the purpose of subsequently writing into the selected ij-th storage block the coefficient value supplied to input 27 of the write data. Input 27 is used as the write data input of the matrix coefficient block. Synchronization input 28 is used to receive the write data synchronization signal from input 27 of the matrix coefficient block. Group of outputs 291, 292, 293 is used as the output of the results of reading the matrix coefficients using three ports. Element AND 30 controls the passage of the write synchronization signal 37 into the storage block with coordinates [i, j], determined by the corresponding signals at inputs 34 and 38. Trigger 31 is used to store the elements of matrix a. ij. The group of AND elements 321–323 controls the passage of a group of 3 values ​​from the output of trigger 31 of each storage block to the corresponding outputs 391–393 of the storage block, wherein the selected values ​​are determined by the coordinates of the rows and columns at inputs 351–353 and 331–333. The group of inputs 331–333 of read column addresses in combination with the group of inputs 351–353 of read row addresses is used to control the passage of the values ​​of a group of 3 matrix coefficients from triggers 31 of storage blocks 40 to outputs 291–293 of the matrix coefficient block. The inputs of the record column address j 34 and the record row i 38 ensure the selection of the ij-th storage block 40 within the block of matrix coefficients 9 by controlling the passage of the recording synchronization signal 37 through the AND element 30 when recording the required coefficient from the input 36 into the trigger 31 of the selected ij-th storage block 40. The recording data input 36 is used for the reception by the storage block 40 of matrix coefficients for the purpose of recording them into the triggers 31.Input 37 of synchronization is used when writing the values ​​of matrix coefficients into triggers 31. Storage blocks 40, combined into an n × n matrix, form a block of matrix coefficients 9. A group of OR elements 411 is used to form, at outputs 291-293 of block of matrix coefficients 9, disjunctions of the values ​​from the outputs of OR elements 42 of block of matrix coefficients 9 in order to form a group of 3 sought matrix coefficients in accordance with their addresses at inputs 23 and 24. A group of OR elements 42 as part of block of matrix coefficients 9 ensures that at outputs 291-293 of block of matrix coefficients 9 the next group of matrix coefficients is obtained in accordance with the operating logic, wherein 3 pairs of addresses of rows and columns of the sought coefficients are determined by the values ​​at inputs 351-353 and 331-333 of storage blocks 40.

[0011] The device operates as follows. Before starting to feed the coefficients of the matrix a ijIn shift registers 4 and 5, it is necessary to form the initial values ​​“00…01” of the addresses of the rows and columns of the matrix coefficients, for which a single sync pulse is supplied to input 15, which passes to the loading inputs of shift registers 4 and 5, thereby ensuring that the single values ​​“00…01” are fixed in them in the unitary code.

[0012] At the stage of loading the initial data, before feeding the matrix coefficients to input 20, a sync pulse is fed, which goes to the setup input of trigger 11, ensuring the recording of a single value, which from the output of trigger 11 goes to the second input of element AND 2, opening it for the passage of sync pulses from input 18 to sync input 28 of the matrix coefficient block 9. Next, a single value is fed to input 13, which goes to the second input of element AND 10, opening it for the passage of the values ​​of the matrix coefficients a ijfrom data input 12 from an external device to the first input of the OR element 7. A unity value from input 13 forms a zero value at the output of the NOT element 3, which ensures the passage of the values ​​of the coefficients of the matrix a ij from the output of the AND element 10 through the OR element 7 to the input 27 of the coefficient block of the matrix 9. The values ​​of a ij matrix elements are fed alternately from an external device to input 27 of the matrix coefficient block 9 through the AND elements 10 and OR 7. The addresses of row i from shift register 4 and column j from shift register 5 in unitary code are fed to the address inputs of row and column 25 and 26 of the matrix coefficient block 9, respectively, recording the next element a ijis performed by applying a synchronization pulse to input 18, which passes through the AND element 2, opened with a unit value from the output of trigger 11 to the input of the matrix coefficient block 28. The value of the coefficient from input 27 of the matrix coefficient block is fed to inputs 36 of storage blocks 40 and then to the information input of trigger 31 in each of the storage blocks. The values ​​of the row and column addresses from inputs 25 and 26 of matrix coefficient block 9 are fed respectively to inputs 38 and 34 of storage blocks 40, where the i-th digit from input 25 is fed to inputs 38 of storage blocks 40 of the i-th row of the matrix coefficient block, and the j-th digit from input 26 is fed to inputs 34 of storage blocks 40 of the j-th column of the matrix coefficient block 9, . The synchronization pulse from input 28 of the matrix coefficient block 9 goes to inputs 37 of storage blocks 40 and then to the input of the AND element 30. Unit values ​​38 and 34, corresponding to the selected storage block 40 ij, are fed to the input of the AND element 30 of the storage block and open it to allow the clock signal to pass to the clock input of the trigger 31, ensuring the recording of the next coefficient. In all other storage blocks 40, at least one of the inputs 38 or 34 has a zero value, the AND elements 30 are closed to allow the clock signal to pass and the value is not written to the trigger 31. After writing the current value a ijThe next value is fed to input 12 of the device. To change the value of the row number, a clock pulse is fed to input 14, which passes to the clock input of shift register 4, providing an increment of its contents in the unitary code. Element AND 1 is currently closed by a zero value from the most significant digit of shift register 4, the passage of the clock pulse from input 14 to the clock input of shift register 5 and no change in its contents occurs. Thus, in n clock cycles, the processing of the values ​​of row numbers 1, 2, ..., n is ensured with an unchanged column number. On the n-th clock cycle, one in the most significant digit of shift register 4 opens element AND 1 for the passage of the next clock signal 14 to the clock input of shift register 5, providing an increment of its contents and the transition to processing the next column. In this case, the value "00...01" is formed in shift register 4. After applying n 2 sync pulses to input 14 in the matrix coefficient block all coefficients a will be written ij matrices.

[0013] At the initialization stage, a zero value is supplied to input 13, which closes the AND element 10 for passing the coefficients of matrix a ij from data inputs 12 from an external device to the first input of the OR element 7. A zero value from input 13 forms a one value at the output of the NOT element 3, which ensures a one value at the output of the OR element 7, which is fed to input 27 of the coefficient block of matrix 9. A clock pulse is fed to input 15, ensuring the recording of the values ​​"00...01" in shift registers 4 and 5. Similarly, a clock pulse is fed to input 17, ensuring the recording of the value "00...01" in shift register 6. A clock pulse is fed to input 19, which is fed to the reset input of trigger 11, ensuring the recording of a zero value, which from the output of trigger 11 is fed to the second input of AND element 2, closing it for the passage of clock pulses from input 18.

[0014] At the stage of multiplying the i-th row by the j-th column, the values ​​i, j, k come from the outputs of shift registers 4, 5, 6, respectively, to inputs 231-233 and 241-243 of the coefficient block of matrix 9, ensuring the reading of the following values: a ij at the output 291, a ik at the output 292i a kj at the output 293, respectively. While the output 291 of the matrix coefficient block 9 contains a zero value, the values ​​of the matrix coefficients a ik and a kj from the corresponding outputs 292 and 293 go to the inputs of the AND element 8, at the output of which the value is formed , which is fed to the data input of trigger 11 and is fixed in it using the clock signal from input 21. In the case of receiving a single value from the output of AND element 8, it is fed from the output of trigger 11 to the second input of AND element 2, opening it for the passage of clock signal 18 to the recording input 28 of the coefficient block of matrix 9. At the data input 27 of the coefficient block of matrix 9, as discussed above, a single value is formed, when clock pulse 18 arrives, it passes through AND element 2 to the recording clock input 28 of the coefficient block of matrix 9, which ensures the recording of the updated single value a ij After recording, the unit value a ijFrom output 291 of matrix coefficient block 9, the signal goes to output 22 and forms a single value of the readiness flag. The multiplication of the current row and column pair is interrupted, and then an early transition to the next pair occurs. If a zero value is received, it goes from the output of trigger 11 to the second input of AND element 2, closing it to allow the passage of clock signal 18 to the write input 28 of matrix coefficient block 9: writing the updated single value a ij does not occur. Next, a clock pulse is applied to input 16, which is fed to the clock input of shift register 6, shifting its contents toward the most significant bits, which is equivalent to incrementing the value of k in the unitary code. The updated value of k from the output of shift register 6 is fed to inputs 242 and 233, which ensures that the updated values ​​of a are read. ik and a kjand transition to a new iteration of the device operation. The transition to the next pair of row and column is realized by applying a clock pulse 14, which arrives at the clock input of shift register 4, providing an increment of its contents in the unitary code. Element AND 1 at this point in time is closed by a zero value from the most significant digit of shift register 4, therefore the passage of the clock pulse from input 14 to the clock input of shift register 5 and a change in its contents does not occur. Thus, in n clock cycles, the processing of the values ​​of row numbers 1, 2, ..., n is ensured with an unchanged column number. On the n-th clock cycle, a one in the most significant digit of shift register 4 opens element AND 1 for the passage of the next clock signal from input 14 to the clock input of shift register 5, providing an increment of its contents and the transition to processing of the next column. In this case, the value "00...01" is formed in register 4. Receipt of n 2 synchronization pulses to input 14 ensures the receipt of n 2results of multiplication of a binary matrix and recording their values ​​in the block of matrix coefficients 9.

[0015] At the stage of data unloading in shift registers 4 and 5, it is necessary to form the initial values ​​of the addresses of the rows and columns of the matrix coefficients. For this, the values ​​"00...01" are supplied to their first inputs, which are fixed in the registers by supplying a synchronization pulse coming from input 15 of the device to the write inputs of shift registers 4 and 5. The values ​​​​i and j come from the outputs of shift registers 4 and 5 to inputs 231 and 241 of the matrix coefficient block 9, ensuring the reading of the value of the matrix a ij at output 291, from where it goes to output 22. To move on to reading the next value, a sync pulse is applied to input 14, which shifts the contents of shift registers 4 and 5 in the same way as discussed above. After applying n 2 sync pulses 14 from the matrix coefficient block 9 all coefficients a will be read ij matrices, which will be sent one after another to the output 22 of the device.

[0016] Let's evaluate the performance advantages of the proposed device compared to the prototype. We'll calculate the performance of an iterative device for squaring a binary matrix, assuming the operating time of one equivalent gate as t0. The general strategy for squaring a binary matrix with the proposed device consists of the following steps:

[0017] 1) loading the initial data (coefficients) of the matrix a ij from RAM to device memory;

[0018] 2) Initialization stage;

[0019] 3) Performing the construction of the matrix a ij squared (multiplication by itself);

[0020] 4) transfer the resulting binary matrix from the device memory to the RAM.

[0021] The operating time of the device for squaring a binary matrix depends on the operating time of each of its stages separately:

[0022]

[0023] where – the time of data transfer from the RAM to the memory of the matrix coefficient block 9; – initialization time of the elements that are part of the operating part of the device; – the execution time of the construction of the matrix a ij squared; – the time it takes to transfer data from the device's memory to the RAM.

[0024] To initialize the data loading mode, a sync pulse is applied to input 20, which is fed to the trigger setup input 11, ensuring the recording of a single value (the required time is 2t0). To generate the initial values ​​of the row and column addresses of the coefficients of the matrix a ij, it is necessary to apply a single sync pulse to input 15, which passes to the load inputs of shift registers 4 and 5, ensuring that single values ​​are written to them in unitary code. Since the shift registers are switched in parallel, the total time is equal to 3t0. Next, a single value is applied to input 13, which goes to the second input of the second AND element 10, opening it for the passage of the values ​​of the coefficients of matrix a ij from data input 12 from an external device to the first input of the OR gate 7 (required time - 2t0). The inverted value from input 13 forms a zero value at the output of the NOT gate 3 (required time - t0), which ensures that a zero value is supplied to the second input of the OR gate 7 (required time - t0), opening it for the passage of the values ​​of the coefficients of the matrix a ij from the output of the AND element 10 to the input 27 of the coefficient block of the matrix 9. The switching of the second AND element 10 and the NOT element 3 occurs simultaneously, so the total time is 2t0.

[0025] The longest path that occurs during boot mode initialization is represented by the elements:

[0026]

[0027] At the stage of loading the initial data, the values ​​of a ij , matrix elements are fed alternately from an external device to input 27 of the matrix coefficient block 9 through the AND element 10 (required time – t0) and the OR element 7 (required time – t0). Thus, the signal transit time of the value of one matrix element a ij to the block of coefficients of matrix 9 is:

[0028]

[0029] When writing a signal from data input 27 of the matrix coefficient block, trigger 31 must be switched (required time: 3t0) upon receipt of a clock signal at the clock input, which must pass through AND element 30 (required time: 2t0). Thus, the total write time for one storage block 40 is:

[0030]

[0031] Considering that the initialization of the boot mode occurs once before booting, the total time for sequentially loading the data of one matrix, which includes n × n cells, is:

[0032]

[0033] Let's calculate the total time of the initial data loading stage:

[0034]

[0035] At the initialization stage, a zero value is supplied to input 13, which closes the AND element 10 (the required time is t0) to pass the values ​​of the coefficients of the matrix a ijfrom data input 12 from an external device to the first input of OR element 7. The inversion of the zero value from input 13 is formed at the output of NOT element 3 (the required time is t0), which provides a unity value at the output of OR element 7 (the required time is t0), which is fed to input 27 of the coefficient block of matrix 9. Since NOT elements 3 and AND elements 10 are switched simultaneously, the total time of this initialization path is 2t0. A clock pulse is applied to input 15, ensuring the writing of the values ​​"00...01" into shift registers 4 and 5. Similarly, a clock pulse is applied to input 17, ensuring the writing of the value "00...01" into shift register 6 (the operations are performed simultaneously, therefore the required time is 3t0). A sync pulse is fed to input 19, which is sent to the reset input of trigger 11, ensuring that a zero value is recorded (the required time is 2t0).

[0036] Let's determine the initialization time by taking the time of the longest path:

[0037]

[0038] At the multiplication stage, shift registers 4, 5, and 6 are switched to supply the row and column address values ​​of matrix elements i, j, and k to the inputs of matrix coefficient block 9 (required time: 3t0). When reading data from storage block 40, the signal from the output of trigger 31 passes through one of the three-input AND elements 32, opened with unity values ​​at inputs 33 and 35, which takes 2t0. All storage blocks 40 operate in parallel. Signals from outputs 39 kj -th column, , , are fed to the inputs of the n-input OR element 42 jk , at the outputs of which the value of the disjunction is formed over time (the element is implemented using a pyramidal circuit of two-input elements). Next, the signals from the outputs of the OR elements 42 jk are fed to the inputs of the group of OR 41 elements, which, using a pyramidal circuit of two-input elements, requires time , Where – rounding up operation.

[0039] Thus, the total time to read data from data block 40 is:

[0040]

[0041] Values ​​of the coefficients of the matrix a ik and a kj from the outputs 292 and 293 of the matrix coefficient block go to the inputs of the AND element 8, at the output of which the value is formed (the required time is t0), which is fed to the data input of trigger 11 and is fixed in it (the required time is 3t0) upon receipt of the clock signal from input 21. In the case of receiving a single value from the output of trigger 11, it is fed to the second input of element AND 2, opening it for the passage of clock signal 18 (the required time is ), the recording of a single value a occurs ij into the block of matrix coefficients 9. The time to write a new value into storage block 40 is 5t0.

[0042] The device operation stage includes: the switching time of shift register 6 (the required time is 3t0), the reading stage from data block 40 discussed above (the required time is ), the signal passes through the AND element 8 (the required time is t0), trigger 11 (the required time is 3t0), the AND element 2 (the required time is t0), the stage of writing the new value into storage block 40 (the required time is ). Thus, the total time of the work stage is:

[0043]

[0044]

[0045] The total execution time of the operation of multiplying the i-th row by the j-th column of a matrix is:

[0046]

[0047]

[0048] where – the ratio of the average number of operations of multiplication of elements of binary matrices to the maximum number of multiplications ( ). To find the result of squaring a binary matrix, it is necessary to organize the sequential multiplication of n rows by n columns of the matrix, which will require the following time:

[0049]

[0050] At the stage of unloading data in shift registers 4 and 5, it is necessary to generate the initial values ​​of the addresses of the rows and columns of the coefficients of the matrix a ij , for this purpose, the values ​​"00...01" are fed to their first inputs, which are fixed by applying a sync pulse coming from input 15 of the device in parallel to the load inputs of shift registers 4 and 5 (the required time is 3t0). The unloading of the values ​​of the matrix elements stored in the matrix coefficient block 9 occurs in sequential mode: a pair of addresses i and j are fed to inputs 231 and 241c of the outputs of shift registers 4 and 5, and the coefficients of matrix a are read ijsimilar to what was discussed above, its values ​​from the output 291 of the matrix coefficient block 9 are sent to the output 22 of the device, which requires time:

[0051]

[0052] Then the total time to unload data from the matrix coefficient block 9, which includes n 2 40 storage blocks, which is:

[0053]

[0054] Thus, the total operating time of the device for squaring a binary matrix is:

[0055]

[0056]

[0057]

[0058] Let's perform a similar calculation of the performance of the prototype device. The numbering of the component elements is given in the patent [1].

[0059] The general strategy for squaring a binary matrix using the prototype device is as follows:

[0060] 1) Initialization stage;

[0061] 2) loading the initial data (coefficients) of the matrix a ij from RAM to device memory;

[0062] 3) Performing the construction of the matrix a ij squared (multiplication by itself);

[0063] 4) transfer the resulting binary matrix from the device memory to the RAM.

[0064] The operating time of the prototype device for squaring a binary matrix depends on the operating time of each of its stages separately:

[0065]

[0066] where – device initialization time; – the time of data transfer from the RAM to the memory of the matrix coefficient block; – the execution time of the matrix construction a ij squared; – the time it takes to transfer data from the device's memory to the RAM.

[0067] For the initialization stage, the signal from clock input 28 is fed in parallel to the data inputs of shift registers 2 and 3 via inverter 1 (required time – t0) and in parallel to the write inputs of shift registers 2 and 3 via delay element 4, which initiates writing the values ​​"00...01" to them (required time – 3t0). Thus, the initialization time of registers 2 and 3 is as follows:

[0068]

[0069] At the same time, the signal from input 28 is sent to reset input 37 of storage unit 10 and is fed to the reset input of triggers 40 of storage unit 52 cells, causing zero values ​​to be written to all triggers 40 of storage unit 52 cells (required time: 2t0). These two actions are performed in parallel, so the total boot initialization time is:

[0070]

[0071] During the initial data loading stage, the matrix element values ​​from input 21 and the row and column address values ​​from inputs 22 and 23 are fed through switches 19 and 20 (the required time is 2t0 per switch) to inputs 31 and 32 of storage unit 10, from where they are fed to the AND elements 39 of storage unit 52 (the required time is 2t0). Since the values ​​are fed in parallel, the required time for feeding the values ​​through the switches is:

[0072]

[0073] The values ​​from input 27 are fed through AND element 15 (t0) and OR element 16 (t0) to input 36 of the matrix coefficient block 10, from where they are fed to input 47 of the storage block cell. The signal transit time is then:

[0074]

[0075] When implementing the operation of recording a signal from data input 36 of the matrix coefficient block 10, it is necessary to switch trigger 40 (the required time is 3t0) upon receipt of a clock signal at the clock input.

[0076] Thus, the writing time of one cell is:

[0077]

[0078] Then the total data loading time, taking into account the matrix bit depth, is:

[0079]

[0080] where d is the matrix density.

[0081] Let's estimate the time costs at the matrix multiplication stage. When reading data from storage block 10, the signal from the output of triggers 40 of storage block 52 passes through one of the three-input AND gates 41, opened by single values ​​at inputs 44 and 46 (the required time is 2t0), through one of the two-input OR gates 42 (the required time is t0). Next, the signal passes n storage block cells from top to bottom (from inputs 43 to outputs 51 of cells) and arrives at the n-input OR gate 53, which, using a pyramidal circuit of two-input gates, requires time , Where – rounding up operation.

[0082] Thus, the time to read a data cell is:

[0083]

[0084] The device operation stage includes: the switching time of the shift register 9 (the required time is 3t0), the data reading stage, the signal passing through the elements AND 13 (the required time is t0), OR 14 (the required time is t0), the switch 11 (the required time is 2t0), the trigger 12 (the required time is 3t0), AND 15 (the required time is t0), OR 16 (the required time is t0), the trigger 40 (the required time is 3t0). Thus, the total time of the operation stage is:

[0085]

[0086]

[0087] The total execution time of the operation of multiplying the i-th row by the j-th column of a matrix is:

[0088]

[0089]

[0090] where – the ratio of the average number of operations of multiplication of elements of binary matrices to the maximum number of multiplications ( ).

[0091] To find the result of squaring a binary matrix, it is necessary to organize the sequential multiplication of n rows by n columns of the matrix, which will require the following time:

[0092]

[0093] At the data upload stage, a zero value is supplied to input 21, which switches switches 19 and 20 (the required time is ) for passing the row and column address signals from inputs 22 and 23 of the device to inputs 311 and 321 of the coefficient block of matrix 10, respectively. The addresses of rows i and columns j of the elements to be read are alternately fed to inputs 22 and 23 of the device, which are fed to inputs 441 and 461 of the cell of storage block 52, respectively, and the coefficients of matrix a are read ij similar to what was discussed above, the output is 381 values ​​of the matrix a ij, arriving at output 30 of the device.

[0094] Taking this into account, the time to unload one matrix coefficient is:

[0095]

[0096] The total time to unload n × n matrix coefficients is:

[0097]

[0098] Thus, the total operating time of the prototype device for squaring a binary matrix is:

[0099]

[0100]

[0101]

[0102]

[0103] Let's estimate the operating time savings of the proposed device and prototype:

[0104]

[0105] The performance values ​​of the proposed device and prototype, calculated for different n and α, are given in the table below (we assume that ns).

[0106] N α d The proposed device, ns Prototype, ns Win, times 10 0,1 0,2 2,08 10 0,1 0,8 2,17 10 0,5 0,2 2,18 10 0,5 0,8 2,21 10 0,9 0,2 2,2 10 0,9 0,8 2,22 100 0,1 0,2 11,48 100 0,1 0,8 11,49 100 0,5 0,2 11,5 100 0,5 0,8 11,5 100 0,9 0,2 11,5 100 0,9 0,8 11,5 1000 0,1 0,2 88,97 1000 0,1 0,8 88,97 1000 0,5 0,2 88,97 1000 0,5 0,8 88,97 1000 0,9 0,2 88,97 1000 0,9 0,8 88,97

[0107] From the presented data it follows that the proposed device has a performance speed that is 2.08 – 88.97 times higher than the prototype, depending on the matrix size n.

[0108] Sources of information

[0109] 1. Russian Federation Patent No. 2744239. Device for squaring a binary matrix, declared 05.07.2020, published 04.03.2021, Bulletin No. 7 (prototype).

[0110] 2. Russian Federation patent for utility model No. 193927, class G06F 15 / 00, filed June 26, 2019, published November 21, 2019, bulletin No. 33.

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