Method for refreshing row hammer, circuit for refreshing row hammer and semiconductor memory

Abstract

Embodiments of the present disclosure provide a method for refreshing row hammer, a circuit for refreshing row hammer and a semiconductor memory. The method includes the following operations. A row hammer refresh instruction for a target word line is determined. According to the row hammer refresh instruction, a preset row hammer refresh signal is set to a valid state. The valid state of the preset row hammer refresh signal indicates that the row hammer refresh instruction is performed in a first refresh period. In response to detecting that the row hammer refresh instruction is not completed within the first refresh period, the valid state of the preset row hammer refresh signal will be continued to a next refresh period of the first refresh period. [Fig. 4]

Description

[ 0001] The present disclosure is proposed based on Chinese patent application No.202111399125.2, filed on November 19, 2021 and entitled "METHOD FORREFRESHING ROW HAMMER, CIRCUIT FOR REFRESHING ROW HAMMER ANDSEMICONDUCTOR MEMORY", and claims priority to the Chinese patent application,the disclosure of which is hereby incorporated by reference in its entirety.TECHNICAL FIELD[ 0002] The present disclosure relates to the technical field of integrated circuits, and inparticular, to a method for refreshing row hammer, a circuit for refreshing row hammerand a semiconductor memory.BACKGROUND[ 0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory devicecommonly used in computers, which is composed of many repeated memory cells, and theselection processing needs to be performed on different memory cells via word lines andbit lines. That is to say, there are a large number of word lines in the DRAM, and theseword lines are arranged adjacently. When a certain word line is subjected to a row hammer,the word lines adjacent to the word line may generate errors. In the related art, after a rowhammer is detected, a refresh processing is performed on the affected word lines. However,the refresh processing needs to be completed by means of two refresh instructions, whichoccupies bandwidth resources and easily leads to refresh errors.SUMMARY[ 0004] The present disclosure provides a method for refreshing row hammer, a circuitfor refreshing row hammer and a semiconductor memory, which can reduce the bandwidthresources occupied by the row hammer refresh processing and improve the refreshcorrectness.[ 0005] In a first aspect, the embodiments of the present disclosure provide a method forrefreshing row hammer. The method includes the following operations.[ 0006] A row hammer refresh instruction for a target word line is determined.[ 0007] According to the row hammer refresh instruction, a preset row hammer refreshsignal is set to a valid state. The valid state of the preset row hammer refresh signalindicates that the row hammer refresh instruction is performed in a first refresh period.[ 0008] In response to detecting that the row hammer refresh instruction is not completedwithin the first refresh period, the valid state of the preset row hammer refresh signal willbe continued to a next refresh period of the first refresh period.[ 0009] In some embodiments, the method further includes the following operation. Inresponse to detecting that the hammering refresh instruction is completed, the preset rowhammer refresh signal is set to an invalid state.[ 0010] In some embodiments, the row hammer refresh instruction instructs to refresh afirst adjacent word line of the target word line and a second adjacent word line of the targetword line.[ 0011] Correspondingly, the method further includes the following operations. Whetherthe first adjacent word line and the second adjacent word line are both refreshed isdetermined in the first refresh period. In response to the first adjacent word line beingrefreshed and the second adjacent word line being not refreshed, it is determined that therow hammer refresh instruction is not completed within the first refresh period.Alternatively, in response to the first adjacent word line and the second adjacent word linebeing both refreshed, it is determined that that the row hammer refresh instruction iscompleted within the first refresh period.[ 0012] In some embodiments, the method further includes the following operations. Afirst target state signal and a second target state signal are determined. The first target statesignal is configured to record a refresh state of the first adjacent word line, and the secondtarget state signal is configured to record a refresh state of the second adjacent word line.When refreshing is conducted for the first adjacent word line, the first target state signal isset to the valid state, and the second target state signal is set to the invalid state. Whenrefreshing is conducted for the second adjacent word line, the first target state signal is setto the invalid state, and the second target state signal is set to the valid state.[ 0013] In some embodiments, in a case of detecting that the row hammer refreshinstruction is not completed within the first refresh period, the method further includes thefollowing operations. Whether a word line activation instruction is received is determined.In response to a determination result being yes, the first target state signal and the secondtarget state signal are both set to the invalid state.[ 0014] In some embodiments, the method further includes the following operations.Whether the preset row hammer refresh signal is in the valid state is determined. In a casethat the preset row hammer refresh signal is in the valid state, the first target state signaland the second target state signal are determined. Word line refresh processing isperformed on adjacent word lines of the target word line according to the first target statesignal and the second target state signal.[ 0015] In some embodiments, the operation of performing the word line refreshprocessing on adjacent word lines of the target word line according to the first target statesignal and the second target state signal includes the following operations. In a case thatthe first target state signal and the second target state signal are both in the invalid state,the word line refresh processing is performed on the first adjacent word line and the secondadjacent word line respectively. In a case that the first target state signal is in the valid stateand the second target state signal is in the invalid state, the word line refresh processing isperformed twice on the second adjacent word line.[ 0016] In a second aspect, the embodiments of the present disclosure provide a circuitfor refreshing a row hammer. The circuit includes a detection circuit.[ 0017] The detection circuit is configured to determine a row hammer refresh triggersignal and a refresh execution signal; and output a preset row hammer refresh signal in avalid state in response to the row hammer refresh trigger signal indicating that a rowhammer refresh instruction for a target word line is received and the refresh executionsignal indicating that the row hammer refresh instruction is not completed.[ 0018] The valid state of the preset row hammer refresh signal indicates that the rowhammer refresh instruction is performed within a first refresh period, and the valid state ofthe preset row hammer refresh signal will be continued to a next refresh period of the firstrefresh period in a case that the row hammer refresh instruction is not completed withinthe first refresh period.[ 0019] In some embodiments, the refresh execution signal includes an initial refreshexecution signal and a refresh pulse signal.[ 0020] Correspondingly, the detection circuit includes a first clock circuit, a first refreshstate determination circuit and a control signal output circuit. The first refresh statedetermination circuit is configured to determine a first refresh state signal and a secondrefresh state signal according to the row hammer refresh trigger signal, a first clock signaland a first inverted clock signal. The first clock circuit is configured to determine the firstclock signal and the first inverted clock signal according to the first refresh state signal, theinitial refresh execution signal and the refresh pulse signal. The control signal output circuitis configured to determine the preset row hammer refresh signal according to the rowhammer refresh trigger signal and the second refresh state signal. The row hammer refreshinstruction instructs to perform word line refresh processing on a first adjacent word lineof the target word line and a second adjacent word line of the target word line, and theinitial refresh execution signal is configured to indicate a word line refresh processing thatoccurs for a first time in each refresh period, and the refresh pulse signal is configured toindicate a word line refresh processing that occurs each time in the each refresh period.[ 0021] In some embodiments, the first clock circuit includes a first two-input NANDgate, a second two-input NAND gate and a first NOT gate. Input ends of the first two-inputNAND gate are respectively connected with the first refresh state and the initial refreshexecution signal. Input ends of the second two-input NAND gate are respectivelyconnected with an output end of the first two-input NAND gate and the refresh pulse signal,and an output end of the second two-input NAND gate is configured to output the firstinverted clock signal. An input end of the first NOT gate is connected with the first invertedclock signal, and an output end of the first NOT gate is configured to output the first clocksignal.[ 0022] In some embodiments, the first refresh state determination circuit includes a firsttwo-input NOR gate, a third two-input NAND gate, a second NOT gate, a first trigger anda second trigger. Input ends of the first two-input NOR gate are respectively connectedwith the first refresh state signal and the second refresh state signal, and input ends of thethird two-input NAND gate are respectively connected with an output end of the first two-input NOR gate and the row hammer refresh trigger signal, and an input end of the secondNOT gate is connected with an output end of the third two-input NAND gate. An input endof the first trigger is connected with an output end of the second NOT gate, and a clockend of the first trigger is respectively connected with the first clock signal and the firstinverted clock signal, and an output end of the first trigger is configured to output the firstrefresh state signal. An input end of the second trigger is connected with the first refreshstate signal, a clock end of the second trigger is respectively connected to the first clocksignal and the first inverted clock signal, and the output end of the second trigger isconfigured to output the second refresh state signal.[ 0023] In some embodiments, the control signal output circuit includes a third NOTgate, a fourth two-input NAND gate and a fourth NOT gate. An input end of the third NOTgate is connected with the second refresh state signal, and input ends of the fourth two-input NAND gate are respectively connected with an output end of the third NOT gate andthe row hammer refresh trigger signal. An input end of the fourth NOT gate is connectedwith an output end of the fourth two-input NAND gate, and an output end of the fourthNOT gate is configured to output the preset row hammer refresh signal.[ 0024] In some embodiments, the circuit for refreshing a row hammer further includesa state counting circuit. The state counting circuit is configured to receive the preset rowhammer refresh signal and the word line state signal, and determine a first target statesignal and a second target state signal according to the preset row hammer refresh signaland the word line state signal. The first target state signal is configured to record a refreshstate of the first adjacent word line, and the second target state signal is configured to recordthe refresh state of the second adjacent word line.[ 0025] In some embodiments, the word line state signal includes a refresh state validsignal and a word line start pulse signal, and the state counting circuit includes a secondclock circuit, a second refresh state determination circuit and a reset circuit. The secondclock circuit is configured to determine a second clock signal and a second inverted clocksignal according to the preset row hammer refresh signal, the refresh state valid signal andthe word line start pulse signal. The reset circuit is configured to determine a reset signalaccording to the refresh state valid signal, the word line start pulse signal and the first targetstate signal. The second refresh state determination circuit is configured to determine thefirst target state signal and the second target state signal according to the second clocksignal, the second inverted clock signal and the reset signal. The refresh state valid signalindicates whether it is in a refresh period, and the word line start pulse signal indicatesstarting of any word line.[ 0026] In some embodiments, the second clock circuit includes a first three-inputNAND gate and a fifth NOT gate. Input ends of the first three-input NAND gate arerespectively connected with the preset row hammer refresh signal, the refresh state validsignal and the word line start pulse signal, and an output end of the first three-input NANDgate is configured to output the second inverted clock signal. An input end of the fifth NOTgate is connected with an output end of the first three-input NAND gate, and an output endof the fifth NOT gate is configured to output the second clock signal.[ 0027] In some embodiments, the second refresh state determination circuit includes athird trigger, a fourth trigger and a sixth NOT gate. An input end of the third trigger isconnected with an output end of the third trigger through the sixth NOT gate, and the outputend of the third trigger is configured to output the first target state signal, and a clock endof the third trigger is respectively connected with the second clock signal and the secondinverted clock signal. An input end of the fourth trigger is connected with the first targetstate signal, a clock end of the fourth trigger is respectively connected to the second clocksignal and the second inverted clock signal, and an output end of the fourth trigger isconfigured to output the second target state signal. A reset end of the third trigger and areset end of the fourth trigger are both connected with the reset signal.[ 0028] In some embodiments, the reset circuit includes a seventh NOT gate and asecond three-input NAND gate. An input end of the seventh NOT gate is connected withthe refresh state valid signal, and input ends of the second three-input NAND gate arerespectively connected with an output end of the seventh NOT gate, the word line startpulse signal and the first target state signal, and an output end of the second three-inputNAND gate is configured to output the reset signal.[ 0029] In a third aspect, embodiments of the present disclosure provide a semiconductormemory, including the circuit for refreshing row hammer described in the second aspect.[ 0030] The embodiments of the present disclosure provide a method for refreshing rowhammer, a circuit for refreshing row hammer and a semiconductor memory. The methodincludes the following operations. A row hammer refresh instruction for a target word lineis determined. According to the row hammer refresh instruction, a preset row hammerrefresh signal is set to a valid state. The valid state of the preset row hammer refresh signalindicates that the row hammer refresh instruction is performed in a first refresh period. Inresponse to detecting that the row hammer refresh instruction is not completed within thefirst refresh period, the valid state of the preset row hammer refresh signal will becontinued to a next refresh period of the first refresh period. In this way, under normalcases, the valid state of the preset row hammer refresh signal lasts for one refresh period,so that the row hammer refresh instruction is completed through one refresh period. In thecase that an occasional error occurs, the valid state of the preset row hammer refresh signalwill be continued to the next refresh period, so that the row hammer refresh instruction iscompleted through two refresh periods, which can not only save bandwidth resources, butalso improve the correctness of row hammer refresh.BRIEF DESCRIPTION OF THE DRAWINGS[ 0031] FIG. 1A is a schematic diagram of a process of refreshing row hammer providedby the related art.[ 0032] FIG. 1B is a schematic diagram of another process of refreshing row hammerprovided by the related art.[ 0033] FIG. 2 is a schematic diagram of another process of refreshing row hammerprovided by the related art.[ 0034] FIG. 3 is a schematic flowchart of a method for refreshing row hammer providedby the embodiments of the present disclosure.[ 0035] FIG. 4 is a schematic structural diagram of a circuit for refreshing row hammerprovided by the embodiments of the present disclosure.[ 0036] FIG. 5 is a schematic structural diagram of a detection circuit provided by theembodiments of the present disclosure.[ 0037] FIG. 6 is a schematic diagram of a specific circuit structure of a first clock circuitprovided by the embodiments of the present disclosure.[ 0038] FIG.7 is a schematic diagram of a specific circuit structure of a first refresh statedetermination circuit provided by the embodiments of the present disclosure.[ 0039] FIG. 8 is a schematic diagram of a specific circuit structure of a control signaloutput circuit provided by the embodiments of the present disclosure.[ 0040] FIG. 9 is a schematic diagram of a signal timing sequence of a detection circuitprovided by the embodiments of the present disclosure.[ 0041] FIG. 10 is a schematic structural diagram of another circuit for refreshing rowhammer provided by the embodiments of the present disclosure.[ 0042] FIG. 11 is a schematic structural diagram of a state counting circuit provided bythe embodiments of the present disclosure.[ 0043] FIG. 12 is a schematic diagram of a specific circuit structure of a second clockcircuit provided by the embodiments of the present disclosure.[ 0044] FIG. 13 is a schematic diagram of a specific circuit structure of a second refreshstate determination circuit provided by the embodiments of the present disclosure.[ 0045] FIG. 14 is a schematic diagram of a specific circuit structure of a reset circuitprovided by the embodiments of the present disclosure.[ 0046] FIG. 15 is a schematic structural diagram of a semiconductor memory providedby the embodiments of the present disclosure.DETAILED DESCRIPTION[ 0047] The technical solutions in the embodiments of the present disclosure will beclearly and completely described below with reference to the accompanying drawings inthe embodiments of the present disclosure. It should be understood that the specificembodiments described herein are only used to explain the related application, but not tolimit the present disclosure. In addition, it should be noted that, for the convenience ofdescription, only the parts related to the relevant application are shown in the drawings.[ 0048] Unless otherwise defined, all technology and scientific terms used herein havethe same meaning as commonly understood by one of ordinary skill in the art to which thepresent disclosure belongs. The terms used herein are for the purpose of describing theembodiments of the present disclosure only and is not intended to limit the presentdisclosure.[ 0049] In the following description, reference is made to “some embodiments” whichdescribe a subset of all possible embodiments, but it should be understood that “someembodiments” may be the same or a different subset of all possible embodiments, and maybe combined with each other without conflict.[ 0050] The “first\second\third” involved in the embodiments of the present disclosureis only used to distinguish similar objects, and does not represent a specific ordering ofobjects. It should be understood that “first\second\third” may be interchanged in a specificorder or precedence if allowed, so that the embodiments of the present disclosure describedherein can be implemented in an order other than those illustrated or described herein.[ 0051] The English words and their abbreviations involved in the embodiments of thepresent disclosure are described below.Row Hammer: hammer, or called row hammerDRAM: Dynamic Random Access MemorySDRAM: Synchronous Dynamic Random Access MemoryMemory Array: storage arrayWL: Word LineBL: Bit LineRHR: Preset row hammer refresh signalRHRact1: First target state signalRHRact2: Second target state signalRHRStart: Row hammer refresh trigger signalRefreshpulse1: Initial refresh execution signalRefPulseCounter: Refresh pulse signalRHRCk: First clock signalRHRCkN: First inverted clock signalRHRState1: First refresh state signalRHRState2: Second refresh state signalRfsh: Refresh state valid signalRasEnpulse: Word line start pulse signalRHRCounter: Second clock signalRHRCounterN: Second inverted clock signalResetN: Reset signal[ 0052] It should be understood that a DRAM is a semiconductor memory devicecommonly used in computers, and many repeated memory cells form a Memory Array,and the selection processing needs to be performed on different memory cells via wordlines and bit lines.[ 0053] At present, as memory cells become denser, the distance between word linesbecomes smaller and smaller, resulting in increased capacitive coupling between adjacentword lines. If the word line (also known as the target row) is repeatedly activated, it maycause two adjacent word lines (also known as the victim rows) to be subjected toelectromagnetic interference, so that the memory cells on the victim rows will occur thephenomenon of losing charge, and eventually these memory cell may lose data before thenext refresh of the victim row. The above case is called row hammer.[ 0054] That is to say, when a word line is subjected to row hammer, the two word linesadjacent to this word line will be greatly interfered. Therefore, in order to eliminate theimpact of the row hammer, when it is detected that the target row is subjected to rowhammer, the victim rows on both sides of the target row need to be refreshed, which iscalled Row hammer Refresh.[ 0055] For convenience of description, the addresses of the two WLs (i.e., the victimrows) are correspondingly called Ra and Rb, and the refresh operations on these twoaddresses are called RHRa and RHRb. Referring to FIG. 1A, a schematic diagram of aprocess of refreshing row hammer provided by the related art is shown. Referring to FIG.1B, a schematic diagram of another process of refreshing row hammer provided by therelated art is shown. In FIG. 1A and FIG. 1B, ActCmd refers to the word line activationcommand, PreCmd refers to the word line precharge command (Pre), REFCmdA refers tothe first refresh command, and REFCmdB refers to the second refresh command. Inaddition, the time required to complete a refresh command is also referred to as one refreshperiod.[ 0056] In a related art, as shown in FIG. 1A, the refresh of adjacent word lines needs toinvolve two refresh commands, which not only occupies bandwidth resources, but alsoeasily leads to some errors. In another related art, as shown in FIG. 1B, the refresh ofadjacent word lines is completed in one refresh command, but this method may also causeRHR errors in some occasional cases.[ 0057] Taking one refresh command to complete the process of refreshing row hammeras an example, the possible occasional error is described. Referring to FIG. 2, a schematicdiagram of another process of method for refreshing row hammer provided by the relatedart is shown. As shown in FIG. 2, after receiving the row hammer refresh instruction, theRHR signal is in a valid state to indicate that the Memory Array performs the row hammerrefresh in the refresh command (REFCmd1, etc.). Here, the refresh command correspondsto two pulses, i.e., 1st Pulse and 2nd Pulse, so that RHRa and RHRb are respectivelyperformed via these two pulses, thereby completing the row hammer refresh in one refreshcommand. However, if some inappropriate operations cause missing for the second pulse(2nd Pulse) of the refresh command REFCmd1, the situation of RHRa and RHRb beingrespectively performed in two Refresh commands will be occurred, resulting in word lineactivation (Active), word line pre-charge (Precharge) and other operations may be occurredbetween RHRa and RHRb. That is, word line activation, word line pre-charge, or otheroperations is occurred when the row hammer refresh has not been completed. This caseneeds to be avoided.[ 0058] Based on this, the embodiments of the present disclosure provide a method forrefreshing row hammer. The method includes the following operations. A row hammerrefresh instruction for a target word line is determined. According to the row hammerrefresh instruction, a preset row hammer refresh signal is set to a valid state. The valid stateof the preset row hammer refresh signal indicates that the row hammer refresh instructionis performed in a first refresh period. In response to detecting that the row hammer refreshinstruction is not completed within the first refresh period, the valid state of the preset rowhammer refresh signal will be continued to a next refresh period of the first refresh period.In this way, under normal cases, the valid state of the preset row hammer refresh signallasts for one refresh period, so that the row hammer refresh instruction is completedthrough one refresh period. In the case that an occasional error occurs, the valid state ofthe preset row hammer refresh signal will be continued to the next refresh period, so thatthe row hammer refresh instruction is completed through two refresh periods, which cannot only save bandwidth resources, but also improve the correctness of row hammer refresh.[ 0059] The embodiments of the present disclosure will be described in detail below withreference to the accompanying drawings.[ 0060] In an embodiment of the present disclosure, referring to FIG. 3, a schematicflowchart of a method for refreshing row hammer provided by the embodiment of thepresent disclosure is shown. As shown in FIG. 3, the method may include the followingsteps.[ 0061] In step S101, a row hammer refresh instruction for a target word line isdetermined.[ 0062] It should be noted that the method for refreshing row hammer provided by theembodiments of the present disclosure is applicable for a semiconductor memory device,such as DRAM, SDRAM, etc., which can better perform refreshing on the word linessubjected to row hammer.[ 0063] Here, the target word line refers to the target row subjected to the row hammer,the first adjacent word line and the second adjacent word line refer to the victim rows inthe row hammer.[ 0064] For semiconductor memory devices, after detecting the row hammer for thetarget word line, a row hammer refresh instruction for the target word line is generated toinstruct to refresh the first adjacent word line and the second adjacent word line, so as toavoid the problem that data loss for the first adjacent word line and the second adjacentword line occurs.[ 0065] Here, for the manner for determining the row hammer, related technologies maybe referred, so the details are not described in the embodiment of the present disclosure.[ 0066] In step S102, according to the row hammer refresh instruction, a preset rowhammer refresh signal is set to a valid state. The valid state of the preset row hammerrefresh signal indicates that the row hammer refresh instruction is performed in a firstrefresh period.[ 0067] It should be noted that, in the semiconductor memory device, a preset rowhammer refresh signal, specially used to instruct the Memory Array to perform the rowhammer refresh operation, is set. In other words, if the preset row hammer refresh signalis valid, the Memory Array needs to perform row hammer refresh for the specified wordlines, and if the preset row hammer refresh signal is invalid, the Memory Array does notneed to perform row hammer refresh.[ 0068] According to the row hammer refresh instruction, the preset row hammer refreshsignal is set to the valid state, so as to perform the refresh instruction in the first refreshperiod. Here, the refresh period may be understood as a time period for performing arefresh operation, and specifically refers to the time after the refresh command is receivedand before the next operation instruction is received, that is, one refresh period correspondsto one refresh command. The first refresh period may refer to the latest refresh period afterthe preset row hammer refresh signal is in the valid state.[ 0069] In step S103, in response to detecting that the row hammer refresh instruction isnot completed within the first refresh period, the valid state of the preset row hammerrefresh signal will be continued to the next refresh period of the first refresh period.[ 0070] It should be noted that, under normal cases, the first adjacent word line and thesecond adjacent word line can be refreshed within the first refresh period to complete therow hammer refresh instruction. However, if an occasional error occurs, the row hammerrefresh instruction may not be completed within the first refresh period, and the valid stateof the preset row hammer refresh signal needs to be continued to the next refresh period ofthe first refresh period, so as to complete the row hammer refresh instruction within tworefresh periods.[ 0071] It should be understood that, in a semiconductor memory device, not onlyrefresh periods but also other operation periods exist, so the first refresh period and thenext refresh period are not consecutive in time.[ 0072] In some embodiments, in response to detecting that the row hammer refreshinstruction is completed, the preset row hammer refresh signal is set to an invalid state.[ 0073] It should be noted that, if the row hammer refresh instruction is completed withinthe first refresh period, then the preset row hammer refresh signal is set to the invalid stateafter the end of the first refresh period. In this way, the row hammer refresh process iscompleted through one refresh command. On the contrary, if the row hammer refreshinstruction is not completed within the first refresh period, the valid state of the preset rowhammer refresh signal will be continued to the next refresh period of the first refreshperiod, so that the row hammer refresh process will be continued to be performed in thenext refresh period. In this way, the row hammer refresh process is completed through tworefresh commands.[ 0074] That is to say, in a related art, the valid state of the preset row hammer refreshsignal lasts for two refresh periods fixedly, so that one row hammer refresh instruction iscompleted in two refresh commands. However, in this way, a larger bandwidth is occupied,and resources are wasted. In another related art, the preset valid state of the row hammerrefresh signal lasts for one refresh period fixedly, so that one row hammer refreshinstruction is completed in one refresh command, but the refresh may fail due to anoccasional error.[ 0075] In the embodiments of the present disclosure, a method for refreshing rowhammer capable of automatic error correction is provided. Under normal cases, the validstate of the preset row hammer refresh signal lasts for one refresh period, so that the rowhammer refresh instruction is completed within one refresh period. In the case that anoccasional error occurs, the valid state of the preset row hammer refresh signal will becontinued to the next refresh period, so that the row hammer refresh instruction iscompleted through two refresh periods, which ican not only save bandwidth resources, butalso improve the correctness of row hammer refresh.[ 0076] It should also be noted that the row hammer refresh instruction instructs torefresh the first adjacent word line of the target word line and the second adjacent wordline of the target word line.[ 0077] Correspondingly, in some embodiments, the method may further include thefollowing operations.[ 0078] Whether the first adjacent word line and the second adjacent word line are bothrefreshed is determined in the first refresh period.[ 0079] If the first adjacent word line is refreshed and the second adjacent word line isnot refreshed, it is determined that the row hammer refresh instruction is not completedwithin the first refresh period.[ 0080] Alternatively, if the first adjacent word line and the second adjacent word lineare both refreshed, it is determined that the row hammer refresh instruction is completedwithin the first refresh period.[ 0081] That is to say, the row hammer refresh instruction includes refreshing the firstadjacent word line and the second adjacent word line on two sides of the target word linerespectively. Therefore, according to the refresh states of the first adjacent word line andthe second adjacent word line, it is determined whether the row hammer refresh instructionis completed in the first refresh period.[ 0082] In some embodiments, a first target state signal and a second target state signalare set and applied to record the states of the first adjacent word line and the secondadjacent word line, respectively. The method may also include the following operations.[ 0083] The first target state signal and the second target state signal are determined. Thefirst target state signal is configured to record the refresh state of the first adjacent wordline, and the second target state signal is configured to record the refresh state of the secondadjacent word line.[ 0084] When refreshing is conducted for the first adjacent word line, the first targetstate signal is set to the valid state, and the second target state signal is set to the invalidstate.[ 0085] When refreshing is conducted for the second adjacent word line, the first targetstate signal is set to the invalid state, and the second target state signal is set to the validstate.[ 0086] It should be noted that the initial states of the first target state signal and thesecond target state signal are both invalid. After receiving the row hammer refreshinstruction, the refreshing is performed for the first adjacent word line. At this time, thefirst target state signal jumps to be valid, and the second target state signal is still invalid.Finally, the refreshing is performed for the second adjacent word line. The first target statesignal jumps again to be invalid, the second target state signal jumps to be valid, and therow hammer refresh instruction is completed.[ 0087] In addition, after the row hammer refresh instruction is completed, the first targetstate signal and the second target state signal will be reset to the invalid state again. Thespecific reset process may be implemented by using circuits with various principles, whichwill not be described in the embodiments of the present disclosure.[ 0088] In addition to the above, the word line activation operation may be interposedbetween the refresh operation of the first adjacent word line and the refresh operation ofthe second adjacent word line. That is to say, only the refresh of the first adjacent wordline is completed within the first refresh period, and the word line activation instruction isreceived after the end of the first refresh period, thus entering the activation operationperiod, and then entering the next refresh period again. The operation on the secondadjacent word line is completed in the next refresh period. This case easily leads toprocessing errors, and the embodiments of the present disclosure record this caseseparately for subsequent processing. Exemplarily, in this case, the first target state signaland the second target state signal are both set to be invalid collectively.[ 0089] Therefore, in some embodiments, in a case of detecting that the row hammerrefresh instruction is not completed within the first refresh period, the method may furtherinclude the following operations.[ 0090] Whether the word line activation instruction is received is determined.[ 0091] If a determination result is yes, the first target state signal and the second targetstate signal are both set to be the invalid state.[ 0092] In this way, at the beginning of a certain refresh period, if the first target statesignal and the second target state signal are invalid, there are two possibilities: the previousrow hammer refresh instruction was completed normally, and the previous row hammerrefresh instruction was not completed and a word line activation instruction was received.It should be understood that the same process may be performed subsequently for the abovetwo possibilities, so no further subdivision is performed. At the beginning of a certainrefresh period, if the first target state signal is valid and the second target state signal isinvalid, the last row hammer refresh instruction is not completed and no word lineactivation instruction is received.[ 0093] In this way, whether the word line activation instruction is inserted in the middlewhen an occasional error occurs may be distinguished through the first target state signaland the second target state signal, so as to perform targeted processing subsequently.[ 0094] It should also be noted that the word line activation instruction may be anactivation instruction for any word line in the Memory Array, and is not limited to thetarget word line, the first adjacent word line and the second adjacent word line.[ 0095] In some embodiments, the method may also include the following operations.[ 0096] In a case that the preset row hammer refresh signal is in the valid state, the firsttarget state signal and the second target state signal are determined.[ 0097] Word line refresh processing is performed on adjacent word lines of the targetword line according to the first target state signal and the second target state signal.[ 0098] It should be noted that, when the preset row hammer refresh signal is valid, thespecific steps for performing the refresh processing need to be determined according to thefirst target state signal and the second target state signal.[ 0099] Specifically, the operation of performing the word line refresh processing onadjacent word lines of the target word line according to the first target state signal and thesecond target state signal may include the following operations.[ 00100] In a case that the first target state signal and the second target state signal areboth in the invalid state, the word line refresh processing is performed on the first adjacentword line and the second adjacent word line respectively.[ 00101] In a case that the first target state signal is in the valid state and the second targetstate signal is in the invalid state, the word line refresh processing is performed twice onthe second adjacent word line.[ 00102] It should be noted that in the case that an occasional error occurs, at thebeginning of the next refresh period, if the first target state signal and the second targetstate signal are both invalid, the refreshing is performed on the first adjacent word line andthe second adjacent word line respectively to avoid inserting the word line activationoperation during the refresh processes of the first adjacent word line and the secondadjacent word line. If the first target state signal is valid and the second target state signalis invalid, the refresh processing is performed twice on the second adjacent word line.[ 00103] In other words, for a certain refresh period, there are at least the following twocases.[ 00104] In the first case, at the beginning of a certain refresh period, the preset rowhammer refresh signal is in the valid state, and the first target state signal and the secondtarget state signal are both invalid. There are two possibilities for this case: (1) The rowhammer refresh instruction is received in the present refresh period. (2) The row hammerrefresh instruction was received in the previous refresh period, but the row hammer refreshinstruction was not completed in the previous refresh period due to the occasional error,and word line activation instruction is occurred between the previous refresh period andthe present refresh period. For the above two possibilities, it is necessary to performrefreshing on the first adjacent word line and the second adjacent word line in the presentrefresh period.[ 00105] In the second case, at the beginning of a certain refresh period, the preset rowhammer refresh signal is in the valid state, the first target state signal is valid, and thesecond target state signal is invalid, which indicates that the row hammer refreshinstruction is received in the previous refresh period of the present refresh period.However, due to an occasional error, the refreshing was only performed on the firstadjacent word line in the previous refresh period, and word line activation instruction wasnot received between the previous refresh period and the present refresh period. At thistime, the word line refresh processing may be directly performed on the second adjacentword line repeatedly, so that the row hammer refresh instruction that was not completed inthe previous refresh period is completed.[ 00106] Here, for the second case, the reasons for not choosing to perform refreshing onthe two word lines once respectively include: only one word line needs to be started whenrefreshing is performed on a certain word line twice. The process is simple, the powerconsumption is low, and the complexity of circuit design is reduced. For this section, pleaserefer to the subsequent description of the row hammer refresh circuit.[ 00107] Of course, in some other embodiments, a manner of performing refreshing onthe first adjacent word line and the second adjacent word line respectively may also beadopted in the second case.[ 00108] In addition, in the embodiments of the present disclosure, the definitions of thevalid state and the invalid state may be selected according to actual application scenarios.For example, the valid state of a certain signal may mean that the signal is at a high levelstate, the invalid state of a certain signal may mean that the signal is at a low level state, orthe valid state of a certain signal may mean that the signal is at a low level state, the invalidstate of a certain signal can mean that the signal is in a high level state.[ 00109] In view of above, the embodiments of the present disclosure provide a methodfor refreshing row hammer, which has the function of automatic error correction. Themethod for refreshing row hammer is accomplished by means of a preset row hammerrefresh signal, a first target state signal and a second target state signal. In this way, on theone hand, under normal cases, the valid state of the preset row hammer refresh signal lastsfor one refresh period, and the row hammer refresh instruction can be completed withinone refresh period. In the case that the occasional error occurs, the valid state of the presetrow hammer refresh signal will be continued to the next refresh period, so that the rowhammer refresh instruction is completed through two refresh periods, which not only savesbandwidth resources, but also ensures the smooth completion of the row hammer refresh.On the other hand, the first target state signal and the two target state signals are used torecord the refresh states of the first adjacent word line and the second adjacent word line,and determine whether the word line activation instruction is received after the firstadjacent word line is refreshed and before the second adjacent word line is refreshed, so asto perform targeted processing subsequently, avoid inserting the word line activationinstruction between the refreshing of the first adjacent word line and the refreshing of thesecond adjacent word line, and improve the correctness of the row hammer refresh.[ 00110] The embodiments of the present disclosure provide a method for refreshing rowhammer. A row hammer refresh instruction for a target word line is determined. Accordingto the row hammer refresh instruction, a preset row hammer refresh signal is set to a validstate. The valid state of the preset row hammer refresh signal indicates that the row hammerrefresh instruction is performed in a first refresh period. In response to detecting that therow hammer refresh instruction is not completed within the first refresh period, the validstate of the preset row hammer refresh signal will be continued to a next refresh period ofthe first refresh period. In this way, under normal cases, the valid state of the preset rowhammer refresh signal lasts for one refresh period, so that the row hammer refreshinstruction is completed through one refresh period. In the case that an occasional erroroccurs, the valid state of the preset row hammer refresh signal will be continued to the nextrefresh period, so that the row hammer refresh instruction is completed through two refreshperiods, which can not only save bandwidth resources, but also improve the correctness ofrow hammer refresh.[ 00111] In another embodiment of the present disclosure, referring to FIG. 4, it shows aschematic structural diagram of a circuit for refreshing row hammer 20 provided by theembodiments of the present disclosure. As shown in FIG. 4, the circuit for refreshing rowhammer 20 includes a detection circuit 21.[ 00112] The detection circuit 21 is configured to determine a row hammer refresh triggersignal RHRStart and a refresh execution signal, and output a preset row hammer refreshsignal RHR in a valid state in response to the row hammer refresh trigger signal RHRStartindicating that a row hammer refresh instruction for a target word line is received and therefresh execution signal indicating that the row hammer refresh instruction is notcompleted.[ 00113] It should be noted that the circuit for refreshing row hammer 20 provided by theembodiments of the present disclosure is applicable for a semiconductor memory device,such as DRAM, SDRAM, etc., which can better perform refreshing on the word linessubjected to row hammer.[ 00114] In the embodiments of the present disclosure, the circuit for refreshing rowhammer 20 includes a detection circuit 21. The input end of the detection circuit 21 is therow hammer refresh trigger signal RHRStart and the refresh execution signal, and theoutput end of the detection circuit 21 is the preset row hammer refresh signal RHRStart.The different states of the row hammer refresh trigger signal RHR can indicate whetherthe row hammer refresh instruction for the target word line is received, and the differentstates of the refresh execution signal can indicate whether the row hammer refreshinstruction is completed.[ 00115] Here, the valid state of the preset row hammer refresh signal RHR indicates thatthe row hammer refresh instruction is performed within the first refresh period, and thevalid state of the preset row hammer refresh signal RHR will be continued to a next refreshperiod of the first refresh period in a case that the row hammer refresh instruction is notcompleted within the first refresh period.[ 00116] That is to say, in a case that the row hammer refresh instruction for the targetword line is received and the row hammer refresh instruction is not completed, thedetection circuit 21 will be continued to output the preset row hammer refresh signal RHRin the valid state to instruct the memory array to perform the relevant row hammer refreshprocessing. In addition, in a case that the row hammer refresh instruction for the targetword line is not received, or the row hammer refresh instruction has been completed, thedetection circuit 21 will output a preset row hammer refresh signal RHR in the invalidstate. In this way, under normal cases, the valid state of the preset row hammer refreshsignal lasts for one refresh period, so that the row hammer refresh instruction is completedthrough one refresh period. In the case that an occasional error occurs, the valid state ofthe preset row hammer refresh signal will be continued to the next refresh period, so thatthe row hammer refresh instruction is completed through two refresh periods, which cannot only save bandwidth resources, but also improve the correctness of row hammerrefresh.[ 00117] Here, the row hammer refresh instruction instructs to perform word line refreshprocessing on the first adjacent word line of the target word line and the second adjacentword line of the target word line. That is, one row hammer refresh instruction includes twoword line refresh processes.[ 00118] In some embodiments, the refresh execution signal includes an initial refreshexecution signal Refreshpulse1 and a refresh pulse signal RefPulseCounter. The initialrefresh execution signal Refreshpulse1 is configured to indicate the word line refreshprocessing that occurs for the first time in each refresh period, and the refresh pulse signalRefPulseCounter is configured to indicate the word line refresh processing that occurs eachtime in the each refresh period.[ 00119] Correspondingly, referring to FIG. 5, it shows a schematic structural diagram ofa detection circuit 21 provided by the embodiments of the present disclosure. As shown inFIG. 5, the detection circuit 21 includes a first clock circuit 211, a first refresh statedetermination circuit 212 and a control signal output circuit 213.[ 00120] The first refresh state determination circuit 212 is configured to determine thefirst refresh state signal RHRState1 and the second refresh state signal RHRState2according to the row hammer refresh trigger signal RHRStart, the first clock signal RHRCkand the first inverted clock signal RHRCkN.[ 00121] The first clock circuit 211 is configured to determine the first clock signalRHRCk and the first inverted clock signal RHRCkN according to the first refresh statesignal RHRState1, the initial refresh execution signal Refreshpulse1 and the refresh pulsesignal RefPulseCounter.[ 00122] The control signal output circuit 213 is configured to determine the preset rowhammer refresh signal RHR according to the row hammer refresh trigger signal RHRStartand the second refresh state signal RHRState2.[ 00123] It should be noted that the detection circuit 21 at least includes the followingthree parts: the first clock circuit 211, the first refresh state determination circuit 212 andthe control signal output circuit 213.[ 00124] (1) The first clock circuit 211 is mainly configured to output the first clock signalRHRCk and the first inverted clock signal RHRCkN, so as to provide necessary signalsupport for the subsequent first refresh state determination circuit 212.[ 00125] Exemplarily, referring to FIG. 6, it shows a schematic diagram of a specificcircuit structure of the first clock circuit 211 provided by the embodiments of the presentdisclosure. As shown in FIG. 6, the first clock circuit includes a first two-input NAND gate2111, a second two-input NAND gate 2112 and a first NOT gate 2113.[ 00126] The input ends of the first two-input NAND gate 2111 are respectivelyconnected with the first refresh state signal RHRState1 and the initial refresh executionsignal Refreshpulse1. The input ends of the second two-input NAND gate 2112 arerespectively connected with the output end of the first two-input NAND gate 2111 and therefresh pulse signal RefPulseCounter. The output end of the second two-input NAND gate2112 is configured to output the first inverted clock signal RHRCkN. The input end of thefirst NOT gate 2113 is connected with the first inverted clock signal RHRCkN, the outputend of the first NOT gate 2113 is configured to output the first clock signal RHRCk.[ 00127] (2) The first refresh state determination circuit 212 is mainly configured tooutput the first refresh state signal RHRState1 and the second refresh state signalRHRState2, so as to record the refresh state of the first adjacent word line and the refreshstate of the second adjacent word line, so as to provide necessary signal support for thesubsequent control signal output circuit 213.[ 00128] Exemplarily, referring to FIG. 7, it shows a schematic diagram of a specificcircuit structure of a first refresh state determination circuit 212 provided by theembodiments of the present disclosure. As shown in FIG. 7, the first refresh statedetermination circuit 212 includes a first two-input NOR gate 2121, a third two-inputNAND gate 2122, a second NOT gate 2123, a first trigger 2124 and a second trigger 2125.[ 00129] The input ends of the first two-input NOR gate 2121 are respectively connectedwith the first refresh state signal RHRState1 and the second refresh state signal RHRState2,and the input ends of the third two-input NAND gate 2122 are respectively connected withthe output end of the first two-input NOR gate 2121 and the row hammer refresh triggersignal RHRStart. The input end of the second NOT gate 2123 is connected with the outputend of the third two-input NAND gate 2122. The input end of the first trigger 2124 isconnected with the output end of the second NOT gate 2123. The clock end of the firsttrigger 2124 is respectively connected with the first clock signal RHRCk and the firstinverted clock signal RHRCkN, and the output end of the first trigger 2124 is configuredto output the first refresh state signal RHRState1. The input end of the second trigger 2125is connected with the first refresh state signal RHRState1, the clock end of the secondtrigger 2125 is respectively connected with the first clock signal RHRCk and the firstinverted clock signal RHRCkN, and the output end of the second trigger 2125 is configuredto output the second refresh state signal RHRState2.[ 00130] In addition, the reset end of the first trigger 2124 and the reset end of the secondtrigger 2125 are both connected with a signal RST, which is used for resetting the firstrefresh state signal and the second refresh state signal.[ 00131] (3) The control signal output circuit 213 is mainly used for the preset rowhammer refresh signal RHR.[ 00132] Exemplarily, referring to FIG. 8, it shows a schematic diagram of a specificcircuit structure of the control signal output circuit 213 provided by the embodiments ofthe present disclosure. As shown in FIG. 8 , the control signal output circuit 213 includesa third NOT gate 2131, a fourth two-input NAND gate 2132 and a fourth NOT gate 2133.[ 00133] The input end of the third NOT gate 2131 is connected with the second refreshstate signal RHRState2, and the input ends of the fourth two-input NAND gate 2132 arerespectively connected with the output end of the third NOT gate 2131 and the row hammerrefresh trigger signal RHRStart. The input end of the fourth NOT gate 2133 is connectedwith the output end of the fourth two-input NAND gate 2132, and the output end of thefourth NOT gate 2133 is configured to output the preset row hammer refresh signal RHR.[ 00134] From the above, by means of of the first refresh state determination circuit 212,the first clock circuit 211 and the control signal output circuit 213, the first refresh statesignal RHRState1 and the second refresh state signal RHRState2 are determined accordingto the refresh execution signal Refreshpulse1, the refresh pulse signal RefPulseCounterand the row hammer refresh trigger signal RHRStart. Finally, the preset row hammerrefresh signal RHR is output.[ 00135] In a specific embodiment, for the above circuit, the initial refresh executionsignal Refreshpulse1 is in the valid state at the first pulse (the pulse is used to start the wordline) in the refresh period, and is in the invalid state at other times. The refresh pulse signalRefPulseCounter will generate a square wave at each pulse in the refresh period. RHRStartwill generate a rising edge after receiving the row hammer refresh instruction, and generatea falling edge after the end of the row hammer refresh instruction. The change mode ofother signals may be inferred from specific circuit elements.[ 00136] Exemplarily, a specific scenario is provided below to illustrate the signalprocessing logic of the first clock circuit 211, the first refresh state determination circuit212 and the control signal output circuit 213.[ 00137] Scenario description: for the row hammer refresh instruction, it is executednormally in the first pulse (1st pulse) in the first refresh period (that is, the refresh periodcorresponding to REFCmd1), but the second pulse (2nd pulse) is missing due to occasionalerrors, causing that only RHRa is executed in the first refresh period, and RHRa and RHRbneed to be executed once again in the next refresh period.[ 00138] Signal processing logic: referring to FIG. 9, it shows a schematic diagram of asignal timing sequence of a detection circuit 21 provided by the embodiments of the presentdisclosure.[ 00139] As shown in FIG. 9, firstly, after receiving the row hammer refresh instruction,RHRStart changes to a high level (that is, the valid state), and RHR changes to a high levelaccordingly, so as to indicate that refreshing is performed on the first adjacent word lineand the second adjacent word line.[ 00140] Next, at the 1st Pulse in the first refresh period, word line refresh processing isperformed on the first adjacent word line, i.e., RHRa. In addition, during 1st Pulse,Refreshpulse1 is at high level, and RefPulseCounter generates a square wave after theaddress of each Pulse is latched, causing the states of RHRCkN (not shown in the figure)and RHRCk output by the first clock circuit are changed, and the state of RHRState1changes after RHRCkN and RHRCk are processed by the first refresh state circuit.Specifically, RHRState1 changes from a low level to a high level in the process of RHRato record and complete the refresh of the first adjacent word line.[ 00141] Next, since the 2nd Pulse in the first refresh period is missing, RefPulseCountewill not generate a square wave again. Therefore, neither RHRState1 nor RHRState2 ischanged, and the valid states of RHRStart and RHR will be continued to the next refreshperiod (that is, the time after REFCmd2 command is received and before a new commandis received).[ 00142] Next, RHRa and RHRb are executed once at the 1st Pulse and 2nd Pulse in thenext refresh period, respectively. At this time, Refreshpulse1 is only at the high level stateduring the 1st Pulse, and RefPulseCounter generates a square wave for each Pulse, soRHRCkN and RHRCk change accordingly. At this time, RHRState1 will be changed fromhigh level to low level at the falling edge of the second square wave of RefPulseCounter.On the contrary, RHRState2 will be changed from low level to high level at the fallingedge of the second square wave of RefPulseCounter to indicate that the refresh of thesecond adjacent word line is completed.[ 00143] Finally, since RHRStart remains high level, RHRState2 is changed from lowlevel to high level, so the RHR signal is changed from high level to low level, andRHRStart will be changed from high level to high level together with the falling edge of2nd Pulse.[ 00144] In this way, in the case that an occasional error occurs, the valid state of thepreset row hammer refresh signal RHR will be continued to the next refresh period, so thatthe row hammer refresh instruction is completed through two refresh periods, which notonly saves bandwidth resources, but also improves the correctness of row hammer refresh.[ 00145] It should be understood that for row hammer refresh instruction, word lineactivation instruction needs to be avoided between refresh operation of the first adjacentword line and refresh operation of the second adjacent word line. That is to say, if a wordline activation instruction is received after refreshing the first adjacent word line and beforerefreshing the second adjacent word line, it needs to be recorded for subsequent processing.[ 00146] Therefore, in some embodiments, referring to FIG. 10, it shows a schematicstructural diagram of another circuit for refreshing row hammer 20 provided by theembodiments of the present disclosure. As shown in FIG. 10, the circuit for refreshing rowhammer 20 further includes a state counting circuit 22.[ 00147] The state counting circuit 22 is configured to receive the preset row hammerrefresh signal RHR and the word line state signal, and determine the first target state signalRHRAct1 and the second target state signal RHRAct2 according to the preset row hammerrefresh signal RHR and the word line state signal.[ 00148] It should be noted that the state counting circuit 22 is configured to output thefirst target state signal RHRAct1 and the second target state signal RHRAct2, so as torecord the current row hammer refresh processing. Specifically, the first target state signalRHRAct1 is configured to record the refresh state of the first adjacent word line, and thesecond target state signal RHRAct2 is configured to record the refresh state of the secondadjacent word line.[ 00149] In some embodiments, the word line state signal includes a refresh state validsignal Rfsh and a word line start pulse signal RasEnpulse. The refresh state valid signalRfsh indicates whether it is in a refresh period, and the word line start pulse signalRasEnpulse indicates starting of any word line.[ 00150] That is to say, if the Memory Array at is in a refresh period at current time, therefresh state valid signal Rfsh is in the valid state, and if the Memory Array is at currenttime in other operation periods such as activation, precharge, standby, etc., the refresh statevalid signal Rfsh is in the invalid state. In addition, the word line start pulse signalRasEnpulse generates a square wave during the starting of any word line.[ 00151] Correspondingly, referring to FIG. 11, it shows a schematic structural diagramof the state counting circuit 22 provided by the embodiments of the present disclosure. Asshown in FIG. 11, the state counting circuit 22 includes a second clock circuit 221, a secondrefresh state determination circuit 222 and a reset circuit 223.[ 00152] The second clock circuit 221 is configured to determine the second clock signalRHRCounter and the second inverted clock signal RHRCounterN according to the presetrow hammer refresh signal RHR, the refresh state valid signal Rfsh and the word line startpulse signal RasEnpulse.[ 00153] The reset circuit 223 is configured to determine a reset signal ResetN accordingto the refresh state valid signal Rfsh, the word line start pulse signal RasEnpulse and thefirst target state signal RHRAct1.[ 00154] The second refresh state determination circuit 222 is configured to determine thefirst target state signal RHRAct1 and the second target state signal RHRAct2 according tothe second clock signal RHRCounter, the second inverted clock signal RHRCounterN andthe reset signal ResetN.[ 00155] It should be noted that the state counting circuit 22 includes at least the followingthree parts: the second clock circuit 221, the second refresh state determination circuit 222and the reset circuit 223.[ 00156] (1) The second clock circuit 221 is mainly configured to output the second clocksignal RHRCounter and the second inverted clock signal RHRCounterN, so as to providenecessary signal support for the subsequent second refresh state determination circuit 222.[ 00157] Exemplarily, referring to FIG. 12, it shows a schematic diagram of a specificcircuit structure of the second clock circuit 221 provided by the embodiments of the presentdisclosure. As shown in FIG. 12, the second clock circuit 221 includes a first three-inputNAND gate 2211 and a fifth NOT gate 2212.[ 00158] The input ends of the first three-input NAND gate 2211 are respectivelyconnected with the preset row hammer refresh signal RHR, the refresh state valid signalRfsh and the word line start pulse signal RasEnpulse, and the output end of the first three-input NAND gate 2211 is configured to output the second inverted clock signalRHRCounterN. The input end of the fifth NOT gate 2212 is connected with the output endof the first three-input NAND gate 2211, and the output end of the fifth NOT gate 2212 isconfigured to output the second clock signal RHRCounter.[ 00159] (2) The second refresh state determination circuit 222 is mainly configured tooutput the first target state signal RHRAct1 and the second refresh state signal RHRAct2to record the refresh state of the first adjacent word line and the refresh state of the secondadjacent word line.[ 00160] Exemplarily, referring to FIG. 13, it shows a schematic diagram of a specificcircuit structure of the second refresh state determination circuit 222 provided by theembodiments of the present disclosure. As shown in FIG. 13, the second refresh statedetermination circuit 222 includes a third trigger 2221, a fourth trigger 2222 and a sixthNOT gate 2223.[ 00161] The input end of the third trigger 2221 is connected with the output end of thethird trigger 2221 through the sixth NOT gate 2223, and the output end of the third trigger2221 is configured to output the first target state signal RHRAct1. The clock end of thethird trigger 2221 is respectively connected with the second clock signal RHRCounter andthe second inverted clock signal RHRCounterN. The input end of the fourth trigger 2222is connected with the first target state signal RHRAct1, and the clock end of the fourthtrigger 2222 is respectively connected with the second clock signal RHRCounter and thesecond inverted clock signal RHRCounterN, and the output end of the fourth trigger 2222is configured to output the second target state signal RHRAct2. The reset end of the thirdtrigger 2221 and the reset end of the fourth trigger 2222 are both connected to the resetsignal ResetN.[ 00162] (3) The reset circuit 223 is mainly configured to output the reset signal ResetNto provide necessary signal support for the second refresh state determination circuit 222.[ 00163] Exemplarily, referring to FIG. 14, it shows a schematic diagram of a specificcircuit structure of the reset circuit 223 provided by the embodiments of the presentdisclosure. As shown in FIG. 14, the reset circuit 223 includes a seventh NOT gate 2231and a second three-input NAND gate 2232.[ 00164] The input end of the seventh NOT gate 2231 is connected with the refresh statevalid signal Rfsh, and the input ends of the second three-input NAND gate 2232 arerespectively connected with the output end of the seventh NOT gate 2231, the word linestart pulse signal RasEnpulse and the first target state signal RHRAct1, and the output endof the second three-input NAND gate 2232 is configured to output the reset signal ResetN.[ 00165] In particular, in the embodiments of the present disclosure, the reset signalResetN is valid at a low level. That is, when the reset signal ResetN is at a low level, thethird trigger 2221 and the fourth trigger 2222 are reset.[ 00166] It should be understood that the initial states of the first target state signalRHRAct1 and the second target state signal RHRAct2 are both invalid states. For the firsttarget state signal RHRAct1 and the second target state signal RHRAct2, the change logicis as follows.[ 00167] Under normal cases, in order to complete the row hammer refresh instruction,the refreshing of the first adjacent word line and the second adjacent word line need to becompleted in sequence in the first refresh period. At this time, when the first word line isstarted, the first target state signal RHRAct1 is changed to be valid, and the second targetstate signal RHRAct2 is still invalid. When the second word line is started, the first targetstate signal RHRAct1 is changed to be invalid, and the second target state signal RHRAct2is changed to be valid.[ 00168] In the case that an occasional error occurs, only the refreshing of the firstadjacent word line is completed within the first refresh period. Specifically, when the firstword line is started, the first target state signal RHRAct1 is changed to the valid state, andthe second target state signal RHRAct2 is still in the invalid state. Then, there are twopossibilities: (1) the word line activation instruction is not received between the firstrefresh period and the next refresh period, that is, the starting of word line does not existbetween the first refresh period and the next refresh period. In this way, at the beginningof the next refresh period, the first target state signal RHRAct1 remains valid, and thesecond target state signal RHRAct2 remains invalid. (2) The word line activationinstruction is received between the first refresh period and the next refresh period. Thestarting of word line exists between the first refresh period and the next refresh period, thereset signal ResetN is presented to be valid, and the first target state signal RHRAct1 andthe second target state signal RHRAct2 are both set to be invalid.[ 00169] In addition, after the row hammer refresh instruction is completed, the first targetstate signal RHRAct1 and the second target state signal RHRAct2 are both reset to theinvalid state, and the specific reset process may be implemented by circuits with variousprinciples, which is not described in the embodiments of the present disclosure.[ 00170] In this way, through the first target state signal RHRAct1 and the second targetstate signal RHRAct2, the refresh states of the first adjacent word line and the secondadjacent word line may be accurately recorded, and targeted refresh processing may beperformed subsequently to avoid that a word line activation instruction is inserted betweenthe refreshing of the word line and the refreshing of the second adjacent word line, resultingin an error problem.[ 00171] Based on the above circuit for refreshing row hammer, the preset row hammerrefresh signal RHR, the first target state signal RHRAct1 and the second target state signalRHRAct2 can be determined, and then a specific process of refreshing row hammer isdetermined according to these signals, including at least the following two cases.[ 00172] In the first case, at the beginning of a certain refresh period, the preset rowhammer refresh signal is in the valid state, the first target state signal is invalid and thesecond target state signal is invalid. There are two possibilities for this case: (1) the rowhammer refresh instruction is received in the present refresh period. (2) The row hammerrefresh instruction was received in the previous refresh period, but the row hammer refreshinstruction was not completed in the previous refresh period due to the occasional error,and word line activation instruction is occurred between the previous refresh period andthe present refresh period. For the above two possibilities, it is necessary to performrefreshing on the first adjacent word line and the second adjacent word line in the presentrefresh period.[ 00173] In the second case, at the beginning of a certain refresh period, the preset rowhammer refresh signal is in the valid state, the first target state signal is valid, and thesecond target state signal is invalid, which indicates that the row hammer refreshinstruction is received in the previous refresh period of the present refresh period.However, due to an occasional error, the refreshing was only performed on the firstadjacent word line in the previous refresh period, and word line activation instruction wasnot received between the previous refresh period and the present refresh period. At thistime, the word line refresh processing may be directly performed on the second adjacentword line repeatedly, so that the row hammer refresh instruction that was not completed inthe previous refresh period is completed.[ 00174] That is to say, based on the circuit for refreshing row hammer provided by theembodiments of the present disclosure, a method for completing the row hammer refreshin one refresh command (equivalent to one refresh period) with automatic error correctionare provided.[ 00175] (1) If the RHRb in the first refresh command is missing, the signal RHRrepresenting row hammer refresh will be continued to the next refresh command.[ 00176] (2) When an active command occurs between two refresh commands, the RHRstate counter (the first trigger and the second trigger) are reset. Specifically, if the RHRbin the first refresh command is missing, and the active command occurs between tworefresh commands, at this time, RHRAct1=1, Rfsh=0, and the storage array needs to startWL Pulse when executing the active command, thereby triggering RasEnPulse, and thenchanging the state of ResetN and resetting the RHR state counter.[ 00177] (3) RHRa and RHRb are completed in the second refresh command.[ 00178] In addition, if the RHRb in the first refresh command is missing, and the activecommand does not occur between the two refresh commands, then the RHRb is performedtwice in the second refresh command.[ 00179] In addition, FIG. 6-FIG. 8 and FIG. 11-FIG. 13 are only possible structures ofcorresponding circuits, and those skilled in the art may add, delete and modifycorresponding circuit elements according to the actual application scenarios of differentcircuits.[ 00180] In this way, the preset row hammer refresh signal can be provided by thedetection circuit, and the first target state signal and the second target state signal can beprovided by the state counting circuit, so as to implement the above method for refreshingrow hammer.[ 00181] The embodiments of the present disclosure provide a circuit for refreshing rowhammer. The circuit includes a detection circuit. The detection circuit is configured todetermine a row hammer refresh trigger signal and a refresh execution signal; and outputa preset row hammer refresh signal in a valid state in response to the row hammer refreshtrigger signal indicating that a row hammer refresh instruction for a target word line isreceived and the refresh execution signal indicating that the row hammer refreshinstruction is not completed. The valid state of the preset row hammer refresh signalindicates that the row hammer refresh instruction is performed within a first refresh period,and the valid state of the preset row hammer refresh signal will be continued to a nextrefresh period of the first refresh period in a case that the row hammer refresh instructionis not completed within the first refresh period. In this way, the preset row hammer refreshsignal can be provided through the detection circuit. Under normal cases, the valid state ofthe preset row hammer refresh signal lasts for one refresh period, so that the row hammerrefresh instruction is completed through one refresh period. In the case that an occasionalerror occurs, the valid state of the preset row hammer refresh signal will be continued tothe next refresh period, so that the row hammer refresh instruction is completed throughtwo refresh periods, which can not only save bandwidth resources, but also improve thecorrectness of row hammer refresh.[ 00182] In another embodiment of the present disclosure, referring to FIG. 15, it showsa schematic structural diagram of a semiconductor memory 30 provided by theembodiments of the present disclosure. As shown in FIG. 15, the semiconductor memory30 includes at least the circuit for refreshing row hammer 20.[ 00183] Since the semiconductor memory 30 includes at least the circuit for refreshingrow hammer 20, it can output a preset row hammer refresh signal. Under normal cases, thevalid state of the preset row hammer refresh signal lasts for one refresh period, so that therow hammer refresh instruction is completed through one refresh period. In the case thatan occasional error occurs, the valid state of the preset row hammer refresh signal will becontinued to the next refresh period, so that the row hammer refresh instruction iscompleted through two refresh periods, which can not only save bandwidth resources, butalso improve the correctness of row hammer refresh.[ 00184] The above are only preferred embodiments of the present disclosure, and are notintended to limit the protection scope of the present disclosure.[ 00185] It should be noted that, in the present disclosure, the terms “comprising”,“containing” or any other variation thereof are intended to encompass non-exclusiveinclusion, such that a process, method, object or device comprising a series of elementsincludes not only those elements, but also other elements not expressly listed or inherentto such a process, method, object or device. Without further limitation, an elementqualified by the phrase “comprising a...” does not preclude the presence of additionalidentical elements in a process, method, object or device that includes the element.[ 00186] The above serial numbers of the embodiments of the present disclosure are onlyfor description, and do not represent the advantages or disadvantages of the embodiments.[ 00187] The methods disclosed in the several method embodiments provided in thepresent disclosure may be combined arbitrarily without conflict to obtain new methodembodiments.[ 00188] The features disclosed in the several product embodiments provided in thepresent disclosure can be combined arbitrarily without conflict to obtain a new productembodiment.[ 00189] The features disclosed in several method or device embodiments provided in thepresent disclosure may be combined arbitrarily without conflict to obtain new methodembodiments or device embodiments.[ 00190] The above are only specific embodiments of the present disclosure, but theprotection scope of the present disclosure is not limited thereto. Any person skilled in theart who is familiar with the technical scope of the present disclosure can easily think ofchanges or substitutions, which should cover within the scope of protection of the presentdisclosure. Therefore, the protection scope of the present disclosure should be subject tothe protection scope of the claims.INDUSTRIAL APPLICABILITY[ 00191] The embodiments of the present disclosure provide a method for refreshing rowhammer, a circuit for refreshing row hammer and a semiconductor memory. The methodincludes the following operations. A row hammer refresh instruction for a target word lineis determined. According to the row hammer refresh instruction, a preset row hammerrefresh signal is set to a valid state. The valid state of the preset row hammer refresh signalindicates that the row hammer refresh instruction is performed in a first refresh period. Inresponse to detecting that the row hammer refresh instruction is not completed within thefirst refresh period, the valid state of the preset row hammer refresh signal will becontinued to a next refresh period of the first refresh period. In this way, under normalcases, the valid state of the preset row hammer refresh signal lasts for one refresh period,so that the row hammer refresh instruction is completed through one refresh period. In thecase that an occasional error occurs, the valid state of the preset row hammer refresh signalwill be continued to the next refresh period, so that the row hammer refresh instruction iscompleted through two refresh periods, which can not only save bandwidth resources, butalso improve the correctness of row hammer refresh.

Claims

1. A method for refreshing a row hammer, comprising:determining a row hammer refresh instruction for a target word line;setting, according to the row hammer refresh instruction, a preset row hammer refreshsignal to a valid state, wherein the valid state of the preset row hammer refresh signal indicatesthat the row hammer refresh instruction is performed in a first refresh period; andin response to detecting that the row hammer refresh instruction is not completed withinthe first refresh period, continuing the valid state of the preset row hammer refresh signal to anext refresh period of the first refresh period.

2. The method for refreshing the row hammer of claim 1, further comprising:in response to detecting that the row hammer refresh instruction is completed, settingthe preset row hammer refresh signal to an invalid state.

3. The method for refreshing the row hammer of claim 2, wherein the row hammer refreshinstruction instructs to refresh a first adjacent word line of the target word line and a secondadjacent word line of the target word line,wherein the method further comprises:determining whether the first adjacent word line and the second adjacent word line areboth refreshed in the first refresh period; andin response to the first adjacent word line being refreshed and the second adjacent wordline being not refreshed, determining that the row hammer refresh instruction is not completedwithin the first refresh period; orin response to the first adjacent word line and the second adjacent word line being bothrefreshed, determining that the row hammer refresh instruction is completed within the firstrefresh period.

4. The method for refreshing the row hammer of claim 3, further comprising:determining a first target state signal and a second target state signal, wherein the firsttarget state signal is configured to record a refresh state of the first adjacent word line, and thesecond target state signal is configured to record a refresh state of second adjacent word line;when refreshing is conducted for the first adjacent word line, setting the first target statesignal to the valid state, and setting the second target state signal to the invalid state; andwhen refreshing is conducted for the second adjacent word line, setting the first targetstate signal to the invalid state, and the second target state signal is set to the valid state.

5. The method for refreshing the row hammer of claim 4, in a case of detecting that the rowhammer refresh instruction is not completed within the first refresh period, wherein the methodfurther comprises:determining whether a word line activation instruction is received; andin response to a determination result being yes, setting both the first target state signaland the second target state signal to the invalid state.

6. The method for refreshing the row hammer of claim 5, further comprising:in a case that the preset row hammer refresh signal is in the valid state, determining thefirst target state signal and the second target state signal; andperforming word line refresh processing on adjacent word lines of the target word lineaccording to the first target state signal and the second target state signal.

7. The method for refreshing the row hammer of claim 6, wherein performing the word linerefresh processing on the adjacent word lines of the target word line according to the first targetstate signal and the second target state signal comprises:in a case that the first target state signal and the second target state signal are both in theinvalid state, performing the word line refresh processing on the first adjacent word line andthe second adjacent word line respectively; andin a case that the first target state signal is in the valid state and the second target statesignal is in the invalid state, performing the word line refresh process twice on the secondadjacent word line.

8. A circuit for refreshing a row hammer, comprising:a detection circuit, configured to:determine a row hammer refresh trigger signal and a refresh execution signal; andoutput a preset row hammer refresh signal in a valid state in response to the row hammerrefresh trigger signal indicating that a row hammer refresh instruction for a target word line isreceived and the refresh execution signal indicating that the row hammer refresh instruction isnot completed,wherein the valid state of the preset row hammer refresh signal indicates that the rowhammer refresh instruction is performed within a first refresh period, and the valid state of thepreset row hammer refresh signal will be continued to a next refresh period of the first refreshperiod in a case that the row hammer refresh instruction is not completed within the first refreshperiod.

9. The circuit for refreshing a row hammer of claim 8, wherein the refresh execution signalcomprises an initial refresh execution signal and a refresh pulse signal, correspondingly, thedetection circuit comprises a first clock circuit, a first refresh state determination circuit and acontrol signal output circuit,wherein the first refresh state determination circuit is configured to determine a firstrefresh state signal and a second refresh state signal according to the row hammer refresh triggersignal, a first clock signal and a first inverted clock signal,wherein the first clock circuit is configured to determine the first clock signal and thefirst inverted clock signal according to the first refresh state signal, the initial refresh executionsignal and the refresh pulse signal,wherein the control signal output circuit is configured to determine the preset rowhammer refresh signal according to the row hammer refresh trigger signal and the secondrefresh state signal,wherein the row hammer refresh instruction instructs to perform word line refreshprocessing on a first adjacent word line of the target word line and a second adjacent word lineof the target word line, and the initial refresh execution signal is configured to indicate a wordline refresh processing that occurs for a first time in each refresh period, and the refresh pulsesignal is configured to indicate a word line refresh processing that occurs each time in the eachrefresh period.

10. The circuit for refreshing a row hammer of claim 9, wherein the first clock circuit comprisesa first two-input NAND gate, a second two-input NAND gate and a first NOT gate,wherein input ends of the first two-input NAND gate are respectively connected withthe first refresh state signal and the initial refresh execution signal;wherein input ends of the second two-input NAND gate are respectively connected withan output end of the first two-input NAND gate and the refresh pulse signal, and an output endof the second two-input NAND gate is configured to output the first inverted clock signal;wherein an input end of the first NOT gate is connected with the first inverted clocksignal, and an output end of the first NOT gate is configured to output the first clock signal.

11. The circuit for refreshing a row hammer of claim 9, wherein the first refresh statedetermination circuit comprises a first two-input NOR gate, a third two-input NAND gate, asecond NOT gate, a first trigger and a second trigger,wherein input ends of the first two-input NOR gate are respectively connected with thefirst refresh state signal and the second refresh state signal, and input ends of the third two-inputNAND gate are respectively connected with an output end of the first two-input NOR gate andthe row hammer refresh trigger signal, and an input end of the second NOT gate is connectedwith an output end of the third two-input NAND gate,wherein an input end of the first trigger is connected with an output end of the secondNOT gate, and a clock end of the first trigger is respectively connected with the first clocksignal and the first inverted clock signal, and an output end of the first trigger is configured tooutput the first refresh state signal,wherein an input end of the second trigger is connected with the first refresh state signal,a clock end of the second trigger is respectively connected with the first clock signal and thefirst inverted clock signal, and the output end of the second trigger is configured to output thesecond refresh state signal.

12. The circuit for refreshing a row hammer of claim 9, wherein the control signal output circuitcomprises a third NOT gate, a fourth two-input NAND gate and a fourth NOT gate,wherein an input end of the third NOT gate is connected with the second refresh statesignal, and input ends of the fourth two-input NAND gate are respectively connected with anoutput end of the third NOT gate and the row hammer refresh trigger signal,wherein an input end of the fourth NOT gate is connected with an output end of thefourth two-input NAND gate, and an output end of the fourth NOT gate is configured to outputthe preset row hammer refresh signal.

13. The circuit for refreshing a row hammer of claim 9, wherein the circuit for refreshing a rowhammer further comprises a state counting circuit,wherein the state counting circuit is configured to receive the preset row hammer refreshsignal and the word line state signal, and determine a first target state signal and a second targetstate signal according to the preset row hammer refresh signal and the word line state signal,wherein the first target state signal is configured to record a refresh state of the firstadjacent word line, and the second target state signal is configured to record the refresh state ofthe second adjacent word line.

14. The circuit for refreshing a row hammer of claim 13, wherein the word line state signalcomprises a refresh state valid signal and a word line start pulse signal, and the state countingcircuit comprises a second clock circuit, a second refresh state determination circuit and a resetcircuit,wherein the second clock circuit is configured to determine a second clock signal and asecond inverted clock signal according to the preset row hammer refresh signal, the refresh statevalid signal and the word line start pulse signal,wherein the reset circuit is configured to determine a reset signal according to the refreshstate valid signal, the word line start pulse signal and the first target state signal,wherein the second refresh state determination circuit is configured to determine thefirst target state signal and the second target state signal according to the second clock signal,the second inverted clock signal and the reset signal,wherein the refresh state valid signal indicates whether a memory array is in a refreshperiod at current time, and the word line start pulse signal indicates starting of any word line.

15. The circuit for refreshing a row hammer of claim 14, wherein the second clock circuitcomprises a first three-input NAND gate and a fifth NOT gate,wherein input ends of the first three-input NAND gate are respectively connected withthe preset row hammer refresh signal, the refresh state valid signal and the word line start pulsesignal, and an output end of the first three-input NAND gate is configured to output the secondinverted clock signal,wherein an input end of the fifth NOT gate is connected with an output end of the firstthree-input NAND gate, and an output end of the fifth NOT gate is configured to output thesecond clock signal.

16. The circuit for refreshing a row hammer of claim 14, wherein the second refresh statedetermination circuit comprises a third trigger, a fourth trigger and a sixth NOT gate,wherein an input end of the third trigger is connected with an output end of the thirdtrigger through the sixth NOT gate, and the output end of the third trigger is configured to outputthe first target state signal, and a clock end of the third trigger is respectively connected withthe second clock signal and the second inverted clock signal,wherein an input end of the fourth trigger is connected with the first target state signal,a clock end of the fourth trigger is respectively connected with the second clock signal and thesecond inverted clock signal, and an output end of the fourth trigger is configured to output thesecond target state signal,wherein a reset end of the third trigger and a reset end of the fourth trigger are bothconnected with the reset signal.

17. The circuit for refreshing a row hammer of claim 14, wherein the reset circuit comprises aseventh NOT gate and a second three-input NAND gate,wherein an input end of the seventh NOT gate is connected with the refresh state validsignal, and input ends of the second three-input NAND gate are respectively connected with anoutput end of the seventh NOT gate, the word line start pulse signal and the first target statesignal, and an output end of the second three-input NAND gate is configured to output the resetsignal.

18. A semiconductor memory comprising the circuit for refreshing row hammer of any one ofclaims 8 to 17.

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