MATRIX-BASED DATA STORAGE AND PROCESSING SYSTEM

Abstract

The present invention is a matrix-based data storage and processing cell, consisting of independent matrix-based write (58), erase (61), and read (62) structures within the cell, as well as independent non-matrix-based write (59) and erase (60) structures. The aim of the project is to make accessing data easier and to provide parallel access-processing capability to data storage and processing systems. Transistors, resistors, diodes, and other circuit elements were used in the design of the matrix structure designed with logic gates and the system formed by combining these structures.

Description

1 TARIFF MATRIX-BASED DATA STORAGE AND PROCESSING SYSTEM Technical Field The invention relates to a matrix-based data storage and processing system. 10 State of the Technology Matrix-based data storage and processing systems have long been used in electronics and computers. It is used in the field of engineering, especially RAM (Random Access Memory) and ROM. In Read-Only Memory designs, matrix structures based on row and column logic are preferred. Traditional RAM types include dynamic RAM (DRAM) and static RAM (SRAM), as well as matrix RAM. It provides fast access to data using structures. In such structures, row and column addressing is used. Data access is provided using this method, employing address encoders and multiplexers. Direct addressing of the data is made possible. However, in order to increase data processing speed, matrix 20 is used in graphics processing units (GPUs). Computing models based on parallel computing logic have been developed for big data processing on GPUs. The sets are processed quickly. In such structures, matrix-based parallel processing capability is essential. high-performance computing such as graphics processing, artificial intelligence, and scientific computations It is widely used in applications. In current technologies, matrix structures are typically constructed using NAND and NOR gates. They are being designed with the aim of reducing transistor density and lowering power consumption. It is being optimized. However, traditional matrix-based systems have some limitations. Specifically, data loss, inadequate error prevention mechanisms, and complex addressing. These requirements are among the biggest shortcomings of these systems. In previous techniques, operations such as writing, reading, and deleting data were performed on rows and columns of the same 30 This is accomplished by triggering the process instantly, and its parallel access and processing capabilities remain limited. Furthermore, data integrity is compromised due to the lack of data security and error correction mechanisms. Problems can arise. This is especially true in big data processing and high reliability applications. It negatively impacts efficiency in applications that require it. 2 Other data storage systems currently in use on the market generally rely on serial access methods. For example, NAND flash memory and SSDs (Solid State Drives) rely on cellular structures. Instead, it works with data blocks, which can result in longer data access times. In addition, error correction codes are used in these systems to prevent data loss. However, this also increases the processing time. In conclusion, traditional matrix-based data storage systems aim to increase data speed and parallel 10 While widely used to enhance processing capabilities, error prevention inadequacies of mechanisms, data security issues, and addressing complexities, etc. It has limitations. Therefore, it offers faster access, higher security, and lower power consumption. Innovative matrix-based solutions that facilitate consumption are needed. Purpose of the Invention The invention enables parallel processing capabilities in matrix-based data storage and processing systems. It allows multiple data to be read, written, and deleted simultaneously. Traditional In matrix-based systems, data access typically occurs sequentially and individually, thus reducing processing speed. It is limited and performance is lost when working with large datasets. This invention, parallel processing 20 By increasing its capacity, it offers the possibility of accessing data simultaneously from multiple points, and thus It significantly increases data processing speed, especially for high-speed data flow and intensive processing. It provides a significant advantage in applications requiring power. To achieve this goal, matrix-based read, write, and erase operations are assigned to independent layers. They are separated, thus creating specialized paths for each operation. This structure allows more than 25 to be processed simultaneously. It enables the processing of large amounts of data while preventing data conflicts, ensuring security and accuracy. It enables the execution of operations. Additionally, it allows for independent writing and deleting that is not matrix-based. Adding these layers allows processes to be carried out in a more flexible and efficient manner. This makes it possible. Especially in data writing operations, different layers are possible thanks to independent layers. Simultaneous data writing to cells at the addresses is possible, thus shortening data access time. 30 Another aim of the invention is to make accessing data much easier and faster. Traditional matrix Addressing complexity and managing combinations in their structures is challenging. This problem... Sensitive triggering using logic gates and cross-connections to overcome this This is ensured. Cross lines make it possible to access all combinations of the matrix, and this This allows for more flexible addressing. Logic gates, on the other hand, only require 35. By triggering transistors, it prevents unnecessary energy consumption and increases efficiency. This 3 The intelligent triggering mechanism simplifies addressing operations, thus speeding up the process. 5 and makes data routing more efficient. In addition, data stability is ensured and the risk of data loss is reduced by using storage circuits. is eliminated. Storage circuits securely hold the data in the storage layer. It prevents data corruption during read and write operations. This is especially important. Parallel processing ensures data integrity while transferring data at high speeds. It includes storage circuits that also allow data to be used as temporary memory. This makes it possible and thereby improves the overall performance of the system. The innovative nature of the invention allows traditional matrix-based data storage and processing systems to... It offers a faster, safer, and more scalable solution by eliminating its disadvantages. By increasing parallel processing capacity, applications with high processing power can achieve 15% higher processing speed. Efficiency is achieved and multiple data points can be processed simultaneously, thus saving time. This is achieved by strengthening data routing capabilities and reducing addressing complexities. This eliminates the need for more flexible data processing and creates a more resilient environment. As a result, this invention provides a better understanding of data. Revolutionizing data storage and processing systems by providing fast, easy, and secure access. It offers an improvement and overcomes the limitations of traditional matrix structures, resulting in a more efficient 20 It demonstrates performance. Shapes Figure 1 shows a view of a cell in a matrix-based data storage and processing system. Figure 2 shows the appearance of the matrix-based write and erase structure. 25 Figure 3 shows the view of the matrix-based readout structure. Figure 4 shows the appearance of a non-matrix-based write and erase structure. Figure 5 shows a view of the storage structure. Description of Part References 30 1. GND source 2. Resistance 4 3. Logic Toggle 5 4. Diode 5. Transistor 6. Resistance 7. Logic Toggle 8. Transistor 10 9. Resistance 10. Logic Toggle 11. Resistance 12. VCC source 13. Diode 15 14. Transistor 15. Resistance 16. VCC source 17. Voltmeter 18. Resistance 20 19. GND source 20. GND source 21. Resistance 22. Transistor 23. VCC source 25 24. VCC source 25. Resistance 26. VCC source 27. Resistance 28. Transistor 30 29. Transistor 30. Transistor 31. Resistance 32. Resistance 33. Resistance 35 34. Logic Toggle 35. Logic Toggle 36. VCC source 37. Resistance 38. Transistor 40 39. Resistance 5 40. Logic Toggle 41. VCC source 42. VCC source 43. Resistance 44. Resistance 10 45. Resistance 46. ​​Resistance 47. Resistance 48. Transistor 49. Voltmeter 15 50. Transistor 51. Transistor 52. GND source 53. Capacitor 54. GND source 20 55. Resistance 56. GND source 57. Storage structure 58. Matrix-based writing structure 59. Non-matrix-based writing structure 25 60. Non-matrix-based deletion structure 61. Matrix-based deletion structure 62. Matrix-based reading structure 63. Transistor 64. VCC source 30 65. GND source Description of the Invention The invention includes at least one matrix-based read (62), write (58), erase (61) and non-matrix-based read (62), write (58), erase (61) operation. at least one data 35 which performs the data storage function with a small delete (60), write (59) part. It consists of a matrix cell (Figure 1) formed by the assembly of the storage circuit (57). 6 In this circuit, matrix-based write and erase operations require at least one transistor and other circuitry components. This is achieved using logic gates, which consist of specific elements. Logic gates are used to create certain elements. It controls access to storage cells by triggering them with combinations. Combinations ensure that data is written to the correct cell or deleted from the relevant cell. It was determined for this purpose. However, logic gates alone cannot capture all combinations. Since it could not be implemented, the circuit needed at least one transistor and 10 other auxiliary components. Cross-line connections have been added. These cross-line connections provide something that the matrix system alone cannot achieve. It enables complex combinations. For example, data can be simultaneously entered into diagonally located cells. Writing or erasing operations are performed thanks to these lines. In matrix-based write and erase operations, transistors other than the crossover line transistor (8) An AND gate is formed with (63 and 5). When this AND gate is triggered, the output 15 The configuration is activated with at least one transistor (14) and other auxiliary circuit elements (13). This structure triggers the relevant sections of the storage circuit to perform data writing or deletion operations. This ensures that matrix-based write and erase operations are performed correctly within the same circuit structure. It uses the write operation, which triggers the write portion of the storage circuit, while the erase operation... It triggers the erase portion of the storage circuit. The difference between them is that only the triggered portion is different. It is the fact that. Matrix-based read operation relies on row and column logic and therefore does not involve cross lines. It was not needed. The reading process involves reading multiple pieces of data simultaneously in parallel. It is based on the principle. In this circuit, at least one transistor (29 and 30) and other circuit elements are used. Logic gates were used. The reading process was first performed on all column (29) transistors 25 This is accomplished by opening and then triggering the transistors of row (30) in sequence. In this way, All data on the same line is read simultaneously. The read operation starts at the output of the storage circuit. It begins with reading the current data state. In this case, it is connected to the output of the storage circuit. and the structure consisting of at least one transistor (22) and other circuit elements is triggered. Then, this The output of the structure is located at the output of the matrix-based readout circuit and again at least one transistor (28) 30 It triggers the structure consisting of other circuit elements. Finally, the voltage produced is measured by the voltmeter (17) The reading process is completed when it is read aloud. A latch-based storage system (57) was used in the circuit for data storage. The latch system, Latch ensures stable data storage and prevents data loss during processing. The circuit is supported by a capacitor (53) to recover from its unstable state. The capacitor is 35 It balances any transient voltage fluctuations that may occur initially and ensures the latch circuit functions correctly. It enables triggering. The latch system has two different input pins and at least one transistor at its output. (48) and a structure is formed with other circuit elements. If no triggering signal is received 7 In these situations, the circuit remains in the passive state of "0". When the trigger signal arrives, the latch circuit activates. When triggered, "1" becomes active and in this state, it holds the data stably. Latch circuit, It maintains its current state and continues to store data unless a reset signal is received. Non-matrix-based write (59) and erase (60) constructs work similarly, and at least It was realized using structures consisting of a transistor (38) and other circuit elements. These non-matrix-based structures are used in situations where the matrix system has difficulty providing access. or used during operations with lower data density. Non-matrix based. The write operation is triggered via an independent write bus, sending the data to the storage circuit. It directs. Similarly, a non-matrix-based erase operation also uses an independent erase line. It cleans the data from the storage circuit via this method. This structure addresses the problems of the matrix-based system. In these situations, it ensures the circuit continues to function, while having a lower data density of 15 It enables the processes to work more efficiently. Industrial Application of the Invention The invention involves high-performance computing, artificial intelligence, data analytics, cloud storage, and embedded systems. This can occur across a wide range of sectors, such as systems and the defense industry. Especially in the fields of high-performance computing (HPC) and big data analytics, fast access to data is crucial. Access and parallel processing capability are required. This invention enables independent read, write, and erase layers. By offering the capacity to perform multiple operations simultaneously, it reduces calculation times. It shortens processing times and increases processing efficiency. Because of this feature, supercomputers are used in data centers. and can be used effectively in scientific computing platforms. Fast processing of large datasets in artificial intelligence (AI) and machine learning applications 25 There is a need to do this. This invention involves logic gates and cross-connections with precision. By triggering, it provides parallel access and processing capabilities for data and AI model training. It speeds up the processes. In addition, it provides data security and stability with latch circuits. protecting data integrity and enabling more accurate results in AI models. He knows. 30 In cloud storage and decentralized data management systems, data can be accessed quickly and securely. It is important that storage and processing are done in this way. This invention is based on cross-line and matrix-based non-matrix systems. It strengthens error prevention mechanisms and data security with independent layers. It also increases cloud-based storage with flexible addressing and data routing capabilities. 35 It provides. 8 In embedded systems and defense industry applications, low power consumption and high reliability 5 This invention requires less energy thanks to latch circuits and parallel processing capability. By spending money, it can process transactions at high speed and provides a high level of data security. Reliable data processing, especially in military communication systems, radar systems, and avionics devices. and meets the needs for quick access. Furthermore, SSDs and other modern data storage technologies overcome the limitations of traditional architectures. By eliminating this, it provides faster data reading and writing and less latency. with its features, the development of high-performance storage devices and modern processors and It can be used in the semiconductor industry to support graphics processing units. In conclusion, this invention enables high-speed data access, secure data processing, parallel processing capability, and Computing, artificial intelligence, cloud storage, embedded systems, and defense that require scalability 15 Modern data storage has a wide range of applications in industrial fields such as manufacturing. by being integrated into technologies, it provides increased efficiency, reliability and performance, and It offers innovative solutions in industry.

Claims

9 REQUESTS 1. The present invention accelerates access to data and enables the simultaneous processing of multiple data points. It is a data storage and processing system that enables; o At least one matrix-based write layer (58), erase layer (61) and read layer 5 (62) includes, o At least one non-matrix-based independent write layer (59) and erase layer (60) includes, at least one data storage facility to enable the storage and processing of data including circuit (57), 10 Write and erase circuits created using logic gates are transistors. It operates with a trigger mechanism based on the principle of operation. that matrix-based read operations in parallel with row-column addressing method to be carried out, 15 with cross-linking mechanisms and specific addressing combinations the creation of, and thus the activation of, the targeted cells, The logic gates are optimized to only trigger the target transistors. and prevent unnecessary energy consumption, To filter out parasitic signals and improve data accuracy in reading operations. It includes additional circuit elements. 20 2. The matrix-based writing structure mentioned in Claim 1 is (58), and its feature is that it uses transistors. installed (63 and 5), current limiting resistors (2, 6, 9, 11 and 15) and other circuit elements. It performs operations based on an AND gate supported by a row-column addressing system. implementing, AND gate to provide access to all data write combinations. A crossover line transistor (8) was added, causing the current to flow in the reverse direction and resulting in erroneous data writing. In order to avoid this, the write section of the storage circuit (57) which contains diodes (4 and 13) It is a structure characterized by its triggering effect.

3. The matrix-based erasure structure mentioned in Claim 1 is (61), and its feature is that it is made with transistors. formed (63 and 5), current limiting resistors (2, 6, 9, 11 and 15) and other circuitry. Row-column addressing operations based on AND gate supported by elements 30 AND enables access to all data deletion combinations through the system. A crossover line transistor (8) was added to its gate, causing the current to flow in the reverse direction and resulting in erroneous data writing. To avoid causing this, the delete stage of the storage circuit (57) contains diodes (4 and 13). It is a structure characterized by its triggering effect.

4. The matrix-based reading structure mentioned in Claim 1 is (62), and its feature is that it performs the reading operation. row and column AND gate based on transistors (22, 28, 29 and 30) It operates on the principle of activating a specified row, thereby deactivating the data in that row. Simultaneously readable, current-limiting resistors (18, 25, 27, 21, 31, 32 and 33) It is characterized by its ability to prevent erroneous data readings by preventing excessive current. It is a structure.

5. The non-matrix-based write structure mentioned in claim 1 is (59), and its feature is that it uses less data. When writing, a specific 10 can be written directly without opening the row and column lines of the matrix. energy saving by transferring data to the cell, occurring in a matrix structure Secures data writing against potential connection errors, bypassing them when necessary. designed to work integrated into a matrix system and optimized for low power consumption. It is a structure characterized by containing transistor structures (38).

6. The non-matrix-based deletion structure mentioned in Claim 1 is (60), and its feature is that it uses less data. 15 When deletion is needed, a specific cell can be deleted directly without opening the row and column lines of the matrix. By resetting, it saves energy and prevents connections that may occur in the matrix structure. secures data deletion in case of errors, and can be bypassed if necessary. transistors that can operate integrated with a matrix system and are optimized for low power consumption. It is a structure characterized by containing (38) structures. 20 Claim 7 refers to parallel data processing, where data can be deleted, read, and processed simultaneously. increasing data processing speed by ensuring all structures work simultaneously for writing. matrix-based and non-matrix-based systems containing independent pipelines for the purpose of Each operation is controlled independently by a control circuit that enables synchronized operation. Managing it through and error correction to prevent data conflicts during the process 25 It is a structure characterized by the inclusion of mechanisms.

8. Claim 1 refers to the simultaneous writing, reading, and deletion of multiple data, Its feature is the simultaneous access capability offered by matrix structures, allowing access on the same row or the same page. A parallel processing mechanism that allows simultaneous access to multiple data points in a column. Thanks to this, multiple data read, write, and delete operations can be synchronized in 30 steps. performs error checking algorithms to maintain data integrity during the process. including, optimizes the addressing system to prevent data conflicts, and the system It is characterized by offering high-performance data processing capabilities by increasing its overall speed. It is a structure that is created.

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