Apparatuses, methods and systems for instructions to multiply values of zero

Abstract

Systems, methods, and apparatuses relating to instructions to multiply values of zero are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number; and an execution circuit to execute the decoded single instruction to: cause a first comparison of the first number to a zero value in the number format of the first number, cause a second comparison of the second number to a zero value in the number format of the second number, provide as a resultant of the single instruction a value of zero when the second comparison indicates the second number equals the zero value in the number format of the second number, provide as the resultant of the single instruction the value of zero when the first comparison indicates the first number equals the zero value in the number format of the first number, and provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the zero value in the number format of the first number and the second comparison indicates the second number does not equal the zero value in the number format of the second number.

Description

[Technical Field]

[0001] This invention generally relates to electronic devices, and more specifically, embodiments of the invention relate to circuitry for implementing instructions for multiplying by zero. [Previous Technology]

[0002] A processor or a group of processors executes instructions from an instruction set (e.g., an instruction set architecture (ISA)). The instruction set is part of a programming-related computer architecture and typically includes native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" as used herein can refer to macro instructions, such as instructions provided to the processor for execution, or to microinstructions, such as instructions obtained by decoding macro instructions by the processor's decoder. [Summary of the Invention]

[0003] and

Implementation Method

[0004] Numerous specific details are set forth in the following description. However, it should be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0005] Embodiments described in the specification using references to "an embodiment," "an embodiment," "an exemplary embodiment," etc., may include specific features, structures, or characteristics, but each embodiment need not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, it is considered that incorporating other embodiments, whether explicitly described or not, to affect such feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0006] A processor (e.g., having one or more cores) (e.g., hardware) can execute instructions (e.g., instruction threads) to manipulate data, such as performing arithmetic, logical, or other functions. For example, software can request an operation, and the hardware processor (e.g., one or more of its cores) can perform the operation in response to the request. A non-limiting example of an operation is multiplication. For example, a computing system forming a neural network can include multiple multiplication operators where the multiplier value is zero and / or the multiplicand value is zero. Some embodiments herein allow skipping certain multiplication operations with zero values. Therefore, these embodiments allow skipping those multiplication operations for hardware performance and power optimization.

[0007] Operations can be performed on numerical data with different formats (e.g., representations) in a computing system (e.g., accelerators and / or processors). In some embodiments, the numbers are in fixed-point or floating-point format. Integers can be represented in binary format. Signed integers can be represented in two's complement format (e.g., where leading zeros represent positive integers and leading 1s represent negative integers). (e.g., real numbers) Numbers can be represented in floating-point format, for example, representing numbers of different orders of magnitude with a fixed number of digits.

[0008] An example of a number format is one where the number is typically approximated by a fixed number of significant digits (manifest numbers) and scaled using an exponent in a fixed radix (e.g., a radix of two, ten, or sixteen). An example of a number format where S represents the sign bit, M represents the mantissa, and E represents the exponent is shown below:

[0009] Examples of floating-point format are as follows:

[0010] According to the IEEE 754 standard for binary FP arithmetic, the mantissa is an unsigned number (e.g., a binary fraction), and the normalized floating-point number has a single one at the most significant bit (MSB) position. In some embodiments, this bit (e.g., to the left of the decimal point) is implicit, so the mantissa does not need to be stored. In some embodiments, the exponent is represented here as a non-negative integer minus a constant bias. Examples of floating-point formats are floating-point 16 (e.g., binary16), floating-point 32 (e.g., binary32), floating-point 64 (e.g., binary64), floating-point 128 (e.g., binary128), and floating-point 256 (e.g., binary256), although in some embodiments any number of sign, significant bits (e.g., its mantissa), or exponent bits can be used. In one embodiment, the binary16 format has one bit for the sign bit, five bits for the exponent, and 11 bits implicitly for the significant bits (10 bits explicitly stored). In one embodiment, the binary32 format has one bit for the sign bit, eight bits for the exponent, and 24 bits implicitly used for the significant digits (23 bits explicitly stored). In one embodiment, the binary64 format has one bit for the sign bit, 11 bits for the exponent, and 53 bits implicitly used for the significant digits (52 bits explicitly stored). In one embodiment, the binary128 format has one bit for the sign bit, 15 bits for the exponent, and 113 bits implicitly used for the significant digits (112 bits explicitly stored). In one embodiment, the binary256 format has one bit for the sign bit, 19 bits for the exponent, and 237 bits implicitly used for the significant digits (236 bits explicitly stored).

[0011] Some embodiments of neural networks (e.g., integer networks or floating-point networks) have many operations that include at least one zero input value. Therefore, for these neural networks (e.g., the circuitry implementing the neural network), hardware performance (e.g., power) optimization is achieved by effectively skipping multiplications that multiply by "zero".

[0012] The instruction format may include an operand (e.g., an appropriate subset of the operand) or other fields (e.g., operands or immediate values) to indicate that multiplications containing one or more "zero" values ​​will not be performed. The instruction format may include an operand (e.g., an appropriate subset of the operand) or other fields (e.g., operands or immediate values) to indicate that the result of the multiplication of a complex number of input values, any of which are zero, is zero (e.g., or the result of the product of a complex number of input values, all of which are zero, is exactly zero). In some embodiments, the numerical format of the instruction indicates when a value of "zero" is included in the instruction (e.g., as an operand or other field). In some embodiments, the multiplier used for multiplication is instead turned off (e.g., turned off or not turned on), thus saving power. Because the number of multiplications can be large (e.g., 10, 100, 1000, etc.), this power saving scales accordingly with the number of multipliers containing circuitry to provide the result of the multiplication of a pair of input values, any of which are zero. Instructions may include one or more of the fields discussed in this article (e.g., any).

[0013] The instructions disclosed herein are improvements to the functionality of the processor itself (e.g., a computer). An instruction decoding circuit (e.g., a decoder) that does not have such instructions as part of its instruction set will not decode as discussed herein. An execution circuit that does not have such instructions as part of its instruction set will not execute as discussed herein. For example, when a processor decodes a single instruction into a decoded instruction and executes the decoded instruction, a first comparison is made between a first number and a zero value in the number format of the first number, a second comparison is made between a second number and a zero value in the number format of the second number, and when the second comparison indicates that the second number is equal to the zero value in the number format of the second number, a value of zero is provided as the result of the single instruction; when the first comparison indicates that the first number is equal to the zero value in the number format of the first number, a value of zero is provided as the result of the single instruction; and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the second comparison indicates that the second number is not equal to the zero value in the number format of the second number, the product of the first number and the second number is provided as the result of the single instruction. Such a single instruction is an improvement to the functionality of the processor itself (e.g., a computer).

[0014] FIG1 shows a hardware processor 100 coupled to memory 110 according to an embodiment of the present invention. The depicted hardware processor 100 includes a hardware decoder 102 (e.g., a decoding unit or decoding circuit) and a hardware execution circuit 104 (e.g., an execution unit). The depicted hardware processor 100 includes a register 106. The register may include one or more registers for accessing (e.g., loading and / or storing) data in memory 110, for example, additionally or alternatively for accessing (e.g., loading or storing) data. The described hardware processor 100 includes cache memory 108. The cache memory may include one or more cache memory libraries for accessing (e.g., loading and / or storing) data in memory 110 and / or register 106, for example, additionally or alternatively for accessing (e.g., loading or storing) data.

[0015] The depicted execution circuitry 104 includes matrix operation circuitry 112, scalar circuitry 114, and / or vector / single instruction multiple data (SIMD) circuitry 116. In some embodiments, only one or any combination of matrix operation circuitry 112, scalar circuitry 114, and / or vector / single instruction multiple data (SIMD) circuitry 116 may be present (e.g., utilized). In some embodiments, matrix operation circuitry 112 operates on one or more matrices. In one embodiment, matrix operation circuitry 112 is an example of the matrix operation circuitry depicted in FIG3. Matrix operation circuitry 112 may be included in the core or as (e.g., external) an accelerator. In some embodiments, scalar circuitry 114 operates on scalar values ​​(e.g., single numbers). In some embodiments, vector / SIMD circuitry 116 operates on vector or compressed data values.

[0016] Note that the accompanying drawings may not depict all data communication connections. Those skilled in the art will recognize that this does not obscure certain details in the drawings. Note that bidirectional arrows in the drawings may not require bidirectional communication; for example, they may indicate unidirectional communication (e.g., to or from the stated element or device). In some embodiments herein, any or all combinations of communication paths may be utilized.

[0017] The hardware decoder 102 can receive (e.g., a single) instruction (e.g., a macro instruction) and decode the instruction into, for example, microinstructions and / or microoperations. The hardware execution circuitry 104 can execute the decoded instruction (e.g., a macro instruction) to perform one or more operations. For example, the instruction decoded by the decoder 102 and the decoded instruction to be executed by the execution circuitry 104 can be any instruction discussed herein (e.g., in Figures 6-8).

[0018] (One or more) multiplier circuits can be any of the multiplier circuits in Figures 2-7. Some embodiments herein relate to processors containing instructions in their instruction set that perform operations in response to a multiplication request. For example, when a processor decodes a single instruction into a decoded instruction and executes the decoded instruction, a first comparison is made between a first number and a zero value in the number format of the first number, a second comparison is made between a second number and a zero value in the number format of the second number, and when the second comparison indicates that the second number is equal to the zero value in the number format of the second number, a zero value is provided as the result of the single instruction; when the first comparison indicates that the first number is equal to the zero value in the number format of the first number, a zero value is provided as the result of the single instruction; and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the second comparison indicates that the second number is not equal to the zero value in the number format of the second number, a single instruction is provided as the result of the product of the first number and the second number.

[0019] The decoder 102, execution circuitry 104, temporary register 106, and / or cache memory 108 may be a single core of a processor, for example, and may include multiple cores, each having instances of the said circuitry. The processor (e.g., and its cores) may be a processor and / or core according to any disclosure herein.

[0020] FIG. 2A shows a circuit 200 according to an embodiment of the present invention, which includes a zero detector circuit 201 coupled to a zero multiplier circuit 228. In FIG. 2A, a digital format stores values ​​indicating the digital format of a first input digit 202 and / or a second input digit 204. In one embodiment, the digital format indicates to comparison circuits 220, 222 how (e.g., accurately) zero is represented in a particular digital format 218.

[0021] The depicted circuit 200 includes storage (e.g., flip-flops) for a first floating-point number 202 and a second floating-point number 204. The depicted format for the first floating-point number 202 is a single-bit sign field 206, a complex number of bits (e.g., eight or eleven bits) for the exponent field 208, and a complex number of bits (e.g., twenty-three or fifty-two bits) for the fraction field 210. The depicted format for the second floating-point number 204 is a single-bit sign field 212, a complex number of bits (e.g., eight or eleven bits) for the exponent field 214, and a complex number of bits (e.g., twenty-three or fifty-two bits) for the fraction field 216. In one embodiment, the sign bit is zero when the number represented in floating-point format is zero or positive, and one when the number represented in floating-point format is negative.

[0022] In some embodiments, the floating-point value indicating zero to the comparison circuit 220 by the number format 218 includes a zero value in the sign bit field 206 of the first number 202, a zero value in the exponent field 208 of the first number 202 (e.g., a complex number of zeros in each bit position of the full bit width of the exponent field), and a zero value in the fraction field 210 of the first number 202 (e.g., a complex number of zeros in each bit position of the full bit width of the fraction field) and / or the floating-point value indicating zero to the comparison circuit 222 includes a zero value in the sign bit field 212 of the second number 204, a zero value in the exponent field 214 of the second number 204 (e.g., a complex number of zeros in each bit position of the full bit width of the exponent field), and a zero value in the fraction field 216 of the second number 204 (e.g., a complex number of zeros in each bit position of the full bit width of the fraction field). In some embodiments, the digital format control circuit 200 (e.g., comparison circuits 220, 224) switches between different digital formats (e.g., modes), for example, for floating-point numbers as shown in FIG2A and for integers as shown in FIG2B.

[0023] In some embodiments, in response to a request caused by a decoding instruction, (i) the comparison circuit 220 is configured to compare a value specified as zero by the number format 218 of the first number 202, and, in one embodiment, through a plurality of comparisons by the comparison circuit 220, including a comparison of the zero value with the sign bit 206 of the first number 202, a comparison of the zero value with the exponent field 208 of the first number 202, a comparison of the zero value with the fraction field 210 of the first number 202, for example, and when the first number 202 is zero (e.g., when the zero value of the comparison circuit 220 is compared with the first number 202), the comparison circuit 220 is configured to compare a value specified as zero by the number format 218 of the first number 202, for example, a comparison of a value specified as zero by ... When all comparisons of the sign bit 206 of the first digit 202, the zero value, and the exponent field 208 of the first digit 202, and the fraction field 210 of the first digit 202, are true (not false), a first value (e.g., zero) is output. And when the first digit 202 is not zero (e.g., when any one of the comparisons of the zero value with the sign bit 206 of the first digit 202, the zero value with the exponent field 208 of the first digit 202, or the zero value with the fraction field 210 of the first digit 202 through the comparison circuit 220 is false (not true), the first value is output. (i) Different second values ​​(e.g., one), and (ii) the comparison circuit 222 is used to compare values ​​specified as zero by the number format 218 of the second number 204, and, in one embodiment, through a plurality of comparisons by the comparison circuit 222, including a comparison of the zero value with the sign bit 212 of the second number 204, a comparison of the zero value with the exponent field 214 of the second number 204, a comparison of the zero value with the fraction field 216 of the second number 204, for example, and when the second number 204 is a zero value (e.g., when the zero value of the comparison circuit 222 is compared with the sign bit 212 of the second number 204). When all comparisons of the zero value with the exponent field 214 of the second digit 204 and the fraction field 216 of the second digit 204 are true (not false), a first value (e.g., zero) is output. And when the second digit 204 is not zero (e.g., when any of the comparisons of the zero value of comparator 222 with the sign bit 212 of the second digit 204, the zero value with the exponent field 214 of the second digit 204, or the zero value with the fraction field 216 of the second digit 204 are false (not true), a different second value (e.g., one) is output. In Figure 2A, the outputs from comparator 220 and each of the comparator circuits 220 are input to logic gate 224 (e.g., so that the AND logic gate 224 asserts that its output 226 is only one when both inputs are one). For example, an AND gate 224 with an assertion value (e.g., one) when the first number 202 is not zero and the second number 204 is not zero.

[0024] In one of these embodiments, the output 226 from the AND logic gate 224 to the "zero" detector circuit 201 is input to the "zero" multiplier circuit 228, such that (i) when the first number 202 is not zero and the second number 204 is not zero, a zero (e.g., a constant, a constant of zero in a specified number format) from the zero output storage 234 is provided as output 236, and (ii) otherwise from the product output by multiplying the first number 202 and the second number 204 by the multiplier 230. In some embodiments, a different number format is provided to each comparator circuit.

[0025] In one embodiment, when the first number 202 is zero or the second number 204 is zero, the multiplier 230 is turned off (e.g., via power control switch 232), for example, to save power from not performing multiplication on the first floating-point number 202 and the second floating-point number 204.

[0026] FIG2B shows a circuit 200 in integer mode according to an embodiment of the present invention, which includes a zero detector circuit 201 coupled to a zero multiplier circuit 228. In FIG2B, the digital format storage indicates the value of the digital format of the first input digit 252 and / or the second input digit 254 (e.g., digits 252 and 254 are in the same storage as digits 202 and 204 used in FIG2A). In one embodiment, the digital format indicates to comparison circuits 220, 222 how (e.g., accurately) zero is represented in a particular digital format 218.

[0027] The depicted circuit 200 includes storage (e.g., flip-flops) for a first integer 252 and a second integer 254. The depicted format for the first integer 252 is a single-bit field (e.g., 32-bit or 64-bit or more). The depicted format for the second integer 254 is a single-bit field (e.g., 32-bit or 64-bit or more).

[0028] In some embodiments, the number format 218 indicates to the comparison circuit 220 that the integer value of zero is zero in all bit positions of the first number 252 (e.g., in contrast, the integer value of one includes one value in the least significant bit preceding a zero value (e.g., 00000001, an eight-bit integer width)) and / or indicates to the comparison circuit 222 that the integer value of zero is zero in all bit positions of the second number 254 (e.g., in contrast, the integer value of one includes one value in the least significant bit preceding a zero value (e.g., 00000001, an eight-bit integer width)). In some embodiments, the number format controls the circuit 200 (e.g., comparison circuits 220, 224) to switch between different number formats, for example, for floating-point numbers as shown in FIG. 2A and for integers as shown in FIG. 2B.

[0029] In some embodiments, in response to a request caused by a decoding instruction, (i) the comparison circuit 220 is configured to compare a value specified as zero by the number format 218 of the first number 252, for example, and outputs a first value (e.g., zero) when the first number 252 is zero, and (ii) the comparison circuit 222 is configured to compare a value specified as zero by the number format 218 of the second number 254, for example, and outputs a first value (e.g., zero) when the second number 254 is zero, and outputs a different second value (e.g., one) when the second number 254 is not zero. In FIG. 2B, the outputs from the comparison circuit 220 and each of the comparison circuits 220 are input to the logic gate 224 (e.g., so that the AND logic gate 224 asserts that its output 226 is only one when both inputs are one). For example, the AND logic gate 224 has an assertion value (e.g., one) when the first number 252 is not zero and the second number 254 is not zero.

[0030] In one of these embodiments, the output 226 from the AND logic gate 224 to the "zero" detector circuit 201 is input to the "zero" multiplier circuit 228 such that (i) when the first number 252 is zero or the second number 254 is zero, a zero from the zero output storage 234 (e.g., a constant zero specifying the number format) is provided as output 236, and (ii) the product of the multiplication of the first number 252 and the second number 254 through the multiplier 230 is output, otherwise. In some embodiments, a different number format is provided to each comparator circuit.

[0031] In one embodiment, when the first number 252 is zero or the second number 254 is zero, the multiplier 230 is turned off (e.g., via power control switch 232), for example, to save power from not performing multiplication on the first integer 252 and the second integer 254.

[0032] In FIG1, matrix operation circuit 112 includes one or more multiplier circuits 112A, scalar circuit 114 includes one or more multiplier circuits 114A, and vector / SIMD circuit 116 includes one or more multiplier circuits 116A. In some embodiments, any one or more multiplier circuits 112A, multiplier circuit 114A, or multiplier circuit 116A is an example of multiplier circuit 228 from FIG2A-2B, for example, having respective matrix operation circuit 112, scalar circuit 114, and vector / SIMD circuit 116 having instances of "zero" detector circuit 201 from FIG2A-2B.

[0033] FIG3 shows a matrix operation circuit 300 including a "zero" mode 350 according to an embodiment of the present invention. The depicted matrix operation circuit 300 includes a plurality of fused multiply-accumulate circuits (FMAs) 302 coupled together, such that in some embodiments, the outputs from some FMAs are passed as inputs to other FMAs.

[0034] For example, in some embodiments, the number of columns in the matrix (block A 304) matches the number of serial (chained) fused multiplier-accumulator (FMA) circuits that include the latency of computation. In some embodiments, each multiplier circuit is an instance of the "zero" multiplier circuit 228 of Figures 2A-2B, and for example, also includes a "zero" detector circuit 201. Optionally, mode selection 350 may include storage for "zero" number format.

[0035] One implementation allows for free recirculation on a grid of lower height, but the computation remains unchanged. In one embodiment, the source / destination vectors come from a tile of N columns (tile C 306), and the grid of FMA 302 performs N vector matrix operations, such that the complete instruction for performing matrix multiplication of a tile (with tile B 308) is another vector source, providing "broadcast" items to the FMA at each stage.

[0036] In operation, in some embodiments, the elements of matrix B (stored in tile B 603) are distributed across a rectangular grid of FMA. Matrix B (stored in tile A 601) transforms its column elements to match the column dimensions of the FMA rectangular grid. At each FMA in the grid, the elements of A and B are multiplied and added to the incoming summation term (e.g., from the FMA above), and then the outgoing sum is passed to the next column of the FMA (or the final output).

[0037] By including a "zero" mode 350, the matrix operation circuit 300 is controllable to allow or disallow the use of the "zero" mode. In some embodiments, a number format 352 defines when a value is "zero". In one embodiment, when the matrix operation circuit 300 is in "zero" mode, the output of the multiplication of a plurality of input values, any of which are zero, is exactly one; otherwise, the result is the actual result of the multiplication (e.g., the result will be suitable for storage provided for the result). In some embodiments, for a set of input values ​​containing at least one zero, the specific multiplier to be used for the corresponding multiplication operation is instead turned off (e.g., turned off or not turned on), thereby saving power. In some embodiments, when the matrix operation circuit 300 is not in "zero" mode, the result of the multiplication of a plurality of input values ​​is simply the actual result of the multiplication (e.g., the result will be suitable for storage provided for the result).

[0038] Figure 4 shows a circuit 400 according to an embodiment of the present invention, which includes a plurality of parallel "zero" multiplier circuits 406, 408, 410, 412 coupled to an adder circuit 414. As shown, a first compressed data (e.g., vector) source 402 A3-A0 and a second compressed data (e.g., vector) source 404 B3-B0 each have four compressed data elements. It should be understood that a single element or any plurality of elements may exist in circuit 400. In one embodiment, each of these elements is a floating-point number. The compressed data elements can be processed in parallel.

[0039] Each multiplier circuit 406, 408, 410, 412 may be an instance of the "zero" multiplier circuit 228 in Figures 2A-2B. Each multiplier circuit may include the "zero" detector circuit 201 in Figures 2A-2B. In some embodiments, a number format 452 defines when a value is "zero," for example, where the number format 452 is set by the execution of instructions as disclosed herein.

[0040] As shown in the figure, the first "zero" multiplier circuit 406 takes (i) element A3 from the first compressed data source 402 and (ii) element B3 from the second compressed data source 404 as inputs. As shown in the figure, the second "zero" multiplier circuit 408 takes (i) element A2 from the first compressed data source 402 and (ii) element B2 from the second compressed data source 404 as inputs. As shown in the figure, the third "zero" multiplier circuit 408 takes (i) element A1 from the first compressed data source 402 and (ii) element B1 from the second compressed data source 404 as inputs. As shown in the figure, the fourth "zero" multiplier circuit 412 takes (i) element A0 from the first compressed data source 402 and (ii) element B0 from the second compressed data source 404 as inputs.

[0041] When circuit 400 is in "zero" mode (e.g., set in storage 450 by execution of instructions disclosed herein), the result of multiplication for a pair of input values ​​that are not zero is the actual result of the multiplication (e.g., the result will be suitable for storage provided for the result), the result is zero when the second input value of the pair is zero, and the result is zero when the first input value of the pair is zero.

[0042] In some embodiments, for any set of input values ​​that is zero, the specific multiplier used for the respective multiplication operation is instead turned off (e.g., turned off or not turned on), thereby saving power. In some embodiments, when circuit 400 is not in "zero" mode, the result of the multiplication of a pair of input values ​​is simply the actual result of the multiplication (e.g., the result will be suitable for the provided storage for the result).

[0043] In one embodiment, setting a "zero" mode in storage 450 causes all (e.g., or an appropriate subset of all) multiplier circuits 406, 408, 410, 412 to be in "zero" mode. As discussed herein, multiplier circuits 406, 408, 410, 412 may (e.g., each) include an instance of the "zero" detector circuit 201 in Figures 2A-2B.

[0044] For example, when each multiplier circuit 406, 408, 410, 412 is in "zero" mode: when either A3 or B3 is zero (e.g., as determined by an example of the "zero" detector circuit 201 in Figures 2A-2B coupled between multiplier circuit 406 and the inputs from the first compressed data source 402 and the second compressed data source 404), multiplier circuit 406 outputs zero, and when neither A3 nor B3 is "zero", it outputs the actual result of the multiplication of A3 and B3; when either A2 or B2 is zero (e.g., as determined by an example of the "zero" detector circuit 201 in Figures 2A-2B coupled between multiplier circuit 408 and the inputs from the first compressed data source 402 and the second compressed data source 404), multiplier circuit 408 outputs zero, and when neither A2 nor B2 is "zero", it outputs the actual result of the multiplication of A3 and B3; when either A2 or B2 is zero (e.g., as determined by an example of the "zero" detector circuit 201 in Figures 2A-2B coupled between multiplier circuit 408 and the inputs from the first compressed data source 402 and the second compressed data source 404), multiplier circuit 408 outputs zero, and when neither A2 nor B2 is "zero", it outputs the actual result of the multiplication of A3 and B3. When A1 or B1 is zero, the multiplier circuit 410 outputs the actual result of multiplying A2 and B2. When either A1 or B1 is zero (as determined by an example of the zero detector circuit 201 in FIG. 2A-2B coupled between the inputs of the multiplier circuit 410 and the first compressed data source 402 and the second compressed data source 404), the multiplier circuit 410 outputs zero, and when neither A1 nor B1 is zero, the multiplier circuit 412 outputs the actual result of multiplying A1 and B1. When either A0 or B0 is zero (as determined by an example of the zero detector circuit 201 in FIG. 2A-2B coupled between the inputs of the multiplier circuit 412 and the first compressed data source 402 and the second compressed data source 404), the multiplier circuit 412 outputs zero, and when neither A0 nor B0 is zero, the multiplier circuit 412 outputs the actual result of multiplying A0 and B0.

[0045] In the described embodiment, the outputs of multiplier circuits 406, 408, 410, 412 are added together through adder circuit 414 to form a single (e.g., floating-point) number, and the single number is added through adder circuit 418 to an initial value (or intermediate result) 416 to produce a result 420. In one embodiment, multiplier circuits 406, 408, 410, 412 perform multiple iterations of multiplication, wherein intermediate results from adder circuit 414 are stored (e.g., accumulated) to intermediate result 416 and added to the next result of adder circuit 414.

[0046] Figure 5 shows a circuit 500 comprising a plurality of parallel "zero" multiplier circuits 506, 508, 510, 512 according to an embodiment of the present invention. As shown, the first compressed data (e.g., vector) source 502 A3-A0 and the second compressed data (e.g., vector) source 504 B3-B0 each have four compressed data elements. It should be understood that a single element or any plurality of elements may exist in circuit 500. In one embodiment, each of these elements is a floating-point number. The compressed data elements can be processed in parallel.

[0047] Each multiplier circuit 506, 508, 510, 512 may be an instance of the "zero" multiplier circuit 228 in Figures 2A-2B. Each multiplier circuit may include the "zero" detector circuit 201 in Figures 2A-2B. In some embodiments, a number format 552 defines when a value is "zero," for example, where the number format 452 is set by the execution of instructions as disclosed herein.

[0048] As shown in the figure, the first "zero" multiplier circuit 506 takes (i) element A3 from the first compressed data source 502 and (ii) element B3 from the second compressed data source 504 as inputs. As shown in the figure, the second "zero" multiplier circuit 508 takes (i) element A2 from the first compressed data source 502 and (ii) element B2 from the second compressed data source 504 as inputs. As shown in the figure, the third "zero" multiplier circuit 508 takes (i) element A1 from the first compressed data source 502 and (ii) element B1 from the second compressed data source 504 as inputs. As shown in the figure, the fourth "zero" multiplier circuit 512 takes (i) element A0 from the first compressed data source 502 and (ii) element B0 from the second compressed data source 504 as inputs.

[0049] When circuit 500 is in "zero" mode (e.g., set in storage 550 by execution of instructions disclosed herein), the result of multiplication of a pair of input values ​​that are not both zero is the actual result of the multiplication (e.g., the result will be suitable for storage provided for the result), the result is the first input value of the pair when the second input value of the pair is zero, and the result is the second input value of the pair when the first input value of the pair is zero.

[0050] In some embodiments, for any set of input values ​​that is zero, the specific multiplier used for the respective multiplication operation is instead turned off (e.g., turned off or not turned on), thereby saving power. In some embodiments, when circuit 500 is not in "zero" mode, the result of the multiplication of a pair of input values ​​is simply the actual result of the multiplication (e.g., the result will be suitable for the provided storage for the result).

[0051] In one embodiment, setting a "zero" mode in storage 550 causes all (e.g., or an appropriate subset of all) multiplier circuits 506, 508, 510, 512 to be in "zero" mode. As discussed herein, multiplier circuits 506, 508, 510, 512 may (e.g., each) include an instance of the "zero" detector circuit 201 in Figures 2A-2B. For example, when each multiplier circuit 506, 508, 510, 512 is in "zero" mode: when either A3 or B3 is zero (e.g., as determined by the example of the "zero" detector circuit 201 in Figures 2A-2B coupled between multiplier circuit 506 and the inputs from the first compressed data source 502 and the second compressed data source 504), multiplier circuit 506 outputs zero, and when neither A3 nor B3 is "zero", it outputs the actual result of the multiplication of A3 and B3; when either A2 or B2 is zero (e.g., as determined by the example of the "zero" detector circuit 201 in Figures 2A-2B coupled between multiplier circuit 508 and the inputs from the first compressed data source 502 and the second compressed data source 504), multiplier circuit 508 outputs zero, and when neither A2 nor B2 is "zero", The multiplier circuit 510 outputs the actual result of the multiplication of A2 and B2. When either A1 or B1 is zero (as determined by an example of the "zero" detector circuit 201 in FIG2A-2B coupled between the inputs of the first compressed data source 502 and the second compressed data source 504), the multiplier circuit 510 outputs zero, and when neither A1 nor B1 is zero, it outputs the actual result of the multiplication of A1 and B1. When either A0 or B0 is zero (as determined by an example of the "zero" detector circuit 201 in FIG2A-2B coupled between the inputs of the first compressed data source 502 and the second compressed data source 504), the multiplier circuit 512 outputs zero, and when neither A0 nor B0 is zero, it outputs the actual result of the multiplication of A0 and B0.

[0052] FIG6 shows a hardware processor 600 according to an embodiment of the present invention coupled to a storage 602 containing one or more "zero" multiplication instructions 604, the hardware processor 600 having a "zero" detector circuit 614 coupled to an execution circuit 616. In some embodiments, the "zero" multiplication instructions are as disclosed herein. In one embodiment, the "zero" multiplication instruction 604 includes a number format field 606 to indicate a number format as discussed herein.

[0053] In one embodiment, for example, in response to a request to perform an operation, an instruction (e.g., a macro instruction) is retrieved from storage 602 and sent to decoder 608. In the depicted embodiment, decoder 608 (e.g., decoder circuitry) decodes the instruction into decoded instructions (e.g., one or more microinstructions or microoperations). The decoded instructions are then sent for execution, for example, scheduled for execution via scheduler circuitry 610.

[0054] In some embodiments (e.g., where the processor / core supports out-of-order (OoO) execution), the processor includes a register renaming / allocator circuitry 610 coupled to register file / memory circuitry 612 (e.g., cells) to allocate resources and perform register renaming for registers (e.g., registers associated with the initial source and final destination of instructions). In some embodiments (e.g., for out-of-order execution), the processor includes one or more scheduler circuits 610 coupled to decoder 608. The scheduler circuitry can schedule one or more operations associated with decoded instructions, including one or more operations decoded from "zero" multiplication instruction 604, for example, for execution on execution circuitry 616. In the depicted embodiments, the zero detector circuit 614 is separate from the execution circuitry. For example, the zero detector circuit is located at the front end of the core (e.g., front-end unit 1230 in FIG. 12B) or between the register read / memory read phase (e.g., phase 1214 in FIG. 12A) and the execution phase (e.g., phase 1216 in FIG. 12A), for example, after retrieving an operand but before executing it. In some embodiments, the zero detector circuit 614 is an example of the zero detector circuit 201 in FIG. 2A-2B.

[0055] For example, the decoded "zero" multiplication instruction 604 is used to cause the first input operand and the second input operand (e.g., a corresponding pair of input operands from a compressed data source) to be compared with a value of zero by the "zero" detector circuit 614 (e.g., indicated by the digital format 606), and is used to cause (i) when either or both of the input values ​​of the pair are not zero, the result of the multiplication of the pair of input values ​​to be output as a zero value (e.g., by sending a zero value via bypass 622), and (ii) otherwise the result is the actual result of the multiplication by the multiplier circuit 618 (e.g., the result will be suitable for the provided storage for the result). In some embodiments, for a set of input values ​​containing at least one "zero" (e.g., only zero) value, the specific multiplier circuit 618 used for the multiplication operation is turned off (e.g., turned off or not turned on), thereby saving power. In another embodiment, instead of shutting down the execution circuit 616 (e.g., multiplier circuit 618) that is determined not to be used for multiplication involving one or more "zero" input values, it is used for calculations of different operations.

[0056] As another example, the decoded "zero" multiplication instruction 604 will cause the first and second input operands (e.g., a corresponding pair of input operands from a compressed data source) to be compared with zero values ​​(e.g., as indicated by the number format 606) respectively via the "zero" detector circuit 614, and cause (i) the output of the result of the multiplication of the pair of input values ​​that are both zero to be zero (e.g., by sending the value of zero via bypass 622), and (ii) otherwise, the result is the actual result of the multiplication via the multiplier circuit 618 (e.g., the result will be suitable for the provided storage for the result). In some embodiments, for a set of input values ​​that are both "zero", the specific multiplier circuit 618 to be used for the multiplication operation is turned off (e.g., turned off or not turned on), thereby saving power. In another embodiment, instead of turning off the execution circuit 616 (e.g., multiplier circuit 618) that is determined not to be used for "zero" input values, it is used for the calculation of different operations.

[0057] Each multiplier circuit 618 may be an instance of the "zero" multiplier circuit 228 in Figures 2A-2B. In some embodiments, the number format 606 defines when a value is zero, for example, where the number format 606 is set by instruction 604.

[0058] In some embodiments, a write-back circuit 620 is included to write the results of the instructions back to a destination (e.g., to temporary registers and / or memory), for example, making those results visible within the processor (e.g., visible outside the execution circuitry that produced those results). In one embodiment, the actual result is determined during the execution of instruction 604 (e.g., via execution unit 616), but after execution (e.g., after the execution phase), for example, in the write-back circuit 620 (e.g., during the write-back phase), the result is replaced with a value of zero (e.g., for the width of the result).

[0059] One or more of these elements (e.g., decoder 608, register renaming / register allocator / scheduler 610, execution circuitry 616, register (e.g., register archive) / memory 612, or write-back circuitry 620) may be located in a single core of the hardware processor (e.g., and multiple cores each have instances of these elements).

[0060] FIG7 illustrates a hardware processor 700 coupled to a storage containing one or more "zero" multiplication instructions 704 according to an embodiment of the present invention, the hardware processor having a "zero" detector circuit 716 of execution circuitry 714. In some embodiments, the "zero" multiplication instructions are according to any disclosed herein. In one embodiment, the "zero" multiplication instruction 704 includes a number format field 706 to indicate a number format as discussed herein.

[0061] In one embodiment, for example, in response to a request to perform an operation, an instruction (e.g., a macro instruction) is retrieved from storage 702 and sent to decoder 708. In the depicted embodiment, decoder 708 (e.g., decoder circuitry) decodes the instruction into decoded instructions (e.g., one or more microinstructions or microoperations). The decoded instructions are then sent for execution, for example, by scheduling the decoded instructions for execution via scheduler circuitry 710.

[0062] In some embodiments (e.g., where the processor / core supports out-of-order (OoO) execution), the processor includes a register renaming / allocator circuit 710 coupled to register file / memory circuitry 712 (e.g., a cell) to allocate resources and perform register renaming for registers (e.g., registers associated with the initial source and final destination of instructions). In some embodiments (e.g., for out-of-order execution), the processor includes one or more scheduler circuits 710 coupled to decoder 708. The scheduler circuitry can schedule one or more operations associated with decoded instructions, including one or more operations decoded from "zero" multiplication instruction 704, for example, to be executed on execution circuitry 714. In the depicted embodiments, "zero" detector circuitry 716 is located within execution circuitry 714, for example, in execution cluster 1260 in FIG. 12B. In some embodiments, "zero" detector circuitry 716 is an example of "zero" detector circuitry 201 in FIG. 2A-2B.

[0063] For example, the decoded "zero" multiplication instruction 704 is used to cause the first input operand and the second input operand (e.g., a corresponding pair of input operands from a compressed data source) to be compared with "zero" values ​​(e.g., as indicated by the number format 706) respectively through the "zero" detector circuit 716 of the execution circuit 714, and is used to cause (i) the result of the multiplication of the pair of input values ​​to be output as a zero value (e.g., by sending a single zero value as output without input to the multiplier circuit 718), and (ii) otherwise the result is the actual result of the multiplication through the multiplier circuit 718 (e.g., the result will be suitable for the provided storage for the result). In some embodiments, for a set of input values ​​containing at least one "zero" value, the specific multiplier circuit 718 used for the multiplication operation is turned off (e.g., turned off or not turned on), thereby saving power. In another embodiment, instead of shutting down the execution circuit multiplier circuit 718, which is determined not to be used for multiplication involving at least one "zero" input value, it is used for calculations of different operations.

[0064] As another example, the decoded "zero" multiplication instruction 704 will cause the first and second input operands (e.g., a corresponding pair of input operands from a compressed data source) to be compared with zero values ​​(e.g., as indicated by the number format 706) respectively via the "zero" detector circuit 716, and cause (i) the output of the result of the multiplication of the pair of input values ​​that are both zero to be zero (e.g., by sending the value of zero via bypass 722), and (ii) otherwise, the result is the actual result of the multiplication via the multiplier circuit 718 (e.g., the result will be suitable for the provided storage for the result). In some embodiments, for a set of input values ​​that are both zero, the specific multiplier circuit 718 to be used for the multiplication operation is turned off (e.g., turned off or not turned on), thereby saving power. In another embodiment, instead of turning off the multiplier circuit 718 that is determined not to be used for "zero" input values, it is used for the calculation of different operations.

[0065] Each multiplier circuit 718 may be an instance of the "zero" multiplier circuit 228 in Figures 2A-2B. In some embodiments, the number format 706 defines when a value is zero, for example, where the number format 706 is set by instruction 704.

[0066] In some embodiments, for example, a write-back circuit 720 is included to write the results of the instruction back to the destination (e.g., to a register and / or memory), for example, making those results visible to the processor (e.g., visible outside the execution circuitry that produced those results). In one embodiment, the actual result is determined during the execution of instruction 704 (e.g., via multiplier circuitry 718), but is replaced with a zero value (e.g., for the width of the result) after execution (e.g., after the execution phase), for example in the write-back circuit 720 (e.g., during the write-back phase).

[0067] One or more of these elements (e.g., decoder 708, register renaming / register allocator / scheduler 710, execution circuitry 714, register (e.g., register archive) / memory 712, or write-back circuitry 720) may reside in a single core of the hardware processor (e.g., and multiple cores, each with instances of these elements).

[0068] In some embodiments, the "zero" multiplication instruction does not have prior knowledge or indication that any of its input values ​​is one.

[0069] FIG8 illustrates a method for processing a "zero" multiplication instruction according to an embodiment of the present invention. A processor (e.g., or a processor core) may execute method 800, for example, in response to a request to execute instructions received from software. The described method 800 includes processing a "zero" multiplication instruction by: acquiring an instruction 802 having a first field identifying a first digit, a second field identifying a second digit, and a third field indicating the number format of the first and second digits; decoding the instruction into a decoded instruction 804; retrieving data 806 associated with the first, second, and third fields; (optionally) scheduling the decoded instruction for execution 808; executing the decoded instruction such that a first comparison is made between the first digit and a zero value in the number format of the first digit; a second comparison is made between the second digit and a zero value in the number format of the second digit; when the second comparison indicates that the second digit is equal to the zero value in the number format of the second digit, providing the value of zero as the result of a single instruction; when the first comparison indicates that the first digit is equal to the zero value in the number format of the first digit, providing the value of zero as the result of a single instruction; and when the first comparison indicates that the first digit is not equal to the zero value in the number format of the first digit and the second comparison indicates that the second digit is not equal to the zero value in the number format of the second digit, providing the product of the first and second digits as the result of a single instruction 810; and submitting the result of the executed instruction 812.

[0070] In one embodiment, the instruction is a compressed data (e.g., vector) instruction, wherein a first field identifies a first vector of numbers, a second field identifies a second vector of numbers, and the execution circuit executes a decoded single instruction to: perform a plurality of first comparisons between each number in the first vector of numbers and a zero value in the number format of the first vector of numbers; perform a plurality of second comparisons between each number in the second vector of numbers and a zero value in the number format of the second vector of numbers; and, as a result of the single instruction, provide a zero value for each of the plurality of second comparisons, the zero value indicating that the corresponding second number in the second vector of numbers is equal to the first vector of numbers. The zero value in the number format of the second vector of the number, as a result of the single instruction, provides the zero value for each of the plurality of first comparisons, the zero value indicating that the corresponding first number of the first vector of the number is equal to the zero value in the number format of the first vector of the number, and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the corresponding second comparison indicates that the second number is not equal to the zero value in the number format of the second number, as a result of the single instruction, the product of the first number of the first vector of the number and the corresponding second number of the second vector of the number is provided.

[0071] In the accompanying drawings (e.g., Figures 2 to 8), data can be loaded from and / or stored in a register / memory (e.g., only at the end of instruction execution). In some embodiments, the data source (input) and data destination (output) each have the same number of bits (e.g., and / or elements for compressing the data source / destination). In some embodiments, some or all of the data can be accessed in (e.g., system) memory. The input and output vector values ​​and sizes described herein are also exemplary, and other values ​​and sizes can be used. Data can be arranged in big-endian or little-endian order.

[0072] Exemplary architectures, systems, etc. that can be used in the above content are described in detail below.

[0073] At least some embodiments of the disclosed technology can be described with reference to the following examples: Example 1. A hardware processor comprising: a decoder for decoding a single instruction into a decoded single instruction having a first field identifying a first digit, a second field identifying a second digit, and a third field indicating the digit format of the first digit and the second digit; and execution circuitry for executing the decoded single instruction to: perform a first comparison of the first digit with a zero value of the digit format of the first digit; perform a second comparison of the second digit with a zero value of the digit format of the second digit; provide a value of zero as a result of the single instruction when the second comparison indicates that the second digit is equal to the zero value of the digit format of the second digit; provide a value of zero as a result of the single instruction when the first comparison indicates that the first digit is equal to the zero value of the digit format of the first digit; and provide a product of the first digit and the second digit as a result of the single instruction when the first comparison indicates that the first digit is not equal to the zero value of the digit format of the first digit, and the second comparison indicates that the second digit is not equal to the zero value of the digit format of the second digit. Example 2. A hardware processor as in Example 1, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates that the first number is equal to the zero value in the number format of the first number or the second comparison indicates that the second number is equal to the zero value in the number format of the second number. Example 3. A hardware processor as in Example 2, wherein the multiplier for performing the multiplication is powered down in response to the first comparison indicating that the first number is equal to the zero value in the number format of the first number or the second comparison indicating that the second number is equal to the zero value in the number format of the second number. Example 4. A hardware processor as in Example 1, wherein the number format is provided as an immediate value of the single instruction. Example 5. A hardware processor as in Example 1, wherein the number format is indicated by the arithmetic code of the single instruction.Example 6. A hardware processor as in Example 1, wherein the first field identifies a first vector of digits, the second field identifies a second vector of digits, and the execution circuit executes the decoded single instruction to: perform a plurality of first comparisons between each digit in the first vector of digits and a zero value in the number format of the first vector of digits; perform a plurality of second comparisons between each digit in the second vector of digits and a zero value in the number format of the second vector of digits; and, as a result of the single instruction, provide a zero value for each of the plurality of second comparisons, the zero value indicating that the corresponding second digit in the second vector of digits is equal to the zero value in the number format of the second vector of digits. As a result of the single instruction, a zero value is provided for each of the plurality of first comparisons, the zero value indicating that the corresponding first number of the first vector of the number is equal to the zero value in the number format of the first vector of the number, and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the corresponding second comparison indicates that the second number is not equal to the zero value in the number format of the second number, as a result of the single instruction, the product of the first number of the first vector of the number and the corresponding second number of the second vector of the number is provided. Example 7. The hardware processor of Example 1, wherein when the number format is a floating-point format for the first value and the second value, the first comparison compares the zero value with the sign bit of the first number, compares the zero value with the exponent field of the first number, and compares the zero value with the fraction field of the first number, while the second comparison compares the zero value with the sign bit of the second number, compares the zero value with the exponent field of the second number, and compares the zero value with the fraction field of the second number. Example 8. A hardware processor as in Example 1, wherein the first comparison and the second comparison are performed separately from the execution circuitry.Example 9. A method comprising: decoding a single instruction into a decoded single instruction using a decoder of a hardware processor, the single instruction having a first field identifying a first digit, a second field identifying a second digit, and a third field indicating the digit format of the first digit and the second digit; and executing the decoded single instruction using an execution circuit of the hardware processor to: perform a first comparison of the first digit with a zero value in the digit format of the first digit; perform a second comparison of the second digit with a zero value in the digit format of the second digit; provide a value of zero as a result of the single instruction when the second comparison indicates that the second digit is equal to the zero value in the digit format of the second digit; provide the value of zero as a result of the single instruction when the first comparison indicates that the first digit is equal to the zero value in the digit format of the first digit; and provide a product of the first digit and the second digit as a result of the single instruction when the first comparison indicates that the first digit is not equal to the zero value in the digit format of the first digit, and the second comparison indicates that the second digit is not equal to the zero value in the digit format of the second digit. Example 10. The method of Example 9, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates that the first number is equal to the zero value in the number format of the first number or the second comparison indicates that the second number is equal to the zero value in the number format of the second number. Example 11. The method of Example 10, wherein the multiplier for performing the multiplication is de-energized in response to the first comparison indicating that the first number is equal to the zero value in the number format of the first number or the second comparison indicating that the second number is equal to the zero value in the number format of the second number. Example 12. The method of Example 9, further comprising reading the number format from the immediate value of the single instruction. Example 13. The method of Example 9, further comprising determining the number format from the operand code of the single instruction.Example 14. The method of Example 9, wherein the first field identifies a first vector of digits, the second field identifies a second vector of digits, and the execution circuit executes the decoded single instruction to: perform a plurality of first comparisons between each digit in the first vector of digits and a zero value in the number format of the first vector of digits; perform a plurality of second comparisons between each digit in the second vector of digits and a zero value in the number format of the second vector of digits; and, as a result of the single instruction, provide a zero value for each of the plurality of second comparisons, the zero value indicating that the corresponding second digit in the second vector of digits is equal to the zero value in the number format of the second vector of digits. As a result of the single instruction, a zero value is provided for each of the plurality of first comparisons, the zero value indicating that the corresponding first number of the first vector of the number is equal to the zero value in the number format of the first vector of the number, and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the corresponding second comparison indicates that the second number is not equal to the zero value in the number format of the second number, as a result of the single instruction, the product of the first number of the first vector of the number and the corresponding second number of the second vector of the number is provided. Example 15. The method of Example 9, wherein when the number format is a floating-point format for the first value and the second value, the first comparison compares the zero value with the sign bit of the first number, compares the zero value with the exponent field of the first number, and compares the zero value with the fraction field of the first number, while the second comparison compares the zero value with the sign bit of the second number, compares the zero value with the exponent field of the second number, and compares the zero value with the fraction field of the second number. Example 16. The method of Example 9, wherein the first comparison and the second comparison are performed separately from the execution circuitry.Example 17. A non-transitory machine-readable medium storing code, said code, when executed by a machine, causing the machine to perform a method comprising: decoding a single instruction into a decoded single instruction using a decoder of a hardware processor, said single instruction having a first field identifying a first digit, a second field identifying a second digit, and a third field indicating the digit format of the first digit and the second digit; and executing said decoded single instruction using execution circuitry of the hardware processor to: perform a first comparison of the first digit with a zero value in the digit format of the first digit; perform a second comparison of the second digit with a zero value in the digit format of the second digit; and, when the second comparison indicates that the second digit is equal to the zero value in the digit format of the second digit, provide a value of zero as a result of said single instruction. When the first comparison indicates that the first number is equal to the zero value in the number format of the first number, the value of the zero is provided as the result of the single instruction; and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number, and the second comparison indicates that the second number is not equal to the zero value in the number format of the second number, the product of the first number and the second number is provided as the result of the single instruction. Example 18. A non-transitory machine-readable medium as in Example 17, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates that the first number is equal to the zero value in the number format of the first number or the second comparison indicates that the second number is equal to the zero value in the number format of the second number. Example 19. A non-transitory machine-readable medium as in Example 18, wherein the multiplier for performing the multiplication is powered off in response to the first comparison indicating that the first number is equal to the zero value in the number format of the first number or the second comparison indicating that the second number is equal to the zero value in the number format of the second number. Example 20. A non-transitory machine-readable medium, as in Example 17, further includes reading the digital format from an immediate value of the single instruction. Example 21. A non-transitory machine-readable medium, as in Example 17, further includes determining the digital format from the operand of the single instruction.Example 22. A non-transitory machine-readable medium as in Example 17, wherein the first field identifies a first vector of digits, the second field identifies a second vector of digits, and the execution circuit executes the decoded single instruction to: perform a plurality of first comparisons between each digit in the first vector of digits and a zero value in the number format of the first vector of digits; perform a plurality of second comparisons between each digit in the second vector of digits and a zero value in the number format of the second vector of digits; and, as a result of the single instruction, provide a zero value for each of the plurality of second comparisons, the zero value indicating that the corresponding second digit in the second vector of digits is equal to the zero value in the number format of the second vector of digits. As a result of the single instruction, a second number of the second vector of the number is provided for each of the plurality of first comparisons, indicating that the corresponding first number of the first vector of the number is equal to the zero value in the number format of the first vector of the number; and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the corresponding second comparison indicates that the second number is not equal to the zero value in the number format of the second number, as a result of the single instruction, the product of the first number of the first vector of the number and the corresponding second number of the second vector of the number is provided. Example 23. A non-transitory machine-readable medium as in Example 22, wherein when the number format is a floating-point format for the first value and the second value, the first comparison compares the zero value with the sign bit of the first number, compares the zero value with the exponent field of the first number, and compares the zero value with the fraction field of the first number, while the second comparison compares the zero value with the sign bit of the second number, compares the zero value with the exponent field of the second number, and compares the zero value with the fraction field of the second number. Example 24. A non-transitory machine-readable medium, such as in Example 17, wherein the first comparison and the second comparison are performed separately from the execution circuitry.

[0074] In yet another embodiment, a device includes a data storage means that stores code, which, when executed by a hardware processor, causes the hardware processor to perform any of the methods disclosed herein. A device may be as described in the detailed description. A method may be as described in the detailed description.

[0075] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit position) to specify, among other things, the operation to be performed (e.g., operand code) and the operands and / or other data fields (e.g., masking) to be executed by said operation. Some instruction formats are further subdivided through the definition of instruction templates (or subformats). For example, an instruction template for a given instruction format may be defined as a different subset of the fields of the instruction format (the fields included generally have the same order, but at least some have different bit positions because they contain fewer fields) and / or defined as given fields with different interpretations. Thus, each instruction of the ISA is represented by a given instruction format (and, if an instruction template is defined in said instruction format), and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific operand and an instruction format including an operand field to specify the operand and an operand field to select operands (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field for selecting specific operands. A set of SIMD extensions, called Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using Vector Extensions (VEX) encoding, has been released and / or publicly disclosed (e.g., see the Intel® 64 and IA-32 Architecture Software Developer's Manual, November 2018, and the Intel® Architecture Instruction Set Extensions Reference, October 2018). Exemplary instruction format

[0076] Embodiments of the instructions described herein may be embodied in different formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instructions may be executed in such systems, architectures, and pipelines, but are not limited to these detailed descriptions. General Vector Affinity Instruction Format

[0077] A vector affinity instruction format is an instruction format suitable for vector instructions (e.g., having certain fields specific to vector operations). Although the embodiments describe that both vector and scalar operations are supported through the vector affinity instruction format, alternative embodiments use vector operations only through the vector affinity instruction format.

[0078] Figures 9A-9B are block diagrams showing a general vector affinity instruction format and its instruction template according to an embodiment of the present invention. Figure 9A shows a block diagram of a general vector affinity instruction format and its Class A instruction template according to an embodiment of the present invention; while Figure 9B shows a block diagram of a general vector affinity instruction format and its Class B instruction template according to an embodiment of the present invention. Specifically, for the general vector affinity instruction format 900 that defines Class A and Class B instruction templates, both include a no-memory access 905 instruction template and a memory access 920 instruction template. The term "general" in the context of vector affinity instruction format refers to an instruction format that is not associated with any particular instruction set.

[0079] Although embodiments of the present invention will be described in a vector affinity instruction format supporting the following functions: 64-byte vector operand length (or size) has a width (or size) of 32-bit (4-byte) or 64-bit (8-byte) data elements (therefore, a 64-byte vector consists of 16 double-word size elements or alternatively, 8 quad-word size elements); 64-byte vector operand length (or size) has a width (or size) of 16-bit (2-byte) or 8-bit (1-byte) data elements; 32-byte vector operand length (or size) has a width (or size) of 32-bit (4-byte) data elements. The width (or size) of data elements can be 32 bits (4 bytes), 64 bits (8 bytes), 16 bits (2 bytes), or 8 bits (1 byte); and the length (or size) of a 16-byte vector operand can be 32 bits (4 bytes), 64 bits (8 bytes), 16 bits (2 bytes), or 8 bits (1 byte); however, alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., 256-byte vector operands) and more, fewer, or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0080] The A-type instruction templates in Figure 9A include: 1) the no-memory access 905 instruction template, which displays the no-memory access, full rounding control operation 910 instruction template and the no-memory access, data conversion operation 915 instruction template; and 2) the memory access 920 instruction template, which displays the memory access, temporary 925 instruction template and the memory access, non-temporary 930 instruction template. The B-type instruction templates in Figure 9B include: 1) the no-memory access 905 instruction template, which displays the no-memory access, write mask control, partial rounding control operation 912 instruction template and the no-memory access, write mask control, VSIZE operation 917 instruction template; and 2) the memory access 920 instruction template, which displays the memory access, write mask control 927 instruction template.

[0081] The general vector affinity instruction format 900 includes the following columns listed in sequence below, as shown in Figures 9A-9B.

[0082] Format field 940 - A specific value (instruction format identifier value) in this field uniquely identifies the vector affinity instruction format, thus allowing instructions of the vector affinity instruction format to appear in the instruction stream. Therefore, this field is optional because it does not require an instruction set that only has a general vector affinity instruction format.

[0083] Basis operation field 942 - its content distinguishes different basis operations.

[0084] Register Index Field 944 - Its contents, generated directly or via address, specify the source and destination operand locations, whether in a register or memory. These include a sufficient number of bits to select N registers from P×Q register files (e.g., 32x512, 16x128, 32x1024, 64x1024). While in one embodiment N may be up to three source and one destination registers, alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources may be supported, where one of these sources also serves as a destination; up to three sources may be supported, where one of these sources also serves as a destination; up to two sources and one destination may be supported).

[0085] Modifier field 946 – Its content distinguishes between memory accesses and those instructions in the general vector instruction format that do not specify memory accesses; that is, it lies between the no-memory-access 905 instruction template and the memory-access 920 instruction template. Memory access operations read and / or write to memory levels (in some cases, using values ​​in registers to specify source and / or destination addresses), while non-memory-access operations do not (e.g., source and destination are registers). Although this field also selects three different ways to perform memory address calculations in the embodiment, alternative embodiments may support more, fewer, or different ways to perform memory address calculations.

[0086] Enhanced Operation Field 950 – Its content is differentiated to perform various different operations in addition to basic operations. This field is context-dependent. In embodiments of the invention, the field is divided into a type field 968, an alpha field 952, and a beta field 954. The enhanced operation field 950 allows common groups of operations to be executed in a single instruction, instead of using 2, 3, or 4 instructions.

[0087] Scaling field 960 - Its contents allow scaling of the index field contents used for memory address generation (e.g., for address generation, it uses 2 scaling * exponent + base).

[0088] Displacement field 962A - Its contents are part of the memory address generation (e.g., for address generation it uses 2 scaling * exponent + base + displacement).

[0089] The displacement coefficient field 962B (note that the parallel existence of displacement field 962A directly exceeding displacement coefficient field 962B indicates that one or more are used) – its contents are part of the address generation; it specifies the displacement coefficient that is scaled through the size (N) of the memory access – where N is the number of bytes in the memory access (e.g., for address generation, it uses a displacement of 2 scaling * exponent + base + scaling). Redundant low-order bits are ignored, therefore, the contents of the displacement coefficient field are multiplied by the total size (N) of the memory operands to produce the final displacement for use in calculating the effective address. The value of N is determined by the runtime processor hardware based on the complete operation code field 974 (described later) and the data processing field 954C. Displacement fields 962A and 962B are optional; they are not used in the no-memory-access 905 instruction template and / or different embodiments may implement only one or neither.

[0090] Data element width field 964 - Its content distinguishes the width of several data elements to be used (in some embodiments for all instructions; in other embodiments for only some instructions). This field is optional and not required if only one data element width is supported and / or the data element width is supported using certain types of operation codes.

[0091] Write mask field 970 - its content is controlled on a per-data-bit basis, regardless of whether the data-bit position in the destination vector operand reflects the results of the base operation and the enhancement operation. Type A instruction templates support merge mask writes, while Type B instruction templates support merge mask writes and zero-mask writes. When merged, vector masking allows any set of elements in the destination to avoid being updated during the execution of any operation (specified by the base operation and the enhancement operation); in another embodiment, when the corresponding mask bit is 0, the old value of each element in the destination is preserved. Conversely, zero-vector masking allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the enhancement operation); in one embodiment, when the corresponding mask bit has a 0 value, the element in the destination is set to 0. A subset of this functionality controls the ability of the vector length of the operation to be executed (i.e., the span of the element is modified from the first to the last); however, this is not necessary, as the modified elements are contiguous. Therefore, the write mask field 970 allows local vector operations, including loading, storing, arithmetic, logic, etc. While embodiments of the invention are described, wherein the content selection of the write mask field 970 includes one of several write mask registers for the write mask to be used (thus the content of the write mask field 970 indirectly identifies the mask to be executed), alternative embodiments instead or additionally allow the content of the mask write field 970 to directly specify the mask to be executed.

[0092] Immediate field 972 - Its content allows for direct specifications. This field is optional; it does not exist in implementations that do not support the direct generic vector affinity format, nor does it exist in implementations that do not use direct instructions.

[0093] Type field 968 - Its content distinguishes different types of instructions. Referring to Figures 9A-B, the content of this field selects between type A and type B instructions. In Figures 9A-B, rounded squares are used to indicate specific values ​​present in the field (e.g., type field 968 in Figures 9A-B is type A 968A and type B 968B, respectively). Type A instruction template

[0094] In the case of the non-memory access 905 instruction template of type A, the alpha field 952 is interpreted as the RS field 952A, the content of which distinguishes one of the different amplification operation types to be performed (for example, rounding 952A.1 and data conversion 952A.2 are respectively the instruction templates for no-memory access, rounding type operation 910 and no-memory access, data conversion type operation 915), while the beta field 954 distinguishes the specified type operation to be performed. In the no-memory access 905 instruction template, the scaling field 960, the shift field 962A, and the shift scaling field 962B do not exist. No-memory access instruction template - full rounding control type operation

[0095] In the no-memory access fully round-control type operation 910 instruction template, the beta field 954 is interpreted as the round control field 954A, the contents of which provide static rounding. Although the round control field 954A described in this embodiment includes a suppress all floating-point exception (SAE) field 956 and a round operation control field 958, alternative embodiments may support encoding these two concepts into the same field or only one of these concepts / fields (e.g., it may only have the round operation control field 958).

[0096] SAE field 956 - its content distinguishes whether exception reporting is disabled; when the content of SAE field 956 indicates that suppression is enabled, the given instruction does not report any kind of floating-point exception flag and does not propose any floating-point exception handler.

[0097] Rounding control field 958 – its contents distinguish one of a group of rounding operations to be performed (such as round up, round down, round to zero, and round to the nearest value). Therefore, the rounding control field 958 allows for a change in the rounding mode on a per-instruction basis. In an embodiment of the invention, the processor includes a control register for specifying the rounding mode, and the contents of the rounding control field 950 overwrite the value of the register. No memory access instruction template – Data conversion type operation

[0098] In the no-memory access data conversion type operation 915 instruction template, beta field 954 is interpreted as data conversion field 954B, the contents of which distinguish one of several data to be executed (e.g., no data conversion, mixing, broadcasting).

[0099] In the case of the Class A memory access 920 instruction template, the alpha field 952 is interpreted as the eviction implicit field 952B, the contents of which distinguish one of the eviction implicit fields to be used (in Figure 9A, temporary 952B.1 and non-temporary 952B.2 are used for memory access, designated as the temporary 925 instruction template and the memory access, non-temporary 930 instruction template, respectively), and the beta field 954 is interpreted as the data processing field 954C, the contents of which distinguish one of several data processing operations (also called primitives) to be performed (e.g., no manipulation; broadcast; source upcast; and destination downcast). The memory access 920 instruction template includes a scaling field 960, and optional displacement field 962A or displacement-scaling field 962B.

[0100] Vector memory instructions have translation support, performing vector loading and storage of vectors from memory. Similar to regular vector instructions, vector memory instructions transfer data to / from memory in data element segments. The actual elements transferred are determined by the content of the vector mask selected as the write mask. Memory Access Instruction Template – Temporary

[0101] Temporary data is data that may be reused soon and can benefit from high-speed access. However, hints and different processors can implement it in different ways, including ignoring hints entirely. Memory Access Instruction Template – Non-Temporary

[0102] Non-temporary data is data that is unlikely to be reused soon and does not benefit from first-order high-speed access, and should be prioritized for eviction. However, hints and different processors can implement it in different ways, including ignoring the hints entirely. Class B instruction template

[0103] In the case of the B-type instruction template, the alpha field 952 is interpreted as the write mask control (Z) field 952C, the contents of which distinguish whether the write mask controlled by the write mask field 970 should be merged or zeroed.

[0104] In the case of the non-memory access 905 instruction template in Class B, a portion of the beta field 954 is interpreted as the RL field 957A, the contents of which distinguish one of the different amplification operation types to be performed (e.g., rounding 957A.1 and vector length (VSIZE) 957A.2 specify for the memoryless access, write mask control, partial rounding control type operation 912 instruction template and the memoryless access, write mask control, VSIZE type operation 917 instruction template, respectively). The remainder of the beta field 954 distinguishes which specified types of operations will be performed. In the memoryless access 905 instruction template, the scaling field 960, the shift field 962A, and the shift scaling field 962B are not present.

[0105] In memoryless access, write mask control, partial round control type operation 910 instruction template, the remainder of beta field 954 is interpreted as round operation field 959A and exception event reporting is disabled (the given instruction does not report any form of floating-point exception flag and does not propose any floating-point exception handler).

[0106] Rounding control field 959A – Similar to rounding control field 958, its contents distinguish one of a set of rounding operations (e.g., round up, round down, round to zero, and round to the nearest value). Therefore, rounding control field 959A allows for changing the rounding mode on a per-instruction basis. In embodiments of the invention, where the processor includes a control register for specifying the rounding mode, the contents of rounding control field 950 overwrite the value of the register.

[0107] In the 917 instruction template for memoryless access, write mask control, and VSIZE-style operation, the remainder of the beta field 954 is interpreted as a vector length field 959B, the contents of which distinguish one of the several data vector lengths to be executed on it (e.g., 128, 256, or 512 bits).

[0108] In the case of the Class B memory access 920 instruction template, a portion of the beta field 954 is interpreted as a broadcast field 957B, the content of which distinguishes whether broadcast type data operation operations will be performed, while the remaining beta fields 954 are interpreted as vector length fields 959B. The memory access 920 instruction template includes a scaling field 960, and optional displacement fields 962A or displacement-scaling fields 962B.

[0109] Regarding the general vector affinity instruction format 900, the complete opcode field 974 shows that it includes the format field 940, the base operation field 942, and the data element width field 964. The embodiment also shows that the complete opcode field 974 includes all of these fields, and includes fewer than all of these fields that are not supported in the embodiment. The complete opcode field 974 provides the opcode.

[0110] The augmentation operation field 950, the data element width field 964, and the write mask field 970 allow these features to be specified on a per-instruction basis in a generic vector affinity instruction format.

[0111] Write the combination of the mask field and the data element width field to establish a type instruction that allows applying a mask based on different data element widths.

[0112] The various instruction templates found in Class A and Class B are advantageous for different situations. In some embodiments of the invention, different processors or different cores within a processor may support only Class A, only Class B, or both simultaneously. For example, a high-performance general-purpose out-of-order core for general computing may only support Class B, a core primarily for graphics and / or scientific (productivity) computing may only support Class A, and cores for both may support both simultaneously (of course, cores with some mixed templates and instructions from both types, rather than all templates and instructions from both types, are within the scope of the invention). Furthermore, a single processor may include multiple cores, all of which support the same type or different cores supporting different types. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores primarily for graphics and / or scientific computing may only support Class A, while one or more general-purpose cores may be high-performance general-purpose cores with out-of-order execution and register renaming for general computing, which only support Class B. Another processor without a separate graphics core may include one or more general-purpose sequential or out-of-order cores that simultaneously support both Class A and Class B. Of course, functionality from one type can also be implemented in other types in different embodiments of the invention. Programs written in high-level languages ​​will be converted (e.g., just-in-time compilation or static compilation) into various executable forms, including: 1) a format having unique instructions of the types supported by the destination processor for execution; or 2) a format having alternative constants written using different combinations of instructions of all types and a format having control flow coding that selects said constants for execution based on instructions supported by the processor currently executing the code. Exemplary vector affinity instruction format

[0113] FIG10 is a block diagram showing an exemplary specific vector affinity instruction format according to an embodiment of the present invention. FIG10 shows a specific vector affinity instruction format 1000, which is specific to the specified position, size, interpretation, and order of fields, as well as the values ​​used for those fields. The specific vector affinity instruction format 1000 can be used to extend the x86 instruction set, and therefore certain fields are similar to or identical to those used in the existing x86 instruction set and its extensions (e.g., AVX). This format maintains consistency with pre-encoded fields, actual operand bit tuple fields, MOD R / M fields, SIB fields, shift fields, and existing direct fields with extended x86 instruction sets. The field mapping from FIG9 to the field system of FIG10 is shown.

[0114] It should be understood that although the embodiments of the present invention are for illustrative purposes, and a particular vector affinity instruction format 1000 is described by reference in the context of a general vector affinity instruction format 900, the present invention is not limited to the particular vector affinity instruction format 1000 unless claimed. For example, the general vector affinity instruction format 900 covers various fields of various possible sizes, while the particular vector affinity instruction format 1000 is displayed as a field of a particular size. By way of specific example, while the data element width field 964 is displayed as a one-bit field in the particular vector affinity instruction format 1000, the present invention is not so limited (i.e., the general vector affinity instruction format 900 envisions other sizes for the data element width field 964).

[0115] The general vector affinity instruction format 900 includes the following fields listed in the following order as shown in Figure 10A.

[0116] EVEX front (bytes 0-3) 1002 – encoded in 4-byte form.

[0117] Format field 940 (EVEX byte 0, bits [7:0]) - The first byte (EVEX byte 0) is format field 940, which contains 0x62 (a unique value used in embodiments of the invention to distinguish vector affinity instruction formats).

[0118] The second to fourth bytes (EVEX bytes 1-3) include several bit fields that provide specific capabilities.

[0119] REX field 1005 (EVEX byte 1, bits [7-5]) - consists of the EVEX.R bit field (EVEX byte 1, bits [7]-R), the EVEX.X bit field (EVEX byte 1, bits [6]-X), and the 957BEX byte 1, bits [5]-B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as their corresponding VEX bit fields and are encoded using the complement of 1, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields of the instruction encode the lower three bits of the register index as known in the field (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0120] REX' field 910 - This is the first part of REX' field 910 and is the EVEX.R' bit field (EVEX byte 1, bit [4]-R'), which is used to encode the higher 16 or lower 16 of the extended 32 register group. In embodiments of the invention, the bit, along with others as shown below, is stored in bit-inverted format to distinguish it from the BOUND instruction (in the well-known x86 32-bit mode), whose actual operand byte is 62, but does not accept the value 11 in the MOD field in the MOD R / M field (described below); alternative embodiments of the invention do not store this and the other inverted format bits indicated below. The value 1 is used to encode the lower 16 register. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R and other RRR to form other fields.

[0121] Operation code mapping field 1015 (EVEX byte 1, byte [3:0]-mmmm) - its content encoding implicit dominant operation code byte (0F, 0F 38 or 0F 3).

[0122] Data element width field 964 (EVEX byte 2, bit [7]-W) - represented by the symbol EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32-bit data element or 64-bit data element).

[0123] EVEX.vvvv 1020 (EVEX byte 2, bits [6:3]-vvvv)-EVEX.vvvv may have the following functions: 1) EVEX.vvvv encodes the first source register operands, specified in inverted (two's complement) form and valid for two or more source operand instructions; 2) EVEX.vvvv encodes the destination register operands, specified in two's complement form for certain vector shifts; or 3) EVEX.vvvv does not encode any operands, the field is reserved and should contain 1111b. Therefore, the EVEX.vvvv field 1020 encodes the 4 least significant bits of the first source register specifier stored in inverted (two's complement) form. Additional distinct EVEX bit fields are used, depending on the instruction, to extend the specifier size to 32 registers.

[0124] EVEX.U 968 Type field (EVEX byte 2, byte [2]-U) - If EVEX.U=0, it indicates class A or EVEX.U0; if EVEX.U=1, it indicates class B or EVEX.U1.

[0125] Prefix encoding field 1025 (EVEX byte 2, bits [1:0]-pp) - provides additional bits for the base operation field. Besides providing support for legacy SSE instructions with EVEX prefix format, this also has the benefit of compressing SIMD prefixes (instead of requiring bytes to represent the SIMD prefix, which only requires 2 bits). In one embodiment, legacy SSE instructions using SIMD prefixes (66H, F2H, F3H) are supported in both legacy and EVEX prefix formats, these legacy SIMD prefixes being encoded into the SIMD prefix encoding field; and at runtime, they are extended to the legacy SIMD prefixes before being provided to the PLA of the decoder (so the PLA can execute both legacy instructions and their EVEX formats without modification). While newer instructions can directly use the contents of the EVEX prefix encoding field as an extension of the operand, some embodiments unfold in a similar manner for consistency, but allow different meanings to be specified through these legacy SIMD prefixes. Alternative embodiments can redesign the PLA to support 2-bit SIMD pre-coding, and therefore no extension is required.

[0126] alpha field 952 (EVEX byte 3, bit [7]-EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control and EVEX.N; also shown as α) - This field is context-specific as previously described.

[0127] beta field 954 (EVEX byte 3, bits [6:4]-SSS, also known as EVEX.s2-0, EVEX.r2-0, EVEX.rr1, EVEX.LL0, EVEX.LLB; also shown as βββ) - This field is context-specific as previously described.

[0128] REX' field 910 – It is the remainder field of REX' and the EVEX.V' bit field (EVEX byte, 3 bits [3]-V') which can be used to encode the higher 16 or lower 16 of the extended 32 register group. The bits are stored in bit-inverted format. A value of 1 is used to encode the lower 16 registers. In other words, V'VVVV is formed by combining EVEX.V' and EVEX.vvvv.

[0129] Write mask field 970 (EVEX byte 3, bits [2:0]-kkk) - its content specifies the index of the register in the write mask register as described above. In embodiments of the invention, specifying the value EVEX.kkk=000 has the implicit special behavior of no write mask being used for a particular instruction (which can be implemented in various ways, including by using write mask hardwired to bypass all or some of the masking hardware).

[0130] The actual operand field 1030 (byte 4) is also referred to as the operand byte. A portion of the operand is specified in this field.

[0131] MOD R / M field 1040 (byte 5) includes MOD field 1042, Reg field 1044, and R / M field 1046. As mentioned above, the content of MOD field 1042 distinguishes between memory access and non-memory access operations. The function of Reg field 1044 can be summarized in two cases: encoding destination register operands or source register operands, or being regarded as an extension of the operand code rather than being used to encode any instruction operands. The function of R / M field 1046 may include the following: encoding instruction operands that reference memory addresses or encode destination register operands or source register operands.

[0132] Scaling, Indexing, Base (SIB) Bytes (Byte 6) - As previously described, the contents of scaling field 950 are used for memory address generation. SIB.xxx 1054 and SIB.bbb 1056 - The contents of these fields have been previously mentioned with respect to register indices Xxxx and Bbbb.

[0133] Displacement field 962A (bytes 7-10) - When MOD field 1042 contains 10, bytes 7-10 are displacement fields 962A, which operate like the old 32-bit displacement (disp32) and operate at the byte granularity.

[0134] Displacement Factor Field 962B (Byte 7) - When MOD field 1042 contains 0 and 1, Byte 7 is displacement factor field 962B. The position of the field is the same as the old x86 instruction set 8-bit displacement (disp8), which operates at the byte granularity. Because disp8 is sign-extended, it can only be addressed by displacements between -128 and 127 bytes; on a 64-byte cache line, disp8 uses 8 bits that can be set to only 4 truly useful values: -128, -64, 0, and 64; since a larger range is usually required, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, displacement factor field 962B is a reinterpretation of disp8; when using displacement factor field 962B, the actual displacement is determined by multiplying the content of the displacement factor field by the size of the memory operand access (N). This type of displacement is called disp8 * N. This reduces the average instruction length (for displacement but with a larger range of single byte). This compact displacement system is based on the assumption of an effective displacement system at the granularity of multiple memory accesses; therefore, redundant low-order bit displacements of the address do not need to be encoded. In other words, the displacement coefficient field 962B replaces the 8-bit displacement of the old x86 instruction set. Therefore, the encoding of the displacement coefficient field 962B is the same as that of the 8-bit displacement of the x86 instruction set (thus the ModRM / SIB encoding rules remain unchanged), with the only exception of disp8 overload to disp8 * N. In other words, the encoding rules or encoding length remain unchanged, only the displacement value interpreted by the hardware (which requires obtaining the byte-by-byte address displacement from the memory operand size and scaling the displacement). Immediate field 972 is operated as previously described. All operand fields

[0135] Figure 10B is a block diagram showing a specific vector affinity instruction format 1000 constituting the complete operand field 974 according to an embodiment of the present invention. Specifically, the complete operand field 974 includes a format field 940, a base operand field 942, and a data element width (W) field 964. The base operand field 942 includes a pre-encoding field 1025, an operand mapping field 1015, and a real operand field 1030. (Temporary register index field)

[0136] Figure 10C is a block diagram showing the fields constituting a specific vector affinity instruction format 1000 of the register index field 944 according to an embodiment of the present invention. Specifically, the register index field 944 includes REX field 1005, REX' field 1010, MODR / M.reg field 1044, MODR / Mr / m field 1046, VVVV field 1020, xxx field 1054, and bbb field 1056. Enhanced operation field

[0137] Figure 10D is a block diagram showing the fields constituting a specific vector affinity instruction format 1000 of the enhanced operation field 950 according to an embodiment of the present invention. When the type (U) field 968 contains 0, it represents EVEX.U0 (Class A 968A); when it contains 1, it represents EVEX.U1 (Class B 968B). When U=0 and the MOD field 1042 contains 11 (representing no memory access operation), the alpha field 952 (EVEX byte 3, bits [7]-EH) is interpreted as the rs field 952A. When the rs field 952A contains 1 (rounding 952A.1), the beta field 954 (EVEX byte 3, bits [6:4]-SSS) is interpreted as the rounding control field 954A. The rounding control field 954A includes a one-bit SAE field 956 and a two-bit rounding operation field 958. When the rs field 952A contains 0 (data conversion 952A.2), the beta field 954 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a 3-bit data conversion field 954B. When U=0 and the MOD field 1042 contains 00, 01, or 10 (indicating memory access operations), the alpha field 952 (EVEX byte 3, bits [7]-EH) is interpreted as an evictory hidden (EH) field 952B and the beta field 954 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a 3-bit data processing field 954C.

[0138] When U=1, alpha field 952 (EVEX byte 3, bit [7]-EH) is interpreted as written to mask control (Z) field 952C. When U=1 and MOD field 1042 contains 11 (indicating no memory access operation), a portion of beta field 954 (EVEX byte 3, bit [4]-S0) is interpreted as RL field 957A; when it contains 1 (rounding 957A.1), the remainder of beta field 954 (EVEX byte 3, bit [6-5]-S2-1) is interpreted as rounding operation field 959A, and when RL field 957A contains 0 (VSIZE 957.A2), the remainder of beta field 954 (EVEX byte 3, bit [6-5]-S2-1) is interpreted as vector length field 959B (EVEX byte 3, bit [6-5]-L1-0). When U=1 and MOD field 1042 contains 00, 01, or 10 (indicating memory access operations), beta field 954 (EVEX byte 3, bits [6:4]-SSS) is interpreted as vector length field 959B (EVEX byte 3, bits [6-5]-L1-0) and broadcast field 957B (EVEX byte 3, bits [4]-B). Exemplary register architecture

[0139] FIG11 is a block diagram of a register architecture 1100 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 1110 with a width of 512 bits; these registers are referred to as zmm0 to zmm31. The lower 256 bits of the lower 16 zmm registers cover registers ymm0-16. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) cover registers xmm0-15. A specific vector affinity instruction format 1000 performs the operations shown in the table below on these covered register files. Adjustable vector length type Operations temporary register Instruction template excluding vector length field 959B A (Figure) 9A;U=0) 910,915,925,930 zmm temporary register (vector length is 64 bits) B (Figure) 9B;U=1) 912 zmm temporary register (vector length is 64 bits) Instruction template including vector length field 959B B (Figure) 9B;U=1) 917,927 The zmm, ymm, or xmm registers (vector length is 64 byte, 32 byte, or 16 byte) are specified according to the vector length field 959B.

[0140] In other words, the vector length field 959B is selected between the maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length; and instruction templates without the vector length field 959B operate with the maximum vector length. Furthermore, in one embodiment, the B-type instruction template of a specific vector affinity instruction format 1000 operates on compressed or scalar single / double precision floating-point data and compressed or scalar integer data. Scalar operations are performed at the lowest-order data element positions in the zmm / ymm / xmm registers; higher-order data element positions are the same as on the left, because they are zeroed in previous instructions or depending on the embodiment.

[0141] Write Mask Register 1115 - In the illustrated embodiment, there are eight write mask registers (k0 to k7), each 64 bits in size. In an alternative embodiment, write mask register 1115 is 16 bits in size. As previously described, in one embodiment of the invention, vector mask register k0 cannot be used as a write mask; when encoded, k0 is typically instructed to be used as a write mask, selecting a hardwired write mask of 0xFFFF, effectively disabling the write mask for the instruction.

[0142] General-purpose registers 1125 - In the illustrated embodiment, there are 16 64-bit general-purpose registers used in conjunction with the existing x86 addressing mode to address memory operands. These registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0143] Scalar Floating Point Stack Register File (x87 Stack) 1145, on which is aliased MMX Compact Integer Plane Register File 1150 - In the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data extended using the x87 instruction set; while the MMX register is used to perform operations on 64-bit compact integer data, and to hold operands for performing several operations between the MMX and XMM registers.

[0144] Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, fewer, or different register files and registers. Exemplary core architecture, processor, and computer architecture

[0145] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, such core implementations may include: 1) general-purpose sequential cores for general-purpose computing; 2) high-performance general-purpose out-of-order cores for general-purpose computing; and 3) special-purpose cores primarily for graphics and / or scientific (productivity) computing. Different processor implementations may include: 1) a central processing unit comprising one or more general-purpose sequential cores for general-purpose computing and / or one or more general-purpose out-of-order cores for general-purpose computing; and 2) a coprocessor comprising one or more special-purpose cores primarily for graphics and / or scientific (productivity) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the central processing unit; 2) a coprocessor on a separate chip in the same package as the central processing unit; 3) a coprocessor on the same chip as the central processing unit (in this case, such a coprocessor is sometimes referred to as special-purpose logic, such as integrated graphics and / or scientific (production) logic, or as a special-purpose core); and 4) a system-on-a-chip (SoC) that may include the aforementioned central processing unit (sometimes referred to as an application core or application processor), the aforementioned coprocessors, and additional functionality on the same chip. An exemplary core architecture will then be described, followed by a description of exemplary processors and computer architectures. Exemplary Core Architecture Sequential and Out-of-Order Core Block Diagrams

[0146] FIG12A is a block diagram showing an exemplary sequential pipeline and an exemplary register renaming, out-of-order send / execution pipeline according to an embodiment of the present invention. FIG12B is a block diagram showing a sequential architecture core and an exemplary register renaming, out-of-order send / execution architecture core included in a processor according to an embodiment of the present invention. The sequential pipeline and sequential core are shown in solid boxes in FIG12A-B, while alternatively, additional dashed boxes show the register renaming, out-of-order send / execution pipeline and core. Given that the sequential state is a subset of the out-of-order state, the out-of-order state will be described.

[0147] In Figure 12A, the processor pipeline 1200 includes an extraction phase 1202, a length decoding phase 1204, a decoding phase 1206, an allocation phase 1208, a renaming phase 1210, a scheduling (also known as scheduling or sending) phase 1212, a register read / memory read phase 1214, an execution phase 1216, a write-back / memory write phase 1218, an exception handling phase 1222, and a commit phase 1224.

[0148] Figure 12B shows a processor core 1290 comprising a front-end unit 1230 coupled to an execution engine unit 1250 and a memory unit 1270. The core 1290 may be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, the core 1290 may be a special-purpose core, such as a networking or communications core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, or the like.

[0149] Front-end unit 1230 includes a branch prediction unit 1232 coupled to instruction cache memory unit 1234, coupled to instruction translation back buffer (TLB) 1236, coupled to instruction fetch unit 1238, and coupled to decoding unit 1240. Decoding unit 1240 (or decoder or decoding unit) can decode instructions (e.g., macro instructions) and generate one or more microoperations, microcode entry points, microinstructions, other instructions, or other control signals as outputs, which are decoded from, reflect, or originate from the original instructions. Decoding unit 1240 can be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 1290 includes microcode ROM or other media that stores microcode for certain macro instructions (e.g., in decoding unit 1240 or front-end unit 1230). The decoding unit 1240 is coupled to the rename / allocator unit 1252 in the execution engine unit 1250.

[0150] The execution engine unit 1250 includes a rename / allocator unit 1252 coupled to a failure unit 1254 and a group of one or more scheduler units 1256. The scheduler units 1256 represent any number of different schedulers, including reservation stations, central command windows, etc. The scheduler units 1256 are coupled to physical register file units 1258. Each physical register file unit 1258 represents one or more physical register files, wherein different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction index is the address of the next instruction to be executed), etc. In one embodiment, the physical register file unit 1258 includes vector register units, write mask register units, and scalar register units. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. Physical register file unit 1258 is overlapped by invalidation unit 1254 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and invalidation register file; using a future file, a history buffer, and invalidation register file; using a register map and a register pool; etc.). Invalidation unit 1254 and physical register file unit 1258 are coupled to execution cluster 1260. Execution cluster 1260 includes a group of one or more execution units 1262 and a group of one or more memory access units 1264. Execution unit 1262 can perform various operations (e.g., shift, addition, subtraction, multiplication) for different types of data (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point). Some embodiments may include several execution units dedicated to a specific function or group of functions, while other embodiments may include only one execution unit or multiple execution units that perform all functions. The scheduler unit 1256, the physical register file unit 1258, and the execution cluster 1260 may be multiple because in some embodiments separate pipelines are established for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each having a scheduler unit, physical register file unit, and / or execution cluster, and in some embodiments implemented with a single memory access pipeline, wherein only the execution cluster of said pipeline has memory access unit 1264). It should also be understood that, where separate pipelines are used, one or more of these pipelines may be out-of-order sent / executed while the rest are sequential.

[0151] The group memory access unit 1264 is coupled to the memory unit 1270, and includes a data translation backup buffer unit 1272 coupled to the data cache memory unit 1274, which is coupled to the second-order (L2) cache memory unit 1276. In an exemplary embodiment, the memory access unit 1264 may include a load unit, a store address unit, and a store data unit, each coupled to the data translation backup buffer unit 1272 in the memory unit 1270. The instruction cache memory unit 1234 is further coupled to the second-order (L2) cache memory unit 1276 in the memory unit 1270. The L2 cache memory unit 1276 is coupled to one or more other levels of cache memory and ultimately to main memory.

[0152] For example, the exemplary register renaming, out-of-order delivery / execution core architecture can implement the pipeline 1200 as follows: 1) The instruction fetching unit 1238 performs fetching and length decoding stages 1202 and 1204; 2) The decoding unit 1240 performs decoding stage 1206; 3) The renaming / allocator unit 1252 performs allocation stage 1208 and renaming stage 1210; 4) The scheduler unit 1256 performs scheduling stage 1212; 5) The entity The temporary register file unit 1258 and the memory unit 1270 execute the temporary register read / memory read phase 1214; the execution cluster 1260 executes the execution phase 1216; 6) the memory unit 1270 and the physical temporary register file unit 1258 execute the write-back / memory write phase 1218; 7) various units may participate in the exception handling phase 1222; 8) the failure unit 1254 and the physical temporary register file unit 1258 execute the commit phase 1224.

[0153] Core 1290 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions); the MIPS instruction set of MIPS Technologies, Sunnyvale, CAN; the ARM instruction set of ARM Holdings, Sunnyvale, CAN (with optional additional extensions such as NEON), which include the instructions described herein. In one embodiment, core 1290 includes logic supporting compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by most multimedia applications that execute using compressed data.

[0154] It should be understood that the core can support multiple threads (execute two or more parallel sets of operations or threads) and can do so in a variety of ways, including time-sharing multiple threads, synchronous multiple threads (where a single entity core provides the logical core for each thread of synchronous multiple threads), or a combination thereof (e.g., time-sharing fetch and decode and subsequent synchronous multiple threads, such as Intel® HyperThreading Technology).

[0155] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in sequential architectures. Although the illustrated processor embodiment also includes separate instruction and data cache memory units 1234 / 1274 and a shared L2 cache memory unit 1276, alternative embodiments may have a single internal cache memory for both instructions and data, such as a first-order (L1) internal cache memory or a multi-order internal cache memory. In some embodiments, the system may include a combination of internal cache memory and external cache memory outside the core and / or the processor. Alternatively, all cache memory may be outside the core and / or the processor. Specific exemplary sequential core architecture

[0156] Figures 13A-B show block diagrams of a more specific example of a sequential core architecture, where the core will be one of several logic blocks in the chip (including other cores of the same type and / or different types). The logic block communicates with certain fixed-function logic, memory I / O interfaces, and other application-dependent I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0157] FIG13A is a block diagram of a single processor core according to an embodiment of the present invention, together with its interconnect network 1302 connected to the chip and a region subset 1304 of its second-order (L2) cache memory. In one embodiment, the instruction decoding unit 1300 supports the x86 instruction set with compressed data instruction set extensions. The L1 cache memory 1306 allows low-latency access to scalar and vector units within the cache memory. Although in one embodiment (for simplicity of design), scalar units 1308 and vector units 1310 use separate register sets (scalar register 1312 and vector register 1314, respectively) and the data transferred between them are written to memory and then read back from the first-order (L1) cache memory 1306, alternative embodiments of the present invention may use different methods (e.g., using a single register set or including a communication path that allows data to be transferred between two register files without being written and read back).

[0158] The L2 cache region subset 1304 is part of the overall L2 cache, which is divided into separate region subsets (one for each processor core). Each processor core has a direct access path to its own L2 cache region subset 1304. Data read by a processor core is stored in its L2 cache subset 1304 and can be accessed quickly, in parallel with other processor cores accessing their own L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1304 and can be cleared from other subsets if necessary. A ring network ensures the consistency of shared data. The ring network is bidirectional to allow proxies, such as processor cores, L2 cache, and other logic blocks, to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0159] FIG13B is an expanded view of a portion of the processor core described in FIG13A according to an embodiment of the present invention. FIG13B includes the L1 data cache 1306A portion of the L1 cache 1304, and more detailed information about the vector unit 1310 and the vector register 1314. Specifically, the vector unit 1310 is a 16-bit wide vector processing unit (VPU) (see 16-bit wide ALU 1328) that executes one or more integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports mixed register input with mixed unit 1320, numerical conversion with numerical conversion units 1322A-B, and copying of memory input with copy unit 1324. Write mask register 1326 allows prediction result vector writing.

[0160] FIG14 is a block diagram of a processor 1400 that may have one or more cores, an integrated memory controller, and integrated graphics according to an embodiment of the present invention. The solid boxes in FIG14 show the processor 1400 having a single core 1402A, a system agent 1410, a group of one or more bus controller units 1416, while optional additional dashed boxes show alternative processors 1400 having multiple cores 1402A-N, a group of one or more integrated memory controller units 1414 in the system agent unit 1410, and special purpose logic 1408.

[0161] Therefore, different implementations of the processor 1400 may include: 1) a central processing unit having special-purpose logic 1408 which is integrated graphics and / or scientific (production) logic (which may include one or more cores) and cores 1402A-N which are one or more general-purpose cores (e.g., general-purpose sequential cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor having cores 1402A-N with a large number of special-purpose cores primarily used for graphics and / or scientific (production); and 3) a coprocessor having cores 1402A-N with a large number of general-purpose sequential cores. Therefore, the processor 1400 may be a general-purpose processor, a coprocessor, or a special-purpose processor, such as a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-production multi-integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1400 may be part of one or more substrates using any number of process technologies (e.g., BiCMOS, CMOS, or NMOS) and / or may be implemented on said substrate.

[0162] The memory hierarchy includes one or more levels of cache memory within the core, a group or one or more shared cache memory units 1406, and external memory (not shown) coupled to a group of integrated memory controller units 1414. The group of shared cache memory units 1406 may include one or more intermediate-level cache memory, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache memory, last-level cache memory (LLC), and / or combinations thereof. Although in one embodiment, a ring interconnect unit 1412 interconnects the integrated graphics logic 1408, the group of shared cache memory units 1406, and the system agent unit 1410 / integrated memory controller unit 1414, alternative embodiments may use any number of well-known techniques to interconnect these units. In one embodiment, consistency is maintained between one or more cache memory units 1406 and cores 1402A-N.

[0163] In some embodiments, one or more cores 1402A-N are capable of multi-threaded execution. System agent 1410 includes these elements that coordinate and operate the cores 1402A-N. System agent unit 1410 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include logic and elements that need to regulate the power state of the cores 1402A-N and the integrated graphics logic 1408. The display unit is for driving one or more externally connected displays.

[0164] The cores 1402A-N can be homogeneous or heterogeneous in terms of the architecture instruction set; that is, two or more cores 1402A-N can execute the same instruction set, while others may only be able to execute a subset of the instruction set or a different instruction set. Exemplary computer architecture

[0165] Figures 15 to 18 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the art, such as notebook computers, desktop computers, handheld computers, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video gaming devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices, are also applicable. In general, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are typically applicable.

[0166] Referring now to FIG15, a block diagram of a system 1500 according to an embodiment of the present invention is shown. The system 1500 may include one or more processors 1510, 1515 coupled to a controller hub 1520. In one embodiment, the controller hub 1520 includes a graphics memory controller hub (GMCH) 1590 and an input / output hub (IOH) 1550 (which may be on a separate chip); the GMCH 1590 includes memory and a graphics controller coupled to memory 1540 and a coprocessor 1545; the IOH 1550 is coupled to an input / output (I / O) device 1560 to the GMCH 1590. Alternatively, one or both of the memory and the graphics controller may be integrated within the processor (as described herein), with the memory 1540 and the coprocessor 1545 directly coupled to the processor 1510 and the controller hub 1520 in a single chip having the IOH 1550. The memory 1540 may contain "zero" multiplication code 1540A, for example, code used to store, when executed, cause the processor to perform any method of the present invention.

[0167] Optional features of the additional processor 1515 are indicated by dashed lines in Figure 15. Each processor 1510, 1515 may include one or more processing cores described herein and may be some version of the processor 1400.

[0168] The memory 1540 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. In at least one embodiment, the controller hub 1520 communicates with the processors 1510, 1515 via a multipoint bus, such as a front-side bus (FSB), a point-to-point interface, such as a fast path interconnect (QPI), or a similar connection 1595.

[0169] In one embodiment, the coprocessor 1545 is a special-purpose processor, such as a high-volume MIC processor, network or communications processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, the controller hub 1520 may include an integrated graphics accelerator.

[0170] In terms of the range of metrics including architecture, microarchitecture, thermal, power consumption characteristics, etc., the entity resources 1510 and 1515 may have various differences.

[0171] In one embodiment, the processor 1510 executes instructions that control general-type data processing operations. These instructions may be embedded as coprocessor instructions. The processor 1510 identifies these coprocessor instructions of a type that should be executed by an attached coprocessor 1545. The processor 1510 then issues these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor 1545 on a coprocessor bus or other interconnect. The coprocessor 1545 receives and executes the received coprocessor instructions.

[0172] Referring now to FIG16, a block diagram of a more specific first exemplary system 1600 according to an embodiment of the present invention is shown. As shown in FIG16, the multiprocessor system 1600 is a point-to-point interconnect system and includes a first processor 1670 and a second processor 1680 coupled via a point-to-point interconnect 1650. Processors 1670 and 1680 may each be some version of processor 1400. In one embodiment of the invention, processors 1670 and 1680 are processors 1510 and 1515, respectively, and coprocessor 1638 is coprocessor 1545. In another embodiment, processors 1670 and 1680 are processor 1510 and coprocessor 1545, respectively.

[0173] Processors 1670 and 1680 are shown to include integrated memory controller (IMC) units 1672 and 1682, respectively. Processor 1670 also includes point-to-point (PP) interfaces 1676 and 1678 as part of its bus controller unit; similarly, the second processor 1680 includes PP interfaces 1686 and 1688. Processors 1670 and 1680 can exchange information through point-to-point (PP) interface 1650 using point-to-point (PP) interface circuitry 1678 and 1688. As shown in FIG16, IMCs 1672 and 1682 are coupled to the processors to their respective memories, namely memories 1632 and 1634, which may be regionally attached to the main memory of their respective processors.

[0174] Processors 1670 and 1680 can each exchange information with chipset 1690 through individual point-to-point interfaces 1652 and 1654 via point-to-point interface circuits 1676, 1694, 1686, and 1698. Chipset 1690 can selectively exchange information with coprocessor 1638 via high-performance interface 1639. In one embodiment, coprocessor 1638 is a special-purpose processor, such as a high-volume MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

[0175] A shared cache (not shown) may be located within one or outside of two processors, but connected to the processors via a PP interconnect, such that if the processors are put into a low-power mode, information from the local caches of one or both processors may be stored in the shared cache.

[0176] Chipset 1690 may be coupled to first bus 1616 via interface 1696. In one embodiment, first bus 1616 may be a peripheral component interconnect (PCI) bus, or a bus such as a fast peripheral component interconnect (PCI Express) bus or another third-generation I / O interconnect bus, although the scope of the invention is not so limited.

[0177] As shown in FIG16, various I / O devices 1614 may be coupled to a first bus 1616, together with a bus bridge 1618 that couples the first bus 1616 to a second bus 1620. In one embodiment, one or more additional processors 1615, such as a coprocessor, a high-volume MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or digital signal processing (DSP) unit), a programmable logic array, or any other processor, are coupled to the first bus 1616. In one embodiment, the second bus 1620 may be a low pin count (LPC) bus. In one embodiment, various devices that may be coupled to the second bus 1620 include, for example, a keyboard and / or mouse 1622, a communication device 1627, and a storage unit 1628, such as a disk drive or other mass storage device, which may include instruction / encoding and data 1630. Furthermore, audio I / O 1624 may be coupled to the second bus 1620. It should be noted that other architectures are also possible. For example, instead of the point-to-point architecture in Figure 16, the system can be implemented as a multi-point bus or other such architectures.

[0178] Referring now to FIG17, a block diagram of a second more specific exemplary system 1700 according to an embodiment of the present invention is shown. Similar elements in FIG16 and FIG17 have similar reference numerals, and some features of FIG16 have been removed from FIG17 to avoid obscuring other features of FIG17.

[0179] Figure 17 shows that the processors 1670 and 1680 may include integrated memory and I / O control logic ("CL") 1672 and 1682, respectively. Therefore, the CLs 1672 and 1682 include integrated memory controller units and I / O control logic. Figure 17 shows that not only are the memories 1632 and 1634 coupled to the CLs 1672 and 1682, but the I / O device 1714 is also coupled to the control logic 1672 and 1682. The legacy I / O device 1715 is coupled to the chipset 1690.

[0180] Referring now to FIG18, a block diagram of a system chip 1800 according to an embodiment of the present invention is shown. Similar elements in FIG14 have similar reference numerals. Additionally, dashed boxes represent optional features on a more advanced system chip. In FIG18, interconnect unit 1802 is coupled to: an application processor 1810, which includes one or more cores 202A-N and a shared cache memory unit 1406; a system proxy unit 1410; a bus controller unit 1416; an integrated memory controller unit 1414; one or more coprocessors 1820, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1830; a direct memory access (DMA) unit 1832; and a display unit 1840 for coupling to one or more external displays. In one embodiment, the coprocessor 1820 includes a special-purpose processor, such as a network or communications processor, a compression engine, a GPGPU, a high-volume MIC processor, an embedded processor, or the like.

[0181] The embodiments disclosed herein (e.g., mechanisms) can be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0182] Program code, such as code 1630 shown in Figure 16, can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as a digital signal processor (DSP), microcontroller, special purpose integrated circuit (ASIC), or microprocessor.

[0183] The code can be implemented using a high-order programming or object-oriented programming language to communicate with the processing system. If necessary, the code can also be implemented using assembly or machine language. In fact, the mechanisms described herein are not limited to any particular programming language. In any case, the language can be a compiled or translated language.

[0184] One or more states in at least one embodiment can be implemented by representative instructions stored on a machine-readable medium representing various logics in a processor, wherein, when read by a machine, the machine manufactures the logic to perform the techniques described herein. Such a representation, referred to as an "IP core," can be stored on a physical machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into the manufacturing machine that actually constitutes the logic or processor.

[0185] Such machine-readable storage media may include (but is not limited to) non-transitory, article-of-writing physical arrangements or formed by a machine or apparatus, including storage media such as hard disks, any other type of magnetic disk including floppy disks, optical disks, read-only optical disks (CD-ROMs), erasable optical disks (CD-RWs) and optical discs, semiconductor devices such as read-only memory (ROMs), random access memory (RAMs) such as dynamic random access memory (DRAMs), static random access memory (SRAMs), erasable programmable read-only memory (EPROMs), flash memory, electronically erasable programmable read-only memory (EEPROMs), phase-change memory (PCMs), magnetic cards or optical cards, or any other media type suitable for storing electronic instructions.

[0186] Therefore, embodiments of the present invention also include non-transitory, physical, machine-readable media containing instructions or design data, such as a hardware description language (HDL), defining the architectures, circuits, devices, processors, and / or system characteristics described herein. Such embodiments may also relate to program products. Simulation (including binary translation, code transformation, etc.)

[0187] In some cases, an instruction translator can be used to translate instructions from a source instruction set to a target instruction set. For example, the instruction translator can translate (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), morph, emulate, or translate instructions to one or more other instructions processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, not on the processor, or partially on the processor and partially not on the processor.

[0188] Figure 19 is a block diagram comparing the use of a software instruction converter for converting binary instructions in a source instruction set to binary instructions in a target instruction set according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively, the instruction converter can be implemented using software, firmware, hardware, or various combinations thereof. Figure 19 shows that a program of high-level language 1902 can be compiled using x86 compiler 1904 to produce x86 binary code 1906, which can be natively executed by a processor 1916 having at least one x86 instruction set core. The processor 1916 having at least one x86 instruction set core represents any processor capable of performing substantially the same functions as an Intel® processor having at least one x86 instruction set core by compatiblely executing or processing (1) a significant portion of the instruction set of the Intel® x86 instruction set core or (2) a target code version of an application or other software aimed at running on an Intel® processor having at least one x86 instruction set core, to achieve substantially the same results as an Intel® processor having at least one x86 instruction set core. The x86 compiler 1904 represents a compiler capable of being computed to produce x86 binary code 1906 (e.g., object code), which may or may not have additional associative processing, and executes on the processor 1916 having at least one x86 instruction set core. Similarly, Figure 19 shows that a program in the high-level language 1902 can be compiled using an alternative instruction set compiler 1908 to produce an alternative instruction set binary code 1910, which can be natively executed by a processor 1914 that does not have at least one x86 instruction set core (e.g., a processor with a core that executes the MIPS instruction set of MIPS Technologies, Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Sunnyvale, California). An instruction converter 1912 is used to convert the x86 binary code 1906 into code that can be natively executed by a processor 1914 that does not have an x86 instruction set core. This converted code is unlikely to be identical to the alternative instruction set binary code 1910, as such an instruction converter would be difficult to manufacture; however, the converted code will perform general operations and compose instructions from the alternative instruction set. Therefore, the instruction converter 1912 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation, or any other program, allows a processor or other electronic device that does not have an x86 instruction set to execute x86 binary code 1906. [Simplified Explanation of the Diagram]

[0190] The invention is shown in the accompanying drawings by way of example rather than limitation, in which similar element symbols indicate similar elements, and wherein:

[0191] [Figure 1] shows a hardware processor coupled to memory according to an embodiment of the present invention.

[0192] [Figure 2A] shows a circuit in floating-point mode according to an embodiment of the present invention, which includes a zero detector circuit coupled to a zero multiplier circuit.

[0193] [Figure 2B] shows a circuit in integer mode according to an embodiment of the present invention and including a zero detector circuit coupled to a zero multiplier circuit.

[0194] [Figure 3] shows a matrix operation circuit including a "zero" mode according to an embodiment of the present invention.

[0195] [Figure 4] shows a circuit according to an embodiment of the present invention, comprising a plurality of parallel "zero" multiplier circuits coupled to an adder circuit.

[0196] [Figure 5] shows a circuit comprising a plurality of parallel "zero" multiplier circuits according to an embodiment of the present invention.

[0197] [Figure 6] shows a hardware processor coupled to a storage containing one or more “zero” multiplication instructions according to an embodiment of the present invention, the hardware processor having a “zero” detector circuit coupled to an execution circuit.

[0198] [Figure 7] shows a hardware processor coupled to a storage containing one or more "zero" multiplication instructions according to an embodiment of the present invention, the hardware processor having a "zero" detector circuit for execution circuitry.

[0199] [Figure 8] shows a method for processing "zero" multiplication instructions according to an embodiment of the present invention.

[0200] [Figure 9A] is a block diagram showing the general vector affinity instruction format and its Class A instruction template according to an embodiment of the present invention.

[0201] [Figure 9B] is a block diagram showing the general vector affinity instruction format and its B-type instruction template according to an embodiment of the present invention.

[0202] [Figure 10A] is a block diagram showing the fields for the general vector affinity instruction format in Figures 9A and 9B according to an embodiment of the present invention.

[0203] [Figure 10B] is a block diagram showing a field of a specific vector affinity instruction format in Figure 10A that constitutes a complete operation code field according to an embodiment of the present invention.

[0204] [Fig. 10C] is a block diagram showing a field of a specific vector affinity instruction format in FIG. 10A that constitutes a temporary register index field according to an embodiment of the present invention.

[0205] [Fig. 10D] is a block diagram showing a field of a specific vector affinity instruction format in Fig. 10A of a compositional enhanced operation field 950 according to an embodiment of the present invention.

[0206] [Figure 11] is a block diagram of a temporary register architecture according to an embodiment of the present invention.

[0207] [Figure 12A] is a block diagram showing both an exemplary sequential pipeline and an exemplary temporary register renaming, out-of-order problem / execution pipeline according to an embodiment of the present invention.

[0208] [Figure 12B] is a block diagram showing an exemplary embodiment of the sequential architecture core and the exemplary register renaming, out-of-order problem / execution architecture core to be included in the processor according to an embodiment of the present invention.

[0209] [Figure 13A] is a block diagram of a single processor core according to an embodiment of the present invention, its connection to the on-die interconnect network, and a local subset of its secondary (L2) cache memory.

[0210] [Fig. 13B] is an enlarged view of a portion of the processor core in Fig. 13A according to an embodiment of the present invention.

[0211] [Figure 14] is a block diagram of a processor that may have more than one core, an integrated memory controller and an integrated graphics according to an embodiment of the present invention.

[0212] [Figure 15] is a block diagram of a system according to an embodiment of the present invention.

[0213] [Figure 16] is a block diagram of a more specific exemplary system according to an embodiment of the present invention.

[0214] [Figure 17] shows a block diagram of a second more specific exemplary system according to an embodiment of the present invention.

[0215] [Figure 18] shows a block diagram of a system-on-a-chip (SoC) according to an embodiment of the present invention.

[0216] [Figure 19] is a block diagram comparing the use of a software instruction converter according to an embodiment of the present invention to convert binary instructions in a source instruction set to binary instructions in a target instruction set.

Claims

1. A hardware processor comprising: a decoder for decoding a single instruction into a decoded single instruction, the single instruction having a first field identifying a first digit, a second field identifying a second digit, and a third field indicating the digit format of the first digit and the second digit; and execution circuitry for executing the decoded single instruction to: perform a first comparison of the first digit with a zero value in the digit format of the first digit; perform a second comparison of the second digit with a zero value in the digit format of the second digit; provide a value of zero as a result of the single instruction when the second comparison indicates that the second digit is equal to the zero value in the digit format of the second digit; provide a value of zero as a result of the single instruction when the first comparison indicates that the first digit is equal to the zero value in the digit format of the first digit; and provide a product of the first digit and the second digit as a result of the single instruction when the first comparison indicates that the first digit is not equal to the zero value in the digit format of the first digit, and the second comparison indicates that the second digit is not equal to the zero value in the digit format of the second digit.

2. The hardware processor of claim 1, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates that the first number is equal to the zero value in the number format of the first number or the second comparison indicates that the second number is equal to the zero value in the number format of the second number.

3. The hardware processor of claim 2, wherein the multiplier for performing the multiplication is powered off in response to a first comparison indicating that the first number is equal to the zero value in the number format of the first number or a second comparison indicating that the second number is equal to the zero value in the number format of the second number.

4. A hardware processor as described in any of requests 1 to 3, wherein the number format is provided as an immediate value of the single instruction.

5. A hardware processor as described in any of claims 1 to 3, wherein the number format is indicated by the arithmetic code of the single instruction.

6. The hardware processor of claim 1, wherein the first field identifies a first vector of digits, the second field identifies a second vector of digits, and the execution circuit executes the decoded single instruction to: perform a plurality of first comparisons between each digit in the first vector of digits and a zero value in the number format of the first vector of digits; perform a plurality of second comparisons between each digit in the second vector of digits and a zero value in the number format of the second vector of digits; and, as a result of the single instruction, provide a zero value for each of the plurality of second comparisons, the zero value indicating that the corresponding second digit in the second vector of digits is equal to the zero value in the number format of the second vector of digits. As a result of the single instruction, a zero value is provided for each of the plurality of first comparisons, the zero value indicating that the corresponding first number of the first vector of the number is equal to the zero value in the number format of the first vector of the number, and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the corresponding second comparison indicates that the second number is not equal to the zero value in the number format of the second number, as a result of the single instruction, the product of the first number of the first vector of the number and the corresponding second number of the second vector of the number is provided.

7. The hardware processor of claim 1, wherein when the number format is a floating-point format for the first value and the second value, the first comparison compares the zero value with the sign bit of the first number, compares the zero value with the exponent field of the first number, and compares the zero value with the fraction field of the first number, while the second comparison compares the zero value with the sign bit of the second number, compares the zero value with the exponent field of the second number, and compares the zero value with the fraction field of the second number.

8. The hardware processor of claim 1, wherein the first comparison and the second comparison are performed separately from the execution circuitry.

9. A method comprising: decoding a single instruction into a decoded single instruction using a decoder of a hardware processor, the single instruction having a first field identifying a first digit, a second field identifying a second digit, and a third field indicating the digit format of the first digit and the second digit; and executing the decoded single instruction using an execution circuit of the hardware processor to: perform a first comparison of the first digit with a zero value in the digit format of the first digit; perform a second comparison of the second digit with a zero value in the digit format of the second digit; provide a value of zero as a result of the single instruction when the second comparison indicates that the second digit is equal to the zero value in the digit format of the second digit; provide a value of zero as a result of the single instruction when the first comparison indicates that the first digit is equal to the zero value in the digit format of the first digit; and provide a product of the first digit and the second digit as a result of the single instruction when the first comparison indicates that the first digit is not equal to the zero value in the digit format of the first digit, and the second comparison indicates that the second digit is not equal to the zero value in the digit format of the second digit.

10. The method of claim 9, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates that the first number is equal to the zero value in the number format of the first number or the second comparison indicates that the second number is equal to the zero value in the number format of the second number.

11. The method of claim 10, wherein the multiplier for performing the multiplication is powered off in response to a first comparison indicating that the first number is equal to the zero value in the number format of the first number or a second comparison indicating that the second number is equal to the zero value in the number format of the second number.

12. The method of any one of claims 9 to 11 further comprises reading the number format from the immediate value of the single instruction.

13. The method of any one of claims 9 to 11 further comprises determining the number format from the arithmetic code of the single instruction.

14. The method of claim 9, wherein the first field identifies a first vector of digits, the second field identifies a second vector of digits, and the execution circuit executes the decoded single instruction to: perform a plurality of first comparisons between each digit in the first vector of digits and a zero value in the number format of the first vector of digits; perform a plurality of second comparisons between each digit in the second vector of digits and a zero value in the number format of the second vector of digits; and, as a result of the single instruction, provide a zero value for each of the plurality of second comparisons, the zero value indicating that the corresponding second digit in the second vector of digits is equal to the zero value in the number format of the second vector of digits. As a result of the single instruction, a zero value is provided for each of the plurality of first comparisons, the zero value indicating that the corresponding first number of the first vector of the number is equal to the zero value in the number format of the first vector of the number, and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the corresponding second comparison indicates that the second number is not equal to the zero value in the number format of the second number, as a result of the single instruction, the product of the first number of the first vector of the number and the corresponding second number of the second vector of the number is provided.

15. The method of claim 9, wherein when the number format is a floating-point format for the first value and the second value, the first comparison compares the zero value with the sign bit of the first number, compares the zero value with the exponent field of the first number, and compares the zero value with the fraction field of the first number, while the second comparison compares the zero value with the sign bit of the second number, compares the zero value with the exponent field of the second number, and compares the zero value with the fraction field of the second number.

16. The method of claim 9, wherein the first comparison and the second comparison are performed separately from the execution circuitry.

17. A non-transitory machine-readable medium storing code, the code causing the machine to execute a method when executed by a machine, comprising: decoding a single instruction into a decoded single instruction using a decoder of a hardware processor, the single instruction having a first field identifying a first digit, a second field identifying a second digit, and a third field indicating the digit format of the first digit and the second digit; and executing the decoded single instruction using an execution circuit of the hardware processor to: perform a first comparison of the first digit with a zero value in the digit format of the first digit; perform a second comparison of the second digit with a zero value in the digit format of the second digit; when the second comparison indicates that the second digit is equal to the zero value in the digit format of the second digit, provide a value of zero as a result of the single instruction; when the first comparison indicates that the first digit is equal to the zero value in the digit format of the first digit, provide a value of zero as a result of the single instruction; and when the first comparison indicates that the first digit is not equal to the zero value in the digit format of the first digit, and the second comparison indicates that the second digit is not equal to the zero value in the digit format of the second digit, provide a product of the first digit and the second digit as a result of the single instruction.

18. A non-transitory machine-readable medium as claimed in claim 17, wherein the execution circuitry does not perform the multiplication of the first number and the second number when the first comparison indicates that the first number is equal to the zero value in the number format of the first number or the second comparison indicates that the second number is equal to the zero value in the number format of the second number.

19. A non-transient machine-readable medium as claimed in claim 18, wherein the multiplier for performing the multiplication is powered off in response to a first comparison indicating that the first number is equal to the zero value in the number format of the first number or a second comparison indicating that the second number is equal to the zero value in the number format of the second number.

20. The non-transient machine-readable medium as claimed in any of claims 17 to 19 further includes the digital format read from the immediate value of the single instruction.

21. The non-transitory machine-readable medium of any of claims 17 to 19 further comprises determining the digital format from the operand of the single instruction.

22. A non-transitory machine-readable medium as claimed in claim 17, wherein the first field identifies a first vector of digits, the second field identifies a second vector of digits, and the execution circuit executes the decoded single instruction to: perform a plurality of first comparisons between each digit in the first vector of digits and a zero value in the number format of the first vector of digits; perform a plurality of second comparisons between each digit in the second vector of digits and a zero value in the number format of the second vector of digits; and, as a result of the single instruction, provide a zero value for each of the plurality of second comparisons, the zero value indicating that a corresponding second digit in the second vector of digits is equal to the zero value in the number format of the second vector of digits. As a result of the single instruction, a zero value is provided for each of the plurality of first comparisons, the zero value indicating that the corresponding first number of the first vector of the number is equal to the zero value in the number format of the first vector of the number, and when the first comparison indicates that the first number is not equal to the zero value in the number format of the first number and the corresponding second comparison indicates that the second number is not equal to the zero value in the number format of the second number, as a result of the single instruction, the product of the first number of the first vector of the number and the corresponding second number of the second vector of the number is provided.

23. The non-transitory machine-readable medium of claim 22, wherein when the number format is a floating-point format for the first value and the second value, the first comparison compares the zero value with the sign bit of the first number, compares the zero value with the exponent field of the first number, and compares the zero value with the fraction field of the first number, while the second comparison compares the zero value with the sign bit of the second number, compares the zero value with the exponent field of the second number, and compares the zero value with the fraction field of the second number.

24. A non-transitory machine-readable medium as claimed in claim 17, wherein the first comparison and the second comparison are performed separately from the execution circuitry.

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