Systems and methods providing leakage reduction for power gated domains

Abstract

A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.

Description

[Technical Field]

[0001] This application claims priority and benefit to U.S. Patent Application No. 17 / 015,466, filed September 9, 2020, the entire contents of which are incorporated herein by reference, as fully set forth below and used for all applicable purposes.

[0002] This application generally relates to the field of power control, and more specifically to reducing leakage in power control switches. [Previous Technology]

[0003] Conventional computing devices (e.g., smartphones, tablets, etc.) may include a system-on-a-chip (SOC), which has a processor and other operating circuitry. The SOC can receive its power from a battery, and therefore conventional designs can balance SOC performance and power usage to deliver the desired experience to the user while requiring as little battery charging as possible.

[0004] Power gating is a technique that can be used to save power in certain situations. One way some systems can use power gating to save power is by implementing power deactivation on certain parts of the processing core (using a first power multiplexer and a first power domain) while simultaneously supplying power to other parts of the processing core (using a second power multiplexer and a second power domain). Another way some conventional systems can use power gating is by switching from a first power supply to a second power supply to power the central processing unit (CPU) memory, and then regulating the second power supply to overdrive the CPU memory. This technique can save power by allowing the SOC to selectively increase the voltage at certain components without increasing the voltage at others. Of course, power gating can also involve simply deactivating power at one or more components that are not in use and then restoring power later.

[0005] Some power gate circuits can use head switches or foot switches, each with a transistor. The transistor can be turned off to de-energize the corresponding part of the processing core or other processing logic. However, even when the transistor is turned off, it can still allow some leakage current. For example, a P-channel metal-oxide-semiconductor (PMOS) head switch is turned off when its gate-source voltage is greater than or equal to zero. Real-world PMOS head switches are not ideal switches and leakage current may exist even in the off state. Leakage can translate into power drawn from the normally open power supply, resulting in reduced battery life. Therefore, circuitry and techniques are needed to reduce leakage. [Summary of the Invention]

[0006] Various implementations provide circuitry and techniques for reducing leakage in power gated switches. In one example implementation, the PMOS head switch is held in an over-cutoff state when it is off. The over-cutoff state may include providing a positive gate-source voltage to the transistor within at least some voltage range. Furthermore, in this example, when the source voltage exceeds a threshold, the system can regulate the gate-source voltage to approximately zero, such that the transistor is held in the off state but not in the over-cutoff state.

[0007] According to one implementation, a system includes: a first power supply; a second power supply; a head switch disposed between the first power supply and a logic circuit device; an enable driver that couples the second power supply to a control terminal of the head switch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the head switch in response to a first voltage level of the first power supply exceeding a reference voltage level.

[0008] According to another implementation, a method includes: enabling a head switch to conduct current from a first power supply to a logic circuit device; and turning off the current by disabling the head switch, including: selecting a first voltage level from the first voltage level and the second voltage level in response to comparing a first voltage level with a second voltage level; and applying the first voltage level from the second power supply to the gate of the head switch.

[0009] According to another implementation, a circuit includes: a first power rail coupled to a first power supply; a second power rail coupled to a second power supply; a power gate switch coupled between the first power rail and a portion of a logic circuit arrangement of a central processing unit (CPU); and a component for selecting a control voltage from the second power rail to a control terminal of the power gate switch in response to a first voltage level of the first power supply being lower than a reference voltage level.

Implementation Method

[0018] Various implementations provided herein include systems and methods for providing power gate control for logic circuits, with reduced leakage compared to other implementations. One example includes a first power supply coupled to the source of a transistor. A second power supply is coupled to a control terminal (e.g., the gate) of the transistor. The transistor itself, which may include a head switch, may be positioned between the first power supply and the logic circuit (e.g., the drain of the transistor may be coupled to the logic circuit). An enable driver, such as a buffer with an inverter, may couple the second power supply to the gate of the transistor.

[0019] Continuing this example, the system may further include a voltage generator operable to regulate the control voltage from the second power supply to the control terminal of the transistor. The voltage generator regulates the control voltage in response to a voltage level from the first power supply exceeding a reference voltage level. The reference voltage level can be set to any suitable value, which can be selected through trial and error, simulation, etc. In this example implementation, the reference voltage level is set such that the potential of the control voltage is lowered or gate-induced drain leakage (GIDL) is avoided.

[0020] Therefore, in this example, during the transistor's off-state, the transistor can be maintained in an over-off state where the gate voltage is higher than the source voltage. However, the transistor may have an operating region in which a positive gate-source voltage exceeding a certain gate voltage level may actually increase leakage rather than decrease it. This increased leakage is called GIDL. If the source voltage changes and may reach a potential that determines the gate voltage that causes GIDL, maintaining a positive gate-source voltage during the transistor's off-state may be ineffective.

[0021] In one example, the proposed system and method reduce or eliminate GIDL by providing a voltage generator that regulates the control voltage from a second power supply to the gate of the transistor. When the source voltage from the first power supply exceeds a reference voltage level, the voltage generator can regulate the control voltage from the second power supply to approximately equal the source voltage.

[0022] In other words, when the source voltage from the first power supply exceeds the reference voltage level, the voltage generator can adjust the control voltage so that the gate-source voltage is zero or approximately zero. As mentioned above, a zero gate-source voltage can still cause leakage, but the system can be designed such that the leakage due to a zero gate-source voltage is less than the leakage experienced due to GIDL.

[0023] In one example, the voltage generator includes a comparator having a first input and a second input, the first input being coupled to a first power supply and the second input being coupled to a reference voltage. The voltage generator may also include circuitry operable to adjust a control voltage between a first voltage level (of the first power supply) and a second voltage level (the reference voltage level) in response to the output of the comparator. For example, if the voltage level of the first power supply exceeds the reference voltage level, the voltage generator may output the voltage level of the first power supply as the control voltage. Conversely, if the voltage level of the first power supply is lower than the voltage level of the reference voltage level, the voltage generator may output the reference voltage level as the control voltage.

[0024] Various implementations may also include methods. One example method includes: enabling a head switch to conduct current from a first power supply to a logic circuit device. When the head switch is in the ON state and current is conducted to the logic circuit device, the logic circuit device does not experience power failure. The method may also include: turning off the current by disabling the head switch, thereby causing the logic circuit device to experience power failure. Turning off the current may include: selecting a first voltage level from a first voltage level and a second voltage level in response to comparing a first voltage level with a second voltage level. For example, the first voltage level may include a source voltage, and the second voltage level may include a reference voltage, so the method includes: selecting either the source voltage or the reference voltage as a control voltage applied to the gate of the transistor.

[0025] Various implementations may include advantages over other systems. One advantage includes reducing leakage by applying an over-cutoff state to the power gate switch. The over-cutoff state can reduce leakage by a greater extent than that could be achieved by simply turning off the power gate switch. Furthermore, the circuits described herein can implement the over-cutoff state using less silicon area compared to other alternatives. Specifically, some implementations described herein can use operational amplifiers and multiple transistors to provide voltage selection, which has less overhead compared to other leakage reduction alternatives previously considered.

[0026] Figure 1 is a simplified diagram illustrating an example system 100 according to an implementation of a power-gated logic circuit device 120. The example system 100 includes an enable driver 102 that provides a control voltage to a control terminal (gate) of a head switch 108. The head switch 108 in this example includes a P-channel metal-oxide-semiconductor (PMOS) transistor disposed between a first power supply (Vdd_ext) and the logic circuit device 120. Specifically, the source of the head switch 108 is coupled to a power supply 106, which supplies power to the logic circuit device 120 when the head switch 108 is turned on. The drain of the head switch 108 is coupled to a power-gated supply rail 110, which supplies power to the logic circuit device 120.

[0027] The behavior of the head switch 108 is such that when its gate-source voltage is greater than or equal to zero, the head switch 108 is turned off, thereby causing the logic circuit device 120 to lose power. Similarly, when its gate-source voltage is negative, the head switch 108 is turned on, thereby supplying power to the logic circuit device 120 from the power rail 106.

[0028] The enable driver 102 is coupled to a second power supply 104 (Vdd_Drvr). The enable driver 102 is also coupled to an electric shifter 112 and an enable control circuit device 114. When the enable signal (Sw_enable) is high, the enable driver 102 drives zero to the gate of the head switch 108, thereby turning on the head switch 108. When the enable signal is low, the enable driver drives logic one to the gate of the head switch 108, thereby turning off the head switch 108. The electric shifter 112 outputs the enable signal at the same voltage (Vdd_Drvr) as the second power supply 104. The enable control circuit device 114 determines whether the enable signal is high or low and can communicate with other components, such as a self-tuning power program running in the kernel of an operating system of a central processing unit (CPU) core, which may or may not include the logic circuit device 120.

[0029] As described above, the enable signal is at the same voltage as the second power supply 104, and the enable driver 102 outputs the same voltage as the voltage received on the power rail coupled to the power supply 104. Therefore, when the head switch 108 is turned off, the enable signal becomes zero, which passes Vdd_Drvr (bit 1) to the gate of the head switch 108. Now, the voltage difference between the gate and source (gate-source voltage) is Vdd_Drvr minus Vdd_ext. As described below, various implementations can change Vdd_Drvr so that it can be higher than Vdd_ext to put the PMOS transistor of the head switch 108 in an over-off state.

[0030] Referring now to Figure 2, which is a graph illustrating an example relationship between the drain current (on the Y-axis) and the gate voltage (on the x-axis) of the head switch 108. The graph in Figure 2 assumes that the voltage Vdd_ext at the first power supply 106 is equal to 0.6V. It should be noted that the various voltages discussed herein are merely examples, and depending on the specific transistor used for the head switch 108, different voltages may be used for the gate or source of the head switch 108 in other applications.

[0031] The drain current is mostly high and positive until the gate voltage equals the source voltage, or in other words, the gate-source voltage is zero. This is shown at 201. However, when the gate-source voltage is zero, the current at the drain is not exactly zero. Instead, the drain current can be further reduced, as shown at point 204, where the gate voltage is 0.7V. The portion of Figure 200 where the gate-source voltage is positive is referred to as the over-cutoff state of the transistor. The current at point 201 is approximately seven times the current at point 204, thus illustrating that the over-cutoff state can further reduce the leakage current in the system of Figure 1. Furthermore, it should be noted that as the gate voltage increases beyond point 205 (the gate voltage is approximately 0.8V), the GIDL increases, thereby offsetting some or all of the gain from placing the transistor in the over-cutoff state. Therefore, the various implementations described herein can adjust the control voltage from the second power supply 104 to the control terminal of the head switch 108 to achieve the over-cutoff state of the transistor while also avoiding GIDL. This will be described in more detail below.

[0032] The concepts of over-cutoff state and GIDL are further illustrated in Figure 3. Figure 3 is a graph showing an example relationship between gate voltage and source voltage according to the implementation of Figure 2. Furthermore, Figure 3 shows different levels of leakage current during the off-state or over-cutoff state of the transistor (such as the transistor of the head switch 108 in Figure 1). Three different levels of leakage current are shown: low and acceptable, higher but acceptable, and high and unacceptable. Of course, these markings are only examples, as are specific gate and source voltages. Other implementations may use different voltages and have different tolerances for leakage current, such that the difference between acceptable and unacceptable may be shifted up or down for other implementations.

[0033] In Figure 3, in this example, a gate voltage above approximately 0.9V provides an unacceptable amount of leakage current, and the leakage current increases with increasing gate voltage. In contrast, a gate voltage below approximately 0.9V is within acceptable limits, and the leakage current decreases with decreasing gate voltage. The lower limit of Figure 3 is when the gate-source voltage is zero, which is represented as higher but acceptable in this example.

[0034] Referring to the examples in Figures 1 and 3, various implementations can prevent leakage by maintaining the head switch 108 in an over-off state. However, if the first power supply (Vdd_ext) changes, the potential of Vdd_ext may rise to a point where the gate voltage (Vdd_Drvr) will cause an unacceptable level of leakage current, high enough to maintain the head switch 108 in an over-off state. Therefore, some implementations of the system in Figure 1 can adjust the control voltage Vdd_Drvr such that it maintains the head switch 108 in an over-off state for some Vdd_ext potential, but if Vdd_ext exceeds a threshold, the system can make the control voltage Vdd_Drvr equal to Vdd_ext, such that the gate-source voltage is zero and the leakage current remains within an acceptable range.

[0035] Therefore, the example implementation includes selecting a reference voltage, such as the voltage shown as Vdd1 in Figure 4. The reference voltage Vdd1 is selected as a potential above which the gate voltage is expected to experience unacceptable GIDL. Of course, this varies from application to application, as some applications typically have a higher tolerance for GIDL or leakage. The example in Figure 4 illustrates some acceptable leakage levels and other unacceptable leakage levels in relation to the relationship shown in Figure 3. Specifically, the potential of the reference voltage Vdd1 is set between 0.7V and 0.8V, which corresponds to the gate voltage with an acceptable leakage level in the example of Figure 3. In some implementations, Vdd1 at a particular potential is not set at a high-precision level, but is set based on experiments or simulations, and can be set within the range where the gate voltage results in an acceptable leakage level. Therefore, the example in Figure 3 can also be served by a reference voltage level Vdd1 up to 0.85V.

[0036] Curve 401 shows the time-varying potential of Vdd_ext associated with the first power supply 106 of FIG1. ​​Curve 402 shows the reference voltage level Vdd1, which is set to a potential between 0.7V and 0.8V. Curve 403 shows the potential of Vdd_Drvr associated with the second power supply 104, as it changes over time in response to changes in the potential of Vdd_ext. For ease of illustration, FIG4 shows curve 403 shifted vertically downwards from curve 401, and it is not intended to show the absolute voltage level of Vdd_Drvr.

[0037] Before time T1, Vdd_ext is below the voltage level Vdd1. Therefore, in the event of a power failure in the logic circuit device 120 of FIG1, the system of FIG1 maintains the head switch 108 in an over-off state by applying a control voltage Vdd_Drvr equal to Vdd1. This is represented by the ellipse on the left-hand side around Vdd1 and Vdd_Drvr. Again, Vdd_ext is associated with the first power supply 106 and is the source voltage. Therefore, before time T1, the gate-source voltage is positive.

[0038] At time T1, Vdd_ext equals the reference voltage Vdd1. As mentioned above, Vdd_ext can be a time-varying voltage, therefore the system uses dynamic setting for Vdd_Drvr. After time T1, if the control voltage Vdd_Drvr is maintained at the value of Vdd1, the gate-source voltage will be negative, thereby turning on the head switch 108. Therefore, in order to keep the head switch 108 in the off state, the system makes Vdd_Drvr equal to Vdd_ext, thereby making the gate-source voltage zero and keeping the head switch 108 in the off state.

[0039] Furthermore, it is anticipated that maintaining the over-off state of the head switch 108 after time T1 would cause unacceptable leakage due to GIDL, as the gate voltage would be above 0.7V-0.8V, as described above with respect to Figure 3. Therefore, the system uses a gate-source voltage of zero after time T1 to keep the head switch 108 in the off state with acceptable leakage.

[0040] Figure 5 is an illustration of an example voltage generator 500 adapted according to one implementation. The voltage generator 500 can be operated to adjust the control voltage Vdd_Drvr from the second power supply 104 to the control terminal of the head switch 108 in response to a voltage level Vdd_ext exceeding a reference voltage level Vdd1. In short, when Vdd1 is higher than Vdd_ext, the voltage generator 500 selects Vdd1 and passes it to Vdd_Drvr. When Vdd1 is lower than Vdd_ext, the voltage generator selects Vdd_ext and passes it to Vdd_Drvr. According to one implementation, the output of the voltage generator 500 can be coupled to a power rail associated with the power supply 104.

[0041] Voltage generator 500 includes comparator 501 (e.g., operational amplifier or op amp), which receives a reference voltage Vdd1 at its positive (+) input and a voltage Vdd_ext from the first power supply 106 at its inverting input. The output of comparator 501 is a digital "1" or a digital "0", which is switched by voltage level shifter 502 to a voltage domain compatible with transistors 510 and 512. When Vdd1 is higher than Vdd_ext, the comparator outputs a digital "1", and the digital "1" turns off PMOS transistor 510 and turns on PMOS transistor 512, thereby causing Vdd1 to appear at Vdd_Drvr.

[0042] When Vdd_ext is higher than Vdd1, this causes a digital "0" to appear at the output of comparator 501. This turns on PMOS 510 and turns off PMOS 512, causing Vdd_ext to appear at Vdd_Drvr. This causes one voltage level (Vdd_ext) to be selected over another voltage level (Vdd1) as the output Vdd_Drvr. As described above, during the design of the system, Vdd1 is selected to be set to be equal to or lower than the potential at which experiments or simulations indicate that GIDL will occur. Therefore, voltage generator 500 makes Vdd_Drvr follow the example of Figure 4, thereby reducing leakage during the off state of head switch 108 by keeping the transistor of head switch 108 in an over-off state or a state where the gate-source voltage is zero (at least when head switch 108 is off).

[0043] Continuing with the example in Figure 5, it also includes a control mechanism 503 coordinating between the voltage level shifter 502 and transistors 510, 512. In this example, the control mechanism 503 can be operated to force the voltage generator 500 to output Vdd_Drvr at a voltage equal to Vdd_ext. In some examples, when the control mechanism 503 controls the output of comparator 501, comparator 501 and voltage level shifter 502 can be turned off. In some cases, it may be preferable to have a zero gate-source voltage rather than changing the gate-source voltage. For example, a sleep mode where Vdd_ext can be zero may exist, and it is generally also preferable to have the gate voltage Vdd_Drvr zero to put the chip into deep sleep. In some examples, the control mechanism 503 may be implemented using software. Of course, the scope of implementation is not limited to using software control in any particular scenario. The overriding mechanism 503 may include logic circuitry with a programmed software control register, or it may include a logic block that combines multiple inputs indicating the state of system 100 at a specific point in time. In one implementation, the overriding mechanism 503 may include logic circuitry for generating enable signals for transistors 510, 512 based on the state of an overriding signal (not shown) from the output of comparator 501 and from another source within system 100. Such logic circuitry may be referred to as an overriding circuitry.

[0044] Figure 6 is an illustration of an example system 600 according to one implementation. Figure 6 is a simplified diagram showing that the system of Figure 1 can be repeated to cause multiple parts of the logic to be electrically degraded. For example, system 600 includes enable drivers 102a to 102N, where N is an integer greater than 1. In fact, N can be any suitable integer. Each enable driver in enable driver 102 is coupled to a second power supply 104.

[0045] Example system 600 also includes a plurality of head switches 108a to 108N, where N is again an integer greater than 1. In this example, there are N enable drivers 102 and N head switches 108, but in other implementations, each enable driver 102 may drive multiple head switches 108, depending on the size of the enable driver 102 and the size of the head switches 108. Furthermore, the head switches 108 may be drain-coupled, as shown in Figure 600, but in other implementations, the drain may be uncoupled.

[0046] The power failure domain 602 may include multiple parts of a logic circuit device (e.g., multiple instances of logic circuit device 120). The parts of the logic circuit device may be similar or dissimilar, and the number of the parts of the logic circuit device may be any suitable number. For example, system 600 may be used to appropriately cause a power failure in the entire domain or in part of the domain.

[0047] It should be understood that some features have been omitted in FIG6 for ease of explanation. For example, although FIG1 shows the electrically shifter 112 and the enable control 114, it should be understood that the same or similar features can be implemented in the system 600 of FIG6 by electrically shifting the software enable signal to a value equal to Vdd_Drvr, and the software enable signal can be controlled to be high or low by the enable control circuitry 114.

[0048] The circuit in Figure 6 operates according to the principles described above. For example, Vdd_Drvr can be provided by a generator such as that shown in Figure 5. Therefore, the Vdd_Drvr voltage can be selected based on the voltage (Vdd_ext) at the source of the head switch 108. Thus, when the head switches 108 are in the off state, they can be maintained in an over-off state or a zero gate-source voltage state, depending on the level of Vdd_ext relative to a reference voltage. When domain 602 is not power-damped, the head switch 108 is turned on, thereby supplying power to domain 602 from the first power supply 106 via its corresponding drain. Logic (such as enable control 114) can power-damp domain 602 or supply power to domain 602 based on any standard and any power algorithm.

[0049] Figure 7 is an illustration of a reference voltage circuit 700 for generating a reference voltage Vdd1 according to one implementation. The example in Figure 7 assumes that the appropriate potential for Vdd1 is 0.7V to 0.8V, and as mentioned above, various implementations can use different voltage levels for the gate or source of the head switch. Therefore, other implementations can use different potentials for the reference voltage Vdd1, and it can be understood that the particular architecture shown in Figure 7 can be adapted to generate any appropriate reference voltage level. Furthermore, the voltage levels for power supplies VddA and VddB are merely exemplary, and it should be understood that other implementations can have different available voltage levels and can be adapted to use these voltage levels to output an appropriate reference voltage level.

[0050] Switches S1 and S2 can be implemented as PMOS switches, N-channel metal-oxide-semiconductor (NMOS) switches, or any other transistor technology. In this example, VddA is a high-voltage rail, such as 1.8V. A low-dropout (LDO) voltage regulator 701 can include a resistor drop that reduces the voltage to 0.7V-0.8V. When switch S1 is closed, it places the voltage from LDO 701 onto rail 708 to generate Vdd1. VddB represents another supply voltage available in the 0.7-0.8V range. However, it may not always be available; therefore, circuit 700 uses both VddA and VddB to provide a reliable Vdd1 across various times and operating modes. For example, VddB may be intermittently available, such as if it is a variable voltage that can fall below or exceed a desired range, in which case it may be unavailable. When VddB is available, circuit 700 can turn on switch S2 to place VddB onto power rail 708 to generate Vdd1.

[0051] In this example, at least when circuit 700 is energized, switches S1 and S2 are complementary, such that only one switch is always open and only one switch is always closed at a time. Current direction control boxes 702 and 703 ensure that current does not flow backward from VddB to VddA (or vice versa) when switching from one power rail to another. Switches S1 and S2 are not ideal in practice, so even though switches S1 and S2 are complementary, there is a possibility of current flowing from one rail to another, which is generally undesirable.

[0052] The current direction control boxes 702 and 703 can be as simple as diodes (or more complex), and they reduce or prevent reverse current from flowing from one track to another. The current direction controller 707 switches the current direction control boxes 702 and 703 on or off when not in use to save power.

[0053] The power controller 706 is the main controller, which understands the potentials of VddA and VddB and controls switches S1 and S2 based on the states of different voltage levels. For example, if VddB is unavailable, the power controller 706 can send a signal to the switch controller 704 to turn on S1 and turn off S2. On the other hand, if VddB is available at the desired potential for Vdd_Drvr, the power controller 706 can send a signal to the switch controller 704 to turn on S2 and turn off S1.

[0054] Various implementations may include one or more advantages over other systems. For example, some systems can use zero gate-source voltage to keep the head switch in the off state for the entire duration of the off state. However, as mentioned above, the system may still experience undesirable leakage because the zero gate-source voltage state may be less effective than the over-cutoff state. In contrast, the implementations described herein can use the over-cutoff state when appropriate, thereby experiencing less leakage, at least at some voltages.

[0055] Furthermore, the implementations described herein can transition from the over-cutoff state to the zero gate-source voltage state when the zero-voltage state is expected to cause less leakage compared to the over-cutoff state. Therefore, the various implementations can experience less total leakage than other systems, thereby increasing battery life. In addition, the various implementations described herein can provide reduced leakage with relatively small increases in silicon area.

[0056] The various implementations described herein can be applied to a System-on-a-Chip (SOC). Examples of SOCs include semiconductor wafers having multiple processing devices, including graphics processing units (GPUs), central processing units (CPUs), modem units, camera units, etc. In some examples, the SOC may be included within a wafer package, mounted on a printed circuit board, or housed within a portable device such as a smartphone or tablet. However, the scope of implementation is not limited to wafers implemented within tablets or smartphones, as other applications are also possible.

[0057] The SOC may include a CPU with multiple cores, and one or more of these cores may execute computer-readable code that provides the functionality of the operating system kernel. Furthermore, the example operating system kernel may include power management software that can power down portions of the logic on the SOC when they are not in use and power them up when those portions of the logic on the SOC are expected to be used. Therefore, the principles described above with respect to Figures 1 through 7 can be implemented in the SOC, and more specifically, the circuits shown in Figures 1 and 5 through 7 can be implemented in the SOC to provide power failure functionality.

[0058] For example, in a multi-core CPU, some cores may be unused at a given time, and power management software may power-down those unused cores. Continuing the example in this document, a given core may be serviced by one or more head switches, as described above with respect to Figures 1 and 6. Power management software can turn the head switches off to provide power-down and turn them on when intended for use.

[0059] A given core may be served by a single head switch (as shown in Figure 1), or it may have multiple parts served by multiple head switches (as shown in Figure 6). Of course, the scope of the implementation is not limited to causing the CPU core to power fail, as other logic circuits in the SOC (such as cameras, modems, GPUs, etc.) may also power fail.

[0060] Figure 8 illustrates a flowchart of an example method 800 for multiplexing among multiple power supplies. In one example, method 800 is performed by the circuitry shown in Figures 1 and 5 through 7. This circuitry can operate under the control of a power management unit, which may include hardware and / or software functionality at the processor (e.g., CPU) of a computing device served by the circuitry of Figures 1 and 5 through 7. In some examples, the power management unit includes a processing circuitry that executes computer-readable instructions to power or de-energize logic circuitry.

[0061] In action 810, a head switch is implemented to conduct current from the first power supply to the logic circuit device. An example is shown in Figure 1, in which the head switch 108 can provide current from the first power supply 106 to the logic circuit device 120 through its drain. Continuing with this example, the current is provided at a voltage Vdd_ext. The head switch 108 in this example is implemented by applying a logic 0 to its control terminal (its gate), which may include a negative gate-source voltage.

[0062] Actions 820 and 830 illustrate turning off the current by disabling the head switch. For example, action 820 includes selecting a first voltage level from a first voltage level and a second voltage level. An example is given in Figure 5, where a voltage generator for Vdd_Drvr selects between a reference voltage Vdd1 and a source voltage Vdd_ext.

[0063] In the example of Figure 5, comparator 501 compares Vdd1 and Vdd_ext. If Vdd1 is at a potential higher than Vdd_ext, voltage generator 500 selects Vdd1 as the output Vdd_Drvr. On the other hand, if Vdd_ext is higher than Vdd1, voltage generator 500 selects Vdd_ext (source voltage) as the output Vdd_Drvr.

[0064] Furthermore, in this example, Vdd1 is a reference voltage set to a potential above which the gate voltage is expected to experience an undesirable GIDL. Therefore, voltage generator 500 makes Vdd_Drvr equal to Vdd_ext, such that the gate-source voltage is zero in the case where GIDL would cause leakage. On the other hand, at the gate voltage (below which GIDL would be undesirable), voltage generator 500 applies Vdd1 as Vdd_Drvr, thereby maintaining the head switch in an over-off state, which is expected to cause less leakage compared to the case where the gate-source voltage is zero.

[0065] In action 530, the circuit applies a first voltage level from the second power supply to the gate of the head switch. Continuing this example, the circuit of Figure 5 causes Vdd1 or Vdd_ext to be applied to the gate of the head switch by the second power supply (Vdd_Drvr).

[0066] The scope of the implementation is not limited to the specific actions shown in Figure 8. Instead, other implementations may add, omit, rearrange, or modify one or more actions. In one example, during normal operation of the computing device, the implementation may switch between energizing the logic circuit, such as in action 810, and de-energizing the logic, such as in actions 820 and 830, multiple times. For example, the logic circuit may be energized when it is used to execute code, and de-energized when it is idle.

[0067] As will now be understood by those skilled in the art, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, arrangements, configurations, and methods of use of the devices of this disclosure without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific implementations shown and described herein, as they are merely examples; more precisely, the scope of this disclosure should be fully commensurate with the scope of the appended claims and their functional equivalents. [Simplified Explanation of the Diagram]

[0010] Figure 1 is a simplified diagram showing an example system of a power gate logic circuit device according to an implementation.

[0011] Figure 2 is a graph showing an example relationship between the drain current and the gate voltage of the head switch in Figure 1 according to one implementation.

[0012] Figure 3 is a graph showing an example relationship between gate voltage and source voltage according to the implementation of Figure 2.

[0013] Figure 4 is a diagram of the various voltage levels used in the implementation of Figure 1.

[0014] Figure 5 is a diagram of an example voltage generator adapted according to one implementation.

[0015] Figure 6 is a simplified diagram illustrating, according to one implementation, that the system of Figure 1 can be repeated to cause multiple parts of the logic to power failure.

[0016] Figure 7 is a diagram of a reference voltage circuit for generating a reference voltage according to an implementation.

[0017] Figure 8 is an illustration of a method for multiplexing among multiple power supplies.

Claims

1. A system comprising: First power supply; Second power supply; A head switch is disposed between the first power supply and the logic circuit device; The power driver couples the second power supply to the control terminal of the head switch; And a voltage generator operable to adjust the control voltage from the second power supply to the control terminal of the head switch in response to a first voltage level of the first power supply exceeding a reference voltage level.

2. The system according to claim 1 further includes: A control circuit is coupled to the voltage generator and can be operated to force the voltage generator to reach the first voltage level.

3. The system according to claim 1, wherein the first power supply includes a power rail.

4. The system according to claim 1, wherein the source terminal of the head switch is coupled to the first power supply.

5. The system according to claim 1, wherein the voltage generator comprises: The comparator has a first input coupled to the first power supply and a second input coupled to a reference voltage circuit that generates the reference voltage level; A first transistor is coupled to a first power rail at the reference voltage, and the first transistor is gate-coupled to the output of the comparator via an inverter. And a second transistor, coupled to the first power supply, and the second transistor is gate-coupled to the output of the comparator.

6. The system according to claim 5, wherein the reference voltage circuit comprises: The first switch is coupled to the first reference voltage source; The second switch is coupled to the second reference voltage source; And a switch controller, operable to select between the first reference voltage source and the second reference voltage source.

7. The system according to claim 5, wherein the head switch includes a positive channel metal-oxide-semiconductor PMOS transistor having a drain coupled to the logic circuit device, and wherein the control terminal includes a gate of the PMOS transistor.

8. A method comprising: Enable the head switch to conduct current from the first power supply to the logic circuit device; And shutting off the current by disabling the head switch includes: in response to comparing a first voltage level with a second voltage level, selecting the first voltage level from the first voltage level and the second voltage level; And to apply the first voltage level from the second power supply to the gate of the head switch.

9. The method according to claim 8, wherein applying the first voltage level comprises: The head switch is kept in the over-cutoff state.

10. The method according to claim 8, wherein applying the first voltage level comprises: When the gate-source voltage is zero, the head switch is kept in the off state.

11. The method according to claim 8, wherein selecting the first voltage level is a response to the first voltage level being higher than the second voltage level, wherein the first voltage level corresponds to a reference voltage.

12. The method according to claim 8, wherein selecting the first voltage level is a response to the first voltage level being higher than the second voltage level, further wherein the first voltage level corresponds to a time-varying power rail voltage and the second voltage level corresponds to a reference voltage.

13. The method according to claim 8, wherein turning off the current comprises: An enable signal is received at a buffer, wherein the enable signal is at the same voltage level as the first voltage level.

14. A circuit comprising: The first electric rail is coupled to the first power supply; The second power rail is coupled to the second power supply; A power control switch is coupled between the first power rail and a portion of the logic circuitry of the central processing unit (CPU). And a component for selecting a control voltage from the second power rail to the control terminal of the power gate switch in response to a first voltage level of the first power supply being lower than a reference voltage level.

15. The circuit according to claim 14, further comprising: A component for applying the control voltage to the control terminal in response to an enable signal.

16. The circuit of claim 15, wherein the component for applying the control voltage includes an inverting buffer configured to receive the enable signal, wherein the enable signal is at the same voltage level as the reference voltage level.

17. The circuit according to claim 14, wherein the power gate switch comprises a positive channel metal-oxide-semiconductor (PMOS) transistor head switch.

18. The circuit according to claim 14, wherein the selection element comprises: The comparator has a first input and a second input, the first input being coupled to the first power rail and the second input being coupled to a component for generating the reference voltage level; And a component for adjusting the control voltage between the first voltage level and the reference voltage level in response to the output of the comparator.

19. The circuit according to claim 18, wherein the components for generating the reference voltage level comprise: The first switch is coupled to the first reference voltage source; The second switch is coupled to the second reference voltage source; And a component for selecting between the first reference voltage source and the second reference voltage source to apply to the second input.

20. The circuit according to claim 14, further comprising: The overclocking circuit is coupled to the selection member and can be operated to force the selection member to reach the first voltage level.

21. The circuit according to claim 14, wherein the selection element comprises: A component for applying the control voltage at the reference voltage level from the second power rail.

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