Transmitter for dual communication over an isolation channel

Abstract

An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.

Description

[Previous Technology]

[0001] This invention relates to isolation technology, and more specifically, to communication across an isolation barrier. [Summary of the Invention]

[0002] Therefore, in one embodiment, a method includes receiving first information and second information for transmission across a single isolated communication channel. The method further includes simultaneously transmitting the first information and the second information across the single isolated communication channel.

[0003] In another embodiment, a device includes at least two input terminals coupled to receive first information and second information, respectively. A modulation circuit uses the first information and the second information to generate a modulated signal. A transmitter simultaneously supplies the first information and the second information to a single isolated communication channel in the modulated signal.

[0004] In another embodiment, a device includes a first input terminal for receiving gate information and one or more input terminals for receiving configuration information. A modulation circuit is configured to generate a modulated signal having one of four possible states, each of the four possible states corresponding to a different pair of unique values ​​of the gate information and the configuration information. The modulation circuit is configured to use frequency modulation to generate the modulated signal to generate one of the four states, wherein the frequency of the modulated signal varies between at least two frequencies to indicate one of the four possible states.

Implementation Method

[0027] Disclosure of Embodiments of the Invention

[0028] Isolated communication channels are used in various applications where it is necessary to prevent current from flowing between isolated circuits while still maintaining communication between them by using an isolation barrier. Isolation may be required for signal isolation, security, or other reasons. Communication between isolated circuits typically involves communication between a transmitter and receiver via an isolated communication channel to provide, for example, control information between different voltage domains. Isolated communication channels can be implemented, for example, using capacitive, inductive (transformer), or optical (optical isolator) isolation techniques. In a typical isolation application, a control system provides one or more control signals for controlling a load system. During normal operation, a large DC or transient voltage difference may exist between the domain of the control system and the domain of the load system, thus requiring an isolation barrier between the control system and the load system. Isolation of circuits in separate voltage domains using an isolation barrier prevents damaging current from flowing between the control system and the load system via a direct conductive path, while the isolated communication channel allows communication between the two systems.

[0029] Figure 1 illustrates a prior art system 100 including an isolation gate driver 101. The gate driver 101 receives control information, specifically a gate signal, of a high-power transistor 102 that provides control information for driving and providing control functionality. In the exemplary system 100, a controller 103 (which may be a microprocessor, microcontroller, or other suitable processing device) operates in a first domain (i.e., a domain including VDD1 and VDD2). The controller 103 provides a gate signal to control a load system operating in a second domain (i.e., a domain including VDD3 and VDD4). The isolation barrier electrical isolation includes a primary side of VDD1 (e.g., less than 20 volts) and VDD2 (e.g., less than 20 volts) and their coupled devices, and a secondary side of VDD3 (e.g., tens of volts) and VDD4 (e.g., hundreds of volts) and their coupled devices.

[0030] The isolated gate driver 101 includes a transmitter circuit 106 and a receiver circuit 108 that communicate via an isolated communication channel 109. In system 100, controller 103 supplies gate information (GATE) to transmitter circuit 106 in a first voltage domain. Transmitter circuit 106 transmits the gate information to receiver circuit 108 in a second voltage domain. Receiver circuit 108 uses the gate information to generate a gate drive signal 120 to drive a high-power transistor 102 used to control a system load.

[0031] Although isolated gate drivers allow communication across isolation barriers, improvements to this communication are desired to provide more precise control over system load. Several modes for implementing the invention.

[0032] A typical CMOS digital isolation solution has a single communication channel 109 as shown in Figure 1. A second isolated communication channel is typically required to dynamically transmit information other than gate information, such as status bits, configuration bits, etc., across the isolation barrier. Gate signals cannot delay a critical control function while transmitting configuration information. Therefore, referring to Figure 2A, in order to provide configuration information (e.g., dynamic drive strength information) in addition to gate information, system 200 utilizes an isolated gate driver 201 with a separate isolated communication channel 210 to transmit configuration information. Separate transmitter circuits 206A and 206B utilize two isolated communication channels 209 and 210 to transmit gate information and configuration information to receiver circuits 208A and 208B on the secondary side, respectively. Transmitter circuit 206A transmits gate information via the first isolated communication channel 209. Transmitter circuit 206B transmits configuration information (information other than gate information) via the second communication channel 210. The illustrated differential isolation communication channels 209 and 210 each transmit a positive (TX-P) signal and a negative (TX-N) signal. While the illustrated isolation channels 209 and 210 utilize capacitive isolation, other embodiments may employ various isolation methods, such as inductive or optical coupling between communication coupling transmitting circuits 206A and 206B and receiving circuits 208A and 208B. Therefore, the physical implementation of the isolated communication channels may differ in different embodiments.

[0033] The secondary side includes a driver circuitry (e.g., included in receiver circuitry 208A) that generates a gate signal 216 based on a GATE signal received from the primary side and provides the gate signal 216 to the gate of device 218. In an exemplary embodiment, high-power device 218 controls the power delivered to a load. Exemplary high-power devices include power metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gallium nitride (GaN) MOSFETs, silicon carbide (SiC) power MOSFETs, and other suitable devices capable of delivering high-power signals.

[0034] In this embodiment, there are two states of the controlled gate signal 216. The receiving circuit 208A controls whether the gate signal is on or off and also controls the drive strength of the gate signal 216 based on the configuration information received from the receiving circuit 208B.

[0035] Therefore, as explained above, in one method, a second isolated communication channel carries configuration information. While providing one communication path for configuration information is beneficial, the second communication channel 210 consumes additional power and requires additional silicon area. Furthermore, packaging limitations typically prevent the inclusion of a second isolated communication channel. To overcome packaging limitations and the disadvantages attributable to the additional power and area of ​​a second isolated communication channel, although dynamic configuration information is still provided, the embodiments described herein transmit configuration information and main digital gate signals simultaneously via a single isolated communication channel without affecting the main performance requirements of the main digital signals.

[0036] Referring to FIG. 2B, in one exemplary embodiment, system 220 includes an isolated gate driver 221, which includes a transmitter circuit 226 and a receiver circuit 227 communicatively coupled across an isolation barrier using an isolated communication channel 228. System 220 includes a primary-side integrated circuit (containing the transmitter 226) and a secondary-side integrated circuit (containing the receiver 227) respectively disposed in a first voltage domain and a second voltage domain. In an embodiment, the transmitter circuit 226 is formed on a first integrated circuit die and the receiver circuit 227 is formed on a second integrated circuit die, both attached to a leadframe and including terminals coupled to the isolated channel 228 formed on the leadframe and packaged as a single device. In other embodiments, the transmitter circuit 226 and the receiver circuit 227 include terminals coupled to the isolated communication channel 228, all of which are formed on an integrated circuit die. In other embodiments, transmitter circuit 226 and receiver circuit 227 are integrated circuits included in a multi-chip module. In embodiments, terminals of the transmitter circuit and receiver circuit are coupled to external components (e.g., transformers, discrete resistors, and discrete capacitors within the multi-chip module) or terminals of the multi-chip module package and one of the packages of controller 222.

[0037] In an embodiment, transmitter circuit 226 and receiver circuit 227 utilize a modified on / off keying (OOK) to allow simultaneous transmission of primary digital signals and configuration information via a single isolated communication channel 228. Compared to the two-channel implementation shown in FIG2A, where one channel is used for primary digital signals and the other for configuration information, the embodiment described herein uses a single isolated communication channel to consume less power and utilize less silicon die area. In one example, as further described herein, the single isolated communication channel 228 carries both gate information and drive strength information of the gate signal 230 used to drive transistor 232.

[0038] Figure 3 illustrates conventional on-off keying (OOK) modulation. OOK is a form of amplitude shift keying modulation that represents digital data as the presence or absence of a high-frequency signal on a communication channel. For example, when the GATE signal (e.g., used to drive the gate of transistor 232 in Figure 2B) is a logic "0", the transmitter transmits a steady-state signal (OV) at 301 on a differential isolation channel (TXP-TXN) (where TXP is the positive transmit signal of the differential pair and TXN is the negative transmit signal). When the GATE signal is a "1", the transmitter transmits a high-frequency signal at 303, for example, with a frequency of 500 MHz, via an isolated communication channel. Thus, the presence of the high frequency represents a binary 1, and its absence represents a binary 0. However, conventional OOK can only transmit one piece of data at a time. In contrast, the embodiments described herein transmit the main digital signal (e.g., the gate signal) and configuration (or other) information via a single isolated communication channel. The primary digital signal can be a logic 1 or a 0, and regardless of the logic value of the primary digital signal, the configuration information can also be a logic 1 or a 0.

[0039] Figure 4 illustrates a high-level block diagram of one embodiment of the transmitter side 400 of an isolated gate driver. In the illustrated embodiment, gate information 401 from controller 222 (Figure 2B) provides information for the main digital signal (gate signal). Additionally, the transmitter side receives configuration information at input terminals 403 and 405. The configuration information may be provided in various forms (such as an analog voltage, a current, a digital voltage, or the resistance value of a resistor coupled to input terminals 403 and 405). The transmitter circuit transmits both configuration information and gate information simultaneously via a single isolated communication channel. Configuration detection and mapping circuitry 407 receives parameters (voltage, current, digital value, resistance) present at input terminals 403 and 405 and maps the parameters to a specific drive strength value. In one embodiment, the configuration detection and mapping logic determines whether to map a voltage value, current value, digital value, or resistance value to a drive strength. This can be accomplished through a one-time programmable memory (OTP) whose parameters are programmed to the isolated gate driver. In one embodiment, the configuration detection and mapping logic maps configuration information to three bit values ​​(P2, P1, P0) for configuration CONFIG1 and three bit values ​​(N2, N1, N0) for CONFIG2. In one embodiment, P2, P1, P0 control the drive strength of the gate signal generated by the PFET when the gate signal is pulled up, and N2, N1, N0 control the drive strength of the gate signal generated by the NFET when the gate signal is pulled down. The configuration detection and mapping circuit 307 supplies the three bit values ​​to the parallel-to-serial logic circuit 409, which converts parallel bits into a serial word. In one embodiment, the parallel-to-serial logic circuit 409 also adds an initial bit, a co-occurrence bit, and redundancy to the serial word (as shown in FIG. 5) for transmission across the isolated communication channel. For example, bit (P2) and its complement () are transmitted via an isolated communication channel. Other embodiments add additional p-bits to provide multi-bit error correction or other error checking techniques. Each serial bit is transmitted on the isolated communication channel along with a value of the GATE signal. A typical serial bit time is 1 μs or 2 μs, but other embodiments use a bit time of a different length. Logic 409 supplies the serial word to the transmit OOK modulation circuit 411, which is further described herein. The transmit OOK modulator also receives the gate signal from input terminal 401.

[0040] Figures 6 and 7 illustrate additional details of the configuration detection and mapping circuit 401. In one embodiment, the resistance values ​​of resistors 601 and 603 coupled to input terminals 403 and 405 determine the drive current strength of the gate signal. Currents from current sources 607 and 608 cause voltages across resistor 601 and variable resistor 609, and comparator 610 receives both voltages. Successive Approximation Register (SAR) 611 adjusts variable resistor 609 until comparator 610 indicates that the voltages at its inputs are equal (e.g., when the comparator output polarity changes) to indicate that the SAR setting corresponds to the value of external resistor 601. Mapping logic 615 maps the final SAR value (or equivalent resistance value) to a three-bit code indicating the drive current strength, as explained in more detail in the example of Figure 7. The configuration information on input terminal 405 is similarly determined using current sources 617 and 619, variable resistor 621, comparator 623, and SAR 625. SAR 625 is adjusted until the voltage at the input of comparator 623 is the same, thereby indicating the value of external resistor 603.

[0041] In another embodiment, a voltage level is supplied to input terminals 403 and 405 to specify configuration information instead of using resistors 601 and 603. In this embodiment, instead of connecting resistors, controller 222 (see FIG. 2B) supplies a voltage from, for example, a digital-to-analog converter (DAC) in the controller to the input terminals. To operate in "analog voltage" mode, current source 607 is turned off and current source 608 supplies a known current to variable resistor 609. SAR 611 adjusts the variable resistor until comparator 610 indicates that the voltages at its inputs are equal. The voltage across variable resistor 609 is supplied to mapping logic or the SAR output (variable resistor setting) is interpreted as an estimate of the voltage level seen at terminal 403. Detection of the voltage at input terminal 405 is similarly accomplished. Current source 617 is turned off and current source 619 supplies a known current. SAR 625 adjusts the variable resistor 621 until the comparator 623 indicates that the voltage at its input is equal. The voltage across the variable resistor 621 (or the SAR output) is supplied to the mapping logic 615, which interprets the SAR setting as an estimate of the voltage seen at terminal 405.

[0042] In another operating mode, instead of applying a resistor or analog voltage to the input terminal receiving configuration information, a digital value is applied to the input terminal to allow selection of two different values ​​of configuration information at each input terminal. In one embodiment of the "digital" mode, current source 607 is turned off and current source 608 supplies a current to a fixed resistance value of variable resistor 609 that causes a threshold voltage value to be supplied to the comparator. The threshold voltage distinguishes between a logic 1 and a logic 0. The comparator output can be directly supplied to the mapped logic 615. In other digital embodiments, a discrete comparator is used to determine a logic 0 or 1. In other embodiments, one or more of terminals 403 and 405 act as a serial input port and supply configuration in a digital word to allow for greater selection of configuration settings. The circuitry associated with input terminal 405 operates in digital mode in a manner similar to that described with respect to input terminal 403. Many other circuits can be used to determine the voltage, resistance, current, capacitance, or other parameter values ​​at terminals 403 and 405. The circuit shown in Figure 6 is an example, and many other circuits can be used to receive and determine parameter values ​​that a skilled technician will understand.

[0043] Figure 7 illustrates one embodiment of a mapping function that maps resistance, analog voltage, or digital values ​​to a specific configuration value. In one embodiment, for example, the operating mode (analog resistance, analog voltage, digital) is programmed into a one-time programmable memory 625 via an interface 627. In other embodiments, the operating mode can be programmed into other types of memory (e.g., non-volatile memory (NVM)) in the transmitter integrated circuit. Referring to the embodiment of Figure 7, in the "analog resistance" mode 701, the resistance value is mapped to configuration states S0 to S7, represented by three bits. The three bits are mapped to eight different drive current intensities, displayed as a percentage of drive current intensity 705. Figure 7 shows that various configuration states S0 to S7 are mapped to a specific percentage of drive current intensity in the range of 8.75% to 100% of the maximum drive current. For example, a resistance close to 4.42 kΩ (state S2) is mapped to a 17.5% drive current intensity. Therefore, 17.5% of the maximum drive current intensity is used for at least one value of the drive gate signal. This specific percentage is merely an example, and other embodiments may utilize different percentages of the drive current intensity and different numbers of configuration bits. It should be noted that the resistance values ​​are illustrative, and other resistance values ​​may be used in other embodiments.

[0044] The table in Figure 7 also illustrates how the voltage level 703 at the input terminal is mapped to different configuration states in "analog voltage" mode. For example, a voltage level close to 221 mV (state S2) is mapped to 17.5% of a drive current intensity percentage. In voltage mode, a controller (e.g., controller 222 in Figure 2B) supplies voltage to the input terminal. Although an analog voltage mode is shown in the figure, other embodiments use an analog current and map the analog current value to the configuration state.

[0045] In "digital mode," an external controller (e.g., controller 222 (FIG. 2B)) uses digital signals to drive configuration terminals and maps states S0 and S8 to arbitrary drive strength values, represented as p / nfet_str_low and p / nfet_str_high. For example, a bit "0" on pin 403 is mapped to pfet_str_low and a bit "1" on pin 403 is mapped to pfet_str_high, and a bit "0" on pin 405 is mapped to nfet_str_low and a bit "1" on pin 405 is mapped to nfet_str_high. PFET and NFET transistors (see, for example, FIG. 18) are used to generate gate drive signals. In one embodiment, the drive strength values ​​of the digital mode are programmed into an OTP (or NVM). Specific mappings of resistance, voltage, and percentage can also be programmed into memory (OTP, NVM, or others) used by the mapping logic 615.

[0046] In one embodiment, the configuration terminal also provides a deactivation feature to disable the transmitter. A bit in memory (OTP, NVM, or others) is set to indicate that the deactivation feature is enabled. If state S8 is received in analog (resistance or voltage) or digital mode, the deactivation feature disables the transmit signal path in the transmit circuit. The deactivation feature may cause 0 V coupling to the transmit signal path or otherwise disable transmit. In analog voltage mode, a voltage >850 mV is mapped to S8, and in analog resistance mode, a high impedance (hiZ) value is mapped to S8. In digital mode, a logic 1 indicates the state of S8 and thus the deactivation mode. When the deactivation feature is enabled, digital mode provides only one single drive current intensity value in S0. Using this deactivation feature, a single pin can be used to control both the drive intensity of the transmitter and the enable / disable function, thus allowing more features in a smaller pin count package.

[0047] In one embodiment, some additional bits in the memory (OTP, NVM, or others) indicate the use of a single pin (instead of two) to indicate signal strength. In one embodiment, the additional bits always indicate the use of a specific input terminal; for example, if a single-pin bit is configured, input terminal 403 is always used. In other embodiments, the additional bits can be used in single-pin mode to indicate which input terminal is a "single pin". Therefore, in single-pin mode, drive strength information from only one of the configuration pins is used to generate both P2, P1, P0 and N2, N1, N0. Using single-pin mapping to both P and N functions, drive strength control can be used to reduce the pin count package, where only a single pin is available for the strength control function. Embodiments may include the ability to support any or all of several operating modes (including analog / digital, disabled / non-disabled, and single-pin / non-single-pin).

[0048] Referring again to Figure 6, after the mapping is completed, the parallel data is converted into serial data in logic 409, and initial bits, redundancy (to the desired extent), and co-occurrence for serial transmission across isolation communication are added. The serial data is supplied to the OOK modulator 411, which modulates the serial configuration data and gate signals. Figures 8 and 9 illustrate the operation of the OOK modulator.

[0049] Figure 8 illustrates one embodiment of a modulation scheme that allows simultaneous transmission of both configuration information and gate information. To transmit configuration information with a value of CONFIG=0 and GATE=0, a constant voltage is transmitted, as shown in 801. For CONFIG=1 and GATE=0, the signal is modulated at a frequency of 64 MHz, as shown in 802. For CONFIG=0 and GATE=1 (as shown in 803), the signal is frequency modulated at the OOK frequency. In one embodiment, the OOK frequency is 450 MHz. When CONFIG=1 and GATE=0, the OOK frequency should be high enough to be easily distinguishable from lower frequency signals. Finally, for GATE=1 and CONFIG=1, the signal is frequency modulated using a first frequency shown in 805 and a second frequency shown in 807 during the bit time period. The frequencies are included in the envelope 809. In one embodiment, the frequency shown at 807 is 450 MHz and the frequency shown at 805 is 550 MHz, and the envelope at 809 is an 8 MHz envelope. Therefore, the modulator responds to the GATE signal by providing direct OOK modulation (a 0 MHz or 450 MHz signal) when the CONFIG signal is equal to 0 and by providing an adjustment to the OOK signal (approximately 64 MHz or 450 MHz / 550 MHz) when the CONFIG signal is equal to 1. It should be noted that the frequency deviation of the transmitted signal responds substantially more to changes in the GATE signal than to changes in the CONFIG signal. For example, a change in the GATE signal causes the modulation frequency to change from 0 MHz to 450 MHz. In contrast, a change in the CONFIG signal (assuming the GATE signal is constant) causes the modulation frequency to change from 0 MHz to 64 MHz or from 450 MHz to 550 MHz. This frequency separation helps ensure accurate demodulation of one of the GATE signals.

[0050] Figure 9 illustrates one embodiment of the OOK modulator 411. A modulated signal is generated based on the values ​​of the CONFIG signal 901 and the GATE signal 903 to produce the signal shown in Figure 8, representing four states (two binary values ​​of CONFIG and two binary values ​​of GATE). The AND gate 905 receives the CONFIG signal 901 and the envelope signal 911. Oscillator control logic 908 receives the output of the AND gate 905 and controls the oscillator 909 to generate a 450 MHz signal or a 550 MHz signal. An output of 0 from the AND gate 905 causes the oscillator 909 to generate a 450 MHz signal, and an output of 1 causes the oscillator to generate a 550 MHz signal. The oscillator 909 can be implemented as a ring oscillator with different taps for different frequencies or different supply voltages or currents, an LC oscillator with an adjustable capacitor, or any other suitable oscillator. When CONFIG=0, oscillator 909 generates a 450 MHz signal, and when CONFIG=1, oscillator 909 generates both 450 MHz and 550 MHz signals according to a ratio determined by the rate of envelope signal 911. For example, using an 8 MHz envelope signal, the 450 MHz and 550 MHz signals repeat at an 8 MHz rate, as shown in Figure 8. Divider circuit 915 divides the oscillator output signal by 8 or another suitable divisor to easily distinguish the lower frequency signal from the 450 MHz / 550 MHz signals. When CONFIG=0, AND gate 917 supplies a -0 to multiplexer 919. Multiplexer 919 receives one input signal from oscillator 909 and another input signal from AND gate 917. The value of the GATE signal is selected as the input to the output of multiplexer 919. When GATE=1, the multiplexer selects the oscillator output signal (450 MHz or 450 MHz / 550 MHz) as the multiplexer output signal depending on the value of CONFIG. When GATE=0, the multiplexer selects the output of the AND gate 917 corresponding to the signal shown in 801 or 802. The AND gate 917 supplies a 0 when CONFIG=0 or supplies the output of the divider 915 when CONFIG=1. It should be noted that in the embodiment of FIG9, when CONFIG=1 and GATE=0, the divider causes the oscillator output to perform division according to the change of the envelope signal. Therefore, when the envelope signal 911 determines the rate of change between two frequencies, the signal is divided by 8 to 450 / 8 MHz and 550 / 8 MHz. In other embodiments, the GATE signal is also supplied to control logic 908 and has GATE=0 and CONFIG=1, and control logic 908 forces the oscillator output to be fixed at 450 MHz or 550 MHz in this state, and therefore the frequency at 802 is fixed at 56.25 MHz or 68.75 MHz.A 64 MHz signal indicates that one of the specific states, where GATE=0 and CONFIG=1, is suitable for a frequency, but the frequency may be higher, lower, or vary depending on the specific embodiment. The signal from multiplexer 919 is then supplied to drivers 921 and 923 and transmitted via an isolated communication channel. The transmitted signal is then received by a receiver coupled to the isolated communication channel and sent to a demodulator to recover the GATE and CONFIG signals. The GATE signal controls the transistor coupled to the receiver circuitry, and the CONFIG information is deserialized to recover the configuration bits, which are then used, for example, to control the drive strength of the GATE signal.

[0051] The drive strength mode of the modulator shown in FIG9 can be easily disabled (for example) by setting CONFIG 901 to 0, and the OOK signal then returns to a conventional OOK modulation with a 1 indicated by a 450 MHz signal and a 0 indicated by a steady-state voltage (such as 0 V). In this way, in applications where a drive strength signal is not provided, the modified OOK modulator can operate as a standard OOK modulator. In one embodiment, this modified OOK modulator is configured as a standard OOK modulator and controlled by OTP in a similar manner to that described in other modes of the embodiments described herein.

[0052] Another example waits until GATE=1 to transmit configuration information. The OOK signal is frequency-modulated to indicate CONFIG=1 (or 0) (as shown in 805 and 807) and the OOK signal is a fixed frequency (as shown in 803) to indicate CONFIG=0 (or 1). This method has the advantage of being simpler but limits the transition to only when the main signal (e.g., GATE) is 1. Furthermore, instead of frequency modulation, other embodiments modulate the OOK signal when GATE=1, but this method becomes more difficult for higher OOK frequencies with smaller pulse widths.

[0053] Various other modulation schemes can be used. For example, four frequencies can be used to represent the four states represented by GATE and CONFIG. In some such embodiments, a change in the GATE signal causes a frequency deviation at the output of the modulator that is much larger than a change in the CONFIG signal. In this way, the integrity of the GATE signal can be maintained, while a relatively small frequency change caused only by the CONFIG signal will only cause a small change in the demodulation of the GATE signal. Alternatively, various patterns of 1 and 0 can be used during a single bit of time to represent different values.

[0054] Figure 10 illustrates a block diagram of one embodiment of the receiver 227 shown in Figure 2B. The receiver receives a differential signal, RXP and RXN, transmitted via an isolated communication channel. These signals are amplified in one or more amplifiers 1001 and supplied to an OOK demodulator 1003 to demodulate gate information from the received differential signals and to supply a gate signal 1005. The gate signal and the received signal, after amplification, are supplied to a configuration demodulation path 1007, which extracts configuration information from the received differential signals and supplies the configuration information to a clock recovery, deserialization, and error checking circuit 1009. The clock recovery, deserialization, and error checking circuit 1009 converts the serial data stream received via the isolated communication channel into a parallel word (e.g., 3 bits) of configuration information for use as a drive strength signal in driver control logic 1010. Therefore, the clock recovery, deserializer, and error checking circuit 1009 recovers a clock signal to sample the serialized output data 1012 via the auto-configuration demodulation path 1007, and then generates P2, P1, P0 and N2, N1, N0. It checks for identical bits, redundant bits, or otherwise performs error checking to ensure the data is correct before updating the configuration settings of the driver control circuit 1010. If an error is found, the drive strength value is not updated. Other configuration settings can also be controlled by the transmitted configuration information. For example, the configuration information can specify the type of error report to be made, the preset value of the drive strength, or the on and off times of the high-power transistor. In the embodiment of FIG10, two output terminals 1020 and 1022 are used to supply the on and off signals of the gate signal, which are externally combined to drive the power transistor. The VOP pin 1020 provides a positive drive current to turn on the power transistor, and the VON pin 1022 provides a sink current to turn off the power transistor. Other embodiments utilize a single output terminal of the gate signal. The intensity of the drive current provided by the driver control logic 1010 is controlled by the configuration information.

[0055] Figure 11 illustrates additional details of one embodiment of a demodulator in the receiving circuit. The demodulator includes a gate demodulation path 1101 and a set-mode demodulation path 1102. Figure 12 illustrates an exemplary waveform involved in the demodulation of the transmitted signal. In the exemplary waveform of Figure 12, ISORX 1104 (the amplified received signal) begins in a state indicating CONFIG=1 and GATE=0 (oscillating at 64 MHz) and then changes to CONFIG=0 and GATE=1 (oscillating at 450 MHz). Referring to Figures 11 and 12, amplifier 1103 supplies an amplifier output ISORX 1104 to a filter 1105. In one embodiment, filter 1105 is implemented as a bandpass filter having a center frequency of approximately 500 MHz and a bandwidth such that it can pass through 450 MHz and 550 MHz but rejects other frequencies such as 64 MHz and frequencies associated with noise in the system. Filter 1105 supplies a filter output 1106 as an input to a root mean square (RMS) detection circuit 1107. The RMS detection circuit 1105 detects the energy in the received signal and supplies an RMS output signal 1108 to comparators 1109 and 1111. Comparator 1109 compares the RMS detection output 1108 with a reference voltage REF1 shown in Figure 12. In Figure 12, the RMS output 1108 is below REF1 (when ISORX oscillates at 64 MHz) until 1201 (when the RMS output signal 1108 becomes above the voltage threshold REF1) to indicate that the RMS value corresponds to an oscillation value of at least 450 MHz. At this time, the GATE signal 1110 changes from 0 to 1. It should be noted that if the oscillation is 450 MHz / 550 MHz (GATE=1, CONFIG=1), the GATE signal supplied by comparator 1109 will still be -1 because the RMS detection output 1108 will still be higher than REF1. Therefore, the gate demodulation path 1101 acts as an OOK demodulator and seeks oscillations at or above a specific frequency (450 MHz) while ignoring oscillations below that frequency, thus ignoring the modification of the OOK signal caused by CONFIG=1 when GATE=0, resulting in ISORX oscillating at approximately 64 MHz. When the RMS detection output rises above REF1, the GATE signal 1110 from comparator 1109 becomes 1, and when the RMS detection output falls below REF1, the gate signal 1110 becomes 0.

[0056] In one part of the configured demodulation path, comparator 1111 compares the output 1108 of the RMS detection circuit 1107 with the voltage threshold REF0. As shown in Figure 12, when ISORX oscillates at 64 MHz (GATE=0 and CONFIG=1), the comparison results in an oscillation signal 1115 at 128 MHz. When ISORX is 0, the slow path signal is zero, and when ISORX is 450 MHz or 450 MHz / 550 MHz, the slow path signal 1115 is a "1". Comparator 1111 supplies the slow path signal 1115 to the digital demodulation block 1118, which contains the sub-demodulation paths further described herein.

[0057] The fast path signal 1117 of the configuration demodulation path originates from the output 1104 of amplifier 1103, and the fast path signal supply (with an 8 MHz envelope when GATE=1 and CONFIG=1, and no envelope when GATE=1 and CONFIG=0) is supplied to the digital demodulation block 1118. A Schmitt trigger 1120 converts the output of amplifier 1103 (after a buffer circuit) into a digital value for use in the digital demodulation block 1118. It should be noted that some circuitry is shared in the gate demodulation path and the configuration demodulation path.

[0058] Figure 13 illustrates additional details of the sub-demodulation paths 1301 (slow path) and 1303 (fast path) of the configuration demodulation path, and some common elements of the configuration demodulation path including selector circuit 1305 and counter 1307. Selector circuit 1305 selects the fast path signal or the slow path signal based on the value of GATE signal 1110. If GATE signal is "1" to indicate that the transmit signal is at least 450 MHz, selector circuit 1305 selects fast path signal 1117. If GATE signal is "0" to indicate that the transmit signal is approximately 64 MHz (variing between 56.25 MHz and 68.75 MHz in the embodiment shown in Figure 9) or a slower frequency, selector circuit selects slow path signal 1115. Ripple counter 1307 counts the number of pulses from the fast path signal or the slow path signal and supplies the count value to fast path sub-demodulation path 1303 and slow path sub-demodulation path. Counter 1307 is periodically reset by reset signal 1306. Slow path sub-demodulation path 1301 receives the count value 1308 and compares it with an integer value to see if the count value is within a frequency range bounded by integer values ​​M and N. If the count value is higher than a minimum value M and lower than a maximum value N, the frequency of the slow path signal is within the frequency range (e.g., a frequency range including 128 MHz), and the output 1312 from AND gate 1310 becomes a "1". If the count value is lower than M (e.g., CONFIG=0), AND gate 1310 supplies a "0" on output 1312. If the count value is higher than N, indicating that the slow path signal has a frequency higher than (e.g.) approximately 128 MHz, AND gate 1310 supplies a "0".

[0059] The fast path sub-demodulation path 1303 receives a count value at comparator logic 1314 and selector circuit 1316. Comparator logic 1314 determines whether the count value is greater than or equal to an integer P to indicate that the frequency of the transmitted signal (and fast path signal) is higher than a predetermined frequency, for example, 450 MHz. If the count value 1308 is less than P, then selector circuit 1316 selects 0, otherwise selects the count value. Envelope detector 1318 detects the presence of an envelope (e.g., an 8 MHz envelope shown in FIG. 8). In one embodiment, envelope detector 1318 performs a discrete Fourier transform (DFT) at a single frequency to find the energy at 8 MHz and detect the envelope. Therefore, if the count value changes between periodic resets based on a 450 MHz / 550 MHz transmitted signal (GATE=1, CONFIG=1), an envelope is detected and the output of envelope detector becomes "1". On the other hand, if no envelope is detected (e.g., the transmitted signal is 450 MHz 1 (GATE=1, CONFIG=0)), the output of the envelope detector is "0". The output 1320 of the envelope detector is combined with the output 1312 of the AND gate 1310 in the OR gate 1322. A filter (e.g., a finite impulse response (FIR) filter 1323) removes short-duration pulses from the output of the OR gate 1320 and supplies a serial output 1324. Additional filters (e.g., additional FIR filters) may be used in the fast and slow sub-demodulation paths, which are not shown for ease of illustration. In one embodiment, the comparison logic uses four samples of every 8 MHz envelope (using a 32 MHz built-in clock signal) in the fast path to compare the count value from the counter 1307 with M, N, and P, and obtains a similar number of counts for the 128 MHz input of the slow path. In one embodiment, comparisons are made only for the selected path (active path), forcing the output of the non-selected path to zero at OR gate 1322. The idea is that at any given time, only one of the slow path and the fast path is active.

[0060] Figure 14 illustrates additional details of the envelope detector 1318. A DFT 1402 supplies a filter 1404. The filter output is squared in 1406, and a comparator 1408 compares the interval energy from 1406 with a reference value corresponding to the interval energy that will exist when the envelope has a minimum amplitude value. If the interval energy is greater than the reference, the envelope detector supplies a "1"; if the interval energy is not greater than the reference, the envelope detector supplies a "0".

[0061] Referring to Figure 15, the serial output 1324 from the configuration demodulator is supplied to the clock recovery, deserializer, and error checking circuit 1009 (see Figure 10). The sampling circuit 1502 samples the serial output, and the serial-to-parallel conversion block 1504 generates configuration information including the start bit, P2, P1, P0, N2, N1, N0, the same bit, and any other redundant bits. After the transmit word is recovered, the error checking logic 1506 checks for errors, such as same bit errors. If no error is detected, the start bit, redundant bits, and (some) same bit bits are removed, and the recovered CONFIG value updates the driver strength (or other configuration settings) in the drive control block.

[0062] Figure 16 illustrates one embodiment of sampling logic 1502. A sampling clock signal is recovered from a transition of the serial output and delayed to cause sampling to occur in the middle of a serial output bit. A transition detector (1 to 0 or 0 to 1) can be used to generate a sampling pulse from a sequence bit having a transition. If a transition is missing in a sequence bit (e.g., sequence 1 or 0), another method is needed to determine a sampling time. Delay block 1601 delays the serial output, and XOR (mutually exclusive) gate 1603 compares the delayed serial output with the current serial output. If the bits differ to indicate a transition, counter 1605 is reset. Flipper 1607 receives the current serial output bit at its D input. Pulse logic 1609 clocks flipper 1607 when the counter equals 2. This causes the pulse to become two clock cycles of counter 1605 after the transition. The counter clock 1611 has one cycle, such that two cycles of the counter will bring the sampled pulse close to the middle of the serial output bit. If no transition is detected, pulse logic 1609 also pulses when the count = 5 to bring the next pulse close to the middle of the next serial output bit. In one embodiment, the serial word (as shown in Figure 5) is defined to ensure that at most two sequential bits are the same before a transition occurs. The counter is reset at the next transition. The output of flip-flop 1607 is supplied to error detection logic 1506.

[0063] Figure 17 illustrates a timing diagram of one of the sampling circuits 1502. When the serial data from filter 1323 (see Figure 13) has an output sequence "1", "0", "1", transition (edge) drive pulses 1702 and 1704 at 1701 and 1703 (on count = 2 after the edge). However, when two consecutive "1" (or "0") occur, edge 1705 drives the first pulse 1706 and count = 5 drives the second pulse 1708. Due to the specified serial word, an edge generation pulse should occur after the count generation pulse 1708. After successfully receiving the transmit signal, GATE information and CONFIG information are used by the driver control block.

[0064] Figure 18 illustrates how the driver control block 1800 uses the drive strength signal. The PFET control logic 1802 receives the configuration bit drive strength P (P2, P1, P0) and adjusts the current supplied by (a number of) PFETs 1804, wherein the PFETs 1804 are eight PFET transistors configured in parallel with the same or different sizes (width / length (W / L) ratio), which are used to adjust the current to achieve, for example, the percentage drive strength shown in Figure 7 and depending on the settings, corresponding to states S0 to S7. The PFET control logic 1802 includes (or is coupled to) an NVM or other memory that specifies the percentage drive strength corresponding to the configuration bit and whether any drive strength has been provided and (if so) its drive strength value for operation in digital mode (for S0 and S8), and other necessary configuration information. M configuration bits (e.g., 3 bits) for the PFET drive strength are mapped to N signal lines (e.g., 8 signal lines) to control the drive strength current coupled to the output terminal 1806 of the gate of the power transistor 1808. Similarly, the NFET control block 1810 receives M configuration bits (drive strength N) to control the drive strength supplied by (a plurality of) NFET (a plurality of) transistors 1812. The control block 1810 maps the M configuration bits to N control lines to adjust the current supplied by (a plurality of) NFET 1812, wherein the NFET 1812 is formed by (a plurality of) eight NFET transistors of the same or different sizes connected in parallel to achieve (a plurality of) percentage drive strengths corresponding to (a plurality of) S0 to S8, as shown in (e.g.) Figure 7. The PFET transistor 1802 and the NFET transistor 1812 also receive a complementary version of the GATE signal (assuming GATE is active high) at their respective gates.

[0065] In one embodiment shown in FIG19, instead of driver control block 1900 (corresponding to driver control block 1010 in FIG10) supplying a single output 1806, discrete output terminals 1902 and 1904 (see VOP and VON in FIG11) are supplied by PFET 1804 and NFET 1812, and the output terminals are externally combined to drive one gate of an external transistor 1906. Terminal 1902 provides a positive drive current to turn on the external transistor (e.g., IGBT 1906), while terminal 1904 provides a sink current to turn off the external transistor 1906. Although not shown in the figure, a Miller clamp can be used in conjunction with both terminals.

[0066] Therefore, a system having an isolated communication channel has been described, which simultaneously transmits gate and configuration information across the isolated communication channel. A modulator in the transmitter encodes information for dual communication, and a demodulator decodes the transmitted information to achieve, for example, dynamic variable drive strength control of an isolated gate driver. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Other variations and modifications to the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the following claims. [Simplified Explanation of the Diagram]

[0005] Those skilled in the art can better understand the present invention and its many objects, features and advantages by referring to the accompanying drawings.

[0006] Figure 1 illustrates a prior art system with an isolated gate driver.

[0007] Figure 2A illustrates a system including an isolated gate driver with one of two isolated communication channels for transmitting gate information and configuration information.

[0008] Figure 2B illustrates one embodiment of an isolated gate driver that transmits two types of information across a single isolated communication channel.

[0009] Figure 3 illustrates a conventional on / off key control (OOK).

[0010] Figure 4 illustrates one embodiment of a high-order block diagram of one of the transmitter sides of an isolated gate driver.

[0011] Figure 5 illustrates a string of words used for transmitting across an isolated communication channel, which provides drive strength information.

[0012] Figure 6 illustrates one embodiment of a state detection and mapping circuit.

[0013] Figure 7 illustrates one embodiment of the mapping configuration parameters for the drive current intensity.

[0014] Figure 8 illustrates one embodiment of a modulation scheme that allows simultaneous transmission of configuration information and gate information.

[0015] Figure 9 shows a high-order diagram of one of the modified OOK modulators.

[0016] Figure 10 shows a block diagram of one embodiment of a receiving circuit.

[0017] Figure 11 illustrates an additional configuration of one embodiment of the demodulator section of the receiving circuit.

[0018] Figure 12 illustrates the waveforms of the demodulator section in operation.

[0019] Figure 13 illustrates the fast and slow paths of configuration demodulation according to one embodiment.

[0020] Figure 14 illustrates additional details of one embodiment of the envelope detector.

[0021] Figure 15 illustrates the processing of serial output data from the configuration demodulator.

[0022] Figure 16 illustrates one of the sampling circuits used for sampling data in an autoconfiguration demodulator.

[0023] Figure 17 shows a timing diagram of one of the sampling circuits.

[0024] Figure 18 illustrates one embodiment of how drive strength information is used to control the drive strength of a transistor that generates a gate signal.

[0025] Figure 19 illustrates an embodiment of how drive strength information is used to generate a gate signal of an external chip assembly.

[0026] Using the same element symbol in different diagrams to indicate similar or identical items.

Claims

1. A method for transmitting information, comprising: Receive first and second information for transmission across a single isolated communication channel; And simultaneously transmit the first information and the second information across the single isolated communication channel.

2. The method of request item 1, further comprising: The first information and the second information are used to generate a modulated signal; And transmit the modulated signal across the single isolated communication channel to simultaneously send the first information and the second information across the single isolated communication channel.

3. The method of claim 2, wherein the modulated signal has a first frequency deviation in response to a change in the first information and the modulated signal has a second frequency deviation in response to a change in the second information, the first frequency deviation being more than twice the second frequency deviation.

4. The method of either claim 2 or 3, further comprising: In response to the first information, an on / off keyed modulation is used to generate the modulated signal, wherein the second information is equal to a first value; and the modulated signal is generated as an adjustment of the on / off keyed modulation, wherein the second information is equal to a second value.

5. The method of request item 4, wherein the adjustment of the on / off key control modulation is a frequency modulation of at least one logic state of the first information and the second information.

6. The method of either claim 2 or 3 further includes using constant amplitude modulation to generate the modulated signal.

7. The method of either claim 2 or 3, further comprising using frequency modulation to generate at least one state represented by the modulated signal.

8. The method of either claim 2 or 3, further comprising: The first information and the second information are used to generate the modulated signal having one of four states, each pair of unique values ​​of the first information and the second information corresponding to one of the four states.

9. The method of claim 8, further comprising: The on / off key control represents two of the four states, wherein the modulated signal has a first frequency for the on state; And use frequency modulation to represent a third state.

10. The method of either claim 2 or 3, further comprising: The modulated signal having a fixed voltage is generated during the first bit time of representing a first value of the first information and a first value of the second information; the modulated signal having at least a first frequency is generated during the second bit time of representing a first value of the first information and a second value of the second information; the modulated signal having a second frequency higher than the first frequency is generated during the third bit time of representing a second value of the first information and a first value of the second information; and the modulated signal having the third frequency and the fourth frequency is generated during the fourth bit time of representing a third frequency and a fourth frequency, wherein the third frequency and the fourth frequency are carried at an envelope having a fifth frequency representing a second value of the first information and a second value of the second information.

11. The method of request item 10, wherein the second frequency is equal to the third frequency.

12. The method of claim 10, further comprising, when the second information is equal to the second value, using an envelope signal having the fifth frequency to cause an oscillator to respond to a first value of the envelope signal to supply an oscillator output signal having the third frequency and responding to a second value of the envelope signal to supply the oscillator output signal having the fourth frequency.

13. The method of any one of claims 1 to 3, wherein the first information indicates a gate signal for driving a gate of a transistor and the second information is configuration information.

14. The method of claim 13, wherein the second information controls one characteristic of the gate signal.

15. The method of either claim 2 or 3, further comprising: The signal is received at a second integrated circuit coupled to one of the single isolated communication channels; Demodulate the signal; Use this first information to control at least one first transistor; And use this second information to control a set of configuration settings.

16. An apparatus for transmitting information, comprising: At least two input terminals, which are coupled to receive first information and second information respectively; a modulation circuit for using the first information and the second information to generate a modulated signal; and a transmitter for simultaneously supplying the first information and the second information to a single isolated communication channel in the modulated signal.

17. The device of claim 16, wherein the first information indicates a gate signal for driving a gate of a transistor and the second information is configuration information.

18. The device of claim 17, wherein the second information controls one characteristic of the gate signal.

19. The apparatus of any one of claims 16 to 18, wherein the modulation circuit is configured to use frequency modulation to generate the modulated signal to generate at least one state represented by the modulated signal and wherein one frequency of the modulated signal varies between at least two frequencies during the at least one state.

20. The device of any one of claims 16 to 18, wherein the modulation circuit is configured to generate the modulated signal having one of four states for each bit time, wherein each pair of unique values ​​of the first information and the second information corresponds to one of the four states.

21. The equipment as requested in any of items 16 to 18, wherein, To represent a first value of the first information and a first value of the second information, the modulation circuit generates a signal having a fixed voltage; to represent the first value of the first information and a second value of the second information, the modulation circuit generates a signal having at least a first frequency; to represent the second value of the first information and the first value of the second information, the modulation circuit generates a signal having a second frequency; and to represent the second value of the first information and the second value of the second information, the modulation circuit uses frequency modulation to generate the modulated signal to thereby generate a modulated frequency having a third frequency and having a fourth frequency supplied in an envelope having a fifth frequency.

22. The device of claim 21, wherein the second frequency is equal to the third frequency and the second frequency is greater than the first frequency and the fourth frequency is greater than the third frequency.

23. The device as claimed in claim 21, further comprising: An oscillator that, in response to the second information being equal to the first value, supplies an oscillator output signal having a second frequency and the first frequency alternating at a rate determined by an envelope signal; and a logic circuit that logically combines the envelope signal at the fifth frequency and the second information and supplies a logic output signal to control the oscillator to supply an oscillator output signal having the third frequency in response to a first value of the envelope signal when the second information is equal to the second value, and to supply the oscillator output signal having the fourth frequency in response to a second value of the envelope signal.

24. The device as claimed in claim 21, further comprising: A second integrated circuit coupled to the single isolated communication channel, the second integrated circuit being used to receive the modulated signal transmitted across the single isolated communication channel and to use the first information to control at least one first transistor and to use the second information to control a set of settings.

25. An apparatus for transmitting information across an isolated communication channel, comprising: A first input terminal is used to receive gate information; One or more input terminals, etc., for receiving configuration information; and a modulation circuit configured to generate a modulated signal having one of four possible states, each of the four possible states corresponding to the gate information and one of the different unique values ​​of the configuration information, the modulation circuit being configured to use frequency modulation to generate the modulated signal to generate one of the four possible states, wherein the frequency of one of the modulated signals varies between at least two frequencies to indicate that one of the four possible states.

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