Dynamic module and decision feedback equalizer

Abstract

A dynamic module and a decision feedback equalizer are provided. The decision feedback equalizer includes two dynamic modules, which have symmetric circuits and connections. The dynamic module includes a first domino circuit, a second domino circuit, and a storage circuit. In response to a first previous decision bit and a second previous decision bit, a first multiplexer output and a second multiplexer output are generated. The dynamic module alternatively operates in an evaluation period and a precharge period, depending on a clock signal. In the evaluation period, the first and the second multiplexer outputs are updated by the first domino circuit and the second domino circuit. In the precharge period, the first and the second multiplexer outputs are held by the storage circuit.

Description

[Technical Field]

[0001] The present invention relates to a dynamic module and decision feedback equalizer, and more particularly to a dynamic module and decision feedback equalizer that can alleviate the time boundary of speculative first-tap (abbreviated as tap1). [Previous Technology]

[0002] Please refer to Figure 1, which is a schematic diagram of the transmission path between the transmitter and the receiver. The data transmitted from the transmitter 11 to the receiver 13 is distorted in the transmission path 12. Therefore, the receiver 13 needs to restore the distorted data. The causes of data distortion are not all the same, one of which is inter-symbol interference (ISI) caused by previous symbols.

[0003] To reduce ISI, a continuous-time linear equalizer (CTLE) 131 and a decision feedback equalizer (DFE) 133 are currently used and applied to the receiver 13. In short, the CTLE adjusts the gain in the frequency domain, while the DFE 13 processes the signal derived from ISI without amplifying noise. Therefore, the CTLE 131 and DFE 133 can be used together to remove ISI and enhance the signal-to-noise ratio (SNR). The DFE output Dout is then transmitted to the serializer / deserializer (SerDes) 135.

[0004] Please refer to Figure 2, which is a schematic diagram of the DFE structure. The DFE 133 includes an adder 133a, a sense amplifier 133b, and an RS latch 133c. After receiving the input data Din and the speculative first-order tap (tap1), the adder 133a transmits the sum of the input data Din and the speculative first-order tap (tap1) to the sense amplifier 133b. The clock signal CLK triggers the sense amplifier 133b and the RS latch 133c.

[0005] The sense amplifier 133b amplifies the signal and outputs it to the RS latch 133c, and the RS latch 133c generates a DFE output Dout. Since the DFE 133 is involved in multiple steps and its operation must be adjusted both instantaneously and recursively, the design of the DFE 133 becomes complex. In high-frequency applications (e.g., above 10 GHz), the tap speed is critical, posing a challenge to the design of the DFE 133. [Summary of the Invention]

[0006] This disclosure relates to a dynamic module and a decision feedback equalizer. By effectively integrating the multiplexer and the dynamic latch into a dynamic module, transmission delay can be reduced and the operational limits of the speculative first-order tap (tap1) can be alleviated.

[0007] According to a first aspect of the present invention, a dynamic module is provided. The dynamic module includes a first domino circuit and a second domino circuit. The first domino circuit generates a first multiplexed output. The first domino circuit includes: a first multiplexer, at least one first phase setting circuit, and a first decision selection stage circuit. The first multiplexer receives two of a first single-rail output, a second single-rail output, a third single-rail output, and a fourth single-rail output. The at least one first phase setting circuit receives a first clock signal. The first decision selection stage circuit is electrically connected to the first multiplexer and the at least one first phase setting circuit. The first decision selection stage circuit receives a first prior decision bit and a second prior decision bit. The first prior decision bit and the second prior decision bit are complementary to each other. The second domino circuit is electrically connected to the first domino circuit and generates a second multiplexed output. The second domino circuit includes: a second multiplexer, at least one second phase setting circuit, and a second decision selection stage circuit. The second multiplexer receives the other two of the first single-rail output, the second single-rail output, the third single-rail output, and the fourth single-rail output. At least one second phase setting circuit receives a second clock signal. The first clock signal and the second clock signal are complementary. A second decision selection stage circuit is electrically connected to the second multiplexer and the at least one second phase setting circuit. The second decision selection stage circuit receives a first prior decision bit and a second prior decision bit. During evaluation, the first multiplexed output and the second multiplexed output are selectively updated with a first single-rail output, a second single-rail output, a third single-rail output, and a fourth single-rail output. During pre-charging, the first multiplexed output and the second multiplexed output remain unchanged.

[0008] According to a second aspect of the present invention, a decision feedback equalizer is provided. The decision feedback equalizer includes a first speculation path and a second speculation path. The first speculation path provides a first prior decision bit and a second prior decision bit during evaluation. The first prior decision bit and the second prior decision bit are complementary to each other. The second speculation path is electrically connected to the first speculation path. The second speculation path includes: a first sensing amplifier, a second sensing amplifier, and a dynamic module. The output of the first sensing amplifier includes a first rail-to-rail output pair of a first single-rail output and a second single-rail output. The output of the second sensing amplifier includes a second rail-to-rail output pair of a third single-rail output and a fourth single-rail output. The dynamic module is electrically connected to the first sensing amplifier and the second sensing amplifier. The dynamic module includes a first domino circuit and a second domino circuit electrically connected to each other. The first domino circuit generates a first multiplexed output, and the second domino circuit generates a second multiplexed output. The first domino circuit includes: a first multiplexer, at least one first phase setting circuit, and a first decision selection stage circuit. A first multiplexer receives two of a first single-rail output, a second single-rail output, a third single-rail output, and a fourth single-rail output. At least one first phase setting circuit receives a first clock signal. A first decision selection stage circuit is electrically connected to the first multiplexer and the at least one first phase setting circuit. The first decision selection stage circuit receives a first prior decision bit and a second prior decision bit. A second domino circuit includes a second multiplexer, at least one second phase setting circuit, and a second decision selection stage circuit. The second multiplexer receives the first single-rail output, the second single-rail output, the third single-rail output, and two of the four single-rail outputs. At least one second phase setting circuit receives a second clock signal. The first clock signal and the second clock signal are complementary to each other. The second decision selection stage circuit is electrically connected to the second multiplexer and the at least one second phase setting circuit. The second decision selection stage circuit receives the first prior decision bit and the second prior decision bit. During evaluation, the first multiplexed output and the second multiplexed output are selectively updated with one of a first rail-to-rail output pair and a second rail-to-rail output pair. During the pre-charging period, the first multiplex output and the second multiplex output remain unchanged.

[0009] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

Implementation Method

[0011] Among all the taps, the first-order tap (tap1) has the most stringent time constraint, namely, one data unit interval (UI). To relax the time constraint of the first-order tap (tap1), a speculative (loop-unrolling) approach can be used to design the DFE. When using a speculative structure, the speculative DFE includes even-numbered and odd-numbered speculative paths, and the time constraint of the speculative first-order tap (tap1) can be extended to twice the data unit interval (2*UI).

[0012] Please refer to Figure 3, which is a schematic diagram of a speculative DFE. DFE 15 includes an even-numbered speculation path 151 and an odd-numbered speculation path 153. The even-numbered speculation path 151 receives input data Din and generates an even-numbered path decision Dout_evn. The even-numbered path decision Dout_evn is further fed into the odd-numbered speculation path 153 for reference. The odd-numbered speculation path 153 receives input data Din and generates an odd-numbered path decision Dout_odd. The odd-numbered path decision Dout_odd is further fed into the even-numbered speculation path 151 for reference. The DFE output Dout then alternately uses the even-numbered path decision Dout_evn and the odd-numbered path decision Dout_odd.

[0013] Please refer to Figure 4, which is a waveform diagram of the operation period during which even-numbered and odd-numbered prediction paths intersect. The horizontal axis represents time, and the vertical axis represents the waveforms of the positive latching clock signal CLK_L(even) for the even-numbered path and the positive latching clock signal CLK_L(odd) for the odd-numbered path. The positive latching clock signal CLK_L(even) for the even-numbered path is provided to even-numbered prediction path 151, and the positive latching clock signal CLK_L(odd) for the odd-numbered path is provided to odd-numbered prediction path 153.

[0014] When the positive latch-up clock signal CLK_L(even) of the even-numbered path is at a high logic level (CLK_L(even)=1), the even-numbered prediction path 151 operates in the evaluation phase. The period during which the even-numbered prediction path 151 operates in the evaluation phase is defined as the evaluation period Teva corresponding to the even-numbered prediction path 151. When the positive latch-up clock signal CLK_L(even) of the even-numbered path is at a low logic level (CLK_L(even)=0), the even-numbered prediction path 151 operates in the pre-charge phase. The period during which the even-numbered prediction path 151 operates in the pre-charge phase is defined as the pre-charge period Tpre corresponding to the even-numbered prediction path 151.

[0015] When the positive latch-up clock signal CLK_L(odd) of the odd-numbered path is at a high logic level (CLK_L(odd)=1), the odd-numbered prediction path operates in the evaluation phase. The period during which the odd-numbered prediction path 153 operates in the evaluation phase is defined as the evaluation period Teva corresponding to the odd-numbered prediction path 153. When the positive latch-up clock signal CLK_L(odd) of the odd-numbered path is at a low logic level (CLK_L(odd)=0), the odd-numbered prediction path 153 operates in the pre-charge phase. The period during which the odd-numbered prediction path 153 operates in the pre-charge phase is defined as the pre-charge period Tpre corresponding to the odd-numbered prediction path 153.

[0016] The positive latch-up clock signal CLK_L(even) of the even-numbered path and the positive CLK_L(odd) of the odd-numbered path are complementary in phase, and the operation phases of the even-numbered prediction path 151 and the odd-numbered prediction path 153 are alternately switched. During T(n) and T(n+2), the even-numbered prediction path 151 operates in the evaluation phase, and the odd-numbered prediction path 153 operates in the pre-charge phase. During T(n+1) and T(n+3), the even-numbered prediction path 151 operates in the pre-charge phase, and the odd-numbered prediction path 153 operates in the evaluation phase. Accordingly, when the even-numbered prediction path 151 is in the evaluation phase Teva, the odd-numbered prediction path 153 is in the pre-charge phase Tpre, and vice versa.

[0017] Figures 5A and 5B show two examples of speculative deduction formulas (DFEs) with a cyclic expansion structure. Figures 5A and 5B illustrate that even-numbered deduction path 151 and odd-numbered deduction path 153 have similar and symmetrical designs.

[0018] Please refer to Figure 5A, which is a schematic diagram of an example of a speculative DFE. The speculative DFE 2 includes an even-numbered speculative path 21 and an odd-numbered speculative path 23. The even-numbered speculative path 21 includes adders 211a and 211b, sense amplifiers 213a and 213b, latches 215a and 215b, a multiplexer 217, and a flip-flop 219. The odd-numbered speculative path 23 includes adders 231a and 231b, sense amplifiers 233a and 233b, latches 235a and 235b, a multiplexer 237, and a flip-flop 239.

[0019] Sensing amplifiers 213a, 213b, 233a, and 233b each operate based on their corresponding latch-up clock signal CLK_L, and each sensing amplifier 213a, 213b, 233a, and 233b has differential input and dual-rail output. The operation of sensing amplifiers 213a and 213b in even-numbered prediction path 21 and the operation of sensing amplifiers 233a and 233b in odd-numbered prediction path 23 are symmetrical to each other. For example, when the positive latch-up clock signal CLK_L(even) of the even-numbered path is at a high logic level, sensing amplifiers 213a and 213b in even-numbered prediction path 21 continue to perform sampling and holding operations, while sensing amplifiers 233a and 233b in odd-numbered prediction path 23 stop their operation. The reverse is also true. When the sense amplifiers 213a, 213b, 233a, and 233b continue to perform sampling and holding operations, one of the two outputs of the same sense amplifier 213a, 213b, 233a, and 233b (depending on the polarity of the input differential voltage) is set to the amplifier supply voltage level; the other is maintained at the amplifier ground voltage level (low logic level).

[0020] Even prediction path 21 and odd prediction path 23 alternately receive input data Din and generate corresponding even path decision Dout_evn and odd path decision Dout_odd. Odd prediction path 23 receives even path decision Dout_evn from even prediction path 21, and even prediction path 21 receives odd path decision Dout_odd from odd prediction path 23.

[0021] Next, the operation of the even-number prediction path 21 in DFE 2 will be explained. Adders 211a and 211b simultaneously receive input data Din and the first-order prediction tap (tap1). After subtracting the first-order prediction tap (tap1) from the input data Din, adder 211a sends the adder output (Din-tap1) to sense amplifier 213a. Adder 211b adds the first-order prediction tap (tap1) to the input data Din (Din+tap1) and sends the adder output (Din+tap1) to sense amplifier 213b.

[0022] Sensing amplifier 213a generates a positive single-rail output APevn and a negative single-rail output ANevn of the first even-numbered path based on the adder output (Din-tap1) of adder 211a. Sensing amplifier 213b generates a positive single-rail output BPevn and a negative single-rail output BNevn of the second even-numbered path based on the adder output (Din+tap1) of adder 211b.

[0023] The latching device 215a and the self-sensing amplifier 213a receive the positive single-rail output APevn and the negative single-rail output ANevn of the first even-numbered path, and generate the even-numbered path multiplexing input MUXevn_in1 accordingly. The latching device 215b and the self-sensing amplifier 213b receive the positive single-rail output BPevn and the negative single-rail output BNevn of the second even-numbered path, and generate the even-numbered path multiplexing input MUXevn_in2 accordingly. The multiplexer 217 selects one of the multiplexing inputs MUXevn_in1 and MUXevn_in2 as the multiplexing output MUXevn_out based on the odd-numbered path decision output Dout_odd. The multiplexing output MUXevn_out is further transmitted to the flip-flop 219. The flip-flop 219 provides the even-numbered path decision output Dout_evn to the odd-numbered prediction path 23.

[0024] Since the operation of odd-numbered prediction path 23 is similar to that of even-numbered prediction path 21, its details will not be elaborated. Also note that this article does not need to limit the source and weight of the first-order tap (tap1) of the prediction formula, and the prediction formula DFE may have multiple taps.

[0025] Please refer to Figure 5B, which is a schematic diagram of another example of a speculative DFE. The speculative DFE 3 includes an even-numbered speculative path 31 and an odd-numbered speculative path 33. The even-numbered speculative path 31 includes adders 311a and 311b, sense amplifiers 313a and 313b, an even-numbered dynamic module 315, and inverters 317a and 317b. The odd-numbered speculative path 33 includes adders 331a and 331b, sense amplifiers 333a and 333b, an odd-numbered dynamic module 335, and inverters 337a and 337b.

[0026] The design of the even-numbered dynamic module 315 is similar to that of the odd-numbered dynamic module 335. The even-numbered dynamic module 315 includes an upper domino circuit 315a, a lower domino circuit 315b, and a storage circuit 315c. The odd-numbered dynamic module 335 includes an upper domino circuit 335a, a lower domino circuit 335b, and a storage circuit 335c. Table 1 summarizes the operation of the components of the speculative DFE 3. Table 1 period Even number prediction path 31 Odd number prediction path 33 During the evaluation period T eva 1. Even-number dynamic module 315 predicts path 33 from odd-number receiving D out_odd 2. Adders 311a and 311b receive D in And tap1, and respectively generate (D) in-tap1), (D in +tap1). 3. Sensing amplifier 313a generates (APevn, ANevn), and sensing amplifier 313b generates (BPevn, BNevn). 4. According to D out_odd The even-numbered dynamic module 315 selects one of (APevn, ANevn) and (BPevn, BNevn) as MXOPevn and MXONevn. 1. Odd-number dynamic module 335 self-even-number prediction path 31 receiving D out_evn 2. Adders 331a and 331b receive Din and tap1, and generate (D) respectively. in -tap1), (D in +tap1). 3. Sensing amplifier 333a generates (APodd, ANodd), and sensing amplifier 333b generates (BPodd, BNodd). 4. According to D out_evn The odd-numbered dynamic module 335 selects one of (APodd, ANodd) and (BPodd, BNodd) as MXOPodd, MXONodd. T during pre-charge pre 1. Storage circuit 315c retains MXOPevn and MXONevn. 2. Inverters 317a and 317b convert MXOPevn and MXONevn to D. out_evn 1. Storage circuit 335c holds MXOPodd and MXONodd. 2. Inverters 337a and 337b convert MXOPevn and MXONevn into D. out_odd

[0027] As can be seen from Table 1, the operation and components of even-number prediction path 31 and odd-number prediction path 33 are similar and symmetrical. Therefore, even-number dynamic module 315 and odd-number dynamic module 335 can adopt the same implementation method. The difference between even-number dynamic module 315 and odd-number dynamic module 335 lies in the source of their input signals, and they use each other's multiplex outputs.

[0028] In Figure 5B, the even-numbered dynamic module 315 integrates the functions of the locking devices 215a and 215b with the multiplexer 217, and the odd-numbered dynamic module 335 integrates the functions of the locking devices 235a and 235b with the multiplexer 237. The even-numbered dynamic module 315 and the odd-numbered dynamic module 335 are designed in a dynamic logic manner to perform locking and multiplexing operations efficiently.

[0029] Please refer to Figure 6, which is a schematic diagram comparing the causes of delay in the speculative DFE in Figures 5A and 5B. The horizontal axis of Figure 6 represents time. The period from time point t1 to time point t7 corresponds to the time limit of the first-order tap (tap1) of the speculative formula. That is, the interval between two data units (2*UI). The upper part of Figure 6 shows the cause of delay in speculative DFE 2, and the lower part of Figure 6 shows the cause of delay in speculative DFE 3.

[0030] The delay causes of speculative DFE 2 include: the clock propagation delay of sense amplifiers 213a and 213b (between time t1 and time t2), the settling time TsuSA of sense amplifiers 213a and 213b (between time t2 and time t3), the propagation delay Tlatch of multiplexer latches 215a and 215ba (between time t3 and time t4), and the propagation delay Tmux of multiplexer 217 (between time t4 and time t6). The difference between twice the data unit interval (2*UI) and the sum of the delay causes of speculative DFE 2 (i.e., between time t6 and time t7) is the operating limit ΔTtap1 of the first-order tap (tap1) when using speculative DFE 2.

[0031] The delay causes of speculative DFE 3 include: the clock propagation delay Tclk2sa of sense amplifiers 313a and 313b (between time t1 and time t2), the set-time TsuSA of sense amplifiers 313a and 313b (between time t2 and time t3), and the propagation delay Tdyn of odd / even dynamic modules 315 and 335 (between time t3 and time t5). The difference between twice the data unit interval (2*UI) and the sum of the delay causes of speculative DFE 3 (i.e., between time t5 and time t7) is the operating boundary ΔTtap1' of the first-order tap (tap1) when speculative DFE 3 is used.

[0032] The dashed circle selection C1 represents the propagation delay along the odd / even speculative path in Figure 5A. The dashed circle selection C2 represents the propagation delay along the odd / even speculative path in Figure 5B. Comparing the dashed circle selections C1 and C2, it can be found that the period selected by the dashed circle selection C1 is longer than the period selected by the dashed circle selection C2. Furthermore, the operational boundary ΔTtap1' of the speculative first-order tap (tap1) in Figure 5B is longer than the operational boundary ΔTtap1 of the speculative first-order tap (tap1) in Figure 5A. Therefore, the speculative DFE 3 in Figure 5B can provide a speculative first-order tap (tap1) with better tolerance.

[0033] Please refer to Figure 7, which is a general block diagram of the dynamic module according to the present disclosure. The dynamic module 5 includes an upper domino circuit 51, a lower domino circuit 53, and a storage circuit 55. The dynamic module 5 can be either the even-numbered dynamic module 315 or the odd-numbered dynamic module 335 in Figure 5B. Table 2 lists the signal correspondences in Figures 5B and 7. Table 2 Signal types Signal Figure 7 Figure 5B Dynamic Module 5 Even-numbered dynamic module 315 Odd Dynamic Module 335 Input signal Locking clock signal Positive latch-up clock signal CLK_L CLK_L(even) CLK_L(odd) Reverse latching clock signal CLKB_L CLKB_L(even) CLKB_L(odd) Single rail output First positive single-rail output AP APevn APodd First negative electrode single-rail output AN ANevn ANodd Second positive single-rail output BP BPevn BPodd Second negative electrode single-rail output BN BNevn BNodd Previously determined bits Positively determined bits Spo S evn S odd Reverse previously determined bits SBpo SB evn SB odd Output signal Multiplex output Forward Multiplexing Output MXOP MXOPevn MXOPodd Reverse multiplexing output MXON MXONevn MXONodd

[0034] The upper domino circuit 51 and the lower domino circuit 53 receive three types of input signals, including: positive / reverse latching clock signals (CLK_L, CLKB_L), first rail-to-rail output pairs (AP, AN), second rail-to-rail output pairs (BP, BN), and previously determined bits (Spo, SBpo). The previously determined bits (Spo, SBpo) are received from other dynamic modules, while the positive latching clock signal CLK_L and the reverse latching clock signal CLKB_L are received from other circuits in the system (e.g., PLL).

[0035] The storage circuit 55 is electrically connected between the positive multiplexing output terminal Nmxop and the negative multiplexing output terminal Nmxon, and is used to bridge the upper domino circuit 51 and the lower domino circuit 53. The positive multiplexing output MXOP is generated at the positive multiplexing output terminal Nmxop, and the negative multiplexing output MXON is generated at the negative multiplexing output terminal Nmxon.

[0036] This document uses some symbols to represent the state of signals. In this document, the symbol "X" indicates that the change of the signal does not affect the operation of the circuit; the symbol "Z" indicates that the signal is floating (high impedance).

[0037] According to the embodiments disclosed herein, the dynamic module 5 operates in a dual-phase manner. During evaluation (Teva), the dynamic module 5 updates the forward multiplexed output MXOP and the reverse multiplexed output MXON based on either the first rail-to-rail output pair (AP, AN) or the second rail-to-rail output pair (BP, BN), according to the forward prior decision bit Spo and the reverse prior decision bit SBpo. During precharge (Tpre), the dynamic module 5 maintains the forward multiplexed output MXOP and the reverse multiplexed output MXON unchanged without updating them.

[0038] This disclosure illustrates the operation of the dynamic module 5 using three embodiments. Figures 8A, 8B, 9, 10A, 10B, 11, and 12 represent the first embodiment. Figures 13A, 13B, 14, 15A, 15B, 16, 17, and 18 represent the second embodiment. Figures 19A, 19B, 20, 21A, 21B, 22, and 23 represent the third embodiment. These embodiments will be presented with block diagrams, circuit designs, and comparison tables of signal states, and the operation of the dynamic module based on these embodiments will be explained. It should also be noted that the implementation of the concepts disclosed herein is not limited to the embodiments described below. First Embodiment

[0039] Figures 8A and 8B are block diagrams and circuit designs of the dynamic module 6 according to the first embodiment of this disclosure, respectively. Figure 9 illustrates the operation of the dynamic module 6 during pre-charging (Tpre). Figures 10A and 10B illustrate the operation of the dynamic module 6 during evaluation (Teva). Figure 11 shows a summary table of the signal states of the dynamic module 6 during pre-charging (Tpre) and evaluation (Teva). Figure 12 illustrates how the dynamic module 6 is applied to the speculative DFE 3.

[0040] Please refer to Figure 8A, which is a block diagram of a dynamic module according to a first embodiment of this disclosure. The dynamic module 6 includes an upper domino circuit 61, a lower domino circuit 63, and a storage circuit 65. The storage circuit 65 is electrically connected to the upper domino circuit 61 via a positive multiplexer terminal Nmxop, and electrically connected to the lower domino circuit 63 via a negative multiplexer terminal Nmxon.

[0041] The upper domino circuit 61 further includes a multiplexer 611 and a dynamic latch 613, and the lower domino circuit 63 further includes a multiplexer 631 and a dynamic latch 633. The dynamic latch 613 includes a selection stage circuit 613a and a phase setting circuit 613b, and the dynamic latch 633 includes a selection stage circuit 633a and a phase setting circuit 633b.

[0042] Please refer to Figure 8B, which is a schematic diagram of the circuit design of the dynamic module according to the first embodiment of this disclosure. In the upper domino circuit 61, the multiplexer 611 includes NMOS transistors uN1 and uN2, the selection stage circuit 613a includes NMOS transistors ulatN1 and ulatN2, and the phase setting circuit 613b includes PMOS transistor uP and NMOS transistor uN. In the lower domino circuit 63, the multiplexer 631 includes PMOS transistors lP1 and lP2, the selection stage circuit 633a includes PMOS transistors llatP1 and llatP2, and the phase setting circuit 633b includes PMOS transistor lP and NMOS transistor lN. The storage circuit 65 includes inverters sinv1 and sinv2.

[0043] Next, the signal and connection relationships related to the multiplexer 611, the selection stage circuit 613a, and the phase setting circuit 613b in the domino circuit 61 above will be explained respectively. In the multiplexer 611, the drains of NMOS transistors uN1 and uN2 are connected to the selection stage circuit 613a; the sources of NMOS transistors uN1 and uN2 are connected to the ground terminal (Gnd). The gate of NMOS transistor uN1 receives the first positive single-rail output AP, and the gate of NMOS transistor uN2 receives the second positive single-rail output BP.

[0044] In the selection stage circuit 613a, the drains of NMOS transistors ulatN1 and ulatN2 are electrically connected to the intermediate terminal Nm1, and the sources of NMOS transistors ulatN1 and ulatN2 are electrically connected to the drains of NMOS transistors uN1 and uN2 in the multiplexer 611, respectively. The gate of NMOS transistor ulatN1 receives the positive previously determined bit Spo, and the gate of NMOS transistor ulatN2 receives the negative previously determined bit SBpo.

[0045] In the phase setting circuit 613b, the source of the PMOS transistor uP is electrically connected to the supply voltage terminal (Vcc), and the source of the NMOS transistor uN is electrically connected to the intermediate terminal Nm1. The gates of the PMOS transistor uP and the NMOS transistor uN are electrically connected to each other to receive the positive latch-up clock signal CLK_L. The drains of both the PMOS transistor uP and the NMOS transistor uN are electrically connected to the positive multiplexing output terminal Nmxop.

[0046] Next, the signal and wiring relationships related to the multiplexer 631, the selection stage circuit 633a, and the phase setting circuit 633b in the domino circuit 63 below will be explained respectively. In the multiplexer 631, the drains of PMOS transistors 1P1 and 1P2 are connected to the selection stage circuit 633a. The sources of PMOS transistors 1P1 and 1P2 are connected to the supply voltage terminal (Vcc). The gate of PMOS transistor 1P1 receives the first negative single-rail output AN, and the gate of PMOS transistor 1P2 receives the second negative single-rail output BN.

[0047] In the selection stage circuit 633a, the drains of PMOS transistors llatP1 and llatP2 are both electrically connected to the intermediate terminal Nm2, and the sources of PMOS transistors llatP1 and llatP2 are respectively electrically connected to the drains of PMOS transistors 1P1 and 1P2. The gate of PMOS transistor llatP1 receives the inverted previously determined bit SBpo, and the gate of PMOS transistor llatP2 receives the positive previously determined bit Spo.

[0048] In the phase setting circuit 633b, the source of NMOS transistor 1N is electrically connected to the ground terminal (Gnd), and the source of PMOS transistor 1P is electrically connected to the intermediate terminal Nm2. The gates of PMOS transistor 1P and NMOS transistor 1N are electrically connected to each other to receive the reverse latch-up clock signal CKB_L. The drains of both PMOS transistor 1P and NMOS transistor 1N are electrically connected to the reverse multiplexing output terminal Nmxon.

[0049] In the storage circuit 65, the input and output terminals of inverter sinv1 are electrically connected to the positive multiplexing output terminal Nmxop and the negative multiplexing output terminal Nmxon, respectively. The input and output terminals of inverter sinv2 are electrically connected to the negative multiplexing output terminal Nmxon and the positive multiplexing output terminal Nmxop, respectively.

[0050] Please refer to Figure 9, which is a schematic diagram illustrating how the dynamic module according to the first embodiment of this disclosure operates during pre-charging. The operation of the upper domino circuit 61 and the lower domino circuit 63 will be described below.

[0051] Next, the operation of the components in the upper domino circuit 61 during the pre-charge period, Tpre, will be explained. In the phase setting circuit 613b, the PMOS transistor uP is turned on, and the NMOS transistor uN is turned off. Therefore, the positive multiplexed output MXOP is equal to the supply voltage Vcc (MXOP=1), and the selection stage circuit 613a and the multiplexer 61 do not affect the positive multiplexed output terminal Nmxop. Accordingly, the positive multiplexed output MXOP is independent of the inputs of the upper domino circuit 61 (i.e., the first positive single-rail output AP and the second positive single-rail output AP). Here, the multiplexer 611 and the selection stage circuit 613a are disabled by dotted-net plot.

[0052] Next, the operation of the components in the lower domino circuit 63 during the pre-charge period, Tpre, will be explained. In the phase setting circuit 633b, the PMOS transistor 1P is off, and the NMOS transistor 1N is on. Therefore, the inverted multiplex output MXON is equal to the ground voltage Gnd (MXON=0), and the selection stage circuit 633a and the multiplexer 631 do not affect the inverted multiplex output terminal Nmxon. Accordingly, the inverted multiplex output MXON is independent of the inputs of the lower domino circuit 63 (i.e., the first negative single-rail output AN and the second negative single-rail output BN). Here, the multiplexer 631 and the selection stage circuit 633a are disabled by a dotted grid.

[0053] Figures 10A and 10B illustrate the signal and component states of the dynamic module 6 during Teva operation during the evaluation period. In the dynamic module 6, the PMOS and NMOS transistors within the selection stage circuits 613a and 633a and the multiplexers 611 and 631 can be divided into four branches based on their position and connection method. These four branches include: the lower left branch (NMOS transistors ulatN1 and uN1), the lower right branch (NMOS transistors ulatN2 and uN2), the upper left branch (PMOS transistors lP1 and lllatP1), and the upper right branch (PMOS transistors lP2 and lllatP2).

[0054] Please refer to Figure 10A, which is a schematic diagram of the Teva operation of the dynamic module according to the first embodiment of this disclosure during the evaluation period when the positive prior decision bit Spo is at a low logic level (Spo=0) and the negative prior decision bit SBpo is at a high logic level (SBpo=1). Please refer to Figure 10B, which is a schematic diagram of the Teva operation of the dynamic module according to the first embodiment of this disclosure during the evaluation period when the positive prior decision bit Spo is at a high logic level (Spo=1) and the negative prior decision bit SBpo is at a low logic level (SBpo=0).

[0055] Depending on the previously determined bits (Spo, SBpo), the forward multiplexing output MXOP and reverse multiplexing output MXON of the 10A and 10B may remain unchanged, or be updated with one of the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN).

[0056] Next, we will explain how the phase setting circuit 613b, the selection stage circuit 613a, and the multiplexer 611 in the domino circuit 61 operate during evaluation. Since the positive latch-up clock signal CLK_L is at a high logic level (CLK_L=1), the PMOS transistor uP in the phase setting circuit 613b is off, and the NMOS transistor uN is on. The positive multiplexing output MXOP is determined by the selection stage circuit 613a and the multiplexer 611.

[0057] When the forward prior decision bit Spo is at a low logic level (Spo=0) and the reverse prior decision bit SBpo is at a high logic level (SBpo=1) (as shown in Figure 10A), the NMOS transistor ulatN1 in the decision selection stage circuit 613a is turned off, and the NMOS transistor ulatN2 is turned on. Consequently, because the NMOS transistor ulatN1 in the decision selection stage circuit 613 is turned off, the NMOS transistor uN1 in the multiplexer 611 is turned off, and the NMOS transistor uN2 in the multiplexer 611 is turned on or off depending on the change of the second positive single-rail output BP. In Figure 10A, the NMOS transistors ulatN1 and uN1, which are drawn with a dotted net at the bottom left, represent that they are unrelated to the forward multiplexing output MXOP.

[0058] In Figure 10A, the NMOS transistor uN2 in the multiplexer 611 may be turned on or off depending on the change in the second positive single-rail output BP. If the second positive single-rail output BP is at a low logic level (BP=0), the NMOS transistor uN2 in the multiplexer 611 is off, and the positive multiplexing output MXOP is not updated. If the second positive single-rail output BP is at a high logic level (BP=1), the NMOS transistor uN2 in the multiplexer 611 will be turned on, making the positive multiplexing output MXOP equal to the ground voltage Gnd (MXOP=0). In short, in Figure 10A, the positive multiplexing output MXOP is determined by the lower right branch.

[0059] When the forward prior decision bit Spo is at a high logic level (Spo=1) and the reverse prior decision bit SBpo is at a low logic level (SBpo=0) (as shown in Figure 10B), the NMOS transistor ulatN1 in the selection stage circuit 613a is turned on, and the NMOS transistor ulatN2 is turned off. Consequently, the NMOS transistor uN1 in the multiplexer 611 may turn on or off depending on the change of the first positive single-rail output AP, and the NMOS transistor uN2 in the multiplexer 611 is turned off because the NMOS transistor ulatN2 in the selection stage circuit 613 is turned off. In Figure 10B, the NMOS transistors ulatN2 and uN2, which are drawn with a dotted net at the bottom right branch, represent that they are independent of the forward multiplexing output MXOP.

[0060] In Figure 10B, the NMOS transistor uN1 in multiplexer 611 may be turned on or off depending on the change of the first positive single-rail output AP. If the first positive single-rail output AP is at a low logic level (AP=0), the NMOS transistor uN1 in multiplexer 611 will be off, and the positive multiplexing output MXOP will not be updated. If the first positive single-rail output AP is at a high logic level (AP=1), the NMOS transistor uN1 in multiplexer 611 will be on, and the positive multiplexing output MXOP will be equal to the ground voltage Gnd (MXOP=0). In short, in Figure 10B, the positive multiplexing output MXOP is determined by the lower left branch.

[0061] When the dynamic module 6 is in the evaluation period (Teva), the phase setting circuit 613b, the selection stage circuit 613a, and the multiplexer 611 in the upper domino circuit 61 will operate sequentially. The phase setting circuit 613b first determines whether the positive multiplexed output MXOP is related to the selection stage circuit 613a and the multiplexer 611. Then, the selection stage circuit 613a determines which of the NMOS transistors uN1 and uN2 in the multiplexer 611 will affect the positive multiplexed output MXOP.

[0062] The phase setting circuit 633b, the selection stage circuit 633a, and the Teva operation of the multiplexer 631 in the lower domino circuit 63 during evaluation are similar to those in the upper domino circuit 61. If the reverse latching clock signal CLKB_L is at a low logic level (CLKB_L=0), the PMOS transistor 1P in the phase setting circuit 633b is turned on, and the NMOS transistor 1N is turned off. The reverse multiplexing output MXON is determined by the selection stage circuit 633a and the multiplexer 631.

[0063] When the forward prior determination bit Spo is at a low logic level (Spo=0), the reverse prior determination bit SBpo is at a high logic level (SBpo=1) (as shown in Figure 10A). At this time, PMOS transistor llatP1 is off and PMOS transistor llatP2 is on, so that the reverse multiplexing output MXON is determined by the upper right branch. In Figure 10A, PMOS transistors llatP1 and 1P1 are shown in a dotted net diagram on the upper left branch, indicating that they are independent of the reverse multiplexing output MXON.

[0064] Alternatively, when the forward prior determination bit Spo is at a high logic level (Spo=1), the reverse prior determination bit SBpo is at a low logic level (SBpo=0) (as shown in Figure 10B). In this case, PMOS transistor llatP1 is turned on and PMOS transistor llatP2 is turned off, so that the reverse multiplex output MXON is determined by the upper left branch. In Figure 10B, PMOS transistors llatP2 and 1P2, located on the upper right branch in a dotted net diagram, represent that they are independent of the reverse multiplex output MXON.

[0065] When the dynamic module 6 is in the evaluation period (Teva), the phase setting circuit 633b, the selection stage circuit 633a, and the multiplexer 631 in the lower domino circuit 63 will operate sequentially. The phase setting circuit 633b first determines whether the inverted multiplexed output MXON is related to the selection stage circuit 633a and the multiplexer 631. Then, the selection stage circuit 633a determines which of the PMOS transistors 1P1 and 1P2 in the multiplexer 631 will affect the inverted multiplexed output MXON.

[0066] The above explains the details of how the dynamic module 6 operates in response to different input signals. For ease of explanation, Figure 11 illustrates the different combinations of input signals of the dynamic module 6, and the corresponding positive multiplexer output MXOP and negative multiplexer output MXON.

[0067] Please refer to Figure 11, which shows a summary table of the signal states of the dynamic module 6 during pre-charging (Tpre) and evaluation (Teva) according to the first embodiment of this disclosure. As described in Figure 9, the signal states of the dynamic module 6 during pre-charging (Tpre) are summarized here. As described in Figures 10A and 10B, the signal states of the dynamic module 6 during evaluation (Teva) are summarized here.

[0068] During the pre-charge period Tpre, because the forward latch-up clock signal CLK_K is at a low logic level (CLK_L=0) and the reverse latch-up clock signal CLKB_L is at a high logic level (CLKB_L=1), the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN) do not affect the forward multiplexed output MXOP and the reverse multiplexed output MXON. Accordingly, the storage circuit 65 will maintain the forward multiplexed output MXOP and the reverse multiplexed output MXON.

[0069] During the evaluation period, when the forward prior decision bit Spo is at a low logic level (Spo=0) and the reverse prior decision bit SBpo is at a high logic level (SBpo=1), the dynamic module 6 selectively updates the forward multiplexing output MXOP and the reverse multiplexing output MXON with the second rail-to-rail output pair (BP, BN). On the other hand, during the evaluation period, when the forward prior decision bit Spo is at a high logic level (Spo=1) and the reverse prior decision bit SBpo is at a low logic level (SBpo=0), the dynamic module 6 selectively updates the forward multiplexing output MXOP and the reverse multiplexing output MXON with the first rail-to-rail output pair (AP, AN).

[0070] As shown in Figure 3, the speculative DFE 15 operates recursively, and the even-numbered speculative path 31 and the odd-numbered speculative path 33 influence each other. To illustrate how the dynamic module 6 is applied to the speculative DFE 3 in Figure 5B, the signal relationships when the speculative DFE 3 uses the dynamic module 6 are then illustrated with waveform diagrams.

[0071] Please refer to Figure 12, which is a waveform diagram illustrating how a data stream is processed according to the speculative DFE of the first embodiment of the present disclosure, using a data stream as an example. The upper part of Figure 12 shows the waveforms of the system clock signal CLK_sys, the input data in(A)~in(F), the positive latching clock signal CLK_L(even) for even-numbered paths, and the positive latching clock signal CLK_L(odd) for odd-numbered paths.

[0072] The even-number dynamic module 315 and the odd-number dynamic module 335 simultaneously receive the system clock signal CLK_sys and the input data in(A)~in(F). The even-number dynamic module 315 receives the positive latching clock signal CLK_L(even) for the even-number path, and the odd-number dynamic module 335 receives the positive latching clock signal CLK_L(odd) for the odd-number path. The system clock signal CLK_sys may be provided by a phase-locked loop (PLL).

[0073] In this document, it is assumed that during the period when the positive latch-up clock signal CLK_L(even) of the even-numbered path is at a high logic level (CLK_L(even)=1), the sensing amplifiers 313a and 313b in the even-numbered prediction path 31 perform sampling and holding operations, and the sensing amplifiers 333a and 333b in the odd-numbered prediction path 33 pause operations. Furthermore, it is assumed here that when the positive latch-up clock signal CLK_L(odd) of the odd-numbered path is at a high logic level (CLK_L(odd)=1), the sensing amplifiers 333a and 333b in the odd-numbered prediction path 31 perform sampling and holding operations; and the sensing amplifiers 313a and 313b in the even-numbered prediction path 33 pause operations. However, in practical applications, the logic level of the latch-up clock signal used to trigger the sensing amplifiers 313a, 313b, 333a, and 333b is not limited to the description herein.

[0074] Figure 12 shows two dashed boxes. The waveform in the upper dashed box is the signal associated with the even-numbered prediction path 31; the waveform in the lower dashed box is the signal associated with the odd-numbered prediction path 33.

[0075] The input data in(A)~in(F) in Figure 12 vary with the rising and falling edges of the system clock signal CLK_sys. Even-numbered prediction path 31 and odd-numbered prediction path 33 process the input data in(A)~in(F) alternately. Even-numbered prediction path 31, triggered by the positive latching clock signal CLK_L(even) of the even-numbered path, processes the input data in(A), in(C), and in(E). Odd-numbered prediction path 33, triggered by the positive latching clock signal CLK_L(odd) of the odd-numbered path, processes the input data in(B), in(D), and in(F).

[0076] Due to the clock propagation delay Tclk2sa, the rising edge of the positive latching clock signal CLK_L(even) of the even-numbered path is slightly behind the rising edge of the system clock signal CLK_sys, and the falling edge of the positive latching clock signal CLK_L(odd) of the odd-numbered path is slightly behind the rising edge of the system clock signal CLK_sys.

[0077] In the even-numbered prediction path 31, when the positive latch-up clock signal CLK_L(even) of the even-numbered path is at a high logic level (CLK_L(even)=1), the sensing amplifiers 313a and 313b sample the input data in(A), in(C), and in(E) and generate sampled data sa(A), sa(C), and sa(E). On the other hand, when the positive latch-up clock signal CLK_L(even) of the even-numbered path is at a low logic level (CLK_L(even)=0), the sensing amplifiers 313a and 313b pause operation.

[0078] In the odd-numbered prediction path 33, when the positive latch-up clock signal CLK_L(odd) of the odd-numbered path is at a high logic level (CLK_L(odd)=1), the sensing amplifiers 333a and 333b sample the input data in(B) and in(D) and generate sampled data sa(B) and sa(D). When the positive latch-up clock signal CLK_L(odd) of the odd-numbered path is at a low logic level (CLK_L(odd)=0), the sensing amplifiers 333a and 333b pause operation.

[0079] For each sampled data point sa(A)~(E), the prediction formula DFE 3 will generate two sets of track-to-track output pairs. The two sets of track-to-track output pairs in the even-numbered prediction path 31 include: the track-to-track output pair of the first even-numbered path (APevn, ANevn), and the track-to-track output pair of the second even-numbered path (BPevn, BNevn). The two sets of track-to-track output pairs in the odd-numbered prediction path 33 include: the track-to-track output pair of the first odd-numbered path (APodd, ANodd), and the track-to-track output pair of the second odd-numbered path (BPodd, BNodd).

[0080] When the clock level of the latching clock signal CLK_L(even) of the even-numbered path is equal to the high logic level (CLK_L(even)=1), in the even-numbered prediction path 31, the sensing amplifier 313a generates the first even-numbered path rail-to-rail output pair (APevn, ANevn) according to the sampled data sa(A), sa(C), sa(E), and the sensing amplifier 313b generates the second rail-to-rail output pair (BPevn, BNevn) according to the sampled data sa(A), sa(C), sa(E). During periods T1, T3, and T5, the rail-to-rail output pairs (APevn, ANevn) of the first even-numbered path generated by sensing amplifier 313a are sa(A)-, sa(C)-, and sa(E)-, respectively, corresponding to the sampled data sa(A), sa(C), and sa(E). The rail-to-rail output pairs (BPevn, BNevn) of the second even-numbered path generated by sensing amplifier 313b are sa(A)+, sa(C)+, and sa(E)+, respectively, corresponding to the sampled data sa(A), sa(C), and sa(E). Simultaneously, the clock level of the positive latching clock signal CLK_L(odd) of the odd-numbered path is equal to the low logic level (CLK_L(odd) = 0), therefore, sensing amplifiers 331a and 331b in the odd-numbered speculative path 33 do not sample or hold any input data.

[0081] When the clock level of the positive latching clock signal CLK_L(odd) of the odd-numbered path is equal to the high logic level (CLK_L(odd)=1), the clock level of the latching clock signal CLK_L(even) of the even-numbered path is equal to the low logic level (CLK_L(even)=0). Therefore, the sensing amplifiers 311a and 311b in the even-numbered prediction path 31 do not sample or hold any input data. At this time, in the odd-numbered prediction path 33, the sensing amplifier 333a generates the first odd-numbered path rail-to-rail output pair (APodd, ANodd) based on the sampled data sa(B) and sa(D), and the sensing amplifier 333b generates the second odd-numbered path rail-to-rail output pair (BPodd, BNodd) based on the sampled data sa(B) and sa(D). During periods T2 and T4, the track-to-track output pairs (APodd, ANodd) of the first odd-numbered path generated by the sensing amplifier 333a are sa(B)- and sa(D)- corresponding to the sampled data sa(B) and sa(D), respectively; the track-to-track output pairs (BPodd, BNodd) of the second odd-numbered path generated by the sensing amplifier 333b are sa(B)+ and sa(D)+ corresponding to the sampled data sa(B) and sa(D), respectively.

[0082] During the evaluation period Teva corresponding to the even-numbered prediction path 31, the even-numbered dynamic module 315 generates the forward multiplexing output MXOPevn of the even-numbered path and the reverse multiplexing output MXONevn of the even-numbered path. The forward multiplexing output MXOPevn of the even-numbered path corresponding to the sampled data sa(C) and sa(E) is mx(C) and mx(E), and the reverse multiplexing output MXONevn of the even-numbered path corresponding to the sampled data sa(C) and sa(E) is mxb(C) and mxb(E).

[0083] During the evaluation period corresponding to the odd prediction path 33, the odd dynamic module 335 generates the positive multiplexing output MXOPodd and the negative multiplexing output MXONodd for the odd path. The positive multiplexing output MXOPodd for the odd path corresponding to the sampled data sa(B) and sa(D) are mx(B) and mx(D), and the negative multiplexing output MXONodd for the odd path corresponding to the sampled data sa(B) and sa(D) are mxb(B) and mxb(D).

[0084] Next, the processing procedure for the input data will be explained. Please refer to Figures 5B and 12. First, in the even-numbered prediction path 31, the input data in(A) is sampled to generate sample data sa(A). Since the input data in(A) is the first input data, the odd-numbered dynamic module 335 directly selects the track-to-track output pair (APodd, ANodd) of the first odd-numbered path or the track-to-track output pair (BPodd, BNodd) of the second odd-numbered path corresponding to the sample data sa(B) based on the sample data sa(A).

[0085] In the odd prediction path 33, the input data in(B) is sampled to generate sample data sa(B). Then, the sense amplifier 333a generates a rail-to-rail output pair sa(B)- for the first odd path, and the sense amplifier 333b generates a rail-to-rail output pair sa(B)+ for the second odd path. After referencing the sample data sa(A), the odd dynamic module 335 selects one of the rail-to-rail output pair sa(B)- for the first odd path and the rail-to-rail output pair sa(B)+ for the second odd path as the positive multiplexing output MXOPodd and the negative multiplexing output MXONodd for the odd path corresponding to the sample data sa(B), (i.e., mx(B) and mxb(B)).

[0086] If the odd-number dynamic module 335 selects the rail-to-rail output pair sa(B)- of the first odd-number path, the positive multiplexing output mx(B) of the odd-number path is equal to the positive single-rail output APodd of the first odd-number path, and the negative multiplexing output mxb(B) of the odd-number path is equal to the negative single-rail output ANodd of the first odd-number path. If the odd-number dynamic module 335 selects the rail-to-rail output pair sa(B)+ of the second odd-number path, the positive multiplexing output mx(B) of the odd-number path is equal to the positive single-rail output BPodd of the second odd-number path, and the negative multiplexing output mxb(B) of the odd-number path is equal to the negative single-rail output BNodd of the second odd-number path. Inverters 337a and 337b further convert the positive multiplexing output mx(B) and the negative multiplexing output mxb(B) of the odd-number path into the odd-number path-determined Dout_odd.

[0087] In the even-number prediction path 31, the input data in(C) is sampled to generate sampled data sa(C). Next, the sense amplifier 313a generates a rail-to-rail output pair sa(C)- for the first even-number path, and the sense amplifier 313b generates a rail-to-rail output pair sa(C)+ for the second even-number path. After determining Dout_odd with reference to the odd-number path, the even-number dynamic module 315 selects either the rail-to-rail output pair sa(C)- for the first even-number path or the rail-to-rail output pair sa(C)+ for the second even-number path to generate a positive multiplexed output MXOPevn for the even-number path and a negative multiplexed output MXONevn for the even-number path corresponding to the sampled data sa(C). That is, mx(C) and mxb(C).

[0088] If the even-numbered dynamic module 315 selects the rail-to-rail output pair sa(C)- of the first even-numbered path, the positive multiplexing output mx(C) of the even-numbered path is equivalent to the positive single-rail output APevn of the first even-numbered path, and the reverse multiplexing output mxb(C) is equivalent to the negative single-rail output ANevn of the first even-numbered path. If the even-numbered dynamic module 315 selects the rail-to-rail output pair sa(C)+ of the second even-numbered path, the positive multiplexing output mx(C) of the even-numbered path is equivalent to the positive single-rail output BPevn of the second even-numbered path, and the reverse multiplexing output mxb(C) of the even-numbered path is equivalent to the negative single-rail output BNevn of the second even-numbered path. Inverters 317a and 317b further convert the positive multiplexing output mx(C) and the reverse multiplexing output mxb(C) of the even-numbered path into the even-numbered path determined Dout_evn.

[0089] The processing of input data in(D) and in(F) is similar to that of input data in(B); and the processing of input data in(E) is similar to that of input data in(C). Therefore, the processing of input data in(D), in(E), and in(F) will not be described here.

[0090] Figure 12 below lists the causes of delays related to the input data in(B). Please also refer to Figures 5B, 6, and 12. The clock propagation delay Tclk2sa of the sensing amplifiers 333a and 333b is between time point t1 and time point t2, the set time TsuSA of the sensing amplifiers 333a and 333b is between time point t2 and time point t3, and the propagation delay Tdyn of the odd dynamic module 335 is between time point t3 and time point t5. Therefore, the processing and propagation delay of the odd speculative path 33 is between time point t1 and time point t4, and the operating boundary ΔTtap1' of the speculative first-order tap (tap1) is between time point t4 and time point t5. Second Embodiment

[0091] Figures 13A and 13B are block diagrams and circuit designs of the dynamic module 7 according to the second embodiment of this disclosure, respectively. Figure 14 illustrates the operation of the dynamic module 7 during pre-charging (Tpre). Figures 15A, 15B, and 16 illustrate the operation of the dynamic module 7 during evaluation (Teva). Figure 17 lists different combinations of signal states of the dynamic module 7. Figure 18 further illustrates how the dynamic module 7 is applied to the speculative DFE 3.

[0092] Please refer to Figure 13A, which is a block diagram of the dynamic module according to the second embodiment of this disclosure. The dynamic module 7 includes an upper domino circuit 71, a lower domino circuit 73, and a storage circuit 75. The storage circuit 75 is electrically connected to the upper domino circuit 71 and the lower domino circuit 73 through multiplexing output terminals Nmxop and Nmxon. The upper domino circuit 71 includes a dynamic latch 713 and a multiplexer 711, and the lower domino circuit 73 includes a dynamic latch 733 and a multiplexer 731.

[0093] In the upper domino circuit 71, the dynamic latch 713 includes phase setting circuits 713a and 713b and a selection stage circuit 713c, and the multiplexer 711 includes a positive output circuit 711a and a negative output circuit 711b. In the lower domino circuit 73, the dynamic latch 733 includes phase setting circuits 733a and 733b and a selection stage circuit 733c, and the multiplexer 731 includes a positive output circuit 731a and a negative output circuit 731b.

[0094] Please refer to Figure 13B, which is a schematic diagram of the circuit design of the dynamic module according to the second embodiment of this disclosure. Please also refer to Figures 13A and 13B.

[0095] Next, the components and connections of the domino circuit 71 above will be explained. In the dynamic latching device 713, the phase setting circuit 713a includes a PMOS transistor upP and an NMOS transistor upN, the phase setting circuit 713b includes a PMOS transistor unP and an NMOS transistor unN, and the selection stage circuit 713c includes a PMOS transistor uinP, an NMOS transistor uinN, and inverters uinv1 and uinv2 that are cross-coupled.

[0096] In the phase setting circuit 713a, the gates of PMOS transistor lpP and NMOS transistor lpN are electrically connected to each other to receive the positive latch-up clock signal CLK_L, and the drains of both PMOS transistor lpP and NMOS transistor lpN are electrically connected to the selection terminal Nbp. The source of PMOS transistor upP is electrically connected to the supply voltage Vcc, and the source of NMOS transistor upN is electrically connected to the selection stage circuit 713c. In the phase setting circuit 713b, the gates of PMOS transistor unP and NMOS transistor unN are electrically connected to each other to receive the latch-up clock signal CLK_L, and the drains of both PMOS transistor unP and NMOS transistor unN are electrically connected to the selection terminal Nan. The source of PMOS transistor unP is electrically connected to the selection stage circuit 713c, and the source of NMOS transistor unN is electrically connected to the ground terminal Gnd.

[0097] In the selection stage circuit 713c, the source of the PMOS transistor uinP is electrically connected to the supply voltage terminal Vcc, and the drain of the PMOS transistor uinP is electrically connected to the phase setting circuit 713b. The source of the NMOS transistor uinN is electrically connected to the ground terminal Gnd, and the drain of the NMOS transistor uinN is electrically connected to the phase setting circuit 713a. The gate of the PMOS transistor uinP receives the forward-biased previously determined bit Spo, and the gate of the PMOS transistor uinN receives the reverse-biased previously determined bit SBpo. The inverters uinv1 and uinv2, which are cross-coupled to each other, are electrically connected between the selection terminals Nap and Nan. The input terminal of inverter uinv1 and the output terminal of inverter uinv2 are electrically connected to the selection terminal Nap. The output terminal of inverter uinv1 and the input terminal of inverter uinv2 are electrically connected to the selection terminal Nan.

[0098] In the multiplexer 711, the positive output circuit 711a includes PMOS transistors upoP1 and upoP2 and NMOS transistors upoN1 and upoN2; the negative output circuit 711b includes PMOS transistors unoP1 and unoP2 and NMOS transistors unoN1 and unoN2. In short, the positive output circuit 711a is related to the positive multiplexer output MXOP, and the negative output circuit 711b is related to the reverse multiplexer output MXON.

[0099] In the positive output circuit 711a, the gate of PMOS transistor upoP2 is electrically connected to the selection terminal Nap, and the gate of NMOS transistor upoN2 ​​is electrically connected to the selection terminal Nan. The gates of PMOS transistor upoP1 and NMOS transistor upoN1 are electrically connected to each other to receive the first negative single-rail output AN. The source of PMOS transistor upoP1 is electrically connected to the supply voltage terminal Vcc, and the drain of PMOS transistor upoP1 is electrically connected to the source of PMOS transistor upoP2. The source of NMOS transistor upoN1 is electrically connected to the ground terminal Gnd, and the drain of NMOS transistor upoN1 is electrically connected to the source of NMOS transistor upoN2. Furthermore, the drains of both PMOS transistor upoP2 and NMOS transistor upoN2 ​​are electrically connected to the positive multiplexing output terminal Nmxop.

[0100] In the negative output circuit 711b, the gate of PMOS transistor unoP2 is electrically connected to the selection terminal Nap, and the gate of NMOS transistor upoN2 ​​is electrically connected to the selection terminal Nan. The gates of PMOS transistor unoP1 and NMOS transistor unoN1 are electrically connected to each other to receive the first positive single-rail output AP. The source of PMOS transistor unoP1 is electrically connected to the supply voltage terminal Vcc, and the drain of PMOS transistor unoP1 is electrically connected to the source of PMOS transistor unoP2. The source of NMOS transistor unoN1 is electrically connected to the ground terminal Gnd, and the drain of NMOS transistor unoN1 is electrically connected to the source of NMOS transistor unoN2. Furthermore, the drains of both PMOS transistor unoP2 and NMOS transistor unoN2 are electrically connected to the inverting multiplex output terminal Nmxon.

[0101] Next, the components and connections of the domino circuit 73 below will be explained. In the dynamic latching device 733, the phase setting circuit 733a includes a PMOS transistor lpP and an NMOS transistor lpN; the phase setting circuit 733b includes a PMOS transistor lnP and an NMOS transistor lnN; and the selection stage circuit 733c includes a PMOS transistor linP, an NMOS transistor linN, and inverters linv1 and linv2 that are cross-coupled.

[0102] In the phase setting circuit 733b, the gates of PMOS transistor lpP and NMOS transistor lpN are electrically connected to each other to receive the positive latch-up clock signal CLK_L, and the drains of PMOS transistor lpP and NMOS transistor lpN are electrically connected to the selection terminal Nbp. The source of PMOS transistor lpP is electrically connected to the supply voltage Vcc, and the source of NMOS transistor lpN is electrically connected to the selection stage circuit 733c. In the phase setting circuit 733b, the gates of PMOS transistor lnP and NMOS transistor lnN are electrically connected to each other to receive the latch-up clock signal CLKB_L, and the drains of PMOS transistor lnP and NMOS transistor lnN are electrically connected to the selection terminal Nbn. The source of PMOS transistor lnP is electrically connected to the selection stage circuit 733c, and the source of NMOS transistor lpN is electrically connected to the ground terminal Gnd.

[0103] In the selection stage circuit 733c, the source of PMOS transistor linP is electrically connected to the supply voltage Vcc, and the drain of PMOS transistor linP is electrically connected to the phase setting circuit 733b. The source of NMOS transistor linN is electrically connected to the ground terminal Gnd, and the drain of NMOS transistor linN is electrically connected to the phase setting circuit 733a. The gate of PMOS transistor linP receives the inverted previously determined bit SBpo, and the gate of NMOS transistor linN receives the positive previously determined bit Spo. Inverters linv1 and linv2, which are cross-coupled to each other, are electrically connected between the selection terminals Nbp and Nbn. The input terminal of inverter linv1 and the output terminal of inverter linv2 are electrically connected to the selection terminal Nbp. The output terminal of inverter linv1 and the input terminal of inverter linv2 are electrically connected to the selection terminal Nbn.

[0104] In the multiplexer 731, the positive output circuit 731a includes PMOS transistors lpoP1 and lpoP2 and NMOS transistors lpoN1 and lpoN2; the negative output circuit 731b includes PMOS transistors lnoP1 and lnoP2 and NMOS transistors lnoN1 and lnoN2. Basically, the positive output circuit 731a is associated with the positive multiplexer output MXOP, and the negative output circuit 731b is associated with the reverse multiplexer output MXON.

[0105] In the positive output circuit 731a, the gate of PMOS transistor lpoP2 is electrically connected to the selection terminal Nbp, and the gate of NMOS transistor lpoN2 is electrically connected to the selection terminal Nbn. The gates of PMOS transistor lpoP1 and NMOS transistor lpoN1 are electrically connected to each other to receive the second negative single-rail output BN. The source of PMOS transistor lpoP1 is electrically connected to the supply voltage terminal Vcc; the drain of PMOS transistor lpoP1 is electrically connected to the source of PMOS transistor lpoP2. The source of NMOS transistor lpoN1 is electrically connected to the ground terminal Gnd, and the drain of NMOS transistor lpoN1 is electrically connected to the source of NMOS transistor lpoN2. Furthermore, the drains of both PMOS transistor lpoP2 and NMOS transistor lpoN2 are electrically connected to the positive multiplexing output terminal Nmxop.

[0106] In the negative output circuit 731b, the gate of PMOS transistor lnoP2 is electrically connected to the selection terminal Nbp, and the gate of NMOS transistor lnoN2 is electrically connected to the selection terminal Nbn. The gates of PMOS transistor lnoP1 and NMOS transistor lnoN1 are electrically connected to each other to receive the second positive single-rail output BP. The source of PMOS transistor lpoP1 is electrically connected to the supply voltage terminal Vcc, and the drain of PMOS transistor lnoP1 is electrically connected to the source of PMOS transistor lnoP2. The source of NMOS transistor lnoN1 is electrically connected to the ground terminal Gnd, and the drain of NMOS transistor lnoN1 is electrically connected to the source of NMOS transistor lnoN2. Furthermore, the drains of both PMOS transistor lnoP2 and NMOS transistor lnoN2 are electrically connected to the inverting multiplex output terminal Nmxon.

[0107] The storage circuit 75 includes cross-coupled inverters sinv1 and sinv2. The input and output terminals of inverter sinv1 are electrically connected to the positive multiplexing output terminal Nmxop and the negative multiplexing output terminal Nmxon, respectively. The input and output terminals of inverter sinv2 are electrically connected to the negative multiplexing output terminal Nmxon and the positive multiplexing output terminal Nmxop, respectively.

[0108] Please refer to Figure 14, which is a schematic diagram of the operation of the dynamic module Tpre during precharging according to the second embodiment of the present disclosure. The operation of the upper domino circuit 71 and the lower domino circuit 73 will be described below.

[0109] Next, the operation of the phase setting circuits 713a and 713b, the selection stage circuit 713c, and the multiplexer 711 in the upper domino circuit 711 will be explained in sequence. Since the positive latch-up clock signal CLK_L is at a low logic level (CLK_L=0), the PMOS transistor upP in the phase setting circuit 713a is turned on, and the NMOS transistor upN is turned off. Since the reverse latch-up clock signal CLKB_L is at a high logic level (CLKB_L=1), the PMOS transistor unP is turned off, and the NMOS transistor unN is turned on. Therefore, in the upper domino circuit 71, the selection signal sa_p is equal to the supply voltage Vcc (sa_p=1), and the selection signal sa_n is equal to the ground voltage Gnd (sa_n=0).

[0110] Since the selection signal sa_p equals the supply voltage Vcc (sa_p=1), the PMOS transistor upoP2 in the positive output circuit 711a is turned off, and the PMOS transistor unoP2 in the negative output circuit 731b is turned off. Since the selection signal sa_n equals the ground voltage Gnd (sa_n=0), the NMOS transistor upoN2 ​​in the positive output circuit 711a is turned off, and the NMOS transistor unoN2 in the negative output circuit 731b is turned off. Consequently, in the multiplexer 711, the PMOS transistors unoP2 and upoP2 and the NMOS transistors unoN2 and upoN2 ​​associated with the multiplexed output terminals Nmxon and Nmxop are all turned off, and the upper domino circuit 7 does not affect the positive multiplexed output MXOP and the reverse multiplexed output MXON during the pre-charging period.

[0111] In short, when the dynamic module 7 is in the pre-charge period Tpre, the upper domino circuit 71 does not update the forward multiplex output MXOP and the reverse multiplex output MXON. In Figure 14, the dotted mesh-based multiplexer 711 is used to indicate that the multiplexer 711 does not affect the forward multiplex output MXOP and the reverse multiplex output MXON during the pre-charge period Tpre.

[0112] The operation of the phase setting circuits 733a and 733b, the selection stage circuit 733c, and the multiplexer 731 in the lower domino circuit 73 are similar to their corresponding components in the upper domino circuit 71. Because the PMOS transistor loP is turned on by the positive latch-up clock signal CLK_L (CLK_L=0), the selection signal sb_p is equal to the supply voltage Vcc (sb_p=1). Because the NMOS transistor lnN is turned on by the reverse latch-up clock signal CLKB_L (CLKB_L=1), the selection signal sb_n is equal to the ground voltage Gnd (sb_n=0). Consequently, in multiplexer 731, the PMOS transistors lnoP2 and lpoP2 and the NMOS transistors lnoN2 and lpoN2 associated with the multiplexed output terminals Nmxon and Nmxop are all disconnected, and the domino circuit 73 below does not affect the forward multiplexed output MXOP and the reverse multiplexed output MXON during the pre-charge period. Figure 14 shows multiplexer 731 with a dotted net bottom, representing that multiplexer 731 does not affect the forward multiplexed output MXOP and the reverse multiplexed output MXON.

[0113] Next, the operation of the dynamic locking devices 713 and 813 and the multiplexers 811 and 831 during the evaluation of Teva will be explained. Figures 15A and 15B illustrate the operation of the dynamic module 7 when the positive locking clock signal CLK_L is at a high logic level (CLK_L=1) and the reverse locking clock signal CLKB_L is at a low logic level (CLKB_L=0).

[0114] Figure 15A is a schematic diagram of the Teva operation of the dynamic module according to the second embodiment of the present disclosure during the evaluation when the positive prior decision bit Spo is at a low logic level (Spo=0) and the negative prior decision bit SBpo is at a high logic level (SBpo=1). On the other hand, Figure 15B is a schematic diagram of the Teva operation of the dynamic module according to the second embodiment of the present disclosure during the evaluation when the positive prior decision bit Spo is at a high logic level (Spo=1) and the negative prior decision bit SBpo is at a low logic level (SBpo=0).

[0115] Please refer to Figure 16, which is a flowchart of the upper domino circuit operating during the evaluation period according to the second embodiment of this disclosure. The operation of the upper domino circuit 71 shown in Figures 15A and 15B is described below. First, the dynamic latch 713 simultaneously generates a selection signal sa_p (step S71) and a selection signal sa_n (step S73).

[0116] Because the latch-up clock signal CLK_L (CLK_L=1) turns on the NMOS transistor upN, the NMOS transistor uinN in the selection stage circuit 713c is turned on to the selection signal sa_p (step S71a), and the selection signal sa_p is determined by the on-state of the NMOS transistor uinN. The NMOS transistor uinN is further controlled by the inverted prior decision bit SBpo (step S71b). As shown in Figure 15A, when the inverted prior decision bit SBpo is at a high logic level (SBpo=1), the selection signal sa_p is equal to the ground voltage Gnd (sa_p=0). As shown in Figure 15B, when the inverted prior decision bit SBpo is at a low logic level (SBpo=0), the selection signal sb_n is floating (sb_n=Z).

[0117] Because the reverse latch-up clock signal CLKB_L (CLKB_L=1) turns on the PMOS transistor unP, the PMOS transistor uinP in the selection stage circuit 713c is turned on to the selection signal sa_n (step S73a), and the selection signal sa_n is determined by the on-state of the PMOS transistor uinP. The PMOS transistor uinP is further controlled by the positive prior determination bit Spo (step S73b). As shown in Figure 15A, when the positive prior determination bit Spo is at a low logic level (Spo=0), the selection signal sa_n is equal to the supply voltage Vcc (sa_n=1). As shown in Figure 15B, when the positive prior determination bit Spo is at a high logic level (Spo=1), the selection signal sa_n is floating (sa_n=Z).

[0118] Therefore, the selection signal sa_p changes with the reverse prior decision bit SBpo, and the selection signal sa_n changes with the forward prior decision bit Spo. Two different scenarios must be considered in response to the changes in the forward prior decision bit Spo and the reverse prior decision bit SBpo.

[0119] When the selection signals sa_p and sa_n are floating (sa_p=Z, sa_n=Z), the multiplexer 711 is disabled, and the upper domino circuit 71 does not affect the forward multiplexing output MXOP and the reverse multiplexing output MXON (step S77). Figure 15B shows the components of the upper domino circuit 71 with a dotted grid bottom, representing that during the evaluation period Teva, if the forward prior decision bit Spo is a high logic level (Spo=1) and the reverse prior decision bit is a low logic level (SBpo=0), the upper domino circuit 73 does not affect the forward multiplexing output MXOP and the reverse multiplexing output MXON.

[0120] When the selection signal sa_p is the ground voltage Gnd (sa_p=0) and the selection signal sa_n is the supply voltage (sa_n=1), the multiplexer 711 generates a positive multiplex output MXOP and a reverse multiplex output MXON (MXOP=AP and MXON=AN) based on the first positive single-rail output AP and the first negative single-rail output AN (step S75).

[0121] As shown in Figure 15A, the low logic level selection signal sa_n (sa_n=0) turns on the PMOS transistor upoP2 in the positive output circuit 711a and the PMOS transistor unoP2 in the negative output circuit 711b; the high logic level selection signal sa_n (sa_n=1) turns on the NMOS transistor upoN1 in the positive output circuit 711a and the NMOS transistor unoN2 in the negative output circuit 711b.

[0122] Next, the positive multiplexing output MXOP is determined by the conduction state of the PMOS transistor upoP1 and the NMOS transistor unoN1 in the positive output circuit 711a. The PMOS transistor upoP1 and the NMOS transistor unoN1 are controlled by the first negative single-rail output AN (step S75a). On the other hand, the reverse multiplexing output MXON is determined by the conduction state of the PMOS transistor unoP1 and the NMOS transistor unoN1 in the negative output circuit 711b. The PMOS transistor unoP1 and the NMOS transistor unoN1 are controlled by the first positive single-rail output AP (step S75b).

[0123] Step S75 needs to consider two cases of the first track-to-track output pair: (AP=0 and AN=1) and (AP=1 and AN=0).

[0124] First, let's explain the case where AP=0 and AN=1. Since the first negative single-rail output AN is at a high logic level (AN=1), in the positive output circuit 711a, the PMOS transistor upoP1 is off, and the NMOS transistor upoN1 is on. Consequently, the positive multiplexed output MXOP equals the ground voltage Gnd (MXOP=0). Simultaneously, in the negative output circuit 711b, since the first positive single-rail output AP is at a low logic level (AP=0), the PMOS transistor unoP1 is on, and the NMOS transistor unoN1 is off. Consequently, the reverse multiplexed output MXON equals the supply voltage Vcc (MXON=1). Therefore, when the first rail-to-rail output pair (AP, AN) satisfies the condition that the first positive single-rail output AP is at a low logic level (AP=0) and the first negative single-rail output AN is at a high logic level (AN=1), the relationship between the positive multiplexing output MXOP and the first positive single-rail output AP is MXOP=AP=0, and the relationship between the reverse multiplexing output MXON and the first negative single-rail output AN is MXON=AN=1.

[0125] Next, we will explain the case where AP=1 and AN=0. Because the first negative single-rail output AN is at a low logic level (AN=0), in the positive output circuit 711a, the PMOS transistor upoP1 is turned on, and the NMOS transistor upoN1 is turned off. Accordingly, the positive multiplexed output MXOP is equal to the supply voltage Vcc (MXOP=1). Simultaneously, because the first positive single-rail output AP is at a high logic level (AP=1), in the negative output circuit 711b, the PMOS transistor unoP1 is turned off, and the NMOS transistor unoN1 is turned on. Consequently, the reverse multiplexed output MXON is equal to the ground voltage Gnd (MXON=0). Therefore, when the first rail-to-rail output pair (AP, AN) meets the condition that the first positive single rail AP output is at a high logic level (AP=1) and the first negative single rail output AN is at a low logic level (AN=0), the relationship between the positive multiplex output MXOP and the first positive single rail output AP is MXOP=AP=1, and the relationship between the reverse multiplex output MXON and the first negative single rail output AN is MXON=AN=0.

[0126] When the dynamic module 7 is in the evaluation period (Teva), the phase setting circuits 713a and 713b, the selection stage circuit 713c, and the multiplexer 711 in the upper domino circuit 71 operate sequentially. The phase setting circuits 713a and 713b first determine whether the selection stage circuit 713c is related to the selection signals sa_p and sa_n in the upper domino circuit 81. If not (as shown in Figure 15B), the selection signals sa_p and sa_n in the upper domino circuit 71 are floating (sa_p=Z, sa_n=Z). If yes (as shown in Figure 15A), the selection signals sa_p and sa_n in the upper domino circuit 71 will enable the positive output circuit 711a and the negative output circuit 711b, and the first rail-to-rail output pair AP and AN are used to update the positive multiplex output MXOP and the reverse multiplex output MXONN. That is, MXOP=AP and MXON=AN.

[0127] In Figures 15A and 15B, the operation of the lower domino circuit 73 is similar to that of the upper domino circuit 71, so its details will not be described further. When the dynamic module 7 operates during the evaluation period (Teva), the phase setting circuits 733a and 733b first determine whether the selection stage circuit 733c is related to the selection signals sb_p and sb_n in the lower domino circuit 73. If not (as shown in Figure 15A), the selection signals sb_p and sb_n in the lower domino circuit 73 are floating (sb_p=Z, sb_n=Z). If yes (as shown in Figure 15B), the selection signals sb_p and sb_n in the lower domino circuit 73 will enable the positive output circuit 731a and the negative output circuit 731b, and update the positive multiplexed output MXOP and the reverse multiplexed output MXON using the second rail-to-rail output pair (BP, BN). That is, MXOP=BP and MXON=BN.

[0128] The above explains the details of how the dynamic module 7 operates in response to different input signals. For ease of comparison, Figure 17 illustrates different combinations of input signals and their corresponding positive multiplex outputs MXOP and negative multiplex outputs MXON.

[0129] Please refer to Figure 17, which shows a summary table of the signal states of the dynamic module 7 during pre-charging (Tpre) and evaluation (Teva) according to the second embodiment of this disclosure. The operation of the dynamic module 7 during pre-charging (Tpre) can be summarized from the descriptions in Figures 14, 15A, 15B, and 16.

[0130] During the pre-charge period Tpre, the latch clock signal CLK_L is at a low logic level (CLK_L=0), and the reverse latch clock signal CLKB_L is at a high logic level (CLKB_L=1). Accordingly, the selection signal sa_p is at a high logic level (sa_p=1); the selection signal sa_n is at a low logic level (sa_n=0); the selection signal sb_p is at a high logic level (sb_p=1); and the selection signal sb_n is at a low logic level (sb_n=0). According to the selection signals sa_p, sa_n, sb_p, and sb_n, the forward prior decision bit Spo, the reverse prior decision bit SBpo, the first rail-to-rail output pair (AP, AN), and the second rail-to-rail output pair (BP, BN) do not affect the forward multiplexed output MXOP and the reverse multiplexed output MXON, and the storage circuit 75 maintains the forward multiplexed output MXOP and the reverse multiplexed output MXON.

[0131] During the evaluation, the selection signals sa_p, sa_n, sb_p, and sb_n change according to the forward prior decision bit Spo and the reverse prior decision bit SBpo. If the forward prior decision bit Spo is at a low logic level (Spo=0) and the reverse prior decision bit SBpo is at a high logic level (SBpo=1), the relationship between the selection signals sa_p and sa_n in the upper domino circuit 71 and the forward and reverse prior decision bits Spo and SBpo is: sa_p=0=Spo, sa_n=1=SBpo. Furthermore, the selection signals sb_p and sb_n in the lower domino circuit 73 are floating (sb_p=Z, sb_n=Z). Next, the forward multiplexed output MXOP and the reverse multiplexed output MXON (MXOP=AP, MXON=AN) are updated with the first rail-to-rail output pair (AP, AN). On the other hand, if the forward prior decision bit Spo is at a high logic level (Spo=1) and the reverse prior decision bit SBpo is at a low logic level (SBpo=0), the relationship between the selection signals sb_p and sb_n in the lower domino circuit 73 and the forward and reverse prior decision bits Spo and SBpo is sb_p=0=Spo, sb_n=1=SBpo. Furthermore, the selection signals sa_p and sa_n in the upper domino circuit 71 are floating (sa_p=Z, sa_n=Z). Next, the forward multiplexed output MXOP and the reverse multiplexed output MXON (MXOP=BP, MXON=BN) are updated with the second rail-to-rail output pair (BP, BN).

[0132] As described above, the speculative DFE 3 operates recursively, and the even-numbered speculative path 31 and the odd-numbered speculative path 33 influence each other. To illustrate how the dynamic module 7 is applied to the speculative DFE 3, the signal relationship when the speculative DFE 3 uses the dynamic module 7 is then illustrated with waveform diagrams.

[0133] Please refer to Figure 18, which is a waveform diagram of an example of processing a data stream using a speculative DFE according to the second embodiment of the present disclosure. Except for the selection signals sa_p, sa_n, sb_p, and sb_n, the waveforms of Figures 12 and 18 are similar. Therefore, the waveforms of the system clock signal CLK_sys, input data in(A)~in(F), even-path positive latching clock signal CLK_L(even), odd-path positive latching clock signal CLK_L(odd), rail-to-rail output pairs (APevn, ANevn), (BPevn, BNevn), (APodd, ANodd), (BPodd, BPevn), and even / odd path positive / negative multiplexed outputs (MXOPevn, MXONevn, MXOPodd, MXONodd) will not be described again here.

[0134] In the even-numbered prediction path 31, selection signals sa_p and sa_n are used to determine whether the rail-to-rail output pair (APevn, ANevn) of the first even-numbered path should be selected as the positive multiplexing output MXOPevn of the even-numbered path and the negative multiplexing output MXONevn of the even-numbered path; selection signals sb_p and sb_n are used to determine whether the rail-to-rail output pair (BPevn, BNevn) of the second even-numbered path should be selected as the positive multiplexing output MXOPevn of the even-numbered path and the negative multiplexing output MXONevn of the even-numbered path. Due to the propagation delay of the phase setting circuit, in even-numbered prediction path 31, the generation periods of selection signals sb_p and sb_n lag behind the generation periods of the rail-to-rail output pairs (APevn, ANevn) of the first even-numbered path and the rail-to-rail output pairs (BPevn, BNevn) of the second even-numbered path. Furthermore, the generation periods of the positive multiplexed output MXOPevn and the negative multiplexed output MXONevn of the even-numbered path lag behind the generation periods of selection signals sb_p and sb_n in even-numbered prediction path 31. The selection signals sa_p, sa_n, sb_p, and sb_n generated from the sampled data sa(A) in even-numbered prediction path 31 are labeled as ap(A), an(A), bp(A), and bn(A), respectively. The labeling of the selection signals sa_p, sa_n, sb_p, and sb_n generated from the sampled data sa(C) and sa(E) in even-numbered prediction path 31 is similar and will not be repeated.

[0135] In the odd prediction path 33, the selection signals sa_p and sa_n are used to determine whether to select the rail-to-rail output pair (APodd, ANodd) of the first odd path as the positive multiplexing output MXOPodd of the odd path and the negative multiplexing output MXONodd of the odd path; the selection signals sb_p and sb_n are used to determine whether to select the rail-to-rail output pair (BPodd, BNodd) of the second odd path as the positive multiplexing output MXOPodd of the odd path and the negative multiplexing output MXONodd of the odd path. Due to the propagation delay of the phase setting circuit, in the odd-numbered prediction path 33, the generation periods of the selection signals sb_p and sb_n lag behind the generation periods of the rail-to-rail output pairs (APodd, ANodd) of the first odd-numbered path and the rail-to-rail output pairs (BPodd, BNodd) of the second even-numbered path. Furthermore, the generation periods of the positive multiplexed output MXOPodd and the negative multiplexed output MXONodd of the odd-numbered path lag behind the generation periods of the selection signals sb_p and sb_n in the odd-numbered prediction path 33. The selection signals sa_p, sa_n, sb_p, and sb_n generated from the sampled data sa(B) in the odd-numbered prediction path 33 are labeled as ap(B), an(B), bp(B), and bn(B), respectively. The labeling method for the selection signals sa_p, sa_n, sb_p, and sb_n generated from the sampled data sa(D) in the odd-numbered prediction path 33 is similar and will not be repeated.

[0136] The lower part of Figure 18 illustrates the cause of the delay in the speculative first-order tap (tap1) that generates the input data in(B). Please also refer to Figures 5B, 6, and 18. The clock propagation delay Tclk2sa of the sensing amplifiers 333a and 333b is between time point t1 and time point t2, the set time TsuSA of the sensing amplifiers 333a and 333b is between time point t2 and time point t3, and the propagation delay Tdyn of the odd dynamic module 335 is between time point t3 and time point t5. Therefore, the processing and propagation delay of the odd speculative path 33 is between time point t1 and time point t4, and the operating boundary of the speculative first-order tap (tap1) is between time point t4 and time point t5.

[0137] Please refer to Figures 12 and 18 simultaneously. In Figure 12, the forward multiplexing output MXOP and the reverse multiplexing output MXON of the first embodiment are directly determined by the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN). On the other hand, in Figure 18, the forward multiplexing output MXOP and the reverse multiplexing output MXON of the second embodiment are indirectly determined by the selection signals sa_p, sa_n, sb_p, and sb_n determined by the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN). Therefore, the transmission delay Tdyn of dynamic module 6 is shorter than the transmission delay Tdyn of dynamic module 7.

[0138] In other words, the forward multiplexed output MXOP and the reverse multiplexed output MXON in the first embodiment and the second embodiment are generated in a single-stage and two-stage manner, respectively. That is, unlike the first embodiment which directly generates the forward multiplexed output MXOP and the reverse multiplexed output MXON based on single-track outputs (AP, AN) and (BP, BN), the second embodiment generates the forward multiplexed output MXOP and the reverse multiplexed output MXON only after generating the selection signals (sa_p, sa_n, sb_p, sb_n). Third Embodiment

[0139] Figures 19A and 19B are block diagrams and circuit designs of the dynamic module 8 according to the third embodiment of this disclosure, respectively. Figure 20 illustrates the operation of the dynamic module 8 during pre-charging (Tpre). Figures 21A, 21B, and 22 illustrate the operation of the dynamic module 8 during evaluation (Teva). Figure 23 lists different combinations of signal states of the dynamic module 8.

[0140] Please refer to Figure 19A, which is a block diagram of a dynamic module according to a third embodiment of the present disclosure. The dynamic module 8 includes an upper domino circuit 81, a lower domino circuit 83, and a storage circuit 85. The upper domino circuit 81 also includes a dynamic latch 813 and a multiplexer 811, and the lower domino circuit 83 also includes a dynamic latch 833 and a multiplexer 831.

[0141] Please also refer to Figures 13A and 19A. The dynamic module in Figure 13A has similar components and wiring relationships to the dynamic module in Figure 19A. The difference between dynamic module 7 and dynamic module 8 lies in the position and arrangement of multiplexers 711, 811, 731, and 831. In dynamic module 7, the components within multiplexers 711 and 731 are arranged vertically. On the other hand, in dynamic module 8, the components within multiplexers 811 and 831 are arranged horizontally.

[0142] Please refer to Figure 19B, which is a schematic diagram of the circuit design of the dynamic module according to the third embodiment of this disclosure. Since the dynamic latches 813 and 833 of the third embodiment are similar to those of the dynamic latches of the second embodiment, the components and connections within the dynamic latches 813 and 833 will not be described here; only the components and connections of the multiplexers 811 and 831 will be described. Basically, the positive output circuits 811a and 831a and the negative output circuits 811b and 831b are implemented using transmission gates.

[0143] In the multiplexer 811, the positive output circuit 811a includes a PMOS transistor upoP and an NMOS transistor upoN, and the negative output circuit 811b includes a PMOS transistor unoP and an NMOS transistor unoN. The gates of the PMOS transistors upoP and unoN are electrically connected to the selection terminal Nap. The gates of the NMOS transistors upoN and unoN are electrically connected to the selection terminal Nan. Next, the signal relationships between the components of the multiplexer 811 will be explained.

[0144] In the positive output circuit 811, the source of the PMOS transistor upoP and the drain of the NMOS transistor upoN jointly receive the first positive single-rail output AP, and the drain of the PMOS transistor upoP and the source of the NMOS transistor are electrically connected to the positive multiplexing output terminal Nmxop. In the negative output circuit 811b, the source of the PMOS transistor unoP and the drain of the NMOS transistor unoN jointly receive the first negative single-rail output AN, and the drain of the PMOS transistor unoP and the source of the NMOS transistor unoN are electrically connected to the reverse multiplexing output terminal Nmxon.

[0145] In the multiplexer 831, the positive output circuit 831a includes a PMOS transistor lpoP and an NMOS transistor lpoN, and the negative output circuit 831b includes a PMOS transistor lnoP and an NMOS transistor lnoN. The gates of the PMOS transistors lpoP and lnoP are electrically connected to the selection terminal Nbp. The gates of the NMOS transistors lpoN and lnoN are electrically connected to the selection terminal Nbn. Next, the signal relationships of the multiplexer 811 will be explained.

[0146] In the positive output circuit 831a, the source of PMOS transistor lpoP and the drain of NMOS transistor lpoN jointly receive the second positive single-rail output BP, and the drain of PMOS transistor lpoP and the source of NMOS transistor lpoN are electrically connected to the positive multiplexing output terminal Nmxop. In the negative output circuit 831b, the source of PMOS transistor lnoP and the drain of NMOS transistor lnoN jointly receive the second negative single-rail output BN, and the drain of PMOS transistor lnoP and the source of NMOS transistor lnoN are electrically connected to the reverse multiplexing output terminal Nmxon.

[0147] The storage circuit 85 includes cross-coupled inverters sinv1 and sinv2. The input and output terminals of inverter sinv1 are electrically connected to the positive multiplexing output terminal Nmxop and the negative multiplexing output terminal Nmxon, respectively. The input and output terminals of inverter sinv2 are electrically connected to the negative multiplexing output terminal Nmxon and the positive multiplexing output terminal Nmxop, respectively.

[0148] Please refer to Figure 20, which is a schematic diagram of how the dynamic module Tpre operates during precharging according to the third embodiment of the present disclosure. Since the phase setting circuits 813a, 813b and the selection stage circuit 813c of the third embodiment are similar to those of the second embodiment, the way in which the selection signals sa_p=1, sa_n=0, sb_p=1, and sb_n=0 are generated is also similar to that in Figure 14, and will not be described here again.

[0149] Next, the operation of the multiplexer 811 will be explained. Since the selection signal sa_p is equal to the supply voltage Vcc (sa_p=1), the PMOS transistor upoP in the positive output circuit 811a is turned off, and the PMOS transistor unoP in the negative output circuit 811b is turned off. Since the selection signal sa_n is equal to the ground voltage Gnd (sa_n=0), the NMOS transistor upoN in the positive output circuit 811a is turned off, and the NMOS transistor unoN in the negative output circuit 811b is turned off. During the pre-charge period Tpre, since the PMOS transistors upoP and unoP and the NMOS transistors upoN and unoN in the multiplexer 811 are all turned off, the multiplexer 811 is disabled, so the upper domino circuit 81 does not affect the positive multiplex output MXOP and the reverse multiplex output MXON.

[0150] Similarly, because the selection signal sb_p is equal to the supply voltage Vcc (sb_p=1) and the selection signal sb_n is equal to the ground voltage Gnd (sb_n=0), the PMOS transistors lpoP and lnoP and the NMOS transistors lpoN and lnoN in the multiplexer 831 are all off. Therefore, according to the third embodiment of this disclosure, the multiplexer 831 is disabled during the pre-charge period Tpre, so the lower domino circuit 83 does not affect the forward multiplex output MXOP and the reverse multiplex output MXON.

[0151] During the precharge period Tpre, the storage circuit 65 maintains the positive multiplexer output MXOP and the reverse multiplexer output MXON in the same state as stored in Teva during the evaluation period. In Figure 20, the dotted mesh-based multiplexers 811 and 831 represent multiplexers 811 and 831 being disabled during the precharge period Tpre.

[0152] Figures 21A and 21B illustrate the signal and component states of the dynamic module 8 during Teva operation in the evaluation period. Please refer to Figure 21A, which is a schematic diagram of the dynamic module according to the third embodiment of this disclosure operating under Teva during the evaluation period when the positive prior decision bit Spo is at a low logic level (Spo=0) and the negative prior decision bit SBpo is at a high logic level (SBpo=1). Please refer to Figure 21B, which is a schematic diagram of the dynamic module according to the third embodiment of this disclosure operating under Teva during the evaluation period when the positive prior decision bit Spo is at a high logic level (Spo=1) and the negative prior decision bit SBpo is at a low logic level (SBpo=0).

[0153] Please refer to Figure 22, which is a flowchart of the upper domino circuit according to the third embodiment of the present disclosure, operating during the evaluation of Teva. Please also refer to Figures 21A, 21B, and 22.

[0154] As previously described, the components and their connection relationships of the dynamic locking device 813 are similar to those of the dynamic locking device 713 in the second embodiment. Therefore, steps S81a, S81b, S83a, and S83b in Figure 22 are similar to steps S71a, S71b, S73a, and S73b in Figure 16 and will not be repeated here. Only steps S85 and S87 will be described here.

[0155] When the selection signals sa_p and sa_n are floating (sa_p=Z, sa_n=Z), the multiplexer 811 is disabled, and the upper domino circuit 71 does not affect the forward multiplexing output MXOP and the reverse multiplexing output MXON (step S87). In Figure 21B, the upper domino circuit 83 is drawn with a dotted grid to indicate that when the forward prior decision bit Spo is at a high logic level (Spo=1) and the reverse prior decision bit SBpo is at a low logic level (SBpo=0), the upper domino circuit 83 does not affect the forward multiplexing output MXOP and the reverse multiplexing output MXON.

[0156] When the selection signal sa_p is the ground voltage Gnd (sa_p=0) and the selection signal sa_n is the supply voltage Vcc (sa_n=1), the multiplexer 811 generates a positive multiplex output MXOP and a reverse multiplex output MXON based on the first positive single-rail output AP and the first negative single-rail output AN. That is, MXOP=AP and MXON=AN (step S85).

[0157] As shown in Figure 21A, the low logic level selection signal sa_n (sa_n=0) turns on the PMOS transistor upoP in the positive output circuit 811a and the PMOS transistor unoP in the negative output circuit 811b; and the high logic level selection signal sa_n (sa_n=1) turns on the NMOS transistor upoN in the positive output circuit 811a and the NMOS transistor unoN in the negative output circuit 811b.

[0158] Next, the positive output circuit 811a turns on the first positive single-rail output AP to the positive multiplexing output terminal Nmxop, as the positive multiplexing output MXOP (step S85a). On the other hand, the negative output circuit 811b turns on the first negative single-rail output AP to the reverse multiplexing output terminal Nmxon, as the reverse multiplexing output MXON (step S85b).

[0159] According to Figure 22, when the dynamic module 8 operates during the evaluation period (Teva), the phase setting circuits 813a and 813b, the selection stage circuit 813c, and the multiplexer 811 in the upper domino circuit 81 operate sequentially. The phase setting circuits 813a and 813b first determine whether the selection stage circuit 813c is related to the selection signals sa_p and sa_n in the upper domino circuit 81. If not (see Figure 21B), the selection signals sa_p and sa_n are floating (sa_p=Z, sa_n=Z), and the multiplexer 811 is disabled. If yes (see Figure 21A), the selection signals sa_p and sa_n will enable the positive output circuit 811a and the negative output circuit 811b, and the first rail-to-rail output pair AP and AN are used to update the positive multiplexer output MXOP and the reverse multiplexer output MXON. That is, MXOP=AP and MXON=AN.

[0160] In Figures 21A and 21B, the operation of the lower domino circuit 83 and the upper domino circuit 81 is symmetrical, so the details will not be described further. When the dynamic module 8 operates during the evaluation period, the phase setting circuits 833a and 833b, the selection stage circuit 833c, and the multiplexer 711 in the lower domino circuit 83 operate sequentially. The phase setting circuits 833a and 833b first determine whether the selection stage circuit 833c is related to the selection signals sb_p and sb_n in the lower domino circuit 83. If not (as shown in Figure 21A), the selection signals sb_p and sb_n are floating (sb_p=Z, sb_n=Z), and the multiplexer 831 is disabled. If so (as shown in Figure 21B), select signals sb_p and sb_n to enable the positive output circuit 831a and the negative output circuit 831b, and use the second rail-to-rail output pair (BP, BN) to update the multiplexed outputs: the positive multiplexed output MXOP and the negative multiplexed output MXON. That is, MXOP = BP and MXON = BN.

[0161] Please refer to Figure 23, which is a summary table of the signal states of the dynamic module according to the third embodiment of the present disclosure during the pre-charge period Tpre and the evaluation period Teva. The operation of the dynamic module 8 during the pre-charge period Tpre can be derived from Figure 20. The operation of the dynamic module 8 during the evaluation period Teva can be derived from Figures 21A, 21B, and 22.

[0162] During the pre-charge period Tpre, because the forward latch-up clock signal CLK_L is at a low logic level (CLK_L=0) and the reverse latch-up clock signal CLKB_L is at a high logic level (CLKB_L=1), the selection signal sa_p is equal to the supply voltage Vcc (sa_p=1); the selection signal sa_n is equal to the ground voltage Gnd (sa_n=0); the selection signal sb_p is equal to the supply voltage Vcc (sb_p=1); and the selection signal sb_n is equal to the ground voltage Gnd (sb_n=0). Based on the selection signals sa_p, sa_n, sb_p, and sb_n, multiplexers 811 and 831 are disabled, and the forward multiplex output MXOP and the reverse multiplex output MXON are not affected by the forward prior decision bit Spo and the reverse prior decision bit SBpo. Consequently, the storage circuit 85 maintains the forward multiplex output MXOP and the reverse multiplex output MXON.

[0163] During the evaluation period, the selection signals sa_p, sa_n, sb_p, and sb_n change according to the forward prior decision bit Spo and the reverse prior decision bit SBpo. During the evaluation period, if the forward prior decision bit Spo is at a low logic level (Spo=0) and the reverse prior decision bit SBpo is at a high logic level (SBpo=1), the relationship between the selection signals sa_p and sa_n in the upper domino circuit 81 and the forward and reverse prior decision bits Spo and SBpo is as follows: sa_p=0=Spo, sa_n=1=SBpo. Furthermore, the selection signals sb_p and sb_n in the lower domino circuit 83 are floating (sb_p=Z, sb_n=Z). Next, the forward multiplexed output MXOP and the reverse multiplexed output MXON are updated with the first rail-to-rail output pair (AP, AN). On the other hand, during the evaluation period, if the forward prior decision bit Spo is at a high logic level (Spo=1) and the reverse prior decision bit SBpo is at a low logic level (SBpo=0), the selection signals sb_p and sb_n in the lower domino circuit are related to the forward prior decision bit Spo and the reverse prior decision bit SBpo as follows: sb_p=0=Spo, sb_n=1=SBpo. Furthermore, the selection signals sa_p and sa_n in the upper domino circuit 81 are floating (sa_p=Z, sa_n=Z). Next, the forward multiplexed output MXOP and the reverse multiplexed output MXON are updated using the second rail-to-rail output pair (BP, BN).

[0164] The aforementioned speculative DFE embodiment can alleviate the time requirement of the speculative first-order tap (tap1), and by combining the latch in the dynamic module with the dynamic module, it can further save more time margins. This disclosure can also be implemented with a four-part rate.

[0165] Please refer to Figure 24, which is a schematic diagram of a speculative DFE with a four-part rate structure. The speculative DFE 90 includes four equally divided paths, namely, speculative paths 91, 92, 93, and 94. Speculative paths 91, 92, 93, and 94 receive input data Din, and respectively generate path decisions Dout_p1, Dout_p2, Dout_p3, and Dout_p4. Path decisions Dout_p1, Dout_p2, Dout_p3, and Dout_p4 together form the DFE output Dout. Since the operation of the speculative DFE 90 can be derived based on the aforementioned half-rate speculative architecture embodiment, the speculative DFE 90 will not be described in detail here.

[0166] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0010] Figure 1 is a schematic diagram of the transmission path. Figure 2 is a schematic diagram of the DFE structure. Figure 3 is a schematic diagram of a speculative DFE. Figure 4 is a waveform diagram during the operation period when even-numbered and odd-numbered speculative paths interleave. Figure 5A is a schematic diagram of an example of a speculative DFE. Figure 5B is a schematic diagram of another example of a speculative DFE. Figure 6 is a schematic diagram comparing the delay causes in the speculative DFEs of Figures 5A and 5B. Figure 7 is a general block diagram of a dynamic module according to the present disclosure. Figure 8A is a block diagram of a dynamic module according to a first embodiment of the present disclosure. Figure 8B is a schematic diagram of the circuit design of a dynamic module according to a first embodiment of the present disclosure. Figure 9 is a schematic diagram illustrating how the dynamic module according to the first embodiment of the present disclosure operates during pre-charging (Tpre). Figure 10A is a schematic diagram of the Teva operation of the dynamic module according to the first embodiment of this disclosure during evaluation when the positive prior decision bit Spo is at a low logic level (Spo=0) and the negative prior decision bit SBpo is at a high logic level (SBpo=1). Figure 10B is a schematic diagram of the Teva operation of the dynamic module according to the first embodiment of this disclosure during evaluation when the positive prior decision bit Spo is at a high logic level (Spo=1) and the negative prior decision bit SBpo is at a low logic level (SBpo=0). Figure 11 is a summary table showing the signal states of the dynamic module according to the first embodiment of this disclosure during the precharge period Tpre and the evaluation period Teva. Figure 12 is a waveform diagram illustrating how a speculative DFE processes a data stream according to the first embodiment of this disclosure. Figure 13A is a block diagram of the dynamic module according to the second embodiment of this disclosure. Figure 13B is a schematic diagram of the circuit design of the dynamic module according to the second embodiment of the present disclosure. Figure 14 is a schematic diagram of the operation of the dynamic module Tpre during pre-charging according to the second embodiment of the present disclosure. Figure 15A is a schematic diagram of the operation of the dynamic module Teva during evaluation when the positive prior decision bit Spo is at a low logic level (Spo=0) and the negative prior decision bit SBpo is at a high logic level (SBpo=1). Figure 15B is a schematic diagram of the operation of the dynamic module Teva during evaluation when the positive prior decision bit Spo is at a high logic level (Spo=1) and the negative prior decision bit SBpo is at a low logic level (SBpo=0). Figure 16 is a flowchart of the operation of the upper domino circuit Teva during evaluation according to the second embodiment of the present disclosure.Figure 17 is a summary table of the signal states of the dynamic module according to the second embodiment of this disclosure during the precharge period (Tpre) and the evaluation period (Teva). Figure 18 is a waveform diagram of an example of data stream processing using a speculative DFE according to the second embodiment of this disclosure. Figure 19A is a block diagram of the dynamic module according to the third embodiment of this disclosure. Figure 19B is a schematic diagram of the circuit design of the dynamic module according to the third embodiment of this disclosure. Figure 20 is a schematic diagram of how the dynamic module according to the third embodiment of this disclosure operates during the precharge period (Tpre). Figure 21A is a schematic diagram of the operation of the dynamic module according to the third embodiment of this disclosure during the evaluation period (Teva) when the positive prior decision bit Spo is low (Spo=0) and the reverse prior decision bit SBpo is high (SBpo=1). Figure 21B is a schematic diagram of the operation of the dynamic module according to the third embodiment of this disclosure during the evaluation period of Teva when the positive prior decision bit Spo is at a high logic level (Spo=1) and the negative prior decision bit SBpo is at a low logic level (SBpo=0). Figure 22 is a flowchart of the operation of the upper domino circuit according to the third embodiment of this disclosure during the evaluation period of Teva. Figure 23 is a summary table of the signal states of the dynamic module according to the third embodiment of this disclosure during the precharge period Tpre and the evaluation period Teva. Figure 24 is a schematic diagram of a speculative DFE with a four-part rate structure.

Claims

1. A dynamic module comprising: a first domino circuit that generates a first multiplexed output, comprising: a first multiplexer that receives two of a first single-rail output, a second single-rail output, a third single-rail output, and a fourth single-rail output; at least one first phase setting circuit that receives a first clock signal; and a first decision selection stage circuit electrically connected to the first multiplexer and the at least one first phase setting circuit, which receives a first prior decision bit and a second prior decision bit, wherein the first prior decision bit and the second prior decision bit are complementary to each other; and a second domino circuit electrically connected to the first domino circuit that generates a second multiplexed output, the second domino circuit comprising: a second multiplexer that receives the other two of the first single-rail output, the second single-rail output, the third single-rail output, and the fourth single-rail output; At least one second phase setting circuit receives a second clock signal, wherein the first clock signal and the second clock signal are complementary; and a second decision selection stage circuit is electrically connected to the second multiplexer and the at least one second phase setting circuit, which receives the first prior decision bit and the second prior decision bit, wherein during an evaluation period, the first multiplex output and the second multiplex output are selectively updated with the first single-rail output, the second single-rail output, the third single-rail output and the fourth single-rail output, and during a pre-charge period, the first multiplex output and the second multiplex output remain unchanged.

2. The dynamic module as described in request item 1, wherein, During the evaluation, the dynamic module receives the first prior decision bit and the second prior decision bit from another dynamic module, and during the pre-charge period, the dynamic module provides a third prior decision bit and a fourth prior decision bit to the other dynamic module, wherein the third prior decision bit is generated based on the first multiplexing output and the fourth prior decision bit is generated based on the second multiplexing output.

3. The dynamic module as described in request item 1, wherein, The first and second single-rail outputs are provided by a first sensing amplifier, and the third and fourth single-rail outputs are provided by a second sensing amplifier. During the evaluation period, the first and second single-rail outputs together form a first rail-to-rail output pair, and the third and fourth single-rail outputs together form a second rail-to-rail output pair. During the pre-charge period, the first single-rail output is equal to the second single-rail output, and the third single-rail output is equal to the fourth single-rail output.

4. The dynamic module as described in claim 3, wherein, The first multiplexer receives the first single-track output from the first sensing amplifier and the third single-track output from the second sensing amplifier; and the second multiplexer receives the second single-track output from the first sensing amplifier and the fourth single-track output from the second sensing amplifier.

5. The dynamic module as described in claim 3, wherein, The first multiplexer receives the first single-rail output and the second single-rail output from the first sensing amplifier, and the second multiplexer receives the third single-rail output and the fourth single-rail output from the second sensing amplifier.

6. The dynamic module as described in claim 1, further comprising: a storage circuit electrically connected to the first domino circuit via a first multiplexing output terminal, and electrically connected to the second domino circuit via a second multiplexing output terminal, wherein, The first multiplexed output is generated at the first multiplexed output terminal; the second multiplexed output is generated at the second multiplexed output terminal; and the storage circuit maintains the first multiplexed output and the second multiplexed output during the precharge period.

7. The dynamic module as described in claim 6, wherein, The at least one first phase setting circuit is electrically connected to the first multiplexing output terminal and is controlled by the first clock signal; and the at least one second phase setting circuit is electrically connected to the second multiplexing output terminal and is controlled by the second clock signal.

8. The dynamic module as described in claim 7, wherein, During the pre-charge period, the first decision selection stage circuitry is disconnected from the first multiplex output terminal, and the second decision selection stage circuitry is disconnected from the second multiplex output terminal.

9. The dynamic module as described in claim 3, wherein, During the evaluation, the first decision selection stage circuitry is selectively electrically connected to the first multiplexing output terminal, and the second decision selection stage circuitry is selectively electrically connected to the second multiplexing output terminal.

10. The dynamic module as described in claim 6, wherein, The first multiplexer includes a first positive output circuit and a first negative output circuit, and the second multiplexer includes a second positive output circuit and a second negative output circuit. During the evaluation, one of the first positive output circuit and the second positive output circuit generates the first multiplexed output, and one of the first negative output circuit and the second negative output circuit generates the second multiplexed output.

11. The dynamic module as described in claim 10, wherein, When the first prior decision bit is a first logic level and the second prior decision bit is a second logic level, the first positive output circuit generates the first multiplexed output and the first negative output circuit generates the second multiplexed output; and when the first prior decision bit is the second logic level and the second prior decision bit is the first logic level, the second positive output circuit generates the first multiplexed output and the second negative output circuit generates the second multiplexed output.

12. The dynamic module as described in claim 10, wherein the at least one first phase setting circuit comprises: a first first phase setting circuit electrically connected to the first decision selection stage circuit, the first positive output circuit, and the first negative output circuit, which receives the first clock signal and generates a first first selection signal; and a second first phase setting circuit electrically connected to the first decision selection stage circuit, the first positive output circuit, and the first negative output circuit, which receives the second clock signal and generates a second first selection signal.

13. The dynamic module as described in claim 12, wherein the at least one second phase setting circuit comprises: a first second phase setting circuit electrically connected to the second decision selection stage circuit, the second positive output circuit, and the second negative output circuit, which receives the first clock signal and generates a first second selection signal; and a second second phase setting circuit electrically connected to the second decision selection stage circuit, the second positive output circuit, and the second negative output circuit, which receives the second clock signal and generates a second second selection signal.

14. The dynamic module as claimed in claim 13, wherein during the pre-charge period, the first positive output circuit and the second positive output circuit cease generating the first multiplexed output, and the first negative output circuit and the second negative output circuit cease generating the second multiplexed output.

15. The dynamic module as described in claim 13, wherein during the evaluation period, if the first prior decision bit is the first logic level and the second prior decision bit is the second logic level, the first first selection signal is equal to the first prior decision bit and the second first selection signal is equal to the second prior decision bit; and if the first prior decision bit is the second logic level and the second prior decision bit is the first logic level, the first second selection signal is equal to the second prior decision bit and the second second selection signal is equal to the first prior decision bit.

16. The dynamic module as described in claim 1, wherein during the evaluation period, if the first prior decision bit is the first logic level and the second prior decision bit is the second logic level, the first domino circuit updates the first multiplexed output with the first single-track output and updates the second multiplexed output with the second single-track output, and the second domino circuit stops generating the first multiplexed output and the second multiplexed output.

17. The dynamic module as described in claim 1, wherein during the evaluation period, when the first prior decision bit is the second logic level and the second prior decision bit is the first logic level, the first domino circuit stops generating the first multiplexed output and the second multiplexed output, and the second domino circuit updates the first multiplexed output with the third single-track output and updates the second multiplexed output with the fourth single-track output.

18. The dynamic module as described in claim 1, wherein the evaluation period and the pre-charge period are determined by the first clock signal and the second clock signal.

19. A decision feedback equalizer, comprising: a first speculation path that provides a first prior decision bit and a second prior decision bit during an evaluation, wherein the first prior decision bit and the second prior decision bit are complementary to each other; and a second speculation path electrically connected to the first speculation path, comprising: a first sense amplifier that outputs a first rail-to-rail output pair including a first single-rail output and a second single-rail output; a second sense amplifier that outputs a second rail-to-rail output pair including a third single-rail output and a fourth single-rail output; and a dynamic module electrically connected to the first sense amplifier and the second sense amplifier, comprising: a first domino circuit that generates a first multiplexed output, the first domino circuit comprising: a first multiplexer that receives two of the first single-rail output, a second single-rail output, a third single-rail output, and a fourth single-rail output; At least one first phase setting circuit receives a first clock signal; and a first decision selection stage circuit electrically connected to the first multiplexer and the at least one first phase setting circuit receives the first prior decision bit and the second prior decision bit; and a second domino circuit generates a second multiplexed output, the second domino circuit comprising: a second multiplexer that receives two of the first single-rail output, the second single-rail output, the third single-rail output, and the fourth single-rail output; At least one second phase setting circuit receives a second clock signal, wherein the first clock signal and the second clock signal are complementary to each other; and a second decision selection stage circuit is electrically connected to the second multiplexer and the at least one second phase setting circuit, which receives the first prior decision bit and the second prior decision bit, wherein during the evaluation period, the first multiplex output and the second multiplex output are selectively updated with one of the first rail-to-rail output pair and the second rail-to-rail output pair, and during the precharge period, the first multiplex output and the second multiplex output remain unchanged.

20. The decision feedback equalizer as claimed in claim 19, wherein the dynamic module further includes: a storage circuit electrically connected to the first domino circuit and the second domino circuit, which maintains the first multiplexed output and the second multiplexed output during the pre-charge period.

21. The decision feedback equalizer as described in claim 20, wherein the second speculative path further comprises: a first inverter electrically connected to the dynamic module, the storage circuit, and the first speculative path; and a second inverter electrically connected to the dynamic module, the storage circuit, and the first speculative path, wherein, During the precharge period, the first inverter converts the first multiplexed output into a third prior decision bit, and the second inverter converts the second multiplexed output into a fourth prior decision bit, wherein the first speculative path receives the third prior decision bit and the fourth prior decision bit.

22. The decision feedback equalizer as described in claim 19, wherein the evaluation period and the precharge period are determined by the first clock signal and the second clock signal.

Images