Semiconductor device and method

Abstract

An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The semiconductor device also includes a plurality of gate structures on the plurality of isolation regions. The semiconductor device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The semiconductor device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor element and method for manufacturing a resonator using a fin structure. [Previous Technology]

[0002] Semiconductor components are used in various electronic devices, such as personal computers, mobile phones, digital cameras and other electronic devices. The manufacturing of semiconductor components usually involves depositing an insulating or dielectric layer, a conductive layer and a semiconductor layer material on a semiconductor substrate in sequence, and using a photolithography process to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry is constantly improving the integration density of various components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the size of the smallest feature components (which allows more components to be integrated into a given area), which enables more components to be integrated into a given area. [Summary of the Invention]

[0004] According to an embodiment of the present invention, a semiconductor device including a fin structure comprises: a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures; a plurality of isolation regions located on the substrate and between the plurality of fin structures; a plurality of gate structures located on the plurality of isolation regions; a plurality of epitaxial structures located on one of the plurality of first fin structures; and a plurality of contact structures located on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are components of one or more resonators.

[0005] According to an embodiment of the present invention, a semiconductor device including a fin structure includes: a substrate having a first surface and a second surface; an isolation structure located above the first surface of the substrate; a plurality of gate structures located above the isolation structure; a resonator including a plurality of first fin structures, at least one epitaxial structure and a contact structure, wherein the plurality of first fin structures are located on the first surface of the substrate, the at least one epitaxial structure is located on the first fin structure, and the contact structure is located on the at least one epitaxial structure; and at least one second fin structure is located on the first surface of the substrate, and the at least one second fin structure is located between two of the plurality of first fin structures, wherein the at least one second fin structure does not contain an epitaxial structure.

[0006] According to an embodiment of the present invention, a method for manufacturing a resonator using fin structures includes: forming a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures; forming a plurality of isolation regions on the substrate and located between the plurality of fin structures; forming a plurality of gate structures on the plurality of isolation regions; growing a plurality of epitaxial structures on the plurality of first fin structures, the plurality of second fin structures having no epitaxial structures; and forming a plurality of contact structures on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are components of one or more resonators.

Implementation Method

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific instances of components and configurations will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first member on or above a second member may include embodiments in which the first and second members are in direct contact, and may also include embodiments in which an additional member may be formed between the first and second members such that the first and second members are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "below," "down," "above," "upper," and the like are used herein to describe the relationship between one element or component and another element(s), as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and thus the spatial relative descriptive terms used herein may be interpreted accordingly.

[0014] Before detailing the illustrated embodiments, certain advantageous features and characteristics of the embodiments disclosed herein will be summarized. In general, this disclosure discloses an element for fabricating a resonator using a fin structure and a method thereof, which can be used as a frequency source in a circuit. In some embodiments, the frequency generated by the element is determined by the fin material and the fin spacing. This element design allows for better integration of this structure into complementary metal-oxide-semiconductor (CMOS) fabrication processes. The disclosed embodiments allow the element to generate more than one frequency in a single structure, while also simplifying the fabrication process and eliminating the need for special packaging.

[0015] The embodiments discussed herein are intended to provide examples enabling the manufacture or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] FIG1 illustrates an example of a FinFET according to some embodiments in a three-dimensional view. The FinFET includes fins 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are located in the substrate 50, and the fins 52 protrude from above and between adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate containing the isolation regions. Furthermore, although the fins 52 are described as being of the same single, continuous material as the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this case, the fins 52 refer to the portion extending between adjacent isolation regions 56.

[0017] Gate dielectric layer 92 runs along the sidewalls and is located above the top surface of fin 52, and gate electrode 94 is located above gate dielectric layer 92. Source / drain regions 82 are located on opposite sides of fin 52 relative to gate dielectric layer 92 and gate electrode 94. FIG1 further illustrates reference cross sections used in subsequent figures. Cross section AA is along the longitudinal axis of gate electrode 94 and in a direction, for example, perpendicular to the current direction between source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and runs along the longitudinal axis of fin 52 and in the current direction, for example, between source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. These reference cross sections are referenced in subsequent figures for clarity.

[0018] Some embodiments discussed herein are discussed in related literature on FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments focus on patterns used in planar devices, such as planar FETs, nanostructures (e.g., nanosheets, nanowires, gate-around transistors, etc.) field-effect transistors (NSFETs), etc.

[0019] Figures 2 to 17 are cross-sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments. Figures 2, 3A, 3B, 4, 5, 6, and 7 show the reference cross-section AA shown in Figure 1, except that multiple fins / FinFETs are not depicted. Figures 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, and 16A are drawn along the reference cross-section AA shown in Figure 1, and Figures 8B, 9B, 10B, 11B, 12B, 13B, 14B, 14C, 15B, and 16B are drawn along a similar cross-section BB shown in Figure 1, except that multiple fins / FinFETs are not depicted. Figures 10C, 10D, 10E, and 17 are drawn along the reference cross-section CC shown in Figure 1, except that multiple fins / FinFETs are not depicted.

[0020] In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is located on the substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0021] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type FinFET). The p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type FinFET). The n-type region 50N can be physically separated from the p-type region 50P (as shown by partition 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P.

[0022] In Figures 3A and 3B, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any suitable etching process, such as reactive ion etching (RIE), neutral particle beam etching (NBE), or a combination thereof. Etching can be anisotropic.

[0023] The fins described above can be patterned by any suitable method. For example, the fins 52 can be patterned using one or more lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine lithography and self-alignment processes, allowing the pitch of the formed pattern to be smaller than that achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins are patterned using the remaining spacers. In some embodiments, a photomask (or other layer) may be retained on the fins 52.

[0024] As shown in FIG. 3B, the substrate 50 has a component region 50N / P (e.g., the region containing the n-type region and the p-type region 50P) and a resonator component region 50R. The component region 50N / P can be a region for forming logic elements, memory elements, input / output elements, etc. The resonator component region 50R can be used to form resonator elements. The component regions 50N / P can be physically separated from the resonator component region 50R (as shown by partition 53), and any number of component features (e.g., other active elements, doped regions, isolation structures, etc.) can be disposed between these regions. Although the resonator component region 50R is not shown in each step, the component regions 50N / P and the resonator component region 50R are formed simultaneously by the same process.

[0025] As illustrated in FIG3B, some fins can be removed in the resonator element region 50R by a fin cutting process. In some embodiments, the fin cutting process includes masking the fins 52 to be retained while etching the exposed fins 52. In some embodiments, photoresist and / or other photomasks (not shown) can be used to achieve the masking function. For example, photoresist can be formed over the fins 52 and patterned to expose the fins to be removed. An etching process can then be performed to remove the exposed fins 52. Etching can be any suitable etching process, such as RIE, NBE, or a combination thereof. Etching can be anisotropic or isotropic. The photoresist can be removed after etching.

[0026] In FIG. 4, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide, such as silicon oxide, nitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of a chemical vapor deposition material in a remote plasma system followed by subsequent curing to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any suitable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed to cover the fins 52 with excess insulating material 54. Although the insulating material 54 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and the fins 52. Then, a filler material can be formed on top of the liner, as discussed above.

[0027] In FIG. 5, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof may be used. The planarization process exposes the fin 52 such that the top surface of the fin 52 and the insulating material 54 are coplanar after the planarization process. In embodiments where a photomask is retained on the fin 52, the planarization process may expose or remove the photomask such that the top surface of the photomask or the fin 52 is coplanar with the insulating material 54 after the planarization process.

[0028] In Figure 6, the insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in the n-type region 50N and the p-type region 50P protrude between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., a dishing), or a combination thereof, as shown. The top surface of the STI region 56 may be formed as flat, convex, and / or concave by appropriate etching. The STI region 56 can be recessed using appropriate etching processes, such as processes selective for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than etching the material of the fins 52). For example, chemical oxides may be removed using, for example, dilute hydrofluoric acid (dHF).

[0029] The process described with respect to Figures 2 through 6 is merely one example of how the fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer to form the fin. Furthermore, in some embodiments, heteroepitaxial structures can be used to form the fin 52. For example, the fin 52 in Figure 5 can be recessed, and a material different from the fin 52 can be epitaxially grown at the location of the recessed fin 52. In such an embodiment, the fin 52 includes the recessed material and a material epitaxially grown above the recessed material. In yet another embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trench using a material different from that of the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fins 52. In some embodiments, when epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be in-situ doped during growth. Although in-situ doping and implantation doping can be performed together, this avoids the need for previous and subsequent implantation steps.

[0030] Furthermore, epitaxially growing different materials in the n-type region 50N (e.g., an NMOS region) and the p-type region 50P (e.g., a PMOS region) can bring some advantages. In various embodiments, the upper portion of the fin 52 may comprise silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or similar materials. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide (InAs), aluminum arsenide (AlAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium antimonide (GaSb), aluminum antimonide (AlSb), aluminum phosphide (AlP), gallium phosphide (GaP), and similar materials.

[0031] Furthermore, in FIG. 6, suitable wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N and an N-well may be formed in the p-type region 50P. In some embodiments, either a P-well or an N-well may be formed in both the n-type region 50N and the p-type region 50P.

[0032] In embodiments with different well types, photoresist and / or other photomasks (not shown) can be used to perform different implantation steps on the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the STI region 56 in the fin 52 and the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using spin coating technology, and the photoresist can be patterned using appropriate lithography techniques. After the photoresist is patterned, n-type impurities are implanted in the p-type region 50P, and the photoresist can act as a photomask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be substances such as phosphorus, arsenic, and antimony, and the concentration of n-type impurities in the implanted region is equal to or less than 10¹⁸ cm⁻³, for example, between about 10¹⁶ cm⁻³ and about 10¹⁸ cm⁻³. After implantation, the photoresist is removed, for example, by an appropriate ashing process.

[0033] After implantation in the p-type region 50P, a photoresist is formed over the fins 52 and STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating technology and can be patterned using appropriate lithography techniques. After patterning the photoresist, p-type impurities are implanted in the n-type region 50N, and the photoresist can act as a photomask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be substances such as boron, boron fluoride, indium, etc., and the concentration of p-type impurities in the implanted region is equal to or less than 10¹⁸ cm⁻³, for example, between about 10¹⁶ cm⁻³ and about 10¹⁸ cm⁻³. After implantation, the photoresist can be removed, for example, by an appropriate ashing process.

[0034] After implantation of the n-type region 50N and the p-type region 50P, an annealing process can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be in-situ doped during growth, which can eliminate the implantation step, although in-situ doping and implantation doping can be used together.

[0035] In FIG. 7, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or similar materials, and may be deposited or thermally grown according to appropriate techniques. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a photomask layer 64 may be formed above the dummy gate layer 62. The dummy gate layer 62 may be deposited above the dummy dielectric layer 60, and then planarized, for example, by CMP. The photomask layer 64 may be deposited above the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material, and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer 62 can be deposited using physical vapor deposition (PVD), CVD, sputtering deposition, or other known or existing techniques for depositing conductive materials. The dummy gate layer 62 can be another material with high etch selectivity compared to the isolation regions (e.g., STI region 56 and / or dummy dielectric layer 60). The photomask layer 64 can comprise one or more layers of material, such as silicon nitride, silicon oxynitride, etc. In this example, the single dummy gate layer 62 and the single photomask layer 64 formed span across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 60 is depicted in the figure only covering the fin 52 for illustrative purposes. In some embodiments, the deposition of the dummy dielectric layer 60 may be such that the dummy dielectric layer 60 covers the STI region 56, extends over the STI region, and extends between the dummy gate layer 62 and the STI region 56.

[0036] Figures 8A to 16B illustrate various additional steps in the manufacturing of the components of the embodiments. Figures 8A to 16B illustrate the characteristics of either the n-type region 50N or the p-type region 50P. For example, the structures illustrated in Figures 8A to 16B can be applied to both the n-type region 50N and the p-type region 50P. The differences (if any) in the structures of the n-type region 50N and the p-type region 50P are described in the content of each figure.

[0037] In Figures 8A and 8B, the photomask layer 64 (see Figure 7) can be patterned using appropriate lithography and etching techniques to form a photomask 74. The pattern of the photomask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the photomask 74 can also be transferred to the dummy dielectric layer 60 by appropriate etching techniques to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the photomask 74 can be used to separate each dummy gate 72 from adjacent dummy gate entities. The dummy gate 72 may also have a length direction substantially perpendicular to the length direction of each fin 52.

[0038] Furthermore, in Figures 8A and 8B, a gate seal spacer layer 80 can be formed on the exposed surfaces of the dummy gate 72, the photomask 74, and / or the fin 52. The gate seal spacer layer 80 can be formed by anisotropic etching following thermal oxidation or deposition. The gate seal spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0039] After forming the gate sealing spacer 80, implantation can be performed for the lightly doped source / drain (LDD) region (not specifically shown). Similar to the implantation discussed in FIG. 6 above, in embodiments of different device types, a photomask, such as a photoresist, can be formed over the n-type region 50N, exposing the p-type region 50P, and an impurity of an appropriate type (e.g., a p-type impurity) can be implanted into the exposed fins 52 in the p-type region 50P. The photomask can then be removed. Next, a photomask, such as a photoresist, can be formed over the p-type region 50P, exposing the n-type region 50N, and an impurity of an appropriate type (e.g., an n-type impurity) can be implanted into the exposed fins 52 in the n-type region 50N. The photomask can then be removed. The n-type impurity can be any of the n-type impurities discussed above, and the p-type impurity can be any of the p-type impurities discussed above. The lightly doped source / drain region can have an impurity concentration of approximately 10¹⁵ cm⁻³ to approximately 10¹⁹ cm⁻³. Annealing can be used to repair implant damage and activate implanted impurities.

[0040] In Figures 9A and 9B, a gate spacer 86 is formed on the gate sealing spacer 80 and along the sidewalls of the dummy gate 72 and the photomask 74. The insulating material of the gate spacer 86 can be deposited conformally, and then the insulating material of the gate spacer 86 can be anisotropically etched to form the gate spacer 86. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0041] It should be noted that the above disclosure provides a general description of the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, such as not etching the gate sealing spacer 80 before forming the gate spacer 86 to produce an "L-shaped" gate sealing spacer, the spacers can be formed and removed, and / or similar steps. Furthermore, different structures and steps can be used to form n-type and p-type elements. For example, the LDD region of an n-type element can be formed before forming the gate sealing spacer 80, while the LDD region of a p-type element can be formed after forming the gate sealing spacer 80.

[0042] In Figures 10A and 10B, epitaxial source / drain regions 82 are formed in fin 52. The epitaxial source / drain regions 82 are formed in fin 52 such that each dummy gate 72 is located between a corresponding pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into or through fin 52. In some embodiments, gate spacers 86 may be used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance, so that the epitaxial source / drain regions 82 do not short-circuit with the gates of subsequently formed FinFETs. The material of the epitaxial source / drain regions 82 may be selected to apply stress to each channel region 58, thereby improving device performance.

[0043] The epitaxial source / drain region 82 in the n-type region 50N can be formed by shielding the p-type region 50P and etching the source / drain region of the fin 52 in the n-type region 50N to form a groove in the fin 52. Then, the epitaxial source / drain region 82 is epitaxially grown in the groove in the n-type region 50N. The epitaxial source / drain region 82 can contain any suitable material, such as that suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N can contain a material capable of applying tensile strain to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The surface of the epitaxial source / drain region 82 in the n-type region 50N can be higher than the surface of each fin 52, and the epitaxial source / drain region 82 can have facets.

[0044] The epitaxial source / drain region 82 in the p-type region 50P can be formed by shielding the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a groove in the fin 52. Then, the epitaxial source / drain region 82 is epitaxially grown in the groove in the p-type region 50P. The epitaxial source / drain region 82 can contain any suitable material, such as that suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P can contain a material capable of applying compressive strain to the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The surface of the epitaxial source / drain region 82 in the p-type region 50P can be higher than the surface of each fin 52, and the epitaxial source / drain region 82 can have facets.

[0045] Dopants can be implanted into the epitaxial source / drain regions 82 and / or fins 52 to form source / drain regions. The fabrication process is similar to the process discussed above for forming lightly doped source / drain regions, followed by an annealing step. The source / drain regions may have an impurity concentration between approximately 10¹⁹ cm⁻³ and approximately 10²¹ cm⁻³. The n-type and / or p-type impurities in the source / drain regions can be any impurities discussed above. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0046] As a result of forming the epitaxial source / drain regions 82 through epitaxial processes in regions 50N and 50P, the upper surface of the epitaxial source / drain regions 82 has facets that extend laterally outward beyond the sidewalls of the fins 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, as shown in FIG10D. In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, as shown in FIG10C and 10E. In the embodiments shown in FIG10C and 10D, the gate spacer 86 is formed as a sidewall covering a portion of the fins 52 extending over the STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 86 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 56.

[0047] In Figures 11A and 11B, a first interlayer dielectric (ILD) 88 can be deposited on the structure shown in Figures 10A and 10B. The first ILD 88 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may comprise phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or similar materials. Other insulating materials formed by any suitable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is provided between the first ILD 88 and the epitaxial source / drain region 82, the photomask 74, and the gate spacer 86. CESL87 may contain dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., with an etch rate lower than that of the overlying first ILD88 material.

[0048] In Figures 12A and 12B, a planarization process, such as CMP, is performed to make the top surface of the first ILD 88 coplanar with the top surface of the dummy gate 72 or the photomask 74. This planarization process may also remove the photomask 74 on the dummy gate 72, as well as portions of the gate sealing spacer 80 and gate spacer 86 on the sidewalls of the photomask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are all coplanar. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the photomask 74 may be retained; in this example, the planarization process makes the top surface of the first ILD 88 coplanar with the top surface of the photomask 74.

[0049] In Figures 13A and 13B, a dummy gate 72 and a photomask 74 (if present) are removed during an etching step to form a recess 90. A portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed while the dummy dielectric layer 60 is retained, exposing the dummy dielectric layer 60 in the recess 90. In some embodiments, the dummy dielectric layer 60 in the recess 90 in a first region of the die (e.g., a core logic region) is removed, and the dummy dielectric layer 60 in the recess 90 in a second region of the die (e.g., an input / output region) is retained. In some embodiments, the dummy gate 72 may be removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 but etches little or no first ILD 88 or gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is located between a pair of adjacent epitaxial source / drain regions 82. During the removal process described above, when etching the dummy gate 72, the dummy dielectric layer 60 can be used as an etch stop layer. Then, after removing the dummy gate 72, the dummy dielectric layer 60 can be selectively removed.

[0050] In Figures 14A and 14B, a gate dielectric layer 92 and a gate electrode 94 are formed for use as replacement gates. Figure 14C illustrates a detailed view of region 89 in Figure 14B. One or more gate dielectric layers 92 are deposited in the recess 90, for example on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxides, metal silicates, etc. For example, in some embodiments, the gate dielectric layer 92 comprises a silicon oxide interface layer formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, of metal oxides or silicates. The gate dielectric layer 92 may comprise a dielectric layer with a k-value greater than about 7.0. The gate dielectric layer 92 may be formed using methods including molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy gate dielectric 60 is retained within the recess 90, the gate dielectric layer 92 comprises the material of the dummy gate dielectric 60 (e.g., SiO2).

[0051] A gate electrode 94 is deposited above the gate dielectric layer 92, and the remaining portion of the recess 90 is filled. The gate electrode 94 may contain a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or a multilayer structure thereof. For example, although a single-layer gate electrode 94 is shown in FIG14B, the gate electrode 94 may contain any number of substrates 94A, any number of work function tuning layers 94B, and filler material 94C, as shown in FIG14C. After filling the recess 90, a planarization process, such as CMP, may be performed to remove excess material from the gate dielectric layer 92 and the gate electrode 94, which are located above the top surface of the ILD88. The remaining material of the gate electrode 94 and the gate dielectric layer 92 thus forms an alternative gate for the fabricated FinFET. The gate electrode 94 and the gate dielectric layer 92 may be referred to together as a "gate stack". The gate and gate stack can extend along the sidewall of the channel region 58 of the fin 52.

[0052] The gate dielectric layer 92 formed in the n-type region 50N and the p-type region 50P can be formed simultaneously, such that the gate dielectric layer 92 in each region can be formed of the same material, and the gate electrode 94 can be formed simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by separate processes, such that the gate dielectric layer 92 in each region can be made of different materials, and / or the gate electrode 94 in each region can be formed by separate processes, such that the gate electrode 94 can be made of different materials. Various masking steps can be used to mask and expose appropriate areas when using separate processes.

[0053] In Figures 15A and 15B, a gate mask 96 is formed over the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask may be located between opposing portions of the gate spacer 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack to form a groove directly over the gate stack and between opposing portions of the gate spacer 86. The gate mask 96, comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), fills the groove, followed by a planarization process to remove excess portions of the dielectric material extending on the first ILD 88. The gate mask 96 is optional and may be omitted in some embodiments. In such embodiments, the gate stack may remain coplanar with the top surface of the first ILD 88.

[0054] Also as shown in Figures 15A and 15B, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 (Figures 16A and 16B) formed thereafter passes through the second ILD 108 and the gate photomask 96 (if present) to contact the top surface of the recessed gate electrode 94.

[0055] In Figures 16A and 16B, according to some embodiments, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. The opening of the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and the opening of the gate contact 110 is formed through the second ILD 108 and the gate mask 96 (if present). Suitable lithography and etching techniques can be used to form these openings. A substrate (not shown) and a conductive material are formed within these openings. The substrate can be, for example, a diffusion barrier layer, an adhesive layer, etc. The substrate can contain materials such as titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be materials such as copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form the source / drain contact 112 and gate contact 110 in the aforementioned opening. An annealing process can be performed to form silica at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contact 112 and gate contact 110 can be formed using different or the same processes. Although the source / drain contact 112 and gate contact 110 are formed in the same cross-section in the figure, it should be understood that each of the source / drain contact 112 and gate contact 110 can also be formed in different cross-sections, which can avoid short circuits at the contacts.

[0056] Figure 17 illustrates a cross-sectional view similar to Figures 3B and 10C, and shows further processing of the structures of Figures 16A and 16B. In Figure 17, a third ILD 114 is deposited over the second ILD 108. In some embodiments, the third ILD 114 is similar to the second ILD 108, and will not be described again here. Vias 116 and metallization patterns 118 are formed in the third ILD 114, and source / drain contacts 112 are electrically connected. Vias 116 and metallization patterns 118 can be formed, for example, by a damascene process. As illustrated in Figure 17, regions 50N / P and 50R form the same ILD, via, and metallization patterns. This design allows this structure to be fully integrated into the CMOS process flow.

[0057] Figures 18A to 25 illustrate top views and cross-sectional views of various configurations of semiconductor elements according to some embodiments.

[0058] FIG18A illustrates a top view of a semiconductor element 210 according to some embodiments of the present disclosure. FIG18B illustrates a cross-sectional view along cross-sectional lines 18B-18B of the semiconductor element 210 in FIG18A according to some embodiments of the present disclosure. FIG18C illustrates a cross-sectional view along cross-sectional lines 18C-18C of the semiconductor element 210 in FIG18A according to some embodiments of the present disclosure. Referring to FIG18A to 18C, the semiconductor element 210 includes a substrate 50, a plurality of fin structures 52, an isolation region 54, a plurality of gate structures 94, a plurality of epitaxial structures 82 (sometimes referred to as source / drain structures 82), and a plurality of contact structures 112. These structures have been described above and will not be repeated here. Details similar to those of the embodiments described above will also not be repeated here.

[0059] In some embodiments, the fin structure 52 has a plurality of first fin structures 52A and a plurality of second fin structures 52B. In some embodiments, the plurality of first fin structures 52A and the plurality of second fin structures 52B are arranged in an alternating pattern, wherein at least one second fin structure 52B separates the first fin structures 52A from each other. Each first fin structure 52A has an epitaxial structure 82 formed on the first fin structure 52A, and each second fin structure 52B does not have an epitaxial structure 82 above it. In some embodiments, the second fin structures 52B separate and isolate the epitaxial structures 82 on the first fin structures 52A, and may be referred to as isolation fin structures 52B. In some embodiments, each epitaxial structure 82 has at least one contact structure 112 formed on the epitaxial structure 82. Each contact structure 112 is electrically connected to at least one epitaxial structure 82. According to some embodiments of this disclosure, the semiconductor element 210 includes a plurality of resonators 217. Although in other embodiments, the epitaxial structures 82 may be combined and formed on multiple first fin structures 52A (see, for example, Figures 19A and 19B), in the illustrated embodiment, each epitaxial structure 82 is only on a single first fin structure 52A. The epitaxial structures 82 are located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structures 52. The gate structure 94 may be the alternative gate structure 94 described above or a dummy gate structure 72.

[0060] In some embodiments, at least one second fin structure 52B is located between two first fin structures 52A. In some embodiments, four second fin structures 52B are located between two first fin structures 52A. In some embodiments, the output frequency of the resonator 217 can be determined by the number of first fin structures 52A, the material composition of the first fin structures 52A, and the number of second fin structures 52B between the first fin structures 52A.

[0061] In the embodiments shown in Figures 18A to 21B, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A and second fin structures 52B below the single combined epitaxial structure 82. Furthermore, in these embodiments, the material composition of the first fin structures 52A can adjust the output frequency of the resonator 217. In the embodiments of Figures 18A-C, the resonator 217 is configured such that each epitaxial structure is located on a single first fin structure 52A, and each first fin structure 52A is separated by four second fin structures 52B.

[0062] FIG19A shows a top view of a semiconductor element 212 according to some embodiments, and FIG19B shows a cross-sectional view of the semiconductor element 212 along section lines 19B-19B in FIG19A according to some embodiments. Details similar to those of the embodiments described above will not be repeated here.

[0063] In the embodiments of Figures 19A-B, the resonator 217 is configured such that each epitaxial structure is located on two adjacent first fin structures 52A, and each pair of first fin structures 52A is separated by a single second fin structure 52B. Epitaxial structures 82 are located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structures 52. The gate structure 94 may be the alternative gate structure 94 described above or a dummy gate structure 72.

[0064] FIG20A illustrates a top view of a semiconductor element 214 according to some embodiments, and FIG20B illustrates a cross-sectional view of the semiconductor element 214 along section lines 20B-20B in FIG20A according to some embodiments. Details similar to those of the embodiments described above will not be repeated here.

[0065] In the embodiment of Figures 20A-B, the resonator 217 is configured such that each epitaxial structure is located on two adjacent first fin structures 52A, and each pair of first fin structures 52A is separated by three second fin structures 52B. Epitaxial structures 82 are located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structures 52. The gate structure 94 may be the alternative gate structure 94 described above or a dummy gate structure 72.

[0066] FIG21A shows a top view of a semiconductor element 216 according to some embodiments, and FIG21B shows a cross-sectional view of the semiconductor element 216 along section lines 21B-21B in FIG21A according to some embodiments. Details similar to those of the embodiments described above will not be repeated here.

[0067] In the embodiments of Figures 21A-B, the resonator 217 is configured such that each epitaxial structure is located on three adjacent first fin structures 52A, and each group of first fin structures 52A is separated by four second fin structures 52B. Epitaxial structures 82 are located between adjacent gate structures 94, wherein the gate structures 94 extend in a direction perpendicular to the fin structures 52. The gate structure 94 may be the alternative gate structure 94 described above or a dummy gate structure 72.

[0068] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A and second fin structures 52B below the single combined epitaxial structure 82. Furthermore, in these embodiments, the material composition of the first fin structure 52A can adjust the output frequency of the resonator 217.

[0069] FIG22 shows a cross-sectional view of a semiconductor element 220 according to some embodiments. In this embodiment, the semiconductor element 220 has fin structures 52 combined together, such that there are multiple fin spacings in the semiconductor element 220. For example, a group of first or second fin structures 52A or 52B may have an internal distance D2, while the spacing between each group of fins and the adjacent group of fins is D1. Details similar to those in the embodiments described above will not be repeated here.

[0070] In the embodiment of FIG. 22, the resonator 217 is configured such that each epitaxial structure is located on a set of two adjacent first fin structures 52A, and each set of first fin structures 52A is separated by two sets of second fin structures 52B. In some embodiments, the spacing between the individual first fins 52A within the plurality of sets of first fin structures 52A is D2. In some embodiments, the spacing between the individual second fin structures 52B within the plurality of sets of second fin structures 52B is D2. In some embodiments, the distance D2 is in the range of 1 nm to 200 nm. In some embodiments, the spacing between each set of first fin structures 52A and the nearest set of fins (first or second fins) is D1. In some embodiments, the distance D1 is in the range of 1 nm to 200 nm. In some embodiments, D1 is different from D2. In some embodiments, D1 is less than D2, while in other embodiments, D1 is greater than D2.

[0071] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A below the single combined epitaxial structure 82, the distance D2, the ratio of distances D1, D1 and D2, or a combination thereof.

[0072] FIG23 illustrates a cross-sectional view of a semiconductor element 222 according to some embodiments. This embodiment is similar to the embodiment of FIG22 and also includes a plurality of internal fin pitches and a plurality of epitaxial structures 82 connected to a single contact structure 112. Details similar to those of the embodiments described above will not be repeated here.

[0073] In the embodiment of FIG. 23, the resonator 217 is configured such that each epitaxial structure is located on a set of three adjacent first fin structures 52A. The spacing between at least two first fin structures 52A in this set is D2. Furthermore, the spacing between at least two first fin structures 52A is D3, which is different from D2. In some embodiments, the distance D3 is in the range of 1 nm to 200 nm. In some embodiments, D3 is different from D2. In some embodiments, D2 is less than D3, while in other embodiments, D2 is greater than D3.

[0074] In some embodiments, at least one of the first fin structures 52A in the group is spaced apart from the nearest second fin structure 52B by a distance D4. In some embodiments, the distance D4 is in the range of 1 nm to 200 nm. In some embodiments, D1 is different from D4. In some embodiments, D1 is less than D4, while in other embodiments, D1 is greater than D4.

[0075] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A below the single combined epitaxial structure 82, the number of epitaxial structures 82 below the single contact structure 112, the distance D2, the distance D1, the distance D3, the distance D4, the ratio of D1 to D2, the ratio of D3 to D2, the ratio of D1 to D4, or a combination thereof.

[0076] Figures 24 and 25 illustrate cross-sectional views of semiconductor elements 224 and 226 according to some embodiments. This embodiment is similar to the embodiment of Figure 22 and also includes a fin structure with a gradient material composition. Details similar to those of the embodiments described above will not be repeated here.

[0077] In the embodiments of Figures 24 and 25, at least one first fin structure 52A has a gradient concentration of material composition. In some embodiments, at least one first fin structure 52A has a gradient compound semiconductor material composition. In some embodiments, at least one first fin structure 52A has a gradient composition of SiGe material and may be a Si1-xGex material composition, 0 < x < 1. In Figure 24, the x value increases from the top of at least one first fin structure 52A to the bottom of at least one first fin structure 52A. In some embodiments, the x value increases from 0.99 to 0.01. In Figure 25, the x value decreases from the top of at least one first fin structure 52A to the bottom of at least one first fin structure 52A. In some embodiments, the x value decreases from 0.99 to 0.01.

[0078] In various configurations of the resonator 217, the output frequency of the resonator 217 can be configured by the number of first fin structures 52A below a single combined epitaxial structure 82, the number of epitaxial structures 82 below a single contact structure 112, the material gradient concentration of at least one first fin structure 52A, the direction of the material gradient concentration of at least one first fin structure 52A, or a combination thereof.

[0079] Figures 26 and 27 illustrate top views of example circuit configurations operating resonator 217 to generate an output frequency. In various examples, external contact structures 112 (e.g., contact structures 112 at the top and bottom of the top views of Figures 26 and 27) are alternately coupled to different input voltages Vin. In some embodiments, the input voltage Vin is an alternating current (AC) signal. For example, in one embodiment, half of the external contact structures 112 is coupled to positive Vin (e.g., +1 / 2 Vin), while the other half is coupled to negative Vin (e.g., -1 / 2 Vin). In each example, one or more gate structures are coupled to a gate voltage Vg. In Figure 26, the left sides of an inner pair of contact structures 112 are coupled together to form an output signal (e.g., an output frequency), and the right sides of an inner pair of contact structures are coupled to a low voltage (e.g., ground). In the embodiment of FIG26, each epitaxial structure 82 and the junction structure 112 are located on a plurality of first fin structures 52A, and there are a plurality of second fin structures 52B between each group of first fin structures 52A.

[0080] Figure 27 shows a minimal resonator configuration. In Figure 27, a pair of internal point structures 112 are coupled together to form an output signal (e.g., an output frequency). In the embodiment of Figure 27, there are no second fin structures 52B between the respective first fin structures 52A, and each epitaxial structure 82 is located only on a single first fin structure 52A.

[0081] In Figures 26 and 27, the input signal Vin and the gate voltage Vg are generated by vibrations in the fin structure based on the resonance of the fin structure. In some embodiments, this vibration causes changes in capacitance and carrier movement in the fins, generating a high-frequency sensing current. In some embodiments, the resonant frequency of the fin structure is related to material properties such as Young's modulus, mass density, geometry, or combinations thereof.

[0082] As an example, the gate structure 94 establishes a capacitor with a first fin structure 52A, with a gate dielectric between them. Therefore, when a gate voltage Vg is applied to the gate, electrostatic force can squeeze the dielectric, and in turn squeeze the first fin structure 52A. A series of regular voltage pulses, as the gate voltage Vg, can generate periodic pulses in the fin structure 52A. By separating a series of first and second fin structures 52A and 52B in various configurations and connecting them all to the gate structure 94, the resonator 217 can resonate at a variety of frequencies ranging from megahertz to gigahertz.

[0083] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructure (e.g., nanosheets, nanowires, gate surrounds, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by stacking alternating layers of patterned channel layers and sacrificial layers. The dummy gate stack and source / drain regions are formed in a similar manner to the embodiments described above. After removing the dummy gate stack, the sacrificial layer in the channel region can be partially or completely removed. The alternative gate structure is formed in a similar manner to the embodiments described above, and the alternative gate structure can partially or completely fill the opening left after removing the sacrificial layer, and the alternative gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and the contacts between the alternative gate structure and the source / drain regions can be formed in a manner similar to the embodiments described above. Nanostructure devices can be formed using the techniques disclosed in U.S. Patent Application Publication No. 2016 / 0365414, the entire contents of which are incorporated herein by reference.

[0084] The embodiments disclosed herein offer advantages. The disclosed apparatus and methods involve using a fin structure to fabricate a resonator that can be used as a frequency source in a circuit. In some embodiments, the frequency generated by the device is determined by the fin material and the fin spacing. Component design allows for better integration of this structure into complementary metal-oxide-semiconductor (CMOS) process flows. The disclosed embodiments allow the device to generate more than one frequency in a single structure, while also simplifying the process and eliminating the need for special packaging.

[0085] One embodiment includes a semiconductor element and a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor element further includes a plurality of isolation regions located on the substrate and between the plurality of fin structures. The element also includes a plurality of gate structures on the plurality of isolation regions. The element further includes a plurality of epitaxial structures on one of the plurality of first fin structures. The element further includes a plurality of contact structures on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are components of one or more resonators.

[0086] Several embodiments may include one or more of the following features. One or more resonators include a semiconductor element comprising a contact structure, an epitaxial structure, and a first fin structure. At least one of a plurality of second fin structures is located between two of the plurality of first fin structures. One or more resonators include a contact structure, a plurality of epitaxial structures, and a plurality of first fin structures. At least one of a plurality of gate structures extends between at least one of the following structures: a plurality of epitaxial structures, a plurality of first fin structures and a plurality of second fin structures arranged in an alternating pattern, and a plurality of second fin structures separating two plurality of first fin structures. Each first fin structure includes a gradient material composition from the top to the bottom of the first fin structure. One of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction. The first sidewall is spaced apart from the nearest fin structure by a first distance in the first direction, and the second sidewall is spaced apart from the nearest fin structure by a second distance in the second direction, the second distance being different from the first distance. The fin structure closest to the first direction is the first fin structure, and the fin structure closest to the second direction is the second fin structure.

[0087] One embodiment includes a semiconductor element and a substrate having a first surface and a second surface. The semiconductor element further includes an isolation structure above the first surface of the substrate. The element also includes a plurality of gate structures above the isolation structure. The element further includes a resonator comprising a plurality of first fin structures, at least one epitaxial structure, and a contact structure, wherein the plurality of first fin structures are located on the first surface of the substrate, the at least one epitaxial structure is located on the first fin structures, and the contact structure is located on the at least one epitaxial structure. The element further includes at least one second fin structure located on the first surface of the substrate, at least one second fin structure located between two of the plurality of first fin structures, and at least one second fin structure not comprising an epitaxial structure.

[0088] Several embodiments may include one or more of the following features. The output frequency of the resonator in the semiconductor element is based on the spacing of the first fin structures and the material composition of the first fin structures. A plurality of second fin structures are located between two first fin structures, wherein there is no first fin structure between the two first fin structures. Each first fin structure comprises a compound semiconductor material. Each first fin structure comprises a gradient material composition from the top to the bottom of the first fin structure. One of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction. The first sidewall is spaced apart from the nearest fin structure by a first distance in the first direction, and the second sidewall is spaced apart from the nearest fin structure in the second direction by a second distance, the second distance being different from the first distance.

[0089] One embodiment includes forming a plurality of fin structures extending from a substrate, the fin structures having a plurality of first fin structures and a plurality of second fin structures. The method further includes forming a plurality of isolation regions on the substrate and located between the plurality of fin structures. The method further includes forming a plurality of gate structures on the isolation regions. The method further includes growing a plurality of epitaxial structures on the plurality of first fin structures, while the plurality of second fin structures do not have epitaxial structures. The method further includes forming a plurality of contact structures on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are components of one or more resonators.

[0090] Several embodiments may include one or more of the following features. At least one first fin structure is made of Si1-xGex material, 0 < x < 1. The x value increases from the top of the at least one first fin structure to the bottom of the at least one first fin structure. The x value decreases from the top of the at least one first fin structure to the bottom of the at least one first fin structure. A plurality of second fin structures are located between two first fin structures, wherein there is no first fin structure between the two first fin structures.

[0091] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other programs and structures to implement the same purposes as the embodiments introduced herein and / or to achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0007] The following detailed description, taken in conjunction with the accompanying drawings, is the best way to understand the nature of this disclosure. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a three-dimensional view illustrating a FinFET example according to some embodiments.

[0009] Figures 2, 3A, 3B, 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 10E, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 14C, 15A, 15B, 16A, 16B, and 17 are cross-sectional views of intermediate manufacturing stages of a FinFET according to some embodiments.

[0010] Figures 18A, 18B, 18C, 19A, 19B, 20A, 20B, 21A, 21B, 22, 23, 24 and 25 show top views and cross-sectional views of various configurations of semiconductor elements according to some embodiments.

[0011] Figures 26 and 27 show top views of various configurations of semiconductor elements according to some embodiments.

Claims

1. A semiconductor device including fin structures, comprising: a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. Multiple isolation regions are located on the substrate and between the multiple fin structures. Multiple gate structures located on multiple isolation regions; multiple epitaxial structures located on one of multiple first fin structures; and multiple contact structures located on the multiple epitaxial structures, wherein the multiple first fin structures, the multiple gate structures, the multiple epitaxial structures and the multiple contact structures are components of one or more resonators.

2. The semiconductor element of claim 1, wherein the one or more resonators comprises a contact structure, an epitaxial structure and a first fin structure.

3. The semiconductor device of claim 1, wherein the one or more resonators comprises a contact structure, the plurality of epitaxial structures and the plurality of first fin structures.

4. The semiconductor element of claim 2, wherein at least one of the plurality of second fin structures is located between two of the plurality of first fin structures.

5. The semiconductor element of claim 4, wherein the plurality of second fin structures are located between two of the plurality of first fin structures.

6. The semiconductor element of claim 1, wherein at least one of the plurality of gate structures extends between the plurality of epitaxial structures, the plurality of first fin structures arranged in an alternating pattern, and the plurality of second fin structures, and at least one of the plurality of second fin structures separating two of the plurality of first fin structures.

7. The semiconductor element of claim 1, wherein each first fin structure comprises a gradient material composition from the top of the first fin structure to the bottom of the first fin structure.

8. The semiconductor element of claim 1, wherein one of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction, the first sidewall being spaced apart from a nearest fin structure by a first distance in the first direction, and the second sidewall being spaced apart from a nearest fin structure by a second distance in the second direction, the second distance being different from the first distance.

9. The semiconductor device of claim 8, wherein the nearest fin structure in the first direction is a first fin structure, and wherein the nearest fin structure in the second direction is a second fin structure.

10. A semiconductor device including a fin structure, comprising: a substrate having a first surface and a second surface; an isolation structure located above the first surface of the substrate; a plurality of gate structures located above the isolation structure; a resonator including a plurality of first fin structures, at least one epitaxial structure, and a contact structure, the plurality of first fin structures located on the first surface of the substrate, the at least one epitaxial structure located on the first fin structure, the contact structure located on the at least one epitaxial structure; and at least one second fin structure located on the first surface of the substrate, and the at least one second fin structure located between two of the plurality of first fin structures, the at least one second fin structure not containing an epitaxial structure.

11. The semiconductor element of claim 10, wherein an output frequency of the resonator is based on a spacing of the first fin structures and a material composition of the first fin structures.

12. The semiconductor device of claim 10, wherein a plurality of second fin structures are located between two of the first fin structures, wherein there are no first fin structures between the two first fin structures.

13. The semiconductor element of claim 10, wherein each of the first fin structures comprises a compound semiconductor material.

14. The semiconductor device of claim 10, wherein each first fin structure comprises a gradient material composition from the top of the first fin structure to the bottom of the first fin structure.

15. The semiconductor element of claim 10, wherein one of the plurality of first fin structures has a first sidewall facing a first direction and a second sidewall facing a second direction opposite to the first direction, the first sidewall being spaced apart from a nearest fin structure by a first distance in the first direction, and the second sidewall being spaced apart from a nearest fin structure by a second distance in the second direction, the second distance being different from the first distance.

16. A method of manufacturing a resonator using fin structures, comprising: forming a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures; forming a plurality of isolation regions on the substrate and located between the plurality of fin structures; forming a plurality of gate structures on the plurality of isolation regions; growing a plurality of epitaxial structures on the plurality of first fin structures, the plurality of second fin structures having no epitaxial structures; and forming a plurality of contact structures on the plurality of epitaxial structures, wherein the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxial structures, and the plurality of contact structures are components of one or more resonators.

17. The method of claim 16, wherein the material of at least one first fin structure is Si1-xGex, 0 < x < 1.

18. The method of claim 17, wherein the x value increases from the top of the at least one first fin structure to the bottom of the at least one first fin structure.

19. The method of claim 17, wherein the x value decreases from the top of the at least one first fin structure to the bottom of the at least one first fin structure.

20. The method of claim 16, wherein the plurality of second fin structures are located between two of the first fin structures, wherein there are no first fin structures between the two first fin structures.

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