Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits

Abstract

Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

Description

[Technical Field]

[0001] The field of this case relates to field-effect transistors (FETs) and complementary metal-oxide-semiconductor (CMOS) integrated circuits employing P-type FETs (PFETs) and N-type FETs (NFETs) for forming logic circuits. [Previous Technology]

[0002] Transistors are essential components in modern electronic devices. Many integrated circuits (ICs) in modern electronic devices use a large number of transistors. For example, components such as central processing units (CPUs), digital signal processors (DSPs), and memory systems each use a large number of transistors for logic circuits and memory devices.

[0003] One type of transistor is the field-effect transistor (FET). FETs use an electric field to control the flow of current between the source and drain. The flow of current is controlled by applying a voltage to the gate of the FET, which in turn changes the conductivity between the source and drain. Different types of FETs include planar FETs, FinFETs (FinFETs), and gate-all-loop (GAA) FETs. In an integrated circuit (IC) employing a FET, the IC includes source, drain, and gate metal contacts formed to contact the corresponding source, drain, and gate of the FET to provide signal routing to the FET. The metal contacts are then connected to metal lines in an interconnect layer of the IC, which is located above the semiconductor or active layer of the IC, which includes the FET for routing signals to the source, drain, and gate of the FET via the source, drain, and gate metal contacts. For example, if a circuit employing a FET requires a power signal to be coupled to the source of the FET, the source contact is connected to a metal line designed to carry power. As another example, if a circuit using a FET requires logic signals to be coupled to the drain of the FET, then the drain contact is connected to a metal line designed to carry the logic signals.

[0004] As the node size of circuits employing FETs is reduced in ICs to save area and / or allow more FETs to be fabricated in a given area or wafer size, the gate spacing between adjacent FETs can also be reduced. This reduces the distance between the source and drain of adjacent FETs in the IC, thereby increasing wiring congestion in the interconnect layer above the FETs to provide signal routing. Increased signal routing congestion can cause metal lines in the interconnect layer to be set closer together, thus increasing the parasitic capacitance of the wiring lines and therefore increasing the capacitance of the FETs. The increased capacitance on the FETs reduces the performance of the FETs. [Summary of the Invention]

[0005] The embodiments disclosed herein include field-effect transistor (FET) circuits that employ top-side and back-side contacts for top-side and back-side wiring of FET power and logic signals. Related complementary metal-oxide-semiconductor (CMOS) circuits employing FETs are also disclosed, which employ top-side and back-side contacts for top-side and back-side wiring of FET power and logic signals. In this embodiment, some exemplary embodiments disclosed herein provide a FET circuit including a conductive channel, a source, a drain, and a gate. The conductive channel is disposed above a substrate. The source is disposed in a first end of the conductive channel. The drain is disposed in a second end of the conductive channel. The gate is disposed above at least a portion of the conductive channel and between the first and second ends of the conductive channel. The FET circuit also includes at least one top-side metal contact contacting at least one top surface of the source, drain, and gate of the FET. The FET circuit also includes at least one back-side metal contact contacting at least one bottom surface of the source, drain, and gate of the FET. The FET circuit also includes top-side metal lines and back-side metal lines electrically coupled to respective top-side and back-side metal contacts to provide power and signal routing to the FET. At least one of the top-side and back-side metal lines is electrically coupled to a power rail configured to carry a power signal, and at least one of the other top-side and back-side metal lines is electrically coupled to a signal transmission metal line configured to carry a logic signal.

[0006] In this manner, the back-side wiring on the FET circuit provides additional area for signal and / or power wiring, which can be advantageously employed, for example, to offset any reduction in wiring area due to factors such as the reduction in FET size and / or the increase in the complexity of the circuitry including the FET circuitry. Increased signal wiring congestion may cause metal lines in the interconnect layer to be positioned closer together, thus increasing the parasitic capacitance of the wiring lines and therefore increasing the capacitance of the FET. The increased capacitance on the FET will reduce the performance of the FET.

[0007] In another exemplary embodiment, a CMOS circuit is provided, the CMOS circuit including a substrate, the substrate including a top surface, a positive (P)-type diffusion region disposed in the substrate, and a negative (N)-type diffusion region disposed in the substrate. The CMOS circuit includes a first power rail and a second power rail, the first power rail being configured adjacent to the P-type diffusion region, and the second power rail being configured adjacent to the N-type diffusion region. At least one P-type FET (PFET) is formed in the N-type diffusion region, and at least one N-type FET (NFET) is formed in the P-type diffusion region. Each of the PFET and NFET in the CMOS circuit includes a conductive channel disposed above the substrate, a source disposed at a first end of its conductive channel, a drain disposed at a second end of its conductive channel, and a gate disposed adjacent to its conductive channel. At least one PFET and at least one NFET in a CMOS circuit each include a source back-side metal contact and a drain back-side metal contact. The source back-side metal contact is disposed below the top surface of a substrate and electrically coupled to the bottom surface of its source. The drain back-side metal contact is disposed below the top surface of the substrate and electrically coupled to the bottom surface of its drain. One of the source back-side metal contacts and the drain back-side metal contacts of the at least one PFET and the at least one NFET is electrically coupled to a back-side power metal line extending on a longitudinal axis parallel to the longitudinal axis of one of the first and second power rails and coupled to the power rail. The other of the source back-side metal contacts and the drain back-side metal contacts of the at least one PFET and the at least one NFET is electrically coupled to a back-side signal transmission metal line configured to carry a logic signal.

[0008] In another exemplary configuration of a CMOS circuit, the back-side signal transmission metal line extends along a longitudinal axis parallel to the longitudinal axis of the back-side power metal line. The back-side signal transmission metal line and the back-side power metal line are disposed between a first power rail and a second power rail.

[0009] In this embodiment, in one exemplary embodiment, a field-effect transistor (FET) circuit is provided. The FET circuit includes a signal transmission metal line configured to carry a logic signal, a power rail configured to carry a power signal from a power source, and the FET. The FET circuit also includes a conductive channel disposed above a substrate, and a source disposed in a first end of the conductive channel, wherein the source includes a source top surface and a source bottom surface. The FET circuit also includes a drain disposed in a second end of the conductive channel opposite to the first end, wherein the drain includes a drain top surface and a drain bottom surface. The FET circuit also includes a gate disposed above at least a portion of the conductive channel and between the first end and the second end of the conductive channel, wherein the gate includes a gate top surface and a gate bottom surface. The FET circuit also includes a top-side metal contact contacting one of the source top surface, the drain top surface, and the gate top surface. The FET also includes a back-side metal contact contacting one of the source bottom surface, the drain bottom surface, and the gate bottom surface, and a top-side metal line disposed above the gate. The top-side metal line is electrically coupled to one of the signal transmission metal line and the power rail, as well as the top-side metal contact. The FET circuit also includes a back-side metal line disposed below the conductive channel, wherein the back-side metal line is electrically coupled to one of the power rail and the signal transmission metal line not coupled to the top-side metal line, as well as the back-side metal contact.

[0010] In another exemplary configuration, the back-side metal contact of the FET includes a vertical interconnect channel (via) that contacts one of the source bottom surface, the drain bottom surface, and the gate bottom surface.

[0011] In another exemplary embodiment, the FET includes a second back-side metal contact that contacts one of the source bottom surface, drain bottom surface, and gate bottom surface that is not in contact with a back-side metal contact. A second back-side metal line is disposed below the conductive channel and electrically coupled to the second back-side metal contact and the signal transmission metal line. In this further exemplary embodiment, the back-side metal contact contacts the source bottom surface, and the second back-side metal contact contacts the drain bottom surface. In another further exemplary embodiment, the back-side metal contact contacts the drain bottom surface, and the second back-side metal contact contacts the source bottom surface. In another further exemplary embodiment, the conductive channel extends along a first longitudinal axis between a first end and a second end of the conductive channel, the back-side metal line extends along a second longitudinal axis parallel to the first longitudinal axis, and the second back-side metal line extends along a third longitudinal axis parallel to the second longitudinal axis.

[0012] In another exemplary embodiment, the FET also includes a substrate having a top surface and a bottom surface, and a buried oxide (BOX) layer disposed on the top surface of the substrate, wherein a back-side metal line is disposed below the bottom surface of the substrate, the source is configured to contact the BOX layer, and the drain is configured to contact the BOX layer. In this additional embodiment, the source extends through the BOX layer such that the bottom surface of the source contacts the top surface of the substrate, and / or the drain extends through the BOX layer such that the bottom surface of the drain contacts the top surface of the substrate. In another exemplary embodiment of this additional embodiment, the back-side metal contact includes a via, the via including a top surface of the via contacting one of the bottom surfaces of the source, drain, and gate.

[0013] In another exemplary embodiment, the back-side metal contact includes a via, the via including a top surface of the via that contacts one of the source bottom surface, the drain bottom surface, and the gate bottom surface. In this further exemplary embodiment, the via contacts the substrate.

[0014] In another exemplary embodiment, the back-side metal contact includes a back-side metal contact top surface that contacts one of the source bottom surface, drain bottom surface, and gate bottom surface. The back-side metal contact also includes a back-side metal contact bottom surface and a via, the via including a via top surface that contacts the back-side metal contact bottom surface. In another exemplary embodiment of this further embodiment, the back-side metal contact contacts a buried oxide (BOX) layer, and the via contacts a substrate. In another exemplary embodiment of this further embodiment, one of the source bottom surface, drain bottom surface, and gate bottom surface that contacts the back-side metal contact top surface of the back-side metal contact contacts the top surface of the BOX layer.

[0015] In another exemplary embodiment, a method of manufacturing a FET circuit is provided, the method comprising the step of forming a FET. Forming the FET comprises: forming a conductive channel over a substrate; forming a source electrode disposed in a first end of the conductive channel, the source electrode including a source top surface and a source bottom surface; forming a drain electrode disposed in a second end of the conductive channel opposite to the first end, the drain electrode including a drain top surface and a drain bottom surface; and forming a gate electrode disposed over at least a portion of the conductive channel and between the first end and the second end of the conductive channel, the gate electrode including a gate top surface and a gate bottom surface. The method also comprises the steps of: forming a top-side metal contact contacting one of the source top surface, the drain top surface, and the gate top surface; forming a back-side metal contact contacting one of the source bottom surface, the drain bottom surface, and the gate bottom surface; and forming a top-side metal line disposed above the gate and electrically contacting the top-side metal contact. The method also comprises the step of: forming a back-side metal line disposed below the conductive channel and electrically contacting the back-side metal contact. The method also includes the steps of: forming a signal transmission metal line configured to contact one of a top-side metal line and a back-side metal line to carry a logic signal. The method also includes the steps of: forming a power rail configured to contact one of the back-side metal line and the top-side metal line that is not in contact with the signal transmission metal line to carry a power signal from a power source.

[0016] In another exemplary embodiment of the method, forming a back-side metal contact includes forming a via, the via including a via top surface that contacts one of the source bottom surface, the drain bottom surface and the gate bottom surface.

[0017] Another exemplary embodiment of the method also includes the steps of: forming a substrate including a top surface and a bottom surface; and forming a buried oxide (BOX) layer on the top surface of the substrate, wherein forming a backside metal line also includes forming a backside metal line below the bottom surface of the substrate, wherein forming a source also includes forming a source in contact with the BOX layer, and wherein forming a drain also includes forming a drain in contact with the BOX layer. In this further embodiment, in another exemplary embodiment, the method includes the step of: forming a source by forming a source extending through the BOX layer such that the bottom surface of the source contacts the top surface of the substrate. In this further embodiment, in another exemplary embodiment, forming a drain also includes forming a drain extending through the BOX layer such that the bottom surface of the drain contacts the top surface of the substrate.

[0018] In another exemplary embodiment of the method, forming a back-side metal contact also includes forming a top surface of the back-side metal contact that contacts one of the source bottom surface, the drain bottom surface, and the gate bottom surface. The method also includes the steps of: forming a bottom surface of the back-side metal contact, and forming a via that includes a top surface of the via that contacts the bottom surface of the back-side metal contact.

[0019] In another exemplary embodiment, a complementary metal-oxide-semiconductor (CMOS) circuit is provided. The CMOS circuit includes a P-type diffusion region disposed in a substrate, an N-type diffusion region disposed in a substrate, a power rail having a first longitudinal axis disposed in a first direction, a signal transmission metal line electrically coupled to another circuit, and a P-type field-effect transistor (FET) (PFET) formed in the N-type diffusion region. The PFET includes a P-type conductive channel, a P-type source disposed in a first end of the P-type conductive channel, a P-type drain disposed in a second end of the P-type conductive channel opposite to the first end, and a first gate disposed above at least a portion of the P-type conductive channel and between the first and second ends of the P-type conductive channel. The CMOS circuit also includes an N-type field-effect transistor (NFET) formed in the P-type diffusion region. An NFET includes an N-type conductive channel, an N-type source disposed at a first end of the N-type conductive channel, an N-type drain disposed at a second end of the N-type conductive channel opposite to the first end, and a second gate disposed above at least a portion of the N-type conductive channel and between the first and second ends of the N-type conductive channel. A CMOS circuit also includes a first back-side metal contact and a second back-side metal contact, the first back-side metal contact being in contact with one of a P-type source, a P-type drain, and a first gate, and the second back-side metal contact being in contact with one of an N-type source, an N-type drain, and a second gate. The CMOS circuit also includes a first back-side metal line disposed under the substrate, electrically coupled to the first back-side metal contact. The CMOS circuit also includes a second back-side metal line disposed under the substrate. The second back-side metal line is electrically coupled to the second back-side metal contact. The first back-side metal line is coupled to one of a power rail and a signal transmission metal line. The second back-side metal line is coupled to one of the signal transmission metal lines and the power rail that is not coupled to the first back-side metal line.

[0020] In another exemplary state of the CMOS circuit, the P-type source includes a P-type source top surface and a P-type source bottom surface, the P-type drain includes a P-type drain top surface and a P-type drain bottom surface, the first gate includes a first gate top surface and a first gate bottom surface, the N-type source includes an N-type source top surface and an N-type source bottom surface, the N-type drain includes an N-type drain top surface and an N-type drain bottom surface, the second gate includes a second gate top surface and a second gate bottom surface, a first back-side metal contact is in contact with one of the P-type source bottom surface, the P-type drain bottom surface and the first gate bottom surface, and a second back-side metal contact is in contact with one of the N-type source bottom surface, the N-type drain bottom surface and the second gate bottom surface.

[0021] In another exemplary configuration of a CMOS circuit, a first back-side metal line is coupled to a power rail, and a second back-side metal line is coupled to a signal transmission metal line.

[0022] In another exemplary configuration of a CMOS circuit, a first back-side metal line is coupled to a signal transmission metal line, and a second back-side metal line is coupled to a power rail.

[0023] In another exemplary form of the CMOS circuit, the CMOS circuit also includes: a second signal transmission metal line electrically coupled to another circuit; a top-side metal contact in contact with one of the P-type source, P-type drain and first gate; and a top-side metal line disposed above the first gate, the top-side metal line being electrically coupled to the top-side metal contact and the second signal transmission metal line.

[0024] In another exemplary configuration of the CMOS circuit, the CMOS circuit also includes: a second signal transmission metal line electrically coupled to another circuit; a top-side metal contact in contact with one of the N-type source, N-type drain and second gate; and a top-side metal line disposed above the second gate, the top-side metal line being electrically coupled to the top-side metal contact and the second signal transmission metal line.

[0025] In another exemplary embodiment of the CMOS circuit, the CMOS circuit also includes: a second power rail having a second longitudinal axis parallel to the first longitudinal axis; a third back-side metal contact contacting one of the N-type source, N-type drain, and second gate; and a third back-side metal line disposed below the substrate, the third back-side metal line being electrically coupled to the second power rail. In this further embodiment, another exemplary embodiment includes: a power rail disposed adjacent to the N-type diffusion region; a second power rail disposed adjacent to the P-type diffusion region; a first back-side metal contact contacting the P-type source; a second back-side metal contact contacting the N-type drain; a third back-side metal contact contacting the N-type source; a first back-side metal line coupled to the power rail; a second back-side metal line coupled to a signal transmission metal line; a third back-side metal line coupled to the second power rail; and a signal transmission metal line disposed between the first power rail and the second power rail. In another exemplary configuration, another exemplary configuration includes a second back-side metal contact, the second back-side metal contact including a second back-side metal contact top surface and a second back-side metal contact bottom surface, and a via, the second back-side metal contact top surface contacting the N-type drain bottom surface, the via including a via top surface contacting the second back-side metal contact bottom surface.

[0026] In another exemplary configuration of a CMOS circuit, a first back-side metal contact includes a vertical interconnect channel (via) that contacts one of a P-type source, a P-type drain, and a first gate, and a second back-side metal contact includes a second via that contacts one of an N-type source, an N-type drain, and a second gate.

[0027] In another exemplary embodiment of the CMOS circuit, the CMOS circuit also includes: a substrate including a top surface and a bottom surface of the substrate; a buried oxide (BOX) layer disposed on the top surface of the substrate, wherein a first back-side metal line is disposed below the bottom surface of the substrate, a second back-side metal line is disposed below the bottom surface of the substrate, a P-type source is configured to contact the BOX layer, a P-type drain is configured to contact the BOX layer, an N-type source is configured to contact the BOX layer, and an N-type drain is configured to contact the BOX layer. In this further exemplary embodiment, in another exemplary embodiment, at least one of the following is true: a P-type source extends through the BOX layer such that the bottom surface of the P-type source contacts the top surface of the substrate; and a P-type drain extends through the BOX layer such that the bottom surface of the P-type drain contacts the top surface of the substrate; and at least one of the following is true: an N-type source extends through the BOX layer such that the bottom surface of the N-type source contacts the top surface of the substrate; and an N-type drain extends through the BOX layer such that the bottom surface of the N-type drain contacts the top surface of the substrate. In another exemplary embodiment, the first back-side metal contact includes a first via, which has a top surface that contacts one of a P-type source bottom surface, a P-type drain bottom surface, and a first gate bottom surface. The second back-side metal contact includes a second via, which has a top surface that contacts one of an N-type source bottom surface, an N-type drain bottom surface, and a second gate bottom surface. In yet another exemplary embodiment, the first via is in contact with the substrate, and the second via is also in contact with the substrate.

[0028] In another exemplary configuration of a CMOS circuit, a first back-side metal contact includes a first back-side metal contact top surface that contacts one of a P-type source bottom surface, a P-type drain bottom surface, and a first gate bottom surface. The first back-side metal contact also includes a first back-side metal contact bottom surface and a first via, the first via including a first via top surface that contacts the first back-side metal contact bottom surface. A second back-side metal contact also includes a second back-side metal contact top surface and a second back-side metal contact bottom surface, and a second via, the second back-side metal contact top surface contacting one of an N-type source bottom surface, an N-type drain bottom surface, and a second gate bottom surface, the second via including a second via top surface that contacts the second back-side metal contact bottom surface. In another exemplary embodiment, the first back-side metal contact is in contact with the buried oxide (BOX) layer, the first via is in contact with the substrate, the second back-side metal contact is in contact with the BOX layer, and the second via is in contact with the substrate. In yet another exemplary embodiment, one of the P-type source bottom surface, the P-type drain bottom surface, and the first gate bottom surface that contacts the top surface of the first back-side metal contact of the first back-side metal contact is in contact with the top surface of the BOX layer, and one of the N-type source bottom surface, the N-type drain bottom surface, and the second gate bottom surface that contacts the top surface of the second back-side metal contact of the second back-side metal contact is in contact with the top surface of the BOX layer.

Implementation Method

[0038] Several exemplary embodiments of this case are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or advantageous to other embodiments.

[0039] The embodiments disclosed herein include field-effect transistor (FET) circuits that employ top-side and back-side contacts for top-side and back-side wiring of FET power and logic signals. Related complementary metal-oxide-semiconductor (CMOS) circuits employing FETs are also disclosed, which employ top-side and back-side contacts for top-side and back-side wiring of FET power and logic signals. In this embodiment, certain exemplary embodiments disclosed herein provide a FET circuit including a conductive channel, a source, a drain, and a gate. The conductive channel is disposed above a substrate. The source is disposed in a first end of the conductive channel. The drain is disposed in a second end of the conductive channel. The gate is disposed above at least a portion of the conductive channel and between the first and second ends of the conductive channel. The FET circuit also includes at least one top-side metal contact contacting at least one top surface of the source, drain, and gate of the FET. The FET circuit also includes at least one back-side metal contact contacting at least one bottom surface of the source, drain, and gate of the FET. The FET circuit also includes top-side metal lines and back-side metal lines electrically coupled to respective top-side and back-side metal contacts to provide power and signal routing to the FET. At least one of the top-side and back-side metal lines is electrically coupled to a power rail configured to carry a power signal, and at least one of the other top-side and back-side metal lines is electrically coupled to a signal transmission metal line configured to carry a logic signal.

[0040] In this manner, the back-side wiring on the FET circuit provides additional area for signal and / or power wiring, which can advantageously offset, for example, any reduction in wiring area due to factors such as a reduction in FET size and / or an increase in the complexity of the circuit including the FET circuit. Increased signal wiring congestion causes metal lines in the top-side interconnect layer to be positioned closer together, thereby increasing the parasitic capacitance of the wiring lines and thus increasing the capacitance of the FET. The increased capacitance on the FET reduces the performance of the FET.

[0041] In this example, Figures 1A and 1B are respectively a cross-sectional side view and a bottom view of an exemplary FET circuit 100, which includes a FET 102. The drain 104D of the FET 102 contacts a top-side metal contact 106 for top-side wiring, and the source 104S of the FET 102 contacts a back-side metal contact 108 for back-side wiring. Figure 1A is a cross-sectional side view of the FET circuit 100 in Figure 1B along the A1-A1' section line. As shown in Figures 1A and 1B, the back-side metal contact 108 is disposed in the FET circuit 100 and contacts a back-side metal line 110 to allow signal wiring to the FET 102 from the back side of the FET 102 below the substrate 112 in the Z-axis direction. In this example, the back-side metal line 110 is below the substrate 112 in the Z-axis direction, as shown in Figure 1A. Similarly, as shown in FIG1A, a top-side metal contact 106 is disposed in the FET circuit 100 and contacts a top-side metal line 114 to allow top-side wiring signals of the FET 102 in the Z-axis direction from above the gate 104G of the FET 102. For example, a back-side metal line 110 may be electrically coupled to a power rail 116 configured to carry a power signal from a power source, such that the back-side metal line 110 receives the power signal and couples it to the source 104S of the FET 102 via a back-side metal contact 108. As another example, the top-side metal line 114 may be electrically coupled to a signal transmission metal line 118 in an interconnect layer 119 above the FET 102, the signal transmission metal line 118 being configured to carry a logic signal to couple the logic signal to the drain 104D of the FET 102 via the top-side metal contact 106. In another example, the back metal line 110 may be electrically coupled to a signal transmission metal line configured to carry logic signals, and the top metal line 114 may be electrically coupled to a power rail configured to carry power signals from a power source.

[0042] In this manner, the back-side wiring to FET 102 provides additional area for signal and / or power wiring to FET 102, which can advantageously offset any reduction in wiring area in FET circuit 100 due to factors such as reduced FET node size and / or increased complexity of circuitry including FET circuit 100. Increased signal wiring congestion causes metal lines in interconnect layer 119 of FET circuit 100 to be positioned closer together, thereby increasing the parasitic capacitance of the wiring lines and thus increasing the capacitance of the FET including FET 102. The increased capacitance on the FET in FET circuit 100 reduces the performance of the FET.

[0043] In this example, FET 102 in Figures 1A and 1B is a full-ring gate (GAA) FET. However, note that as other non-limiting examples, FET 102 can be a planar FET or a FinFET. A GAA FET is also called a ring-gate transistor (SGT), and its concept is similar to that of a FinFET, except that the gate material surrounds the channel region on all sides. A FinFET is a multi-gate device, a type of MOSFET (metal-oxide-semiconductor field-effect transistor). FinFETs are built on a substrate, with the gate placed on two, three, or more faces of the channel to form a multi-gate structure. A planar FET includes a conductive channel formed in a substrate, with the gate placed above the conductive channel and an insulating material between them. FET 102 includes a conductive channel 120 disposed above a substrate 112 in the Z-axis direction, the substrate 112 being a bulk substrate in this example. A plurality of nanostructures 122(1) to 122(3) (e.g., nanowires or nanoplates) are provided, which may be formed from substrate 112 and made of a semiconductor material capable of conducting current in response to an electric field. The substrate is a self-supporting substrate. FET 102 includes a source 104S disposed in a first end 124(1) of conductive channel 120. In this example, since the backside metal line 110 is below substrate 112 in the Z-axis direction, the backside metal line 110 is also below conductive channel 120, because FET 102 in this example is a GAA FET, wherein conductive channel 120 is disposed above substrate 112. For example, if FET circuit 100 includes planar FET, wherein conductive channel is disposed below gate and in substrate, the backside metal line may be below conductive channel 120 of planar FET, but may not be completely below substrate.

[0044] The FET also includes a drain 104D, which is disposed in the X-axis direction in a second end 124(2) of the conductive channel 120 opposite to the first end 124(1). A gate 104G is disposed above at least a portion of the conductive channel 120 between the first end 124(1) and the second end 124(2). In this example, the gate 104G includes a gate material surrounding each of the nanostructures 122(1) to 122(3) of the conductive channel 120. In this way, a voltage applied between the gate 104G and the source 104S of the FET 102 can generate an electric field in the conductive channel 120, which is sufficient to cause the nanostructures 122(1) to 122(3) of the conductive channel 120 to conduct current between the source 104S and the drain 104D.

[0045] Continuing to refer to FIG1A, in this example, the source 104S has a source top surface 126T and a source bottom surface 126B, and the drain 104D has a drain top surface 128T and a drain bottom surface 128B. For example, the source 104S and drain 104D may have been epitaxially grown on the substrate 112 or formed via implantation into the substrate 112. In this example, the top-side metal contact 106 contacts the drain top surface 128T of the drain 104D of the FET 102 to provide a connection between the drain 104D and the top-side metal line 114. For example, the top-side metal contact 106 may be a conductive post or a vertical interconnect channel (via) connecting the drain top surface 128T to the top-side metal line 114. For example, the top-side metal contact 106 can be a silicon via (TSV) or other via with a diameter small enough to connect the drain top surface 128T to the top-side metal line 114 without interfering with adjacent wiring areas. Similarly, in this example, the back-side metal contact 108 contacts the source bottom surface 126B of the source 104S of the FET 102 to provide a connection between the source 104S and the back-side metal line 110. For example, the back-side metal contact 108 can be a conductive post or via connecting the source bottom surface 126B to the back-side metal line 110. For example, the back-side metal contact 108 can be a TSV or other via with a diameter small enough to connect the source bottom surface 126B to the back-side metal line 110. The back-side metal line 110 does not interfere with adjacent wiring areas.

[0046] Note that although the FET 102 in Figures 1A and 1B illustrates a source 104S connected to a back-side metal line 110 for back-side wiring to the source 104S, and a drain 104D connected to a top-side metal line 114 for top-side wiring to the drain 104D, this is not limiting. As another example, the drain 104D may be connected to the back-side metal line 110 for back-side wiring to the drain 104D, and the source 104S may be connected to the top-side metal line 114 for top-side wiring to the source 104S. Furthermore, if desired, the source 104S and / or drain 104D of the FET may be connected via top-side and back-side wiring for signal and / or power wiring. Additionally, the gate 104G of the FET 102 may be connected to a top-side metal contact and / or a back-side metal contact to provide gate connections to the top-side and / or back-side metal lines for signal and / or power wiring. The gate 104G of FET 102 includes a gate top surface 130T that can be connected to a top-side metal contact and a gate bottom surface 130B that can be connected to a back-side metal contact to provide top-side and / or back-side wiring to the gate 104G.

[0047] As an example, a FET circuit (FET circuit 100 in Figures 1A and 1B) including back-side and / or top-side metal contacts for back-side and / or top-side signal routing can be disposed in a complementary metal-oxide-semiconductor (CMOS) circuit to form logic circuits and gates. In this case, Figure 2 is a top view of an exemplary CMOS circuit 200, which may be included in a semiconductor die 201 and includes a FET circuit 203 having a FET, which may be similar to FET circuits 100 and FET 102 in Figures 1A and 1B. The FET circuit includes one or more back-side metal contacts for back-side routing of power and / or signals to the FET. The FET may also include one or more top-side metal contacts for top-side routing of power and / or signals to the FET. In this example, the CMOS circuit 200 includes a positive (P)-type diffusion region 202P in a semiconductor substrate 204 ("substrate 204") and a negative (N)-type diffusion region 202N formed in the substrate 204. For example, the P-type diffusion region 202P can be formed by doping a portion of the substrate 204 with an impurity material capable of leaving pores in the substrate 204. The N-type diffusion region 202N can be formed by doping a portion of the substrate 204 with an impurity material as a donor material, which can release free electrons in the substrate 204. A PFET can be formed in the CMOS circuit 200 by forming a P-type source and a P-type drain in the N-type diffusion region 202N. An NFET can be formed in the CMOS circuit 200 by forming an N-type source and an N-type drain in the P-type diffusion region 202P. A diffusion interruption 207 is provided between the P-type diffusion region 202P and the N-type diffusion region 202N to provide electrical isolation.

[0048] As shown in FIG2, a P-type conductive channel 206P and an N-type conductive channel 206N are formed in a CMOS circuit 200 above a substrate 204 and extend along the longitudinal axes LC(P) and LC(N) in the X-axis direction. Gates G(1) to G(4) are formed in the CMOS circuit 200 along the longitudinal axes LG(1) to LG(4) in the Y-axis direction. The longitudinal axes LG(1) to LG(4) are orthogonal to the longitudinal axes LC(P) and LC(N) of the P-type conductive channel 206P and the N-type conductive channel 206N in the X-axis direction, and the gates G(1) to G(4) extend above and around at least a portion of the P-type conductive channel 206P and the N-type conductive channel 206N. Gates G(1) and G(4) are active gates of conductive materials, such as metals (referred to herein as "active gates" G(1) or G(4)), and gates G(2) and G(3) are dummy gates of dielectric materials (referred to herein as "dummy gates" G(2) or G(3)). An active gate is a gate that forms part of the FET and is used to control the electric field in the channel region when a sufficient voltage is applied to the gate. A dummy gate is a structure of gate material that is not part of the FET but is placed on the edge of a circuit cell to electrically isolate one circuit cell from adjacent circuit cells.

[0049] As shown in FIG2, a PFET 208P (such as a GAA PFET) is formed in the N-type diffusion region 202N by forming a P-type source SP and a P-type drain DP on the opposite side of the active gate G(1) in the N-type diffusion region 202N. Similarly, as shown in FIG2, an NFET 208N (such as a GAA NFET) is formed in the P-type diffusion region 202P by forming an N-type source SN and an N-type drain DN on the opposite side of the active gate G(1) in the P-type diffusion region 202P.

[0050] Continuing to refer to FIG2, in this example, a P-type conductive channel 206P and an N-type conductive channel 206N are disposed on the top surface 210 of the substrate 204. According to the layout of the circuit unit, gates G(1) to G(4) are adjacent to each other and have a gate spacing PG. For example, the active gate G(1) is adjacent to the dummy gate G(2). The dummy gate G(2) is disposed between the active gate G(1) and the dummy gate G(3) and adjacent to the active gate G(1) and the dummy gate G(3). In this example, for example, the active gates G(1) and G(4) extend around at least a portion of the P-type conductive channel 206P and the N-type conductive channel 206N to form a FET, such as a FinFET or a gate-all-around (GAA) FET. As shown in FIG2, a gate contact CG(P) is formed above a portion of the active gate G(1) to form an active gate GA(P) for the PFET 208P. Similarly, a gate contact CG(N) is formed above a portion of the active gate G(1) to form the active gate GA(N) for the NFET 208N. The P-type source SP and P-type drain DP of the PFET 208P are formed on opposite sides of the active gate G(1) in the first end 212(1) and the second end 212(2) of the P-type conductive channel 206P, wherein the gate contact CG(P) is formed above the active gate G(1). The N-type source SN and N-type drain DN of the NFET 208N are formed on opposite sides of the active gate G(1) in the first end 214(1) and the second end 214(2) of the N-type conductive channel 206N, wherein the gate contact CG(N) is formed above the active gate G(1).

[0051] Exemplary procedures 300 for forming the FET circuits 100 and 203 in Figures 1A to 2 are provided in Figures 3A and 3B. Procedure 300 is described with reference to the FET circuit 100 in Figures 1A to 1B, but is also applicable to the FET circuit 203 in Figure 2 and its PFET 208P and NFET 208N. In this case, procedure 300 includes forming a FET 102 (block 302 in Figure 3A). Forming the FET 102 includes forming a conductive channel 120 (block 304 in Figure 3A) over a substrate 112. Forming the FET 102 also includes forming a source 104S disposed in a first end 124(1) of the conductive channel 120, the source 104S including a source top surface 126T and a source bottom surface 126B (block 306 in Figure 3A). Forming the FET 102 also includes forming a drain 104D disposed in a second end 124(2) of the conductive channel 120 opposite to the first end 124(1), the drain 104D including a drain top surface 128T and a drain bottom surface 128B (block 308 in FIG. 3A). Forming the FET 102 also includes forming a gate 104G disposed above at least a portion of the conductive channel 120 and between the first end 124(1) and the second end 124(2) of the conductive channel 120, the gate 104G including a gate top surface 130T and a gate bottom surface 130B (block 310 in FIG. 3A).

[0052] Continuing to refer to Figures 3A and 3B, forming the FET circuit 100 also includes forming a top-side metal contact 106 (block 312 in Figure 3A) that contacts one of the source top surface 126T, the drain top surface 128T, and the gate top surface 130T. Forming the FET circuit 100 also includes forming a back-side metal contact 108 (block 314 in Figure 3A) that contacts one of the source bottom surface 126B, the drain bottom surface 128B, and the gate bottom surface 130B. Forming the FET circuit 100 also includes forming a top-side metal line 114 (block 316 in Figure 3B) that is disposed above the gate 104G and electrically contacts the top-side metal contact 106. Forming the FET circuit 100 also includes forming a back-side metal line 110 (block 318 in Figure 3B) that is disposed below the conductive channel 120 and electrically contacts the back-side metal contact 108. The FET circuit 100 also includes forming a signal transmission metal line 118, which is configured to carry a logic signal and is in contact with one of the top-side metal line 114 and the back-side metal line 110 (block 320 in FIG. 3B). The FET circuit 100 also includes forming a power rail 116, which is configured to carry a power signal from a power source and is in contact with one of the back-side metal line 110 and the top-side metal line 114 that is not in contact with the signal transmission metal line 118 (block 322 in FIG. 3B).

[0053] Different variations of the CMOS circuit including back-side and / or top-side wiring for power and / or signals are possible. For example, Figures 4A and 4B illustrate corresponding cross-sectional side and bottom views of another exemplary CMOS circuit 400 including FET circuits 402(1) to 402(3), which respectively include PFETs 404P(1) to 404P(3) formed in an N-type diffusion region 406N and NFETs 404N(1) to 404N(3) formed in a P-type diffusion region 406P (as shown in Figure 4B). These PFETs and NFETs have a shared drain and employ back-side wiring for source and drain connections. Figure 4A is a cross-sectional side view of the CMOS circuit 400 in Figure 4B along section line A4-A4'. The FET circuit 402(1), comprising PFET 404P(1) and NFET 404N(1), will now be discussed as an example, but this example is also applicable to FET circuits 402(2) and 402(3). In this example, PFET 404P(1) and NFET 404N(1) are GAA FETs, but note that, as other non-limiting examples, PFET 404P(1) and NFET 404N(1) can be planar FETs or FinFETs. PFET 404P(1) includes a P-type conductive channel 408P(1), and NFET 404N(1) includes an N-type conductive channel 408N(1), both of which are disposed above substrate 410 in the Z-axis direction, as shown in FIG4A. In this example, PFET 404P(1) and NFET 404N(1) are semiconductor-on-insulator (SOI) FETs disposed on a buried oxide (BOX) layer 412 disposed on a substrate 410. The P-type conductive channel 408P(1) and N-type conductive channel 408N(1) are made of a plurality of corresponding nanostructures 414P, 414N (e.g., nanowires or nanosheets) made of semiconductor material to conduct current in response to an electric field. In semiconductor manufacturing, an SOI FET is a FET fabricated as a semiconductor element within a layered silicon-insulator substrate to reduce parasitic capacitance within the element, thereby improving performance. SOI-based elements differ from conventional silicon-based elements in that the silicon junction is located above an electrically insulating material, which can be silicon dioxide or sapphire. The choice of insulator largely depends on the intended application. BOX layer 412 is an oxide layer in an SOI substrate (such as SiO2) buried in a silicon wafer.

[0054] Continuing to refer to Figures 4A and 4B, the PFET 404P(1) in the FET circuit 402(1) includes a P-type source 416S(1), which is disposed in the BOX layer 412 in the N-type diffusion region 406N in the first end 418(1) of the P-type conductive channel 408P(1) and extends through the BOX layer 412. The PFET 404P(1) also includes a P-type drain 416D(1), which is disposed in the BOX layer 412 in the N-type diffusion region 406N on the second end 418(2) of the P-type conductive channel 408P(1) opposite to the first end 418(1) in the X-axis direction and extends through the BOX layer 412. For example, the P-type source 416S(1) and P-type drain 416D(1) may have been epitaxially grown on the substrate 410 or formed by implantation into the substrate 410. The PFET 404P(1) also includes a gate 420G(1) disposed on the BOX layer 412 and above at least a portion of the P-type conductive channel 408P(1) between the first end 418(1) and the second end 418(2). In this example, the gate 420G(1) is made of a gate material surrounding each of the nanostructures 414P of the P-type conductive channel 408P(1). In this way, the voltage applied between the gate 420G(1) and the P-type source 416S(1) of the PFET 404P(1) can generate an electric field in the P-type conductive channel 408P(1), which is sufficient to cause the nanostructure 414P of the P-type conductive channel 408P(1) to conduct current between the P-type source 416S(1) and the P-type drain 416D(1).

[0055] As shown in the bottom view of the CMOS circuit 400 in FIG4B, the NFET 404N(1) in the FET circuit 402(1) includes an N-type source 422S(1), which is disposed in the BOX layer 412 in the P-type diffusion region 406P in the first end 424(1) of the N-type conductive channel 408N(1) and extends through the BOX layer 412. The NFET 404N(1) also includes an N-type drain 422D(1), which is disposed in the BOX layer 412 in the P-type diffusion region 406P in the second end 424(2) of the N-type conductive channel 408N(1) opposite to the first end 424(1) in the X-axis direction and extends through the BOX layer 412. For example, the N-type source 422S(1) and N-type drain 422D(1) may have been epitaxially grown on the substrate 410 or formed by implantation into the substrate 410. In this example, the drains 416D(1) and 422D(1) of the corresponding PFET 404P(1) and NFET 404N(1) are coupled together. The NFET 404N(1) also includes a gate 426G(1) disposed on the BOX layer 412 and above at least a portion of the N-type conductive channel 408N(1) between the first end 424(1) and the second end 424(2). In this example, the gate 426G(1) is composed of a gate material of each of the nanostructures 414N surrounding the N-type conductive channel 408N(1). In this way, the voltage applied between the gate 426G(1) and the N-type source 422S(1) of the NFET 404N(1) can generate an electric field in the N-type conductive channel 408N(1), which is sufficient to cause the nanostructure 414N of the N-type conductive channel 408N(1) to conduct current between the N-type source 422S(1) and the N-type drain 422D(1).

[0056] Continuing to refer to Figures 4A and 4B, in this example, the P-type source 416S(1) of the PFET 404P has a source top surface 428T(1) and a source bottom surface 428B(1), and the P-type drain 416D(1) has a drain top surface 430T(1) and a drain bottom surface 430B(1). As shown in Figure 4A, the source bottom surface 428B(1) and the drain bottom surface 430B(1) are in contact with the top surface 438 of the substrate 410. In this example, the back metal contact 432(1) is in contact with the source bottom surface 428B(1) of the P-type source 416S(1) of the PFET 404P(1) to provide a connection between the P-type source 416S(1) and the back metal line 434(1) adjacent to the N-type diffusion region 406N, as shown in Figure 4B. As shown in FIG4A, the back metal contact 432(1) also contacts the top surface 438 of the substrate 410. The back metal line 434(1) extends along the longitudinal axis LA1 in the X-axis direction. In this example, as shown in FIG4A, the back metal line 434(1) is disposed below the bottom surface 450 of the substrate 410 of the CMOS circuit 400 in the Z-axis direction. For example, the back metal contact 432(1) may be a conductive post or via that connects the source bottom surface 428B(1) to the back metal line 434(1). For example, the back metal contact 432(1) may be small enough in diameter to connect the source bottom surface 428B(1) to the back metal line 434(1) without interfering with the TSV or other vias in adjacent wiring areas. For example, the backside metal line 434(1) can be a power rail, such as a positive power rail configured to carry a power signal, or it can be coupled to power rail 442, as shown in another top perspective view of the CMOS circuit 400 in FIG4C, to carry a power signal. In this way, in this example, the power signal can be routed from the backside of the substrate 410 and coupled to the P-type source 416S(1) of the PFET 404P(1).

[0057] In addition, in this example, the back metal contact 432(2) contacts the bottom surface 430B(1) of the drain 416D(1) of the P-type drain 416D(1) of the PFET 404P(1) to provide a connection between the P-type drain 416D(1) and the back metal line 434(2), as shown in FIG4B. The back metal contact 432(2) also contacts the top surface 438 of the substrate 410. The back metal line 434(2) extends along the longitudinal axis LA2 in the X-axis direction parallel to the longitudinal axis LA1 of the back metal line 434(1). As shown in FIG4A, the back metal line 434(2) is disposed below the bottom surface 450 of the substrate 410 of the CMOS circuit 400 in the Z-axis direction. For example, the back metal contact 432(2) may be a conductive post or via connecting the bottom surface 430B(1) of the drain to the back metal line 434(2). For example, the back-side metal contact 432(2) may be small enough to connect the drain bottom surface 430B(1) to the back-side metal line 434(2) without interfering with TSVs or other vias in adjacent wiring areas. For example, the back-side metal line 434(2) may be a signal transmission metal line for carrying logic signals to or from another circuit, or it may be coupled to a signal transmission metal line 446, as shown in another top perspective view of the CMOS circuit 400 in FIG4C, to carry logic signals. In this way, in this example, logic signals can be routed from the back side of the substrate 410 and coupled to the P-type drain 416D(1) of the PFET 404P(1).

[0058] Continuing to refer to Figures 4A and 4B, in this example, the N-type source 422S(1) of the NFET 404N has a source bottom surface 436B(1), and the N-type drain 422D(1) has a drain bottom surface 440B(1). As shown in Figure 4A, the source bottom surface 436B(1) and the drain bottom surface 440B(1) are in contact with the top surface 438 of the substrate 410. In this example, the back metal contact 432(3) is in contact with the source bottom surface 436B(1) of the N-type source 422S(1) of the NFET 404N(1) to provide a connection between the N-type source 422S(1) and the back metal line 434(3) adjacent to the P-type diffusion region 406P, as shown in Figure 4B. The back metal contact 432(3) is also in contact with the top surface 438 of the substrate 410. The back metal line 434(3) extends along the longitudinal axis LA3 parallel to the longitudinal axes LA1 and LA2 of the back metal lines 434(1) and 434(2) in the X-axis direction. In this example, the back metal line 434(3) is provided such that the back metal line 434(2) is disposed between the back metal lines 434(1) and 434(3) in the Y-axis direction. As shown in FIG4A, the back metal line 434(3) is disposed below the bottom surface 450 of the substrate 410 of the CMOS circuit 400 in the Z-axis direction. For example, the back metal contact 432(3) may be a conductive post or via that connects the source bottom surface 436B(1) to the back metal line 434(3). For example, the back metal contact 432(1) may be small enough in diameter to connect the source bottom surface 436B(1) to the back metal line 434(3) without interfering with the TSV or other vias in the adjacent wiring area. As an example, the backside metal line 434(3) may be a second power rail, such as a negative power rail or ground, or coupled to a second power rail 444, as shown in another top perspective view of the CMOS circuit 400 in Figure 4C.

[0059] Furthermore, in this example, the back-side metal contact 432(2) contacts the bottom surface 440B(1) of the drain 422D(1) of the N-type drain 404N(1) to provide a connection between the N-type drain 422D(1) and the back-side metal line 434(2), as shown in FIG4B. As mentioned above, in this example, the P-type drain 416D(1) of the PFET 404P(1) and the N-type drain 422D(1) of the NFET 404N(1) are coupled together.

[0060] Note that although the PFET 404P(1) and NFET 404N(1) in Figures 4A and 4B are illustrated with their sources 416S(1) and 422S(1) connected to back-side metal lines 434(1) and 434(3) for back-side wiring, and their drains 416D(1) and 422D(1) connected to back-side metal line 434(2) for back-side wiring, this is not limiting. As another example, the sources 416S(1) and / or 422S(1) may be connected to the top-side metal line 448(1), as shown in the side perspective view of the CMOS circuit 400 in Figure 4D, for additional or only top-side wiring. The same applies to the drains 416D(1) and / or 422D(1) of the PFET 404P(1) and NFET 404N(1). Furthermore, if necessary, the sources 416S(1), 422S(1) and / or drains 416D(1), 422D(1) of the PFET 404P(1) and NFET 404N(1) can be connected via top-side and back-side wiring for signal and / or power wiring. Additionally, the gates 420G(1), 426G(1) of the PFET 404P(1) and NFET 404N(1) can also be connected to back-side metal contacts and / or top-side metal contacts to provide gate connections to top-side and / or back-side metal lines for signal and / or power wiring. Also note that the FET circuits 402(2) and 402(3) shown in Figures 4A and 4B can also include back-side and / or top-side wiring, just like the FET circuit 402(1).

[0061] Therefore, in this manner, the back-side wiring to the FET circuit 402(1) in Figures 4A to 4D provides additional area for signal and / or power wiring to the PFET 404P(1) and NFET 404N(1), which can advantageously be used to offset any reduction in wiring area in the CMOS circuit 400 due to factors such as the reduction in FET node size and / or the increase in circuit complexity including the CMOS circuit 400. Furthermore, the back-side wiring is compatible with existing manufacturing methods for providing the fabrication of the CMOS circuit 400, as additional top-side wiring may not be required.

[0062] Figures 5A and 5B illustrate corresponding cross-sectional side and bottom views of another exemplary CMOS circuit 500 including FET circuits 502(1) to 502(3), which respectively include PFETs 504P(1) to 504P(3) formed in the N-type diffusion region 406N and NFETs 504N(1) to 504N(3) formed in the P-type diffusion region 406P, similar to the PFETs 404P(1) to 404P(3) and NFETs 404N(1) to 404N(3) in the FET circuits 402(1) to 402(3) in Figures 4A and 4B. Figure 5A is a cross-sectional side view of the CMOS circuit 500 in Figure 5B along the section line A5-A5'. The common components between the CMOS circuit 400 in Figures 4A and 4B and the CMOS circuit 500 in Figures 5A and 5B are illustrated with the same component numbers, and the discussion of these common components in Figures 4A to 4D applies to Figures 5A and 5B. However, in the FET circuit 502(1) in Figures 5A and 5B, the corresponding drains 516D(1) and 522D(1) of the PFET 504P(1) and NFET 504N(1) do not extend into the BOX layer 412, but extend to the top surface 550 of the BOX layer 412. As will be discussed below, the back-side metal contacts of the drains 516D(1) and 522D(1) of the PFET 504P(1) and NFET 504N(1) include a first back-side metal contact 554(1), as shown in FIG5A. The first back-side metal contact 554(1) extends below both drains 516D(1) and 522D(1) in the Z-axis direction. A via 552(1) connects the first back-side metal contact 554(1) to a back-side metal line 434(2) for back-side wiring to drains 516D(1) and 522D(1).

[0063] As shown in FIG5B, in this example, the back metal contact 532(2) contacts the bottom surface 530B(1) of the drain of the P-type drain 516D(1) of PFET 504P(1) and the bottom surface 540B(1) of the drain of the N-type drain 522D(1) of NFET 504N(1) to provide a connection between the P-type drain 516D(1) and the N-type drain 522D(1) and the back metal line 434(2), as shown in FIG5B. In this example, the back metal contact 532(2) consists of a first back metal contact 554(1) connected to a via 552(1) connected to the back metal line 434(2). The first back metal contact 554(1) provides a metal contact to provide a connection with the shared P-type drain 516D(1) and N-type drain 522D(1). The top surface 556T(1) of the first back-side metal contact 554(1) contacts the bottom surfaces 530B(1) and 540B(1) of the drains 516D(1) and 522D(1). The bottom surface 556B(1) of the first back-side metal contact 554(1) contacts the top surface 558T(1) of the via 552(1). The bottom surface 558B(1) of the via 552(1) contacts the back-side metal line 434(2). The via 552(1) may be small enough to connect the first back-side metal contact 554(1) to the back-side metal line 434(2) without interfering with TSVs or other vias in adjacent wiring areas.

[0064] Figures 6A and 6B illustrate corresponding cross-sectional side and bottom views of another exemplary CMOS circuit 600 including FET circuits 502(1) to 502(3), which respectively include NFETs 504N(1) to 504N(3) formed in N-type diffusion region 406N and PFETs 504P(1) to 504P(3) formed in P-type diffusion region 406P, similar to Figures 5A and 5B. Figure 6A is a cross-sectional side view of the CMOS circuit 600 in Figure 6B along section line A6-A6'. Common elements between the CMOS circuits 500 in Figures 5A and 5B and the CMOS circuit 600 in Figures 6A and 6B are illustrated with the same element numbers. However, as shown in Figures 6A and 6B, the gate 660G is also connected to the back metal line 434(2), which is also connected to the corresponding drains 516D(1) and 522D(1) of the PFET 504P(1) and NFET 504N(1). The gate 660G does not extend into the BOX layer 412, but extends to the top surface 550 of the BOX layer 412.

[0065] As shown in Figures 6A and 6B, in this example, the back-side metal contact 662 contacts the bottom surface 664B of the gate of the gate 660G. In this example, the back-side metal contact 662 is composed of a first back-side metal contact 666 connected to a via 668 connected to a back-side metal line 434(2). The first back-side metal contact 666 is provided as part of the back-side metal contact 662 to provide a metal contact for providing a connection to the gate 660G. The top surface 668T of the first back-side metal contact 666 contacts the bottom surface 664B of the gate of the gate 660G. As shown in Figure 6A, the bottom surface 670B of the first back-side metal contact 666 contacts the top surface 672T of the via 668. The bottom surface 672B of the via 668 contacts the back-side metal line 434(2). Via 668 may be small enough to connect the first back-side metal contact 666 to the back-side metal line 434(2) without interfering with TSVs or other vias in adjacent wiring areas. The above discussion of the back-side metal contacts and vias in Figures 1A to 1B and Figures 4A to 5B also applies to the first back-side metal contact 666 and via 668 in Figures 6A to 6B.

[0066] It should be noted that the terms “top” and “bottom” used in this document are relative terms and are not intended to restrict or imply that “top” referenced elements must always be strictly oriented above “bottom” referenced elements, and vice versa.

[0067] Any type of FET disclosed herein may be provided in or integrated into any processor-based device, such FET employing back-side contacts for back-side wiring of power and / or logic signals to the FET, including but not limited to the FETs in Figures 1A to 1B, Figure 2, Figures 4A to 4D, Figures 5A to 5B and Figures 6A to 6B, and wherein the FET may be included in CMOS circuitry including back-side contacts for back-side wiring of power and logic signals to the FET, including but not limited to the CMOS circuitry in Figures 2, 4A to 4D, Figures 5A to 5B and Figures 6A to 6B. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablets, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0068] In this embodiment, FIG. 7 illustrates an example of a processor-based system 700 comprising FETs among various elements of the system according to any embodiment disclosed herein. These FETs employ back-side contacts for back-side wiring of power and / or logic signals to the FETs, including but not limited to the FETs in FIG. 1A-1B, FIG. 2, FIG. 4A-4D, FIG. 5A-5B, and FIG. 6A-6B. The FETs may be included in CMOS circuitry, which includes back-side contacts for back-side wiring of power and logic signals to the FETs, including but not limited to the CMOS circuitry in FIG. 2, FIG. 4A-4D, FIG. 5A-5B, and FIG. 6A-6B. In this example, the processor-based system 700 may be configured as an IC 704 as a System-on-Chip (SoC) 706. The processor-based system 700 includes a CPU 708, which includes one or more processors 710, which may also be referred to as CPU cores or processor cores. CPU 708 may have cache memory 712 coupled to CPU 708 for fast access to temporarily stored data. CPU 708 is coupled to system bus 714, which interconnects master and slave devices included in the processor-based system 700. As is known, CPU 708 communicates with these other devices by exchanging address, control, and data information on system bus 714. For example, CPU 708 may transmit bus transaction requests to memory controller 716, which is an instance of a slave device. Although not shown in Figure 7, multiple system buses 714 may be provided, each with a different configuration.

[0069] Other master and slave devices may be connected to system bus 714. As shown in FIG7, such devices may, for example, include a memory system 720, which includes a memory controller 716 and multiple memory arrays 718, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728. Each of the memory system 720, the one or more input devices 722, the one or more output devices 724, the one or more network interface devices 726, and the one or more display controllers 728 may include a FET. The multiple input devices 722 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The multiple output devices 724 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The multiple network interface devices 726 may be any device configured to allow data exchange with network 730. Network 730 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. Network interface device 726 can be configured to support any type of communication protocol required.

[0070] The CPU 708 can also be configured to access (multiple) display controllers 728 via system bus 714 to control information sent to one or more displays 732. The display controllers 728 send information to (multiple) displays 732 for display via one or more video processors 734, which process the information to be displayed into a format suitable for (multiple) displays 732. The displays 732 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0071] FIG8 illustrates an exemplary wireless communication device 800 according to any of the types disclosed herein. The wireless communication device 800 includes radio frequency (RF) elements formed by one or more ICs 802, wherein any one of the ICs 802 may include FETs, which employ back-side contacts for back-side wiring of power and / or logic signals to the FETs, including but not limited to the FETs in FIG1A-1B, FIG2, FIG4A-4D, FIG5A-5B and FIG6A-6B, and wherein the FETs may be included in CMOS circuitry, which includes back-side contacts for back-side wiring of power and logic signals to the FETs, including but not limited to the CMOS circuitry in FIG2, FIG4A-4D, FIG5A-5B and FIG6A-6B.

[0072] As shown in FIG8, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. Typically, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0073] The transmitter 808 or receiver 810 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages, for example, from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 800 in Figure 8, the transmitter 808 and receiver 810 are implemented using a direct conversion architecture.

[0074] In the transmission path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) to convert digital signals generated by the data processor 806 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0075] Within transmitter 808, low-pass filters 814(1) and 814(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1) and 816(2) amplify the signals from low-pass filters 814(1) and 814(2), respectively, and provide I and Q baseband signals. Upconverter 818 uses the I and Q transmission (TX) local oscillator (LO) signals from TX LO signal generator 822 via mixers 820(1) and 820(2) to upconvert the I and Q baseband signals to provide upconverted signals 824. Filter 826 filters upconverted signals 824 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 828 amplifies upconverted signals 824 from filter 826 to obtain the desired output power level and provides the transmitted RF signal. The RF signal is transmitted via a duplexer or switch 830 and via an antenna 832.

[0076] In the receiving path, antenna 832 receives signals transmitted from the base station and provides received RF signals, which are routed via duplexer or switch 830 and provided to low-noise amplifier (LNA) 834. Duplexer or switch 830 is designed to operate at a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Down-conversion mixers 838(1) and 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q fundamental frequency signals are amplified by amplifiers (AMPs) 842(1) and 842(2) and further filtered by low-pass filters 844(1) and 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, data processor 806 includes ADCs 846(1) and 846(2) to convert the analog input signals into digital signals for further processing by data processor 806.

[0077] In the wireless communication device 800 of Figure 8, the TX LO signal generator 822 generates I and Q TX LO signals for up-conversion, while the RX LO signal generator 840 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 822. The RX PLL circuit 850 receives timing information from the data processor 806 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 840.

[0078] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the various forms disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. For example, the master and slave devices described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the various illustrative elements, blocks, modules, circuits, and steps have been described in general for the functional forms above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as leading outside the scope of this document.

[0079] The various illustrative logic blocks, modules, and circuits described in connection with the various forms disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, individual hardware element, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any known processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0080] The various embodiments disclosed herein can be implemented as hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as separate components in a remote station, base station, or server.

[0081] It should also be noted that the operational steps described in any of the exemplary forms herein are for the purpose of providing examples and discussion. The described operations can be performed in many different orders other than those shown. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary forms can be combined. It should be understood that the operational steps illustrated in the flowcharts can be modified in many different ways, which will be clear to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and skills. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0082] The foregoing description of this invention is provided to enable those skilled in the art to make or use the invention. Various modifications to this invention will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, the invention is not intended to be limited to the examples and designs described herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Simplified Explanation of the Diagram]

[0029] Figures 1A and 1B are respectively a cross-sectional side view and a bottom view of an exemplary field-effect transistor (FET) circuit, which includes a FET having a gate, a source and a drain. The FET circuit also includes a top-side metal contact and a back-side metal contact. The top-side metal contact is in contact with the drain and electrically coupled to a top-side metal line, and the back-side metal contact is in contact with the source and electrically coupled to a back-side metal line.

[0030] FIG2 is a top view of an exemplary complementary metal-oxide-semiconductor (CMOS) circuit, which includes FET circuits similar to the FET circuits in FIG1A and FIG1B. The FET circuits include back-side metal contacts for power and / or signal routing to the FET circuits, wherein the FET circuits may include positive (P) type FETs (PFETs) and negative (N) type FETs (NFETs) for forming logic circuits.

[0031] Figures 3A and 3B are flowcharts illustrating exemplary procedures for manufacturing the FET in the FET circuits of Figures 1A and 1B and Figure 2;

[0032] Figures 4A and 4B respectively illustrate a cross-sectional side view and a bottom view of an exemplary CMOS circuit, which includes a FET circuit having a PFET and an NFET, wherein the FET circuit includes a PFET and an NFET, each of the PFET and NFET including a source back-side metal contact that contacts the bottom surface of its respective source electrically coupled to a corresponding power metal line, and wherein the FET circuit also includes a drain back-side metal contact that is electrically coupled to the bottom surface of a common drain that extends through a buried oxide (BOX) layer and is electrically coupled to a signal transmission metal line;

[0033] Figures 4C and 4D respectively illustrate the top and bottom perspective views of the FET circuit in Figures 4A and 4B;

[0034] Figures 5A and 5B respectively illustrate a cross-sectional side view and a bottom view of an exemplary CMOS circuit, which includes a FET circuit having a semiconductor-on-insulator (SOI) PFET and an NFET, wherein the FET circuit includes a PFET and an NFET, each of the PFET and NFET including a source backside metal contact that contacts the bottom surface of its respective source extending through the BOX layer and electrically coupled to the respective power metal line, and wherein the FET circuit also includes a common drain backside metal contact line electrically coupled to the signal transmission metal line and electrically coupled to the bottom surface of the respective drain of the PFET and NFET;

[0035] Figures 6A and 6B respectively illustrate a cross-sectional side view and a bottom view of an exemplary CMOS circuit, which includes a FET circuit having a semiconductor-on-insulator (SOI) PFET and an NFET, wherein the FET circuit includes a PFET and an NFET, each of the PFET and NFET including a source back-side metal contact that contacts the bottom surface of its respective source extending through the BOX layer and electrically coupled to a respective power metal line, and wherein the FET circuit also includes a common drain back-side metal contact line electrically coupled to a signal transmission metal line and electrically coupled to the bottom surface of the respective drains of the PFET and NFET, and wherein the FET circuit also includes a gate back-side metal contact that is electrically coupled to the bottom surface of the gate and electrically coupled to the back-side metal contact line;

[0036] FIG7 is a block diagram of an exemplary processor-based system, which may include a FET, wherein power and / or logic signals are back-side wired to the FET using back-side contacts, including but not limited to the FETs in FIG1A-1B, FIG2, FIG4A-4D, FIG5A-5B and FIG6A-6B, and wherein the FET may be included in a CMOS circuit, the CMOS circuit including back-side contacts for back-side wiring of power and logic signals to the FET, including but not limited to the CMOS circuits in FIG2, FIG4A-4D, FIG5A-5B and FIG6A-6B; and

[0037] FIG8 is a block diagram of an exemplary wireless communication device, which includes radio frequency (RF) elements formed by FETs, the FETs employing back-side contacts to back-side route power and / or logic signals to the FETs, including but not limited to the FETs in FIG1A to FIG1B, FIG2, FIG4A to FIG4D, FIG5A to FIG5B and FIG6A to FIG6B, and wherein the FETs may be included in CMOS circuitry, the CMOS circuitry including back-side contacts for back-side routing power and logic signals to the FETs, including but not limited to the CMOS circuitry in FIG2, FIG4A to FIG4D, FIG5A to FIG5B and FIG6A to FIG6B. [Biomaterial Storage]

[0084] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A field-effect transistor (FET) circuit, comprising: A signal transmission metal line is configured to carry logic signals; An electric rail is configured to carry an electrical signal from a power source; A FET includes: a conductive channel disposed above a substrate; a source disposed in a first end of the conductive channel, the source including a source top surface and a source bottom surface; a drain disposed in a second end of the conductive channel opposite to the first end, the drain including a drain top surface and a drain bottom surface; and a gate disposed above at least a portion of the conductive channel and between the first end and the second end of the conductive channel, the gate including a gate top surface and a gate bottom surface; a top-side metal contact contacting one of the source top surface, the drain top surface, and the gate top surface; and a back-side metal contact contacting one of the source bottom surface, the drain bottom surface, and the gate bottom surface. A top-side metal wire is disposed above the gate, and the top-side metal wire is electrically coupled to one of the signal transmission metal wire and the power rail and the top-side metal contact; and a back-side metal wire is disposed below the conductive channel, and the back-side metal wire is electrically coupled to one of the power rail and the signal transmission metal wire that is not coupled to the top-side metal wire and the back-side metal contact.

2. The FET circuit according to claim 1, wherein the back-side metal contact includes a vertical interconnect channel (via) in contact with one of the source bottom surface, the drain bottom surface and the gate bottom surface.

3. The FET circuit according to claim 1 also includes: A second back-side metal contact is in contact with one of the source bottom surface, the drain bottom surface, and the gate bottom surface that is not in contact with the back-side metal contact; A second back-side metal line is disposed below the conductive channel, and the second back-side metal line is electrically coupled to the second back-side metal contact and the signal transmission metal line.

4. The FET circuit according to request item 3, wherein: The back-side metal contact is in contact with the bottom surface of the source electrode; and the second back-side metal contact is in contact with the bottom surface of the drain electrode.

5. The FET circuit according to request item 3, wherein: The back-side metal contact is in contact with the bottom surface of the drain electrode; and the second back-side metal contact is in contact with the bottom surface of the source electrode.

6. The FET circuit according to claim 3, wherein: The conductive channel extends along a first longitudinal axis between the first end and the second end of the conductive channel; the back metal wire extends along a second longitudinal axis parallel to the first longitudinal axis; and the second back metal wire extends along a third longitudinal axis parallel to the second longitudinal axis.

7. The FET circuit according to claim 1 also includes: The substrate includes a top surface and a bottom surface; a buried oxide (BOX) layer is disposed on the top surface of the substrate; a back-side metal line is disposed below the bottom surface of the substrate; a source electrode is configured to contact the BOX layer; and a drain electrode is configured to contact the BOX layer.

8. The FET circuit according to claim 7, wherein at least one of the following: the source extends through the BOX layer such that the bottom surface of the source contacts the top surface of the substrate; and the drain extends through the BOX layer such that the bottom surface of the drain contacts the top surface of the substrate.

9. The FET circuit according to request item 8, wherein: The back-side metal contact includes a vertical interconnect channel (via) that includes a via top surface that contacts one of the source bottom surface and the drain bottom surface.

10. The FET circuit according to claim 9, wherein the via is in contact with the substrate.

11. The FET circuit according to claim 7, wherein the back-side metal contact includes: A top surface of a back-side metal contact and a bottom surface of a back-side metal contact, the top surface of the back-side metal contact contacting one of the bottom surfaces of the source, the drain, and the gate; and a vertical interconnect channel (via) including a top surface of the via in contact with the bottom surface of the back-side metal contact.

12. The FET circuit according to request item 11, wherein: The back metal contact contacts the BOX layer; and the via contacts the substrate.

13. The FET circuit according to claim 11, wherein: One of the source bottom surface, the drain bottom surface, and the gate bottom surface that are in contact with the top surface of the back metal contact is in contact with the top surface of the BOX layer.

14. The FET circuitry of claim 1, integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular phone; a smartphone; a SIP phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multi-rotor aircraft.

15. The FET circuit according to claim 1 is integrated into a semiconductor die.

16. A method of manufacturing a field-effect transistor (FET) circuit, comprising the steps of: forming a FET, comprising the steps of: forming a conductive channel over a substrate; forming a source electrode disposed in a first end of the conductive channel, the source electrode including a source top surface and a source bottom surface; forming a drain electrode disposed in a second end of the conductive channel opposite to the first end, the drain electrode including a drain top surface and a drain bottom surface; and forming a gate electrode disposed over at least a portion of the conductive channel and between the first end and the second end of the conductive channel, the gate electrode including a gate top surface and a gate bottom surface; forming a top-side metal contact contacting one of the source top surface, the drain top surface, and the gate top surface; and forming a back-side metal contact contacting one of the source bottom surface, the drain bottom surface, and the gate bottom surface. A top-side metal line is formed, which is disposed above the gate and electrically contacts the top-side metal contact; a back-side metal line is formed, which is disposed below the conductive channel and electrically contacts the back-side metal contact; a signal transmission metal line is formed, which is configured to contact one of the top-side metal line and the back-side metal line to carry a logic signal; and a power rail is formed, which is configured to contact one of the back-side metal line and the top-side metal line that is not in contact with the signal transmission metal line to carry a power signal from a power source.

17. The method of claim 16, wherein the step of forming the back-side metal contact includes the following steps: forming a vertical interconnect channel (via), the vertical interconnect channel (via) including a via top surface in contact with one of the source bottom surface, the drain bottom surface and the gate bottom surface.

18. The method according to claim 16 also includes the steps of: forming the substrate, the substrate including a top surface and a bottom surface; and forming a buried oxide (BOX) layer on the top surface of the substrate; wherein: The step of forming the back metal line also includes the following steps: forming the back metal line below the bottom surface of the substrate; The steps of forming the source electrode also include the following steps: forming the source electrode in contact with the BOX layer; The process of forming the absorber also includes the following steps: forming the absorber in contact with the BOX layer.

19. The method of claim 18, wherein the step of forming the source electrode also includes the following steps: forming the source electrode to extend through the BOX layer such that the bottom surface of the source electrode contacts the top surface of the substrate.

20. The method of claim 18, wherein the step of forming the drain also includes the following steps: forming the drain to extend through the BOX layer such that the bottom surface of the drain contacts the top surface of the substrate.

21. The method of claim 18, wherein the step of forming the back metal contact also includes the following steps: forming a back metal contact top surface and a back metal contact bottom surface, the back metal contact top surface contacting one of the source bottom surface, the drain bottom surface and the gate bottom surface; and forming a vertical interconnect channel (via), the vertical interconnect channel (via) including a via top surface contacting the back metal contact bottom surface.

22. A complementary metal-oxide-semiconductor (CMOS) circuit, comprising: A positive (P) type diffusion region is disposed in a substrate; A negative (N) type diffusion region is disposed in the substrate; An electric rail having a first longitudinal axis set in a first direction; a signal transmission metal wire electrically coupled to another circuit; A P-type field-effect transistor (FET) is formed in the N-type diffusion region. The PFET includes: a P-type conductive channel; a P-type source disposed in a first end of the P-type conductive channel; a P-type drain disposed in a second end of the P-type conductive channel opposite to the first end; and a first gate disposed above at least a portion of the P-type conductive channel and between the first end and the second end of the P-type conductive channel. An N-type field-effect transistor (NFET) is formed in the P-type diffusion region. The NFET includes: an N-type conductive channel; an N-type source disposed in a first end of the N-type conductive channel; an N-type drain disposed in a second end of the N-type conductive channel opposite to the first end; and a second gate disposed above at least a portion of the N-type conductive channel and between the first end and the second end of the N-type conductive channel. A first back-side metal contact is in contact with one of the P-type source, the P-type drain, and the first gate; a second back-side metal contact is in contact with one of the N-type source, the N-type drain, and the second gate; a first back-side metal line is disposed below the substrate and electrically coupled to the first back-side metal contact; a second back-side metal line is disposed below the substrate and electrically coupled to the second back-side metal contact; the first back-side metal line is coupled to one of the power rail and the signal transmission metal line; and the second back-side metal line is coupled to one of the signal transmission metal line and the power rail that is not coupled to the first back-side metal line.

23. The CMOS circuit according to request item 22, wherein: The P-type source includes a P-type source top surface and a P-type source bottom surface; the P-type drain includes a P-type drain top surface and a P-type drain bottom surface; the first gate includes a first gate top surface and a first gate bottom surface; the N-type source includes an N-type source top surface and an N-type source bottom surface; the N-type drain includes an N-type drain top surface and an N-type drain bottom surface; the second gate includes a second gate top surface and a second gate bottom surface; the first back-side metal contact is in contact with one of the P-type source bottom surface, the P-type drain bottom surface, and the first gate bottom surface; and the second back-side metal contact is in contact with one of the N-type source bottom surface, the N-type drain bottom surface, and the second gate bottom surface.

24. The CMOS circuit according to request item 22, wherein: The first back-side metal wire is coupled to the power rail; and the second back-side metal wire is coupled to the signal transmission metal wire.

25. The CMOS circuit according to request item 22, wherein: The first back-side metal wire is coupled to the signal transmission metal wire; and the second back-side metal wire is coupled to the power rail.

26. The CMOS circuitry according to claim 22 also includes: A second signal transmission metal wire is electrically coupled to another circuit; A top-side metal contact is in contact with one of the P-type source, the P-type drain, and the first gate; and a top-side metal line is disposed above the first gate, the top-side metal line being electrically coupled to the top-side metal contact and the second signal transmission metal line.

27. The CMOS circuit according to claim 22 also includes: A second signal transmission metal line is electrically coupled to another circuit; a top-side metal contact is in contact with one of the N-type source, the N-type drain, and the second gate; and a top-side metal line is disposed above the second gate, the top-side metal line being electrically coupled to the top-side metal contact and the second signal transmission metal line.

28. The CMOS circuit according to claim 23 also includes: A second power rail having a second longitudinal axis parallel to the first longitudinal axis; a third back-side metal contact in contact with one of the N-type source, the N-type drain and the second gate; and a third back-side metal line disposed below the substrate, the third back-side metal line being electrically coupled to the third back-side metal contact and the second power rail.

29. The CMOS circuit according to request item 28, wherein: The power rail is positioned adjacent to the N-type diffusion region; the second power rail is positioned adjacent to the P-type diffusion region; the first back-side metal contact is in contact with the P-type source; the second back-side metal contact is in contact with the N-type drain; the third back-side metal contact is in contact with the N-type source; the first back-side metal line is coupled to the power rail; the second back-side metal line is coupled to the signal transmission metal line; and the signal transmission metal line is positioned between the first power rail and the second power rail.

30. The CMOS circuit according to claim 29, wherein the second back-side metal contact includes: A second back-side metal contact top surface and a second back-side metal contact bottom surface, wherein the second back-side metal contact top surface is in contact with the N-type drain bottom surface; and a vertical interconnect channel (via), including a via top surface that contacts the bottom surface of the second back metal contact.

31. The CMOS circuit according to request item 22, wherein: The first back-side metal contact includes a vertical interconnect channel (via) that contacts one of the P-type source, the P-type drain, and the first gate; and the second back-side metal contact includes a second via that contacts one of the N-type source, the N-type drain, and the second gate.

32. The CMOS circuit according to claim 23 also includes: The substrate includes a top surface and a bottom surface; a buried oxide (BOX) layer is disposed on the top surface of the substrate; and a first back-side metal line is disposed below the bottom surface of the substrate. The second back-side metal line is disposed below the bottom surface of the substrate; The P-type source is configured to contact the BOX layer; The P-type drain is configured to contact the BOX layer; the N-type source is configured to contact the BOX layer; and the N-type drain is configured to contact the BOX layer.

33. The CMOS circuit according to request item 32, wherein: At least one of the following: the P-type source extends through the BOX layer such that the bottom surface of the P-type source contacts the top surface of the substrate; and the P-type drain extends through the BOX layer such that the bottom surface of the P-type drain contacts the top surface of the substrate; and at least one of the following: the N-type source extends through the BOX layer such that the bottom surface of the N-type source contacts the top surface of the substrate; and the N-type drain extends through the BOX layer such that the bottom surface of the N-type drain contacts the top surface of the substrate.

34. According to the CMOS circuit of request item 23, wherein: The first back-side metal contact includes a first vertical interconnect channel (via), the first vertical interconnect channel (via) including a via top surface that contacts one of the P-type source bottom surface, the P-type drain bottom surface and the first gate bottom surface; and the second back-side metal contact includes a second via, the second via including a second via top surface that contacts one of the N-type source bottom surface, the N-type drain bottom surface and the second gate bottom surface.

35. The CMOS circuit according to request item 34, wherein: The first via is in contact with the substrate; and the second via is in contact with the substrate.

36. The CMOS circuit according to request item 32, wherein: The first back-side metal contact includes: a first back-side metal contact top surface and a first back-side metal contact bottom surface, the first back-side metal contact top surface contacting one of the P-type source bottom surface, the P-type drain bottom surface and the first gate bottom surface; and a first vertical interconnect channel (via), including a first via top surface contacting the first back-side metal contact bottom surface; and the second back-side metal contact includes: a second back-side metal contact top surface and a second back-side metal contact bottom surface, the second back-side metal contact top surface contacting one of the N-type source bottom surface, the N-type drain bottom surface and the second gate bottom surface; and a second via, including a second via top surface contacting the second back-side metal contact bottom surface.

37. The CMOS circuit according to request item 36, wherein: The first back-side metal contact contacts the BOX layer; the first via contacts the substrate; the second back-side metal contact contacts the BOX layer; and the second via contacts the substrate.

38. The CMOS circuit according to request item 37, wherein: One of the bottom surfaces of the P-type source electrode, the bottom surface of the P-type drain electrode, and the bottom surface of the first gate electrode that is in contact with the top surface of the first back-side metal contact of the first back-side metal contact is in contact with the top surface of the BOX layer; and one of the bottom surfaces of the N-type source electrode, the bottom surface of the N-type drain electrode, and the bottom surface of the second gate electrode that is in contact with the top surface of the second back-side metal contact of the second back-side metal contact is in contact with the top surface of the BOX layer of the BOX layer.

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