Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2021-08-02
- Publication Date
- 2022-08-16
Smart Images
Figure TWG2TA000870687_001 
Figure TWG2TA000870687_002 
Figure TWG2TA000870687_003
Abstract
Description
[Technical Field]
[0001] The field of this case relates to unit circuits that employ a circuit unit architecture for the formation of semiconductor elements, including field-effect transistors (FETs) and complementary metal-oxide-semiconductor (CMOS) integrated circuits, which employ P-type FETs (PFETs) and N-type FETs (NFETs) to form logic circuits. [Previous Technology]
[0002] Transistors are essential components in modern electronic devices. Many integrated circuits (ICs) in modern electronic devices use a large number of transistors. For example, components such as central processing units (CPUs), digital signal processors (DSPs), and memory systems use a large number of transistors for logic circuits and memory devices.
[0003] One type of transistor is the field-effect transistor (FET). FETs use an electric field to control the flow of current between the source and drain. The flow of current is controlled by applying a voltage to the gate of the FET, which in turn changes the conductivity between the source and drain. Different types of FETs include planar FETs, FinFETs (FinFETs), and gate-all-around (GAA) FETs. In an IC employing a FET, the IC includes source metal contacts, drain metal contacts, and gate metal contacts formed to contact the corresponding source, drain, and gate of the FET to provide signal routing to the FET. The metal contacts are then connected to metal lines in the interconnect layer of the IC, which is above the semiconductor layer or active layer of the IC including the FET, for routing signals to the source, drain, and gate of the FET via the source, drain, and gate metal contacts. For example, if a circuit employing a FET needs to couple a power signal to the source of the FET, the source contact is connected to a metal line designed to carry power. As another example, if a circuit using a FET needs to couple logic signals to the drain of the FET, the drain contact is connected to a metal line designed to carry the logic signal.
[0004] As the node size of circuits using FETs in an IC decreases to save area and / or allow more FETs to be fabricated within a given area or wafer size, the gate spacing between adjacent FETs can also be reduced. This reduces the distance between the source and drain of adjacent FETs in the IC, which increases wiring congestion in the interconnect layer above the FETs used for signal routing. Increased signal routing congestion can cause metal lines in the interconnect layer to be arranged closer together, thus increasing the parasitic capacitance of the wiring and therefore increasing the capacitance of the FET. The increased capacitance on the FET can reduce the performance of the FET. [Summary of the Invention]
[0005] The embodiments disclosed herein include circuits employing a back-side-front-side connection structure for coupling back-side wiring to front-side wiring. Related complementary metal-oxide-semiconductor (CMOS) circuits and methods are also disclosed. For example, the circuit may include cell circuits fabricated according to a circuit cell architecture to support the fabrication of semiconductor devices such as field-effect transistors (FETs). In an exemplary embodiment, the circuit includes a semiconductor device. The circuit also includes front-side metal lines in a metallization structure arranged adjacent to the front side of the semiconductor device, wherein the front-side metal lines are configured to be coupled to the semiconductor device (e.g., coupled to the gate, source, and / or drain of the FET) to provide front-side signal routing for power signals or logic signals to the semiconductor device. The circuit also includes rear-side metal lines arranged adjacent to the rear side of the semiconductor device, wherein the rear-side metal lines are configured to be coupled to the semiconductor device (e.g., coupled to the gate, source, and / or drain of the FET) to provide rear-side routing for power signals or logic signals. In this way, the area on the back side of the semiconductor element can be advantageously used for signal routing to save area and / or reduce wiring complexity.
[0006] In another exemplary embodiment, the circuit also includes a rear-to-front connection structure that electrically couples front-side metal lines to rear-side metal lines for coupling rear-side routing to front-side routing. The rear-to-front connection structure is used to substantially "lift" signals routed in rear-side routing to front-side metal lines in the circuit. The rear-to-front connection structure can "lift" rear-side-routed signals to front-side metal lines in the desired front-side metal layer of the circuit. In this way, greater routing flexibility can be provided by being able to route signals routed on the rear side of the circuit to the front side of the circuit, or vice versa. For example, if power is routed on the rear side, but the circuit only supports front-side routing, the rear-to-front connection structure allows power to be routed from the rear side of the circuit to the front side. As another example, if a circuit is connected to a power signal source or a logic signal source via its package and via front and rear interconnects (e.g., bumps), a rear-to-front connection structure can be used to couple the front and rear routes of the signals to achieve enhanced signal routing integrity and / or redundancy.
[0007] In another exemplary embodiment, the back-to-front connection structure can be a conductive vertical interconnect (via), such as a through-silicon via (TSV), configured to extend through the semiconductor layer of the semiconductor element and couple the front metal line to the back metal line. If desired or desired, the front metal line coupled to the back-to-front connection structure can also be routed to a higher metal layer in the metallization structure for higher metal layer routing. Furthermore, in another exemplary embodiment, the back-to-front connection structure can be formed adjacent to a dummy gate so as not to interfere with other routing in the circuit. For example, the region adjacent to an adjacent dummy gate on an adjacent edge of an adjacent circuit and / or the region between such adjacent dummy gates may be unrouted or have reduced routing. This is also referred to as "blank space". A dummy gate is part of an active semiconductor element but is formed on the edge of the circuit to electrically isolate the circuit from adjacent circuits. In this way, the back-to-front connection structure is arranged adjacent to the dummy gate because the "blank space" does not interfere with another active semiconductor element formed in the circuit. Arranging the rear-to-front connection structure adjacent to the dummy gate in the circuit can also avoid, for example, the need to expand the circuit layout to provide the area for the rear-to-front connection structure without interfering with the wiring of the active semiconductor elements.
[0008] In another exemplary embodiment, a CMOS circuit is provided, comprising a substrate having a top surface, a positive (P)-type diffusion region disposed in the substrate, and a negative (N)-type diffusion region disposed in the substrate. At least one P-type FET (PFET) is formed in the P-type diffusion region, and at least one N-type FET (NFET) is formed in the N-type diffusion region. Each of the PFET and NFET in the CMOS circuit includes a conductive channel disposed on the front side of the substrate, a source disposed at a first end of its conductive channel, a drain disposed at a second end of its conductive channel, and a gate disposed adjacent to its conductive channel. The CMOS circuit includes at least one front-side metal line disposed adjacent to the front side of the diffusion region in the metallization structure, wherein the front-side metal line is configured to couple to at least one of the PFET and NFET (e.g., coupled to its gate, source, and / or drain) for providing front-side signal routing for power signals or logic signals. The CMOS circuit also includes a rear-side metal line disposed adjacent to the rear side of the diffusion region, wherein the rear-side metal line is configured to be coupled to at least one of the PFET and NFET (e.g., coupled to its gate, source, and / or drain) to provide rear-side routing for power signals or logic signals. The CMOS circuit also includes a rear-side-front-side connection structure that electrically couples the front-side metal line to the rear-side metal line to enable routing signals routed on the rear side of the CMOS circuit to the front side of the CMOS circuit, or vice versa.
[0009] In this regard, in one exemplary embodiment, a circuit is provided. The circuit includes a semiconductor element having a front side and a rear side, and has a metallization structure arranged adjacent to the front side of the semiconductor element, the metallization structure including a front side metal line. The circuit also includes a rear side metal line arranged adjacent to the rear side of the semiconductor element, the rear side metal line being coupled to the semiconductor element, and further includes a rear-side-front connection structure coupling the rear side metal line to the front side metal line.
[0010] In another exemplary embodiment, a method of manufacturing a circuit is provided. The method includes: forming a semiconductor element on a substrate, the semiconductor element including a front side and a rear side disposed adjacent to the substrate; and forming a metallization structure adjacent to the front side of the semiconductor element, the metallization structure including a front side metal line. The method further includes: forming a rear side metal line adjacent to the rear side of the semiconductor element, coupling the rear side metal line to the semiconductor element; and forming a rear-side-front-side connection structure coupling the rear side metal line to the front side metal line.
[0011] In another exemplary embodiment, a CMOS circuit is provided. The CMOS circuit includes a PFET, an NFET, and a metallization structure disposed adjacent to the front side of at least one of the PFET and NFET, the metallization structure including a front metal line. The CMOS circuit also includes a rear metal line disposed adjacent to the rear side of at least one of the NFET and PFET, the rear metal line being coupled to at least one of the NFET and PFET, and further includes a rear-side-front connection structure coupling the rear metal line to the front metal line.
Implementation Method
[0022] Several exemplary embodiments of this case are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
[0023] The embodiments disclosed herein include circuits employing a back-side-front-side connection structure for coupling back-side wiring to front-side wiring. Related complementary metal-oxide-semiconductor (CMOS) circuits and methods are also disclosed. For example, the circuit may include cell circuits fabricated according to a circuit cell architecture to support the fabrication of semiconductor devices such as field-effect transistors (FETs). In an exemplary embodiment, the circuit includes a semiconductor device. The circuit also includes front-side metal lines in a metallization structure arranged adjacent to the front side of the semiconductor device, wherein the front-side metal lines are configured to be coupled to the semiconductor device (e.g., coupled to the gate, source, and / or drain of the FET) to provide front-side signal routing for power signals or logic signals to the semiconductor device. The circuit also includes rear-side metal lines arranged adjacent to the rear side of the semiconductor device, wherein the rear-side metal lines are configured to be coupled to the semiconductor device (e.g., coupled to the gate, source, and / or drain of the FET) to provide rear-side routing for power signals or logic signals. In this way, the area on the back side of the semiconductor element can be advantageously used for signal routing to save area and / or reduce wiring complexity.
[0024] In another exemplary embodiment, the circuit also includes a rear-to-front connection structure that electrically couples front-side metal lines to rear-side metal lines for coupling rear-side routing to front-side routing. The rear-to-front connection structure is employed to substantially "boost" signals routed in rear-side routing to front-side metal lines in the circuit. The rear-to-front connection structure can "boost" rear-side routed signals to front-side metal lines in a desired front-side metal layer of the circuit. In this way, greater routing flexibility can be provided by being able to route signals routed on the rear side of the circuit to the front side of the circuit, or vice versa. For example, if power is routed on the rear side, but the circuit only supports front-side routing, the rear-to-front connection structure allows power to be routed from the rear side of the circuit to the front side. As another example, if a circuit is connected to a power signal source or a logic signal source via its package and via front and rear interconnects (e.g., bumps), a rear-to-front connection structure can be used to couple the front and rear routes of the signals to achieve enhanced signal routing integrity and / or redundancy.
[0025] In this regard, Figures 1A and 1B are corresponding cross-sectional side and top views of an exemplary circuit 100. Figure 1A is a cross-sectional side view of the circuit 100 in Figure 1B along the section line A1-A1'. As will be discussed in more detail below, the circuit 100 includes a rear wiring 102B on the rear side 104B of the circuit 100. The circuit 100 also includes a front wiring 102F on the front side 104F of the circuit 100. The circuit 100 also includes a rear-to-front connection structure 106 that couples a rear metal line 108B in the rear wiring 102B on the rear side 104B to a front metal line 108F in the metallization structure 109 in the front wiring 102F on the front side 104F. The front metal line 108F may be in any metal layer of the metallization structure, but in this example, the front metal line 108F is in metal layer one (M1). For example, the rear-to-front connection structure 106 can be a vertical interconnect path (via) 110, such as a through-silicon via (TSV). The rear-to-front connection structure 106 is employed to substantially "boost" signals routed in the rear metal line 108B of the rear wiring 102B to the front metal line 108F of the front wiring 102F in the circuit 100. The rear-to-front connection structure 106 can "boost" rear-routed signals to couple to the front metal line 108F.
[0026] In this way, greater wiring flexibility can be provided by enabling signals routed in the rear side 104B of circuit 100 to the front side 104F of circuit 100, or vice versa. For example, if power is routed rear-side, but a particular device within circuit 100 only supports front-side wiring 102F, the rear-to-front connection structure 106 allows power to be routed from the rear side 102B of the device to the front side 102F. As another example, if circuit 100 is connected to a power signal source or logic signal source via its package and via front and rear interconnects (e.g., bumps), the rear-to-front connection structure 106 can be used to couple the front-side routes 102F and rear-side routes 102B of signals to obtain enhanced signal routing integrity and / or redundancy. Furthermore, as discussed in more detail below, in one example, the rear-to-front connection structure 106 may be located in a "blank space" of circuit 100 in which no other semiconductor element is formed and therefore no wiring or wiring reduction is used to utilize the additional area to elevate the rear wiring 102B to the front wiring 102F.
[0027] In this example, circuit 100 is a CMOS circuit 112 including semiconductor element 114, which in this example includes FET 116. As shown in FIG1A, semiconductor element 114 has a front side 104F and a rear side 104B. FIG1A illustrates a side view of PFET 116P in circuit 100. FIG1B illustrates a top view of PFET 116P and NFET 116N in circuit 100. As shown in FIG1B, PFET 116P is formed in a negative (N)-type diffusion region 118N in circuit 100, and NFET 116N is formed in a positive (P)-type diffusion region 118P in circuit 100, as shown in FIG1A and FIG1B. For example, the N-type diffusion region 118N can be formed by doping a portion of the semiconductor substrate using a pentavalent impurity material as a donor material capable of releasing free electrons in the substrate. The P-type diffusion region 118P can be formed by doping a portion of the semiconductor substrate with an impurity material capable of leaving holes in the substrate. A P-type source and a P-type drain are formed in the N-type diffusion region 118N to form a PFET 116P in the CMOS circuit 112. An N-type source and an N-type drain are formed in the P-type diffusion region 118P to form an NFET 116N in the CMOS circuit 112. As shown in FIG1B, a diffusion interruption 119 is provided between the P-type diffusion region 118P and the N-type diffusion region 118N to provide electrical isolation between them. In this example, PFET 116P and NFET 116N are GAA FETs; however, it should be noted that, as other non-limiting examples, PFET 116P and NFET 116N can be planar FETs or FinFETs. Circuit 100 is formed in semiconductor die 120. As shown in Figures 1A and 1B, the PFET 116P includes a P-type conductive channel 122P. In this example, the rear side 104B of the PFET 116P is disposed above and adjacent to the substrate 124 in the Z-axis direction. In this example, the front side 104F of the PFET 116P is disposed adjacent to the metallization structure 109 of the circuit 110 in the Z-axis direction. As shown in Figure 1B, the NFET 116N includes an N-type conductive channel 122N, which is disposed above the substrate 124 in the Z-axis direction as shown in Figure 1B. In this example, as shown in Figure 1A, the PFET 116P and NFET 116N are semiconductor-on-insulator (SOI) FETs disposed on a buried oxide (BOX) layer 126 disposed on the substrate 124.Taking the PFET 116P in Figure 1A as an example, the P-type conductive channel 122P is made of a plurality of corresponding nanostructures 128P (e.g., nanowires or nanosheets) made of semiconductor material, capable of conducting current in response to an electric field. In semiconductor manufacturing, SOI FETs are FETs fabricated from semiconductor elements within a layered insulator-silicon substrate to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-based devices in that the silicon junction is above an electrically insulating material, which can be silicon dioxide or sapphire. The choice of insulator largely depends on the intended application. The BOX layer 126 is an oxide layer, such as SiO2, in the SOI substrate, which is buried at a certain depth within the silicon wafer.
[0028] Continuing to refer to Figures 1A and 1B, taking PFET 116P as an example, PFET 116P in circuit 100 includes a P-type source 130S, which is disposed at the first end 132(1) of the P-type conduction channel 122P in the BOX layer 126 in the N-type diffusion region 118N and extends through the BOX layer 126. PFET 116P also includes a P-type drain 130D, which is disposed at the second end 132(2) of the P-type conduction channel 122P in the BOX layer 126 in the P-type diffusion region 118P and extends through the BOX layer 126. The second end 132(2) is opposite to the first end 132(1) in the X-axis direction. For example, the P-type source 130S and P-type drain 130D can be epitaxially grown on the substrate 124 or formed as implants into the substrate 124. The PFET 116P also includes a P-type gate 130G disposed on the BOX layer 126 and above at least a portion of the P-type conductive channel 122P between the first end 132(1) and the second end 132(2). In this example, the P-type gate 130G is composed of gate material surrounding each nanostructure 128P of the P-type conductive channel 122P. In this way, the voltage applied between the P-type gate 130G and the P-type source 130S of the PFET 116P can generate an electric field in the P-type conduction channel 122P that is sufficient to conduct current between the nanostructure 128P of the P-type conduction channel 122P and the P-type source 130S and the P-type drain 130D of the PFET 116P.
[0029] Similarly, as shown in the top view of circuit 100 in FIG1B, the NFET 116N in CMOS circuit 112 includes an N-type source 134S, which is disposed at a first end 136 (1) of the N-type conductive channel 122N in a BOX layer 126 in a P-type diffusion region 118P and extends through the BOX layer 126. The NFET 116N also includes an N-type drain 134D, which is disposed at a second end 136 (2) of the N-type conductive channel 122N in a BOX layer 126 in a P-type diffusion region 118P and extends through the BOX layer 126. The second end 136 (2) is opposite to the first end 136 (1) in the X-axis direction. For example, the N-type source 134S and the N-type drain 134D may have been epitaxially grown on a substrate 124 or formed as implants into the substrate 124. The NFET 116N also includes an N-type gate 134G disposed on the BOX layer 126 and above at least a portion of the N-type conductive channel 122N between the first end 136(1) and the second end 136(2). In this example, the N-type gate 134G is made of a gate material with a nanostructure surrounding the N-type conductive channel 122N. In this way, a voltage applied between the N-type gate 134G and the N-type source 134S of the NFET 116N can generate an electric field in the N-type conductive channel 122N sufficient to conduct current between the N-type source 134S and the N-type drain 134D of the NFET 116N.
[0030] Referring to FIG1A, in this example, the P-type source 130S of the PFET 116P has a source top surface 138T on the front side 104F and a source bottom surface 138B adjacent to the rear side 104B. The P-type drain 130D has a drain top surface 140T on the front side 104F and a drain bottom surface 140B adjacent to the rear side 104B. The source bottom surface 138B and the drain bottom surface 140B are in contact with the top surface 142 of the substrate 124. In this example, the rear metal contact 144 contacts the source bottom surface 138B of the P-type source 130S of the PFET 116P to provide connectivity between the P-type source 130S and the rear metal line 108B. The rear metal contact 144 is also in contact with the top surface 142 of the substrate 124. The rear metal line 108B is disposed below the bottom surface 146 of the substrate 124. For example, the rear metal contact 144 may be a conductive post or via that connects the rear metal contact 144 to the rear metal line 108B. For example, the rear metal contact 144 may be a TSV or other via with a sufficiently small diameter to connect the rear metal contact 144 to the rear metal line 108B without interfering with adjacent wiring areas. For example, the rear metal line 108B may be a power rail (such as a positive power rail) configured to carry a power signal, or the rear metal line 108B may be coupled to a power rail to carry a power signal. In this manner, in this example, a power signal can be routed from the rear 104B of the substrate 124 and coupled to the P-type source 130S of the PFET 116P. In an alternative example, a rear metal contact 144 may also be provided to couple the P-type drain 130D and / or the P-type gate 130G to the rear metal line 108B.
[0031] Therefore, in this manner, the back-side wiring 104B of the PFET 116P in FIG1A, as an example, can provide additional areas for routing signals and / or power to the PFET 116P and / or NFET 116N. The back-side wiring 104B can advantageously offset any reduction in wiring area in the CMOS circuit 112, such as due to a reduction in FET node size and / or an increase in circuit complexity including the CMOS circuit 112. Furthermore, since additional front-side wiring may not be required, the back-side wiring 102B can be compatible with existing manufacturing methods used to fabricate the CMOS circuit 112.
[0032] Note that, for example, the P-type source 130S of the PFET 116P is connected to the rear metal line 108B for the rear wiring 102B, but this is not limiting. As another example, the P-type source 130S can be connected to a front metal line, such as the front metal line 108F, for additional or only front wiring 102F. The same applies to the P-type drain 130D and / or the P-type gate 130G of the PFET 116P. Furthermore, if desired, the P-type source 130S, P-type drain 130D, and / or P-type gate 130G of the PFET 116P can be connected via both the front wiring 102F and the rear wiring 102B for signal routing and / or power routing.
[0033] As shown in FIG1B, a P-type conductive channel 122P and an N-type conductive channel 122N are formed in a CMOS circuit 112 above a substrate 124 and extend along the vertical axes LC(P) and LC(N) in the X-axis direction. Gates G(1)-G(4) are formed in the CMOS circuit 112 along the vertical axes LG(1)-LG(4) in the Y-axis direction. The vertical axes LG(1)-LG(4) in the Y-axis direction are orthogonal to the vertical axes LC(P) and LC(N) of the P-type conductive channel 122P and the N-type conductive channel 122N in the X-axis direction, and extend above and around at least a portion of the P-type conductive channel 122P and the N-type conductive channel 122N. According to the circuit cell layout of the CMOS circuit 112, the gates G(1)-G(4) are positioned adjacent to each other and have a gate spacing PG. Gates G(1) and G(4) are active gates of conductive materials such as metals (referred to herein as "active gates" G(1) or G(4)), and gates G(2) and G(3) are dummy gates of dielectric materials (referred to herein as "dummy gates" G(2) or G(3)). An active gate is a gate that forms part of the FET to control the electric field in the channel region when a sufficient voltage is applied to the gate. A dummy gate is a structure of gate material that is not part of the FET but is placed at the edge of a circuit cell to electrically isolate one circuit cell from an adjacent circuit cell.
[0034] In this example, as shown in Figures 1A and 1B, the rear-to-front connection structure 106 is arranged adjacent to the dummy gate G(3) and extends through the P-type conduction channel 122P in the N-type diffusion region 118N. In this example, the circuit 100 includes two (2) adjacent dummy gates G(3) and G(4). In this example, the rear-to-front connection structure 106 is arranged between the two (2) dummy gates G(3) and G(4) in the circuit 100. For example, the dummy gate G(3) may be on the edge of the CMOS circuit 112, and the dummy gate G(4) may be on the edge of the circuit adjacent to the CMOS circuit 112. The FET does not use the dummy gates G(3) and G(4) in the circuit 100 as gates. Therefore, as shown in Figure 1A, the region between the dummy gates G(3) and G(4) may not have a source or drain structure. This means that arranging the rear-to-front connection structure 106 between the dummy gates G(3), G(4) allows the rear-to-front connection structure 106 to extend upward in the Y-axis direction without being obstructed or interfered with by other wiring, which would otherwise be present if a source or drain structure is formed between the dummy gates G(3), G(4). For example, the region adjacent to the adjacent dummy gates G(3), G(4) and / or the region between adjacent dummy gates G(3), G(4) may be without wiring or have reduced wiring. This is also referred to as "blank space". In this way, the rear-to-front connection structure 106 is arranged adjacent to the dummy gates G(3), G(4) because the "blank area" does not interfere with another active semiconductor element, such as a FET, formed in the circuit 100. The rear-to-front connection structure 106 is arranged adjacent to the dummy gates G(3) and G(4) in the circuit 100, which can also avoid, for example, having to expand the layout of the circuit 100, in order to provide an area for the rear-to-front connection structure 106 without interfering with other wiring.
[0035] Furthermore, in this example, referring to FIG1A, the rear-to-front connection structure 106 is shown as a single conductive structure (e.g., via, conductive pillar). The rear-to-front connection structure 106 extends through a P-type conductive channel 122P, which serves as a semiconductor layer 148 (also referred to as an active layer). The semiconductor layer 148 has a front side 150F disposed adjacent to the metallization structure 109 on a front side 104F, and a rear side 150B disposed adjacent to the substrate 124. In this example, the rear-to-front connection structure 106 is a via 110 that extends from the front side 150F of the semiconductor layer 148 through the semiconductor layer 148 to the rear side 150B of the semiconductor layer 148, and is coupled to the front metal line 108F and the rear metal line 108B. However, it should be noted that the rear-to-front connection structure 106 may also include multiple elements and contacts for coupling to the front metal line 108F and the rear metal line 108B.
[0036] FIG2 is a flowchart illustrating an exemplary process 200 for manufacturing the circuit 100 in FIG1A and FIG1B. The process 200 in FIG2 will be discussed with reference to the circuit 100 in FIG1A and FIG1B. In this regard, the first step of process 200 may be to provide a substrate 124 as a base layer or base material for forming semiconductor elements 114 and other structures of semiconductor die 120 (box 202 in FIG2). For example, as an example, substrate 124 may be a semiconductor material such as silicon, aluminum oxide or gallium arsenide. The next step of process 200 may be to form semiconductor elements 114 on substrate 124 (box 204 in FIG2). For example, the PFET 116P and NFET 116N in the CMOS circuit 112 in FIG1A and FIG1B described above are examples of semiconductor elements 114 that can be formed together with substrate 124. Semiconductor element 114 includes a front side 104F and a rear side 104B arranged adjacent to substrate 124. The next step in process 200 may be to form a metallization structure 109 (box 206 in FIG. 2) adjacent to the front side 104F of semiconductor element 114. Metallization structure 109 is an interconnect structure comprising one or more metal layers, each metal layer including one or more formed metal lines to provide connectivity to semiconductor element 114, and other interconnects extending to external interconnects (e.g., bumps) of a package including semiconductor layer 148. Metallization structure 109 includes a front side metal line 108F in the metal layers of metallization structure 109. The next step in process 200 may be to form a rear side metal line 108B adjacent to the rear side 104B of semiconductor element 114 (box 208 in FIG. 2). The next step in process 200 may be to couple the rear side metal line 108B to semiconductor element 114 to provide rear side wiring for semiconductor element 114 (box 210 in FIG. 2). The next step in process 200 may be to form a rear-to-front connection structure 106 that couples the rear metal line 108B to the front metal line 108F, so that the signal in the rear metal line 108B is coupled to the front metal line 108F in a conventional manner (box 212 in FIG2).
[0037] FIG3A is a top perspective view of another exemplary circuit 300, which includes front-side wiring and rear-side wiring, and also includes a rear-side-front connection structure coupling the front-side wiring to the rear-side wiring. FIG3B-1 and FIG3B-2 are the right front perspective view and left front perspective view of the circuit 300 in FIG3A, respectively. FIG3C is a front view of the circuit 300 in FIG3A. FIG3D and FIG3E are the side perspective view and side view of the circuit 300 in FIG3A, respectively.
[0038] As shown in Figures 3A-3E, circuit 300 includes two CMOS circuits 302(1) and 302(2) manufactured according to a circuit cell layout. CMOS circuit 302(1) includes active gates GA(1)-GA(4) arranged between two dummy gates GD(1) and GD(2). CMOS circuit 302(2) adjacent to CMOS circuit 302(1) is shown as including a dummy gate GD(3) arranged adjacent to the dummy gate GD(2) in CMOS circuit 302(1) and including an active gate GA(5). Also as shown in Figures 3A-3E, according to both CMOS circuits 302(1) and 302(2), circuit 300 includes an N-type diffusion region 304N and a P-type diffusion region 304P extending longitudinally in the X-axis direction. As discussed in a similar example of CMOS circuit 112 in Figures 1A and 1B, PFET and NFET can be formed in the corresponding N-type diffusion region 304N and P-type diffusion region 304P in CMOS circuits 302(1) and 302(2), respectively.
[0039] As shown in Figures 3A-3E, rear metal lines 306(1)-306(4) are arranged below the N-type diffusion region 304N and the P-type diffusion region 304P to provide rear wiring for CMOS circuits 302(1) and 302(2). In the metallization structure 310, front metal lines 308(1)(1), 308(1)(2), and 308(2) are arranged above the N-type diffusion region 304N and the P-type diffusion region 304P to provide front wiring for CMOS circuits 302(1) and 302(2). In this example, front metal lines 308(1)(1) and 308(1)(2) are arranged in the first metal layer (M1) of the metallization structure 310, and front metal line 308(2) is arranged in the second metal layer (M2) of the metallization structure 310. As shown in Figures 3A-3E, and especially in Figures 3D and 3E, two (2) rear-to-front connection structures 312 (1) and 312 (2) are arranged between two dummy gates GD (2) and GD (3) to couple additional rear metal lines 314 (1) and 314 (2) to front metal lines 308 (1) and 308 (1) (2). The rear-to-front connection structure 312 (1) is used to couple the rear metal line 314 (1) to the front metal line 308 (1) (1). The rear-to-front connection structure 312 (2) is used to couple the rear metal line 314 (2) to the front metal line 308 (1) (2). In this example, the rear-to-front connection structures 312(1), 312(2) include conductive elements 316(1), 316(2) that may be conductive pillars or through-holes, which include TSVs above corresponding N-type diffusion regions 304N and P-type diffusion regions 304P in the front side 317F of the circuit 300. The rear-to-front connection structures 312(1), 312(2) are configured to boost and couple signals routed in the rear metal lines 314(1), 314(2) to the front metal lines 308(1)(1), 308(1)(2).
[0040] Continuing to refer to Figures 3A-3B-2, the rear-to-front connection structures 312(1), 312(2) and their conductive elements 316(1), 316(2) are arranged to contact the corresponding front metal contacts 318(1), 318(2), which are arranged above the corresponding N-type diffusion region 304N and P-type diffusion region 304P. As shown in Figure 3D, the rear-to-front connection structures 312(1), 312(2) also include additional conductive elements 320(1), 320(2), which may be, for example, conductive pillars or vias below the N-type diffusion region 304N and P-type diffusion region 304P in the rear side 317B of the circuit 300. Conductive elements 320(1), 320(2) are coupled to and contact the corresponding rear metal lines 314(1), 314(2) to couple the rear metal lines 314(1), 314(2) to the front metal lines 308(1)(1), 308(1)(2). In this example, as shown in FIG3E, intermediate metal lines 322(1), 322(2) are provided in the metallization structure 310 to bridge the coupling of the rear metal lines 314(1), 314(2) to the front metal lines 308(1)(1), 308(1)(2). For example, electricity can be routed via the rear metal lines 314(1), 314(2) and then routed to the front metal lines 308(1)(1), 308(1)(2) via the rear-to-front connection structure 312(1), 312(2). For example, it may be necessary to provide multiple rear-side-front connection structures 312(1), 312(2) to provide more material to reduce the coupling resistance between the rear metal lines 314(1), 314(2) and the front metal lines 308(1)(1), 308(1)(2). In this example, providing multiple rear-side-front connection structures 312(1), 312(2) can also be used to utilize the space between the two dummy gates GD(2), GD(3).
[0041] FIG4A is a front and side perspective view of another exemplary circuit 400, which includes front wiring and rear wiring, and also includes a rear-to-front connection structure coupling the front wiring to the rear wiring. FIG4B is a bottom and side perspective view of the circuit in FIG4A.
[0042] As shown in Figures 4A and 4B, circuit 400 includes two CMOS circuits 402(1) and 402(2) fabricated according to a circuit cell layout. CMOS circuit 402(1) includes active gates GA(1) and GA(2) and includes three (3) dummy gates GD(1)-GD(3) to provide additional isolation between adjacent CMOS circuits 402(1) and 402(2). Also as shown in Figure 4A, according to both CMOS circuits 402(1) and 402(2), circuit 300 includes an N-type diffusion region 404N and a P-type diffusion region 404P extending longitudinally in the X-axis direction. As discussed in a similar example of CMOS circuit 112 in Figures 1A and 1B, PFETs and NFETs may be formed in the corresponding N-type diffusion regions 404N and P-type diffusion regions 404P in CMOS circuits 402(1) and 402(1).
[0043] As shown in Figures 4A and 4B, rear metal lines 406(1)-406(4) are arranged below the N-type diffusion region 404N and the P-type diffusion region 404P to provide rear wiring for CMOS circuits 402(1) and 402(2). As shown in Figure 4A, in the metallization structure 410, front metal lines 408(1)(1), 408(1)(2), and 408(2) are arranged above the N-type diffusion region 404N and the P-type diffusion region 404P to provide front wiring to CMOS circuits 402(1) and 402(2). In this example, as shown in Figure 4A, front metal lines 408(1)(1) and 408(1)(2) are arranged in the first metal layer (M1) of the metallization structure 410, and front metal line 408(2) is arranged in the second metal layer (M2) of the metallization structure 410. Two (2) rear-to-front connection structures 412(1), 412(2) are arranged to pass through the dummy gate GD(2) to couple additional rear metal lines 414(1), 414(2) to front metal lines 408(1)(1), 408(1)(2). The rear-to-front connection structure 412(1) is used to couple the rear metal line 414(1) to the front metal line 408(1)(1). The rear-to-front connection structure 412(2) is used to couple the rear metal line 414(2) to the front metal line 408(1)(2). Two (2) rear-to-front connection structures 412(3), 412(4) are also arranged to pass through the dummy gate GD(3) to couple additional rear metal lines 414(3), 414(4) to front metal lines 408(1)(1), 408(1)(2). This could be to reduce the resistance of the rear-side wiring to the front-side wiring, as there is an additional region due to the three (3) adjacent dummy gates GD(1)-GD(3). The rear-side-front connection structure 412(3) is used to connect the rear metal line 414(3) to the front metal line 408(1) (1). The rear-side-front connection structure 412(4) is used to couple the rear metal line 414(4) to the front metal line 408(1) (2). In this example, the rear-side-front connection structures 412(1)-414(4) include corresponding conductive elements 416(1)-416(4) which may be conductive pillars or vias, and the corresponding conductive elements 416(1)-416(4) include TSVs above the corresponding N-type diffusion region 404N and P-type diffusion region 404P in the front side 417F of the circuit 400, as shown in FIG4A. The rear-to-front connection structure 412(1)-412(2) is configured to boost and couple the signal routed in the rear metal line 414(1)-414(2) to the front metal line 408(1)(1), 408(1)(2).
[0044] Continuing to refer to Figures 4A and 4B, the rear-to-front connection structure 412(1)-412(4) also includes additional corresponding conductive elements 420(1)-420(4), which may be, for example, conductive pillars or vias below the N-type diffusion region 404N and the P-type diffusion region 404P in the rear side 417B of the circuit 400. The conductive elements 420(1)-420(4) are coupled to and contact the corresponding rear metal lines 414(1), 414(2) to couple the corresponding rear metal lines 414(1), 414(2) to the front metal lines 408(1)(1), 408(1)(2). In this example, as shown in Figure 4A, intermediate metal lines 422(1)-422(4) are provided in the metallization structure 410 to bridge the coupling between the rear metal lines 414(1), 414(2) and the front metal lines 408(1)(1), 408(1)(2). For example, power can be routed via the rear metal lines 414(1), 414(2) and then via the rear-to-front connection structure 412(1)-412(4) to the front metal lines 408(1)(1), 408(1)(2). For example, multiple rear-to-front connection structures 412(1)-412(4) may be provided to provide more material to reduce the resistance of the coupling between the rear metal lines 414(1)-414(4) and the front metal lines 408(1)(1), 408(1)(2).
[0045] Note that the terms “front,” “front side,” “rear,” and “rear side” used herein are relative terms. These terms are not intended to limit or imply a strict orientation of “front” or “front side” relative to the ground above “rear” or “rear side,” but only a relative orientation relative to another stated orientation. For example, the “front side” of an element is one side of the element opposite to the “rear side.”
[0046] Includes front-side wiring and rear-side wiring, and also includes circuitry for a rear-side-front connection structure that couples the front-side wiring to the rear-side wiring (including, but not limited to, the circuitry in Figures 1A-1B, 3A-3E and 4A-4B, and any type of circuitry disclosed herein), which may be provided in or integrated into any processor-based device. Examples include, but are not limited to: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; Global Positioning System (GPS) devices; mobile phones; cellular phones; smartphones; SIP phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.); desktop computers; personal digital assistants (PDAs); monitors, computer monitors; televisions; tuners; radios; satellite broadcasting; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multirotor aircraft.
[0047] In this regard, FIG5 illustrates an example of a processor-based system 500, which includes circuitry having front-side wiring and rear-side wiring, and further having a rear-side-front connection structure coupling the front-side wiring to the rear-side wiring, including but not limited to the circuitry in FIG1A-FIG., FIG3A-FIG., and FIG4A-FIG., and any type of circuitry disclosed herein in various components of the system. For example, the circuitry may be a FET employed in CMOS circuitry. In this example, the processor-based system 500 may be configured as an IC 504 as a system-on-a-chip (SoC) 506. The processor-based system 500 includes a CPU 508, which includes one or more processors 510, which may also be referred to as a CPU core or processor core. The CPU 508 may have a cache memory 512 coupled to the CPU 508 for fast access to temporarily stored data. CPU 508 is coupled to system bus 514 and can couple master and slave devices included in processor-based system 500 to each other. As is well known, CPU 508 communicates with these other devices by exchanging address information, control information, and data information on system bus 514. For example, CPU 508 can transmit bus transaction requests to memory controller 516, which is an example of a slave device. Although not shown in Figure 5, multiple system buses 514 may be provided, each with a different configuration.
[0048] Other master and slave devices may be connected to system bus 514. As shown in FIG5, as an example, these devices may include a memory system 520 (which includes a memory controller 516 and a memory array 518), one or more input devices 522, one or more output devices 524, one or more network interface devices 526, and one or more display controllers 528. Each of the memory system 520, one or more input devices 522, one or more output devices 524, one or more network interface devices 526, and one or more display controllers 528 may include circuitry. Input devices 522 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 524 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 526 may be any device configured to allow the exchange of data to network 530 and slave network 530. Network 530 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. Network interface device 526 can be configured to support any type of communication protocol desired.
[0049] The CPU 508 can also be configured to access the display controller 528 via the system bus 514 to control the information sent to one or more displays 532. The display controller 528 sends information to the displays 532 for display via one or more video processors 534, which process the information to be displayed into a format suitable for the displays 532. The displays 532 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.
[0050] FIG6 illustrates an exemplary wireless communication device 600, which includes a radio frequency (RF) component formed by one or more ICs 602, wherein any one of the ICs 602 may include circuitry including front-side wiring and rear-side wiring, and further including a rear-side-front-side connection structure coupling the front-side wiring to the rear-side wiring, including but not limited to the circuitry in FIG1A-FIG, FIG3A-FIG, and FIG4A-FIG, and any type of circuitry disclosed herein. For example, the circuitry may be a FET employed in CMOS circuitry, and may be any type of circuitry disclosed herein.
[0051] As an example, wireless communication device 600 may be included in or provided in any of the devices mentioned above. As shown in FIG6, wireless communication device 600 includes a transceiver 604 and a data processor 606. Data processor 606 may include memory for storing data and program code. Transceiver 604 includes a transmitter 608 and a receiver 610 supporting bidirectional communication. Generally, wireless communication device 600 may include any number of transmitters 608 and / or receivers 610 for any number of communication systems and frequency bands. All or part of transceiver 604 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.
[0052] The transmitter 608 or receiver 610 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages, for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 600 of Figure 6, the transmitter 608 and receiver 610 are implemented using a direct conversion architecture.
[0053] In the transmission path, the data processor 606 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 608. In the exemplary wireless communication device 600, the data processor 606 includes digital-to-analog converters (DACs) 612(1) and 612(2) for converting digital signals generated by the data processor 606 into I and Q analog output signals, such as I and Q output currents, for further processing.
[0054] Within transmitter 608, low-pass filters 614(1) and 614(2) filter the I and Q analog output signals respectively to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 616(1) and 616(2) amplify the signals from low-pass filters 614(1) and 614(2) respectively, and provide I and Q baseband signals. Upconverter 618 uses mixers 620(1) and 620(2) to upconvert the I and Q baseband signals using the I and Q transmit (TX) local oscillator (LO) signals from TX LO signal generator 622 to provide upconverted signal 624. Filter 626 filters upconverted signal 624 to remove unwanted signals caused by frequency upconversion and noise in the receive band. A power amplifier (PA) 628 amplifies the up-conversion signal 624 from a filter 626 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed via a duplexer or switch 630 and transmitted via an antenna 632.
[0055] In the receiving path, antenna 632 receives the signal transmitted by the base station and provides the received RF signal, which is routed by duplexer or switch 630 and provided to low noise amplifier (LNA) 634. Duplexer or switch 630 is designed to operate at a specific receive (RX) to TX duplexer frequency to isolate the RX signal from the TX signal. The received RF signal is amplified by LNA 634 and filtered by filter 636 to obtain the desired RF input signal. Down-conversion mixers 638(1) and 638(2) mix the output of filter 636 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 640 to generate I and Q baseband signals. The I and Q fundamental frequency signals are amplified by amplifiers (AMPs) 642(1) and 642(2) and further filtered by low-pass filters 644(1) and 644(2) to obtain I and Q analog input signals, which are then provided to data processor 606. In this example, data processor 606 includes ADCs 646(1) and 646(2) for converting the analog input signals into digital signals for further processing by data processor 606.
[0056] In the wireless communication device 600 of FIG. 6, the TX LO signal generator 622 generates I and Q TX LO signals for frequency up-conversion, while the RX LO signal generator 640 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 648 receives timing information from the data processor 606 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 622. Similarly, the RX PLL circuit 650 receives timing information from the data processor 606 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 640.
[0057] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their function. How such function is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described function in varying ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this document.
[0058] The various illustrative logic blocks, modules, and circuits described in connection with the states disclosed herein can be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, individual hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).
[0059] The configurations disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electronically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable magnetic disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as separate components in a remote station, base station, or server.
[0060] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The described operations can be performed in many different orders other than those illustrated. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. It should be understood that the operational steps illustrated in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.
[0061] The prior description of this invention is provided to enable those skilled in the art to make or use this invention. Various modifications to this invention will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, the content of this invention is not intended to be limited to the examples and designs described herein, but is consistent with the widest range of principles and novel features disclosed herein. [Simplified Explanation of the Diagram]
[0012] FIG1A and FIG1B are corresponding cross-sectional side and top views of an exemplary circuit, which includes a field-effect transistor (FET) and includes front-side wiring and rear-side wiring to the FET, and includes a rear-side-front connection structure that couples the rear-side wiring to the front-side wiring.
[0013] Figure 2 is a flowchart illustrating an exemplary process for manufacturing a circuit similar to the circuits in Figures 1A-1B;
[0014] FIG3A is a top perspective view of another exemplary circuit of an exemplary form of an exemplary complementary metal-oxide-semiconductor (CMOS) circuit, which includes front-side wiring and rear-side wiring coupled to a FET, and also includes a rear-side-front-side connection structure that couples the front-side wiring to the rear-side wiring coupled to the FET.
[0015] Figures 3B-1 and 3B-2 are the right front perspective view and left front perspective view of the circuit in Figure 3A, respectively;
[0016] Figure 3C is a front view of the circuit in Figure 3A;
[0017] Figure 3D and Figure 3E are the side perspective view and side view of the circuit in Figure 3A, respectively;
[0018] FIG4A is a front and side perspective view of another exemplary circuit in an exemplary form of an exemplary CMOS circuit, the CMOS circuit including front and rear wiring coupled to a FET, and also including a rear-to-front connection structure that couples the front wiring to the rear wiring coupled to the FET.
[0019] Figure 4B is a bottom and side perspective view of the circuit in Figure 4A;
[0020] Figure 5 is a block diagram of an exemplary processor-based system, which may include circuitry with front-side and rear-side routing, and further includes a rear-side-front connection structure coupling the front-side routing to the rear-side routing, including but not limited to the circuitry in Figures 1A-1B, 3A-3E, and 4A-4B; and
[0021] FIG6 is a block diagram of an exemplary wireless communication device, which includes a radio frequency (RF) component formed by circuitry, the circuitry including front-side wiring and rear-side wiring, and further including a rear-side-front-side connection structure that couples the front-side wiring to the rear-side wiring, including but not limited to the circuitry in FIG1A-FIG1B, FIG3A-FIG3E and FIG4A-FIG4B. [Biomaterial Storage]
[0063] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.
Claims
1. A circuit comprising: A semiconductor device, including a front side and a rear side; A metallization structure is arranged adjacent to the front side of the semiconductor element, the metallization structure including a front metal line; a rear metal line is arranged adjacent to the rear side of the semiconductor element and coupled to the semiconductor element; and a rear-front connection structure is used to couple the rear metal line to the front metal line.
2. The circuit according to claim 1 further includes a dummy gate; the rear-to-front connection structure is arranged adjacent to the dummy gate.
3. The circuit according to claim 2 further includes: A second dummy gate is arranged adjacent to the dummy gate, wherein the rear-to-front connection structure is also arranged between the dummy gate and the second dummy gate.
4. The circuit according to claim 1, wherein the rear-to-front connection structure includes a conductive vertical interconnect (via).
5. The circuit according to claim 1, wherein the rear-to-front connection structure includes a through-silicon via (TSV) disposed through at least a portion of the semiconductor element.
6. The circuit according to claim 1, wherein the front metal line is coupled to the semiconductor element.
7. The circuit according to claim 1 further includes a rear metal contact coupled to the semiconductor element and the rear metal line.
8. The circuit according to claim 1, wherein the rear-to-front connection structure includes: A front-side through-hole is coupled to the front-side metal line; And a rear through hole, coupled to the rear metal line.
9. The circuit according to request item 1, wherein: The semiconductor device includes a semiconductor layer having a front side and a rear side; the front side of the semiconductor layer is disposed adjacent to the metallization structure. Furthermore, the rear side of the semiconductor layer is disposed adjacent to a substrate; and the rear-front connection structure includes: a via extending from the front side of the semiconductor layer through the semiconductor layer to the rear side of the semiconductor layer, and coupled to the front metal line and the rear metal line.
10. The circuit according to claim 1 further includes a field-effect transistor (FET) circuit, comprising: The FET includes: a conductive channel disposed above a substrate; a source disposed in a first end of the conductive channel; a drain disposed in a second end of the conductive channel opposite to the first end; and a gate disposed above at least a portion of the conductive channel and between the first end and the second end of the conductive channel; and a rear-side metal line is in contact with one of the source, drain, and gate of the FET.
11. The circuit according to claim 10 further includes a rear metal contact coupled to one of a back surface of the source, a back surface of the drain, and a back surface of the gate; the rear metal contact is coupled to the rear metal line.
12. The circuitry of claim 1 is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular phone; a smartphone; a SIP phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite broadcasting system; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multi-rotor aircraft.
13. The circuit according to claim 1 is integrated into a semiconductor die.
14. A method of manufacturing a circuit, comprising: Provide a substrate; A semiconductor element is formed on the substrate, the semiconductor element including a front side and a rear side arranged adjacent to the substrate; A metallization structure is formed adjacent to the front side of the semiconductor element, the metallization structure including a front metal line; a rear metal line is formed adjacent to the rear side of the semiconductor element; the rear metal line is coupled to the semiconductor element; and a rear-front connection structure is formed, the rear-front connection structure coupling the rear metal line to the front metal line.
15. The method according to claim 14 further includes: This creates a virtual gate; Furthermore, the rear-front connection structure also includes: arranging the rear-front connection structure adjacent to the dummy gate.
16. The method according to claim 15 further includes: Forming a second dummy gate adjacent to the dummy gate, wherein forming the rear-front connection structure further includes: arranging the rear-front connection structure between the dummy gate and the second dummy gate.
17. According to the method of request item 14, wherein: Forming the semiconductor device on the substrate includes forming a field-effect transistor (FET) circuit, comprising: forming a conductive channel disposed above the substrate; forming a source disposed in a first end of the conductive channel; forming a drain disposed in a second end of the conductive channel opposite to the first end; and forming a gate disposed above at least a portion of the conductive channel and between the first end and the second end of the conductive channel; and the rear metal line contacts one of the source, drain, and gate of the FET circuit.
18. A complementary metal-oxide-semiconductor (CMOS) circuit, comprising: A positive (P) type field-effect transistor (FET) (PFET); a negative (N) type FET (NFET); a metallization structure disposed adjacent to a front side of at least one of the PFET and the NFET, the metallization structure including a front metal line; a rear metal line disposed adjacent to a rear side of at least one of the NFET and the PFET, the rear metal line being coupled to at least one of the NFET and the PFET; and a rear-front connection structure coupling the rear metal line to the front metal line.
19. The CMOS circuit according to claim 18 further includes a dummy gate, wherein the rear-to-front connection structure is arranged adjacent to the dummy gate.
20. The CMOS circuit according to claim 19 further includes: A second dummy gate is arranged adjacent to the dummy gate, wherein: the rear-front connection structure is also arranged between the dummy gate and the second dummy gate.