Process for transferring a thin layer to a carrier substrate provided with a charge-trapping layer

Abstract

simultaneously implements the deposition and the ion sputtering of the dielectric layer. The transfer process also comprises the joining, by means of molecular bonding and without preparing the free face of the dielectric layer

Description

[Technical Field]

[0001] This invention relates to a method for transferring a thin layer to a carrier substrate including a charge trapping layer. Specifically, such substrates are applicable to the field of radio frequency integrated devices (i.e., electronic devices that handle signals in the frequency range of about 3 kHz to about 300 GHz), such as in the telecommunications field (telephone, Wi-Fi, Bluetooth, etc.). Such substrates are also applicable to the photonics field. [Previous Technology]

[0002] To prevent or limit electromagnetic coupling effects that can occur between electronic or photonic devices and the carrier substrate of an insulator-coated silicon (SOI) substrate on which such devices are formed, it is known practice to insert a charge-trapping layer directly beneath the dielectric layer between the buried dielectric layer and the SOI carrier. This layer may consist of, for example, a polycrystalline silicon layer of 1 to 10 micrometers. The boundaries of the polycrystalline grains then form traps for charge carriers, which may originate from the trapping layer itself or from the underlying substrate. This prevents the formation of a conductive plane beneath the insulating layer. Well-known SOI substrates of this type are described, for example, in documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, US6544656, US20200020520, or WO2020008116.

[0003] To form an SOI substrate characterized by this charge-trapping layer, a carrier substrate is prepared by forming the charge-trapping layer on a base substrate. Next, a thin layer is transferred to this carrier substrate using a layer transfer process (e.g., using Smart Cut® technology). According to this technique, a donor substrate is typically bonded to the carrier substrate by molecular bonding, the donor substrate having a weak surface that, together with its exposed surface, defines the thin layer to be transferred. Then, the donor substrate is split at the weak surface to transfer the thin layer to the carrier substrate. A dielectric layer (e.g., by oxidizing one or both of these substrates before bonding them) is inserted between the carrier substrate and the thin layer.

[0004] Using Smart Cut® technology, a weak point is obtained by introducing light species (such as hydrogen and / or helium) into a donor substrate through an existing dielectric layer (usually implanted). The thickness of the thin layer to be transferred determines the energy and dose of the species to be implanted: the greater the thickness, the greater the energy and dose. Implanting large doses at high energies is industrially disadvantageous; therefore, to address this issue, it is preferable to form at least a portion of the dielectric layer on a carrier substrate rather than on the donor substrate, specifically when this dielectric layer is chosen to be relatively thick (e.g., thicker than 200 nm). In the field of photonics, this thickness can reach one micrometer, or even several micrometers, which exacerbates all the problems associated with the presence of a dielectric layer of substantial thickness.

[0005] Therefore, experiments conducted by the applicant have shown that forming a dielectric layer by oxidizing a charge-trapping layer made of polycrystalline silicon presents several problems. This oxidation tends to form a carrier substrate exhibiting a rough surface condition, which therefore must be prepared before the bonding step (e.g., by polishing), thereby complicating the process. The embedded interface between the silicon oxide and the remaining polycrystalline silicon layer is also rough, which can cause problems when optically inspecting the SOI substrate during device manufacturing steps. Accordingly, it should be noted that this interface cannot be used for polishing and must remain within the substrate itself, which can negatively impact the operation of devices (specifically photonic devices) on / within this carrier substrate. In addition, the oxidation step tends to deform the carrier substrate and result in substantial bending. The presence of this bending complicates subsequent bonding, and more generally, the handling of the carrier substrate on the production line using conventional equipment.

[0006] It should be noted that similar problems exist in forming dielectric layers by depositing on a carrier substrate rather than by oxidizing the carrier. Specifically, conventional techniques such as PECVD (plasma-assisted chemical vapor deposition) or LPCVD (low-pressure chemical vapor deposition) cause substantial shape distortion and usually result in very rough layers that must be prepared by polishing before any bonding can be considered.

[0007] The documents "High density plasma CVD and CMP for 0.25 M intermetal dielectric processing" by Pye et al., Solid State Technology, Penwell Corporation, Vol. 38, No. 12, 1995, and "New planarization technology using bias ECR plasma deposition" by Machida et al., Japanese journal of applied physics, pp. 329-332 (1985), teach techniques for depositing intermetallic dielectric films typically located between two metal layers in a functional semiconductor structure. These films are designed to fill topographic patterns exhibiting substantial aspect ratios, and their deposition is followed by a polishing step.

[0008] Subject of the Invention The present invention aims to overcome all or some of the aforementioned disadvantages. [Summary of the Invention]

[0009] To achieve one of these objectives, the subject matter of the present invention relates to a method for transferring a thin layer to a carrier substrate, comprising the following steps: - preparing a carrier substrate using a fabrication process including providing a base substrate having a charge-trapping layer on a main surface and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer, the formation of the dielectric layer simultaneously performing deposition and ion sputtering of the dielectric layer; - bonding a donor substrate to the dielectric layer of the carrier substrate by molecular bonding and without the need for polishing to prepare a free surface of the dielectric layer, the donor substrate being characterized by defining a weak surface of the thin layer; - splitting the donor substrate at the weak surface to release the thin layer and transferring it to the carrier substrate.

[0010] According to other advantageous and non-limiting features of the invention, individually or in any technically feasible combination: - The fabrication process includes forming an arcuate compensation layer on the back side of the base substrate opposite the main surface; - The arcuate compensation layer has a thickness between 500 nm and 1000 nm; - The base substrate is a monocrystalline silicon substrate exhibiting a resistivity of less than 1000 ohm·cm; - The base substrate is a monocrystalline silicon substrate exhibiting a resistivity of greater than 600 ohm·cm; - The charge trapping layer comprises polycrystalline silicon; - The charge trapping layer comprises carbon; - The charge trapping layer has a thickness between 1 micrometer and 20 micrometers; - The dielectric layer is composed of silicon oxide; - The dielectric layer comprises a barrier layer made of silicon nitride or silicon oxynitride; - The dielectric layer has a thickness between 200 nm and 10 micrometers, and preferably between 600 nm and 10 micrometers; The deposition / sputtering ratio is between 1 and 10, preferably between 2 and 5; - The dielectric layer is formed at a temperature between 300°C and 450°C, preferably between 350°C and 400°C; - The dielectric layer is formed in an atmosphere exhibiting a pressure below atmospheric pressure; - The process further includes annealing the dielectric layer in a neutral atmosphere and at a temperature exceeding the temperature at which the dielectric layer is formed, preferably below 950°C; - The free surface of the dielectric layer exhibits a roughness of less than 0.5 nm RMS value within a measurement range of 10 μm × 10 μm; - The substrate has no dielectric surface layer.

Implementation Method

[0016] Referring to FIG2, the final substrate S in one embodiment includes a base substrate 3, a charge trapping layer 2 disposed on the base substrate 3, a dielectric layer 4 disposed on and in direct contact with the charge trapping layer 2, and a thin layer 5 disposed on the dielectric layer 4. The base substrate 3, which has the charge trapping layer and the dielectric layer 4, forms the carrier substrate 1 of the final substrate S.

[0017] In the embodiment illustrated in FIG4, the carrier substrate 1 of the final substrate S includes a base substrate 3 provided with a charge trapping layer 2 and an arcuate compensation layer 32. The function of this layer is to cause deformation of the base substrate 3, and specifically, its purpose is to at least partially compensate for future deformations that the base substrate 3 and the final substrate S will undergo during the various steps of the process forming the main subject of this description. Specifically, this means that when the dielectric layer 4 and the charge trapping layer 2 are formed on the base substrate 3, the stress exerted by the dielectric layer 4 and, to a lesser extent, the stress exerted by the charge trapping layer 2 are compensated.

[0018] The charge trapping layer 2 is disposed on the main surface 31 of the base substrate 3, and the compensation layer 32 is disposed on the back surface 33 of the base substrate 3, which is opposite to the main surface 31. Preferably, the compensation layer 32 is made of silicon oxide or silicon nitride. It has a thickness greater than 200 nm, and more preferably a thickness between 500 nm and 1000 nm.

[0019] The final substrate S (and therefore the carrier substrate 1) of the embodiments of Figures 2 and 4 can be in the form of a standard-sized (e.g., 200 mm or 300 mm in diameter, or even 450 mm) circular wafer. This is especially true when the final substrate S, and specifically the thin layer 5, still contains no devices. However, the present invention is not limited in any way to such dimensions or forms.

[0020] The base substrate 3 has a thickness of several hundred micrometers. Preferably, the base substrate 3 exhibits a high resistivity, greater than 100 ohm·cm or 1000 ohm·cm, and more preferably still greater than 3000 ohm·cm. In this way, the density of charge (i.e., holes or electrons) that moves easily within the base substrate 3 and thus limits the degradation of the RF performance of the final substrate S is limited. However, the present invention is not limited to the base substrate 3 exhibiting this resistivity, and the present invention also provides advantages in RF performance when the base substrate 3 exhibits a more typical resistivity (below 1000 ohm·cm) of about several hundred ohm·cm or 100 ohm·cm or less.

[0021] For usability and cost reasons, the base substrate 3 is preferably made of silicon, specifically monocrystalline silicon. It can be, for example, a CZ substrate containing a small amount of interstitial oxygen with a resistivity greater than 1000 ohm·cm, a type of substrate that is well known. Alternatively, the base substrate 3 can be formed of another material: it can be made of, for example, sapphire, silicon carbide, germanium silicon, III-V group materials, glass, etc. Alternatively, it can be a more standard CZ monocrystalline substrate with a resistivity less than 1000 ohm·cm, or a CZ substrate containing a large or moderate amount of interstitial oxygen, which can be n-doped or p-doped and has a resistivity of about 500 ohm·cm or less.

[0022] The carrier substrate 1 of various embodiments of the present invention may include, as appropriate, a dielectric thin layer disposed on and in direct contact with the base substrate 3, for example, made of silicon dioxide or silicon nitride. The dielectric thin layer (not shown in Figures 1 and 2) has a thickness greater than a few nanometers (e.g., between 5 nm and 500 nm). It can be obtained by oxidizing the base substrate 3 or by deposition on this substrate. To limit the time and cost required to form this thin layer, its thickness can be selected such that it is between 5 nm and 200 nm, such as (e.g.) 145 nm. When the carrier substrate 1 or the final substrate S is exposed to high temperatures, the dielectric thin layer enables the prevention or limitation of recrystallization of the charge trapping layer 3.

[0023] The carrier substrate 1 also includes a charge trapping layer 2 disposed on and in direct contact with the base substrate 3 (or, when present, in contact with the dielectric thin layer). The trapping layer 2 has a resistivity greater than 500 ohm·cm, preferably greater than 1000 ohm·cm, and even more preferably greater than 10 kohm·cm. As mentioned above in the description of this application, the function of the trapping layer is to trap any charge carriers present in the carrier 1 and limit their mobility. This is especially true when the final substrate S includes a semiconductor structure that emits an electromagnetic field that penetrates the carrier substrate 1 and is therefore readily able to interact with and move such charges. The charge trapping layer 2 typically has a thickness between 1 micrometer and 15 micrometers or even up to 20 micrometers.

[0024] Generally, the trapping layer 2 can be formed from a non-single-crystal semiconductor layer with structural defects (such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, pores, etc.). These structural defects form traps for any charge flowing through the material at sites of incomplete or dangling chemical bonds. Therefore, conduction is prevented in the trapping layer, which subsequently exhibits high resistivity.

[0025] For the same reasons mentioned above regarding usability and cost, the trapping layer 2 is preferably made of polycrystalline silicon. However, it may be formed of or include another polycrystalline semiconductor material. Of course, this charge trapping layer 2 can be formed by techniques other than those involving layers formed of polycrystalline silicon. This layer may also include carbon or be composed of or include silicon carbide or an alloy of silicon and carbon, for example, in the form of interlayers inserted into the thickness of the polycrystalline silicon. When the trapping layer 2 is composed of silicon carbide or an alloy of silicon and carbon, its thickness is preferably between a few nanometers (e.g., 2 nm) and tens of nanometers (e.g., 50 nm). Alternatively, electric traps can be formed in layer 2 to create crystal defects capable of trapping charges by ion bombardment of a relatively heavy species (e.g., argon) on a surface portion of the substrate 3. It is also conceivable that the charge trapping layer 2 is formed of a porous material, for example, when it is made of silicon, by making the surface portion of the base substrate 3 porous.

[0026] In any case, the trapping layer 2 exhibits a high resistivity of over 500 ohm·cm. Accordingly, the trapping layer 2 is not intentionally doped, i.e., it has a charge carrier dopant concentration of less than 10 E14 atoms per cubic centimeter. It may be enriched with nitrogen or carbon to improve its resistivity characteristics.

[0027] Returning to the general description of Figures 1 and 4, the carrier substrate 1 also includes a dielectric layer 4 disposed directly on the trapping layer 2. For example, the dielectric layer 4 may be composed of or include silicon dioxide or silicon nitride. It may also be a stack of these materials. The thickness of the dielectric layer 4 may be between 10 nm and 10 micrometers, but in the context of this description, this layer has a relatively substantial thickness, for example, greater than 200 nm, and preferably between 200 nm and 10 micrometers, or between 200 nm and 1 micrometer. This is especially true when the final substrate is targeted at photonic applications requiring a thick dielectric layer 4 (typically greater than 600 nm and even up to 10 micrometers).

[0028] The final substrate S includes a thin layer 5 located on and in contact with the dielectric layer 4 of the carrier substrate 1. The thin layer is typically made of monocrystalline silicon, but it may include any other material, whether semiconductor or other, depending on the nature of the device to be formed thereon or therein. Thus, when the final substrate S is intended to receive a semiconductor integrated assembly, the thin layer 5 may be made of monocrystalline silicon or any other semiconductor material (such as germanium, silicon germanium, or silicon carbide).

[0029] Specifically, semiconductor integrated components can be photonic in nature, such as passive or active components, like waveguides, ring resonators, or Mach-Zende interferometers. This type of device (specifically optical phase shifters and switches) must be able to efficiently transmit large amounts of signals while adhering to specifications for compactness, low power consumption, limiting electromagnetic coupling effects, and switching speed, which can be advantageously provided by advanced substrates (such as final substrate S).

[0030] Advantageously, the photonic device 51 (shown as illustrated in FIG4) forms a switch, waveguide, phase shifter, modulator, laser emitter, amplifier, directional coupler, filter and / or multiplexer.

[0031] When the final substrate S is intended to receive a surface acoustic wave filter, the thin layer 5 may be made of piezoelectric and / or ferroelectric materials, such as lithium tantalate or lithium niobate. The thin layer 5 may also include a finished or semi-finished integrated assembly formed on the donor substrate and transferred to the carrier substrate 1 during the production of the final substrate S. Generally, the thin layer 5 may have a thickness between 10 nm and 10 micrometers.

[0032] Preparation of carrier substrate

[0033] A process for preparing the carrier substrate 1 shown in FIG. 1 is now presented. In a first step, a base substrate 3 is provided with a charge trapping layer 2 exhibited on its main surface. When made of polycrystalline silicon, this trapping layer 2 can be produced using industrial standard deposition equipment. Therefore, it can involve RPCVD (remote plasma-assisted chemical vapor deposition) or PECVD (plasma-assisted chemical vapor deposition). Low-pressure chemical vapor deposition (LPCVD) is also possible. However, as seen above, the formation of the trapping layer on or in the base substrate 3 can be achieved in many other ways (e.g., by implanting heavy species or by making the surface layer of the base substrate 3 porous).

[0034] Before forming the charge trapping layer 2 thereon, a dielectric thin layer may be formed on the base substrate 3 by means of oxidation or deposition of oxide thickness, for example.

[0035] In the embodiment where an arcuate compensation layer is provided, this first step includes a subsequent first sub-step (Figures 3A and 3B) for forming the compensation layer on all exposed surfaces of the base substrate prior to forming the capture layer. For the same reasons of usability and cost mentioned above, the compensation layer 32 may be made of silicon oxide formed by thermally oxidizing the silicon base substrate 3, for example at a temperature between 800°C and 1100°C.

[0036] In the subsequent sub-step shown in FIG3C, before the formation of the trapping layer 2 and the dielectric layer 4, the compensation layer 32 is at least partially removed from the front side 31. Specifically, this sub-step can be performed by polishing the front side 31. It is conceivable to leave a portion of the compensation layer 32 on the front side 31 of the base substrate to form a dielectric thin layer on which the charge trapping layer will be formed.

[0037] When the compensation layer 32 is present on both the main surface 31 and the back surface 33 of the base substrate 3, the stress in this layer is balanced. The sub-step of removing the compensation layer 32 from the main surface 31 while retaining the layer 32 at least on the back surface 33 disrupts this balance and causes curvature in the base substrate 3. Therefore, when the compensation layer 32 is subjected to compressive strain, the base substrate 3 will exhibit negative curvature, giving it a slightly concave shape.

[0038] Therefore, for example, when the base substrate 3 is made of silicon and has a known thickness of about 650 micrometers, maintaining only the compensation layer 32 (about 600 nm thick) made of thermally oxidized silicon on the back surface 33 will produce a concave curvature of about -110 μm. This concave curvature will at least partially compensate for the deformation caused by the trapping layer and the dielectric layer.

[0039] Therefore, the thickness of the compensation layer 32 is determined based on the target thicknesses of the charge trapping layer 2 and the dielectric layer 4 so that the carrier substrate exhibits a predetermined permissible curvature after these layers are formed. For a substrate with a diameter of 300 mm, this permissible curvature is at most 100 micrometers (and preferably at most 60 micrometers or 40 micrometers), and this maximum value allows the carrier substrate to be handled and processed using conventional equipment. The thickness of the compensation layer 32 is typically between 500 nm and 1000 nm.

[0040] Figure 3D shows the carrier substrate of this embodiment when this first step is completed (i.e., after the formation of the charge trapping layer 2).

[0041] In the second step of the process for preparing the carrier substrate 1, regardless of whether the base substrate is provided with a compensation layer, the dielectric layer 4 is formed on the charge trapping layer 2. According to an important aspect of the process, the formation of the dielectric layer 4 is performed simultaneously with the deposition and ion sputtering of the dielectric layer 4.

[0042] This technique for forming a dielectric layer can be performed by placing a base substrate 3, which provides a trapping layer 2 and may provide a compensation layer 32, in the chamber of an HDP-CVD (high-density plasma chemical vapor deposition) apparatus.

[0043] This chamber is provided with a plasma source located in the upper part of the chamber, excited by an RF source (e.g., having a frequency of about 13 MHz), to form plasma in which electrons and ions present at a very high density (about 10^10 to 10^12 per cm3) can be extracted. A substrate introduced into the chamber is disposed on a carrier forming a second electrode connected to a second RF source (e.g., having a frequency of about 2 MHz), which is generally referred to in the field as a "bias source," to allow ions and electrons to be projected onto the exposed surface of the substrate, the effect being a slight etching (sputtering) of this surface. The first and second sources are activated at a power typically between 1000 W and 10000 W (for a device intended to receive a substrate in the form of a circular wafer with a diameter of 300 mm). A precursor gas is introduced into the chamber to react with each other above the exposed surface of the substrate and gradually form a dielectric layer thereon. The chamber is maintained at a very low pressure of about one mTorr or several tens of mTorr by circulating the injected gas and residual species from the reaction and extracting them from the chamber. The chamber is also maintained at a relatively low temperature, typically between 200°C and 450°C. Therefore, to form the silicon oxide layer, silicon-containing gas, oxygen-containing gas, and an inert gas (e.g., argon or helium) are introduced into the chamber. By controlling the chamber parameters, specifically the inlet flow rate and source power, the deposition and sputtering effects occurring simultaneously during the formation of the dielectric layer in the chamber can be controlled at a deposition / sputtering ratio between 1 and 10, preferably between 2 and 5. This combined effect tends to compensate for the topology that may exist on the substrate surface and form a particularly uniform and smooth layer. Accordingly, it should be recalled that to obtain a surface that can be bonded by molecular bonding, the surface must exhibit a roughness of less than 0.5 nm RMS (root mean square) within a measurement range of 10 μm × 10 μm. What is particularly surprising is that, specifically for relatively thick dielectric layers greater than 200 nm, this formation process allows for low roughness requirements. Specifically, in typical use with HDP CVD equipment, the formed layers are intended to fill topological patterns exhibiting substantial aspect ratios, and these depositions must be followed by a polishing step. Therefore, it is undesirable to form a dielectric layer on a charge-trapping layer resulting in a layer exhibiting surface roughness as low as 0.5 nm RMS within a 10 μm × 10 μm measurement range.

[0044] Returning to the process for preparing the carrier substrate 1, this process includes forming the dielectric layer 4 by performing this technique of simultaneous deposition and ion sputtering. In a preferred embodiment, the dielectric layer 4 is composed of silicon oxide. In this case, and for a carrier substrate 1 having a size of 300 mm, the gas introduced into the chamber may include silane (SiH4), oxygen, and argon (or another inert gas, such as helium) with a mass flow rate between 20 sccm and 80 sccm (standard cubic centimeters per minute). The power of the source may be selected between 1000 W and 5000 W. The dielectric layer 4 is formed at a temperature between 300°C and 450°C, preferably between 350°C and 400°C, and the pressure in the chamber is maintained below atmospheric pressure, and preferably below 5 mTorr. These parameters can be controlled to define a deposition / sputtering ratio preferably between 2 and 5.

[0045] Of course, the dielectric layer 4 other than the silicon oxide layer can be selected to be formed by modifying the nature of the gas introduced into the chamber (N2, NH3 or N2O instead of oxygen in this example) and by adjusting other parameters of the procedure.

[0046] Specifically, the airflow entering the chamber can be controlled to form the dielectric layer 4, comprising at least one alternation of a first base layer of silicon oxide and a second base layer of silicon oxynitride or silicon nitride. Thus, in a particular embodiment, the silicon oxynitride or nitride layer may be embedded within the thickness of the dielectric layer, which is primarily formed of silicon oxide. Therefore, a barrier layer is formed within the dielectric layer 4, which allows for the restriction of the diffusion of certain species (e.g., hydrogen) through the depth of the dielectric layer, particularly during subsequent steps in the production of the final substrate. Advantageously, this barrier of silicon oxynitride or nitride is configured close to the free surface of the dielectric layer, for example, beneath a silicon oxide surface layer of 10 nm to 50 nm.

[0047] In any case, and regardless of the exact nature of the dielectric layer 4, the deposition chamber will be maintained for a sufficiently long operating time to form the dielectric layer 4 of a selected thickness. In the context of this description, this thickness is relatively thick, for example, thicker than 200 nm and advantageously between 200 nm and 1 micrometer or even 10 micrometers. As a supplementary example, this could be a problem of forming a dielectric layer 4 with a thickness of 400 nm.

[0048] Tests conducted by the applicant have demonstrated that forming this 400 nm silicon oxide layer on a polycrystalline silicon trapping layer 2 in the shape of a circular wafer with a diameter of 300 mm can produce a carrier substrate 1 with properties particularly suitable for the formation of the final substrate S.

[0049] Therefore, and quite unexpectedly, as mentioned above, the exposed surface of the carrier substrate 1 (i.e., the free surface of the dielectric layer 4 made of silicon oxide) exhibits a surface roughness of less than 2 angstroms (RMS) in both the 10 μm × 10 μm measurement range and the 30 μm × 30 μm measurement range. This roughness is similar to the roughness obtained by oxidizing the trapping layer made of polycrystalline silicon after the layer has undergone a polishing step to adjust its roughness. It is low enough to be compatible with steps involving molecular bonding. Therefore, the proposed procedure for forming the dielectric layer 4 is highly advantageous because it allows the polishing step to be omitted, thereby simplifying the procedure for preparing the carrier substrate 1.

[0050] In addition, the interface between the silicon oxide dielectric layer 4 and the polycrystalline silicon trapping layer exhibits a roughness of less than 2 angstroms RMS (for the same measurement range of 10 μm × 10 μm and 30 μm × 30 μm), while the silicon oxide dielectric layer with the same thickness of 400 nm formed by the polycrystalline silicon oxide trapping layer exhibits a roughness of about 50 angstroms RMS.

[0051] The process for forming dielectric layer 4 is carried out at relatively low temperatures, below 400°C and about 380°C, to form a silicon oxide dielectric layer. Therefore, the recrystallization of charge trapping layer 2 and the loss of electric traps, which may occur when the layer is exposed to higher temperatures via solid-phase recrystallization from this layer, are avoided.

[0052] Furthermore, the deformation of the carrier substrate 1 caused by the formation of the dielectric layer 4 according to the proposed technology (approximately 100 micrometers on a 300 mm carrier substrate 1 provided with a 400 nm silicon oxide layer) is significantly less than the deformation caused by the charge trapping layer of polycrystalline silicon oxide (approximately 150 micrometers). Again, this property makes the carrier substrate 1 obtained by the procedure according to the invention more compatible with steps involving molecular bonding. This property is further improved when the carrier substrate is provided with a compensation layer, the thickness of which can be selected to precisely compensate for the deformation caused by the dielectric layer 4 and, to a lesser extent, by the charge trapping layer. This embodiment is particularly useful when the dielectric layer exhibits a substantial thickness greater than 600 nm.

[0053] It should be noted that the process used to prepare the carrier substrate 1 can also be incorporated into the annealing step of the dielectric layer 4. This annealing (referring to degassing or densification annealing) is advantageously performed in a neutral atmosphere. It is performed at a temperature higher than the deposition temperature of the dielectric layer 4 and preferably lower than 950°C for a relatively short time, shorter than 1 hour, for example, 30 minutes. The time and temperature of this annealing are chosen to avoid or at least limit the recrystallization of the trapping layer 2. This annealing step can affect the curvature of the carrier substrate and will be taken into account when determining the thickness of the compensation layer.

[0054] The final substrate is obtained after the fabrication process described above is completed, which is a carrier substrate 1 having at least one capture layer 2 and a dielectric layer 4 continuously disposed on the base substrate 3. The carrier substrate may also include a compensation layer 32 that allows the curvature of the substrate to remain less than or equal to 100 micrometers (e.g., between 100 micrometers and 60 micrometers, or even with a thicker dielectric layer, e.g., 600 nm).

[0055] As mentioned above, the carrier substrate 1 is intended to receive the thin layer 5 by transfer and thus form the final substrate S. The carrier substrate 1 exhibits properties suitable (specifically, in terms of surface roughness and deformation) for receiving this thin layer 5.

[0056] As is well known, this transfer is typically achieved by bonding the free surface of the donor substrate to the carrier substrate 1 (preferably by molecular bonding). Since the dielectric layer 4 has already been formed on the carrier substrate 1, the donor substrate itself does not need to provide this dielectric layer. However, the donor substrate may provide a thin dielectric layer (e.g., thinner than 150 nm), but in any case, this thickness will always be much less than the thickness of the dielectric layer 4 of the final structure S, because a portion of this thickness will be provided by the dielectric layer 4 formed on the carrier substrate 1. Therefore, the donor substrate preferably does not have any intentionally formed dielectric surface layer. The nature of the donor substrate is selected according to the desired nature of the thin layer 5, as described in the preceding paragraphs of this description. Thus, it may be a substrate formed of a single-crystal silicon semiconductor (e.g., silicon), or a substrate formed of a piezoelectric material or including a surface layer of such piezoelectric material.

[0057] Following this bonding step, the thickness of the donor substrate is reduced to form thin layer 5. This reduction step can be performed by mechanical or chemical thinning, but in the context of this description and to best utilize the advantageous properties of the carrier substrate 1, the thickness of the donor substrate is reduced by splitting on the weak surface described above, for example, according to the principles of Smart Cut™ technology, as explained in the description of this application. This weak surface, together with the free surface of the donor substrate, defines thin layer 5.

[0058] It should be noted that since the donor substrate preferably does not have a surface dielectric layer (or has a relatively low thickness layer), the dose and energy of the species implanted to form the weakened plane can be kept at reasonable levels even when the final substrate S exhibits a dielectric layer 4 of 200 nm or greater.

[0059] The transfer of the thin layer does not change the stress balance, so that at this stage, the final substrate exhibits a curvature that is very similar to that of the carrier substrate.

[0060] After the thinning or preferably splitting step, steps for completing the thin layer 5, such as polishing, heat treatment in a reducing or inert atmosphere, and sacrificial oxidation, may be performed after the thickness reduction step.

[0061] When the donor substrate is merely a substrate (i.e., excluding integrated devices), a final substrate S is thus formed "on-insulator," wherein the thin layer 5 comprises the original material layer of the carrier substrate 1 according to the present invention. As illustrated in FIG4, this final substrate S can then be used to form integrated or photonic devices. When the donor substrate has been pre-treated to form integrated devices on its surface, a thin layer 5 comprising such devices is obtained at the end of this process.

[0062] Of course, the present invention is not limited to the described embodiments and can be modified without departing from the scope of the present invention as defined by the claims. [Simplified Explanation of the Diagram]

[0011] Other features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings, in which:

[0012] FIG1 shows a carrier substrate of the layer transfer process according to the present invention;

[0013] Figure 2 shows the final substrate obtained when the layer transfer process is completed according to the present invention;

[0014] Figures 3A to 3E show one embodiment of the carrier substrate;

[0015] Figure 4 shows the final substrate obtained when completing the layer transfer procedure of one embodiment.

Claims

1. A method for transferring a thin layer (5) to a carrier substrate (1), comprising the following steps: A carrier substrate (1) is prepared using a preparation process including providing a base substrate (3) having a charge trapping layer (2) on a main surface and forming a dielectric layer (4) having a thickness greater than 200 nm on the charge trapping layer (2), the formation of the dielectric layer (4) being performed simultaneously with the deposition and ion sputtering of the dielectric layer; a donor substrate is bonded to the dielectric layer (4) of the carrier substrate (1) by molecular bonding without the need for polishing to prepare the free surface of the dielectric layer (4), the donor substrate being characterized by defining the weak surface of the thin layer (5); the donor substrate is split at the weak surface to release the thin layer (5) and transfer it to the carrier substrate (1).

2. The method of the aforementioned claim, wherein the preparation process includes forming an arc-shaped compensation layer (32) on the back side of the base substrate (3) opposite to the main surface.

3. The method of the aforementioned claim, wherein the bow-shaped compensation layer (32) has a thickness between 500 nm and 1000 nm.

4. The method of any of the preceding claims, wherein the base substrate (3) is a monocrystalline silicon substrate exhibiting a resistivity of more than 600 ohm·cm.

5. The method of any of the preceding claims, wherein the charge trapping layer (2) comprises polycrystalline silicon.

6. The method of any of the preceding claims, wherein the charge trapping layer (2) comprises carbon.

7. The method of any of the preceding claims, wherein the charge trapping layer (2) has a thickness between 1 micrometer and 20 micrometers.

8. The method of any of the preceding claims, wherein the dielectric layer (4) is composed of silicon oxide.

9. The method of any of the preceding claims, wherein the dielectric layer (4) comprises a barrier layer made of silicon nitride or silicon oxynitride.

10. The method of any of the preceding claims, wherein the dielectric layer (4) has a thickness between 200 nm and 10 micrometers, and preferably between 600 nm and 10 micrometers.

11. The method of any of the preceding claims, wherein the deposition / sputtering ratio is between 1 and 10, preferably between 2 and 5.

12. The method of any of the preceding claims, wherein the dielectric layer (4) is formed at a temperature between 300°C and 450°C, preferably between 350°C and 400°C.

13. The method of any of the preceding claims, wherein the dielectric layer (4) is formed in an atmosphere exhibiting a pressure lower than atmospheric pressure.

14. The method of any of the preceding claims further includes annealing the dielectric layer (4) in a neutral atmosphere and at a temperature exceeding the temperature at which the dielectric layer is formed, preferably below 950°C.

15. The method of any of the preceding claims, wherein the free surface of the dielectric layer (4) exhibits a roughness of less than 0.5 nm RMS value within a measurement range of 10 μm × 10 μm.

16. The method of any of the preceding claims, wherein the substrate has no dielectric surface layer.

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