Heterogeneous height logic cell architecture

Abstract

A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h 1and a first number of M xlayer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h 2and a second number of M xlayer tracks that extend unidirectionally in the second direction, where h

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 065,746, entitled “HETEROGENEOUS HEIGHT LOGIC CELL ARCHITECTURE”, filed on October 8, 2020, which is expressly incorporated herein by reference in its entirety.

[0002] This disclosure generally relates to standard / logic unit architecture, and more specifically, to heterogeneous high standard / logic unit architecture. [Previous Technology]

[0003] Standard cell devices are integrated circuits (ICs) that implement digital logic. Such standard cell devices can be reused multiple times within application-specific integrated circuits (ASICs). ASICs, such as system-on-a-chip (SoC) devices, can contain thousands to millions of standard cell devices. Typical ICs consist of a stack of layers formed sequentially. Each layer can be stacked or overlaid on the previous layer and patterned to define the shape of transistors (e.g., field-effect transistors (FETs), FinFETs, full-around-gate (GAA) FETs (GAAFETs), and / or other multi-gate FETs) and to connect the transistors to the circuitry.

[0004] A higher standard cell architecture used for high standard cells can provide higher performance than a lower standard cell architecture used for low standard cells, while a lower standard cell architecture used for low standard cells can provide better area efficiency than a higher standard cell architecture used for high standard cells. Low standard cell architectures and high standard cell architectures can be used separately to achieve either higher performance or higher area efficiency. Currently, there is a need for heterogeneous high standard cell architectures that utilize both low and high standard cells. [Summary of the Invention]

[0005] In one aspect of this disclosure, a metal-oxide-semiconductor (MOS) IC includes a first transistor logic assembly. The first transistor logic assembly has a first plurality of gate interconnects extending in a first direction. The first plurality of gate interconnects have a gate spacing. The first transistor logic assembly has one or more power rail pairs that provide a power supply voltage and a ground voltage to the logic between each corresponding power rail pair. The first transistor logic assembly has a first cell height h1 and has a first number of metal x (Mx) layer rails extending unidirectionally in a second direction between each power rail pair. The second direction is orthogonal to the first direction. The MOS IC also includes a second transistor logic assembly. The second transistor logic assembly is adjacent to the first transistor logic assembly in the first direction. The second transistor logic assembly has a second plurality of gate interconnects extending in the first direction. The second plurality of gate interconnects have the same gate spacing as the first plurality of gate interconnects, and each is collinear with a corresponding one of the first plurality of gate interconnects. The second transistor logic assembly has one or more power rail pairs that provide a power supply voltage and a ground voltage to the logic between each corresponding power rail pair. The second transistor logic set has a second cell height h2 and a second number of Mx layer tracks extending unidirectionally in a second direction between each power supply track pair. The second cell height h2 is greater than the first cell height h1. The second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of the following is satisfied: the height ratio hR = h2 / h1 is a non-integer value, or a subset of the first transistor logic set and a subset of the second transistor logic set are within a single logic cell.

Implementation Method

[0013] The specific embodiments described below with reference to the figures are intended as descriptions of various configurations and are not intended to represent the only configuration in which the concepts described herein can be practiced. The specific embodiments include particular details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, known structures and components are shown in block diagram form to avoid confusion with these concepts. Apparatus and methods will be described in the following specific embodiments and can be illustrated in the figures through various blocks, modules, components, circuits, steps, programs, algorithms, elements, etc.

[0014] FIG1 is a first figure 100 showing a side view of various layers within a standard cell of an IC. The various layers change in the y-direction. As shown in FIG1, the transistor has a gate 102 (which may be referred to as POLY, even if the gate 102 may be formed of metal, polysilicon, or a combination of polysilicon and metal), a source 104, and a drain 106. The source 104 and drain 106 may be arranged on a silicon substrate and formed by fins. The gate 102 may extend in a first direction (e.g., a direction perpendicular to the z-axis away from the page), and the fins may extend in a second direction orthogonal to the first direction (e.g., a horizontal direction along the x-axis). A contact layer interconnect 108 (also referred to as a metal POLY (MP) layer interconnect) may contact the gate 102. A contact layer interconnect 110 (also referred to as a metal diffused (MD) layer interconnect) may contact the source 104 and / or the drain 106. A via 112 may contact the contact layer interconnect 110. Metal 1 (M1) layer interconnect 114 can contact via 112. M1 layer interconnect 114 can extend only in the second direction (i.e., unidirectionally in the second direction). Via V1 116 can contact M1 layer interconnect 114. Metal 2 (M2) layer interconnect 118 can contact via V1 116. M2 layer interconnect 118 can extend only in the first direction (i.e., unidirectionally in the first direction). M2 layer is the lowest vertical layer. Specifically, M2 layer can be unidirectional in the vertical direction and is the vertically unidirectional layer closest to the silicon substrate. Higher layers include a via layer containing via V2 and a metal 3 (M3) layer containing M3 layer interconnects. M3 layer interconnects can extend in the second direction.

[0015] Figure 2 is a second figure 200 illustrating a side view of a standard cell and various layers within an IC. The various layers change in the y-direction. As shown in Figure 2, the transistor has a gate 202, a source 204, and a drain 206. The source 204 and drain 206 may be formed by fins. The gate 202 may extend in a first direction (e.g., a direction perpendicular to the z-axis away from the page), and the fins may extend in a second direction orthogonal to the first direction (e.g., a horizontal direction along the x-axis). Contact layer interconnect 208 may contact the gate 202. Contact layer interconnect 210 may contact the source 204 and / or drain 206. Through-hole 212 may contact the contact layer interconnect 208. M1 layer interconnect 214 may contact the through-hole 212. M1 layer interconnect 214 may extend only in the second direction (i.e., unidirectionally in the second direction). Through-hole V1 216 may contact the M1 layer interconnect 214. M2 layer interconnect 218 can contact via V1 216. M2 layer interconnect 218 can extend only in a first direction (i.e., unidirectionally in the first direction). M2 layer is the lowest vertical layer. Specifically, M2 layer can be unidirectional in the vertical direction and is the vertical unidirectional layer closest to the silicon substrate. Higher layers include via layers containing via V2 and M3 layers containing M3 layer interconnects. M3 layer interconnects can extend in a second direction. Although the IC is illustrated using FinFET in Figures 1 and 2, the IC can include other multi-gate FETs, such as dual-gate FETs, tri-gate FETs, and / or GAAFETs.

[0016] A standard cell is a cell standardized in a design. The same standard cell can be used thousands of times throughout an IC. Hereinafter, a standard cell may be referred to as a logic cell. A logic cell has a set of inputs and a set of outputs, where the inputs / outputs are interconnected via intra-cell routing within the logic cell (rather than inter-cell routing across different logic cells). Using the same intra-cell routing configuration, such a logic cell can be used hundreds to thousands of times in an IC. The height of the cell is equal to the distance between corresponding power rail pairs located at the top and bottom of the cell (in the first direction in Figures 1 and 2), where the top and bottom cell edges extend through the center of each power rail. The cell height of a logic cell can be reduced through technological improvements and design advancements. Regarding technological improvements, the cell height can be reduced by transitioning to a smaller technology program node, where the minimum feature size of the program is reduced. This improvement reduces the cell height of the logic cell without reducing the number of rails within the logic cell used for intra-cell routing (interconnections between transistors within the logic cell to enable the logic cell to provide logic functionality). Regarding design advancements, the cell height can be reduced by reducing the number of rails within the logic cell used for intra-cell routing. Reducing the cell height of a logic cell by decreasing the number of tracks used for intra-cell routing (e.g., from 5 to 4, 3, or 2) increases area efficiency but may make intra-cell routing more difficult, if not impossible. If intra-cell routing is still possible, reducing the number of tracks may degrade logic cell performance. As discussed above, a higher logic cell architecture for high logic cells can provide higher performance than a lower logic cell architecture for low logic cells, and a lower logic cell architecture for low logic cells can provide better area efficiency than a higher logic cell architecture for high logic cells. Both higher performance and area efficiency can be achieved by utilizing both low-logic and high logic cell architectures with the same technology program nodes. Heterogeneous height logic cell architectures utilizing low-logic and high logic cells are described below.

[0017] Figure 3 is a first figure 300, a top view conceptually illustrating a heterogeneous height logic cell architecture. As shown in Figure 3, the heterogeneous height logic cell architecture may include a hybrid height architecture, wherein a higher height portion 370 having height h2 is adjacent to a lower height portion 380 having height h1, where h2 > h1 and a power supply rail 330 is shared between the two portions. The height ratio hR = h2 / h1 between the two heights may be a non-integer value in a first configuration or an integer value (e.g., 2, 3) in a second configuration. The power supply rail 330 may provide a power supply voltage Vdd or a ground voltage Vss to both the higher height portion 370 and the lower height portion 380. The higher height portion 370 includes power supply rails 310, 330 extending in a second direction and includes a gate interconnect 360 extending in a first direction orthogonal to the second direction. The higher height portion 370 provides a set of Mx layer rails 320 extending unidirectionally in the second direction between the power supply rails 310, 330. The Mx layer can be the lowest metal layer extending unidirectionally in the second direction. For example, the Mx layer can be an M1 metal layer or an M0 metal layer. The Mx layer track 320 can be used for intra-cell routing. The lower height portion 380 includes power supply rails 330, 350 extending in the second direction and includes gate interconnects 360. The lower height portion 380 provides a set of Mx layer tracks 340 extending unidirectionally in the second direction between the power supply rails 330, 350. The Mx layer track 340 can also be used for intra-cell routing.

[0018] For both the higher height portion 370 and the lower height portion 380, the gate interconnects 360 have the same spacing pg, where the spacing pg is the distance between the centers of adjacent gate interconnects. The spacing p2 of the set of Mx layer tracks 320 may be the same as or different from the spacing p1 of the set of Mx layer tracks 340, where the spacings p1 and p2 are the distance between the centers of corresponding adjacent Mx layer tracks. In the first configuration, the set of Mx layer tracks 320 and the set of Mx layer tracks 340 have the same spacing (p2=p1). In the second configuration, the set of Mx layer tracks 320 and the set of Mx layer tracks 340 have different spacings (p2≠p1).

[0019] The higher-height portion 370 can be used for complex logic cells (e.g., flip-flops or other complex or high-performance logic) because it provides a sufficient number of Mx-layer tracks 320 for intra-cell routing of the complex logic cell. The higher-height portion 370 also provides a larger area (i.e., a larger number of fins) for p-type and n-type diffusion regions, thus providing higher performance than the lower-height portion 380. The lower-height portion 380 can be used for simple logic cells (e.g., combinational logic cells) because it provides fewer Mx-layer tracks 340.

[0020] Logic units can be located within the higher height portion 370 and the lower height portion 380. A logic unit may span only one of portions 370 and 380 or span both portions 370 and 380. Referring again to the height ratio hR = h2 / h1, the height ratio hR = h2 / h1 can be a non-integer value or an integer value. If the height ratio hR = h2 / h1 is a non-integer value, then an individual logic unit may span one of portions 370 and 380 and / or span both portions 370 and 380. Therefore, the individual logic units of the IC can have a homogeneous height design and / or a heterogeneous height design. If the height ratio hR = h2 / h1 is an integer value, then two configurations are possible. In the first configuration, an individual logic unit may span both portions 370 and 380. Therefore, all individual logic units of the IC can have a heterogeneous height design. In the second configuration, an individual logic unit may span one of portions 370 and 380 and / or both portions 370 and 380. Therefore, individual logic cells of an IC can have homogeneous height designs and / or heterogeneous height designs. Example locations of logic cells within a heterogeneous height logic cell architecture are illustrated in Figures 4 and 5.

[0021] Figure 4 is a second figure 400, a top view conceptually illustrating a heterogeneous height logic unit architecture. As shown in Figure 4, logic unit 402 can be a low single-height unit with height h1, logic unit 404 can be a low double-height unit with height 2*h1, logic unit 408 can be a high single-height unit with height h2, logic unit 410 can be a high double-height unit with height 2*h2, and logic unit 406 can span both high and low height portions, having height h1+h2. In one example, logic units 402 and 404 can be simple logic units; logic units 408 and 410 can be complex logic units; and logic unit 406 can have a mixture of simple and complex functions.

[0022] Figure 5 is a third figure 500, a top view conceptually illustrating a heterogeneous height logic unit architecture. As shown in Figure 5, logic unit 502 can be a low single-height unit with height h1, logic unit 506 can be a low double-height unit with height 2*h1, logic unit 514 can be a high single-height unit with height h2, logic unit 512 can be a high double-height unit with height 2*h2, and logic units 504, 508, and 510 can include high and low height portions. For example, logic unit 504 can sequentially include a low portion, a high portion, a high portion, and a low portion, with a height of 2*h1+2*h2; logic unit 508 can include a low portion and a high portion, with a height of h1+h2; and logic unit 510 can sequentially include a high portion, a low portion, a low portion, and a high portion, with a height of 2*h1+2*h2. In one example, logic units 502 and 506 can be simple logic units; logic units 512 and 514 can be complex logic units; and logic units 504, 508, and 510 can have a mixture of simple and complex functions.

[0023] Figure 6 is a fourth figure 600, a top view conceptually illustrating a heterogeneous height logic cell architecture. The heterogeneous height logic cell architecture may include a lower height portion having a first height h1 and a higher height portion having a second height h2, where h2 > h1, and where the higher height portion has a greater number of Mx layer tracks than the lower height portion. A logic cell 602 may include both the higher height portion and the lower height portion. For example, logic cell 602 may include a first transistor logic set 604 and a second transistor logic set 606. The transistor logic includes p-type MOS (pMOS) and n-type MOS (nMOS) transistors, which form logic gates within the corresponding higher / lower height portions. The height hm of a logic unit 602 is equal to (n1-1)h1 + (n2-1)h2, where n1 ≥ 2 and is the number of power supply rails in the first transistor logic set, and n2 ≥ 2 and is the number of power supply rails in the second transistor logic set, and n1 + n2 - 1 is the total number of power supply rails in a logic unit 602. As shown in Figure 6, n1 = 7 and n2 = 3, therefore the height of logic unit 602 is 6 * h1 + 2 * h2.

[0024] Figure 7 is a set of Figures 700, 720, 740, and 760, which conceptually illustrate different configurations of heterogeneous height logic unit architectures from top views. Each transistor logic set is depicted by a single-height unit representing a set of Ms units, where s is a specific set and the transistor logic set has a height Ms*h. For example, in Figure 700, a first transistor logic set with a smaller height architecture includes n1 = M1 + 1 power rails and has a height M1*h1, and correspondingly, a height of (n1 - 1)h1. Adjacent to the first transistor logic set is a second transistor logic set with a larger height architecture. The second transistor logic set includes n2 = M2 + 1 power rails and has a height M2*h2, and correspondingly, a height of (n2 - 1)h2. Adjacent to the second transistor logic set is a third transistor logic set with a smaller height architecture. The third transistor logic set comprises n3 = M3 + 1 power rails and has a height of M3 * h1, corresponding to a height of (n3 - 1)h1. Adjacent to the third transistor logic set are different sets of higher and lower height architectures, ultimately leading to the Nth transistor logic set with a lower height architecture. The Nth transistor logic set comprises nN = MN + 1 power rails and has a height of MN * h1, corresponding to a height of (nN - 1)h1.

[0025] As another example, in Figure 720, a first transistor logic set with a smaller height architecture includes n1 = M1 + 1 power rails and has a height of M1 * h1, correspondingly, a height of (n1 - 1)h1. Adjacent to the first transistor logic set is a second transistor logic set with a larger height architecture. The second transistor logic set includes n2 = M2 + 1 power rails and has a height of M2 * h2, correspondingly, a height of (n2 - 1)h2. Adjacent to the second transistor logic set is a third transistor logic set with a smaller height architecture. The third transistor logic set includes n3 = M3 + 1 power rails and has a height of M3 * h1, correspondingly, a height of (n3 - 1)h1. Adjacent to the third transistor logic set are different sets with different larger and smaller height architectures, ultimately resulting in an Nth transistor logic set with a larger height architecture. The Nth transistor logic set includes nN=MN+1 power supply rails and has a height of MN*h2, and correspondingly, a height of (nN-1)h2.

[0026] As another example, in Figure 740, a first transistor logic set with a higher height architecture includes n1 = M1 + 1 power rails and has a height of M1 * h2, correspondingly, a height of (n1 - 1)h2. Adjacent to the first transistor logic set is a second transistor logic set with a lower height architecture. The second transistor logic set includes n2 = M2 + 1 power rails and has a height of M2 * h1, correspondingly, a height of (n2 - 1)h1. Adjacent to the second transistor logic set is a third transistor logic set with a higher height architecture. The third transistor logic set includes n3 = M3 + 1 power rails and has a height of M3 * h2, correspondingly, a height of (n3 - 1)h2. Adjacent to the third transistor logic set are different sets with different higher and lower height architectures, ultimately resulting in an Nth transistor logic set with a lower height architecture. The Nth transistor logic set includes nN=MN+1 power supply rails and has a height of MN*h1, and correspondingly, a height of (nN-1)h1.

[0027] As another example, in Figure 760, a first transistor logic set with a higher height architecture includes n1 = M1 + 1 power rails and has a height of M1 * h2, correspondingly, a height of (n1 - 1)h2. Adjacent to the first transistor logic set is a second transistor logic set with a lower height architecture. The second transistor logic set includes n2 = M2 + 1 power rails and has a height of M2 * h1, correspondingly, a height of (n2 - 1)h1. Adjacent to the second transistor logic set is a third transistor logic set with a higher height architecture. The third transistor logic set includes n3 = M3 + 1 power rails and has a height of M3 * h2, correspondingly, a height of (n3 - 1)h2. Adjacent to the third transistor logic set are different sets with different higher and lower height architectures, ultimately resulting in an Nth transistor logic set with a higher height architecture. The Nth transistor logic set includes nN=MN+1 power supply rails and has a height of MN*h2, and correspondingly, a height of (nN-1)h2.

[0028] Typically, a logic unit may include any combination of the logic unit sets shown in Figures 700, 720, 740, and 760. For example, if a logic unit includes a first transistor logic set, a second transistor logic set, and a third transistor logic set, having a combined low-high-low architecture, then the height hm of the logic unit will be equal to (n1-1)h1 + (n2-1)h2 + (n3-1)h1, where n1 ≥ 2 and is the number of power supply rails in the first transistor logic set, n2 ≥ 2 and is the number of power supply rails in the second transistor logic set, and n3 ≥ 2 and is the number of power supply rails in the third transistor logic set, where n1 + n2 + n3 - 2 is the total number of power supply rails in a logic unit. Furthermore, in another example, if a logic unit comprises a first transistor logic set, a second transistor logic set, and a third transistor logic set, having a combined high-low-high architecture, then the height hm of the logic unit will be equal to (n1-1)h2+(n2-1)h1+(n3-1)h2, where n1≥2 and is the number of power supply rails in the first transistor logic set, n2≥2 and is the number of power supply rails in the second transistor logic set, and n3≥2 and is the number of power supply rails in the third transistor logic set, where n1+n2+n3-2 is the total number of power supply rails in a logic unit.

[0029] Referring again to Figures 3-7, the MOS IC includes a first transistor logic assembly 380. The first transistor logic assembly 380 has a first plurality of gate interconnects 360 extending in a first direction. The first plurality of gate interconnects 360 have a gate spacing pg. The first transistor logic assembly 380 has one or more power supply rail pairs 330, 350, which provide a power supply voltage and a ground voltage to the logic between each corresponding power supply rail pair 330, 350. The first transistor logic assembly 380 has a first cell height h1 and has a first number of Mx layer rails 340 extending unidirectionally in a second direction between each power supply rail pair 330, 350. The second direction is orthogonal to the first direction. The MOS IC also includes a second transistor logic assembly 370. The second transistor logic assembly 370 is adjacent to the first transistor logic assembly 380 in the first direction. The second transistor logic assembly 370 has a second plurality of gate interconnects 360 extending in the first direction. The second plurality of gate interconnects 360 have the same gate spacing pg as the first plurality of gate interconnects 360 and each is collinear with a corresponding one of the first plurality of gate interconnects 360. Two gate interconnects can be considered "collinear" if they lie on the same straight line. The second transistor logic set 370 has one or more power rail pairs 310, 330 that provide power supply voltage and ground voltage to the logic between each corresponding power rail pair 310, 330. The second transistor logic set 370 has a second cell height h2 and a second number of Mx layer rails 320 extending unidirectionally in a second direction between each power rail pair 310, 330. The second cell height h2 is greater than the first cell height h1. The second number of Mx layer rails 320 is greater than the first number of Mx layer rails 340. The following conditions must be met: (1) The height ratio hR = h2 / h1 is a non-integer value, and the subset of the first transistor logic set and the subset of the second transistor logic set may or may not be in the same logic unit, or (2) The height ratio hR = h2 / h1 is an integer value, and the subset of the first transistor logic set and the subset of the second transistor logic set are in the same logic unit.

[0030] In one configuration, one or more power supply rail pairs 350, 330, 310 of the first and second transistor logic sets 380, 370, with power supply rail 330 extending in a second direction between the first transistor logic set 380 and the second transistor logic set 370. The power supply rail 330 is a common power supply rail and is configured to provide either a power supply voltage or a ground voltage to at least one subset of the first transistor logic set 380 and at least one subset of the second transistor logic set 370.

[0031] In one configuration, the spacing p1 of the first number of Mx layer tracks 340 of the first transistor logic set 380 and the spacing p2 of the second number of Mx layer tracks 320 of the second transistor logic set 370 are the same. In another configuration, p1 ≠ p2.

[0032] In one configuration, the Mx layer is the lowest metal layer extending unidirectionally in the second direction. For example, the Mx layer may be the M0 layer or the M1 layer.

[0033] In one configuration, the height ratio hR = h2 / h1 is a non-integer value, and the first transistor logic set 380 includes a first set of logic cells, and the second transistor logic set 370 includes a second set of logic cells (e.g., see logic cells 402, 404, 408, 410 of FIG. 4; also see logic cells 502, 506, 512, 514 of FIG. 5). Alternatively, the first and second transistor logic sets 370, 380, or subsets of the first and second transistor logic sets 370, 380, may be within the same logic cell (e.g., see logic cell 406 of FIG. 4; also see logic cells 504, 508 of FIG. 5). In this configuration, the height ratio hR = h2 / h1 may or may not be a non-integer value.

[0034] In one configuration, a subset of the first transistor logic sets 380, 604 and a subset of the second transistor logic sets 370, 606 are located within a logic unit 602 (see, for example, FIG. 6; also see logic unit 406 of FIG. 4 and logic units 504, 508 of FIG. 5). The height hm of a logic unit 602 is equal to (n1-1)h1+(n2-1)h2, where n1≥2 and is the number of power supply rails within the subset of the first transistor logic set 604, n2≥2 and is the number of power supply rails within the subset of the second transistor logic set 606, and where n1+n2-1 is the total number of power supply rails within a logic unit 602. In one configuration, a subset of the first transistor logic sets 380, 604 and a subset of the second transistor logic sets 370, 606 are coupled together within a logic unit 602. That is, the first transistor logic sets 380, 604 and the second transistor logic sets 370, 606 can be decoupled from each other or coupled together within a single logic unit 602. When the first transistor logic sets 380, 604 and the second transistor logic sets 370, 606 are decoupled from each other, the single logic unit 602 can have separate inputs and separate outputs for each of the first transistor logic sets 380, 604 and the second transistor logic sets 370, 606. When the first transistor logic sets 380, 604 and the second transistor logic sets 370, 606 are coupled from each other, the single logic unit 602 can have combined inputs and combined outputs for each of the first transistor logic sets 380, 604 and the second transistor logic sets 370, 606.

[0035] In one configuration, for a low-high-low architecture (e.g., see Figures 700 and 720 of FIG7), the MOS IC may further include a third transistor logic set. The third transistor logic set has a third plurality of gate interconnects extending in a first direction. The third plurality of gate interconnects has the same gate spacing as the first plurality of gate interconnects and the second plurality of gate interconnects, and each is collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects. The third transistor logic set has one or more power rail pairs that provide a power supply voltage and a ground voltage to the logic between each corresponding power rail pair. The third transistor logic set has a first cell height h1 and has a first number of Mx layer rails extending unidirectionally in a second direction between each power rail pair. A second transistor logic set is located between the first transistor logic set and the third transistor logic set. In one configuration, the power rails in one or more power rail pairs of the second and third transistor logic sets extend in a second direction between the second and third transistor logic sets. The power supply rails are shared power supply rails and are configured to provide either a power supply voltage or a ground voltage to at least one subset of the second transistor logic set and at least one subset of the third transistor logic set. In one configuration, subsets of the first transistor logic set, subsets of the second transistor logic set, and subsets of the third transistor logic set are located within a single logic unit. The height hm of the single logic unit is equal to (n1-1)h1 + (n2-1)h2 + (n3-1)h1, where n1 ≥ 2 and is the number of power supply rails within the subset of the first transistor logic set, n2 ≥ 2 and is the number of power supply rails within the subset of the second transistor logic set, and n3 ≥ 2 and is the number of power supply rails within the subset of the third transistor logic set, and where n1 + n2 + n3 - 2 is the total number of power supply rails within the single logic unit. In one configuration, subsets of the first transistor logic set, subsets of the second transistor logic set, and subsets of the third transistor logic set are coupled together within a single logic unit.

[0036] In one configuration, for a high-low-high architecture (see, for example, Figures 740 and 760 of FIG7), the MOS IC may further include a third transistor logic set. The third transistor logic set has a third plurality of gate interconnects extending in a first direction. The third plurality of gate interconnects has the same gate spacing as the first plurality of gate interconnects and the second plurality of gate interconnects, and each is collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects. The third transistor logic set has one or more power rail pairs that provide a power supply voltage and a ground voltage to the logic between each corresponding power rail pair. The third transistor logic set has a second cell height h2 and has a second number of Mx layer rails extending unidirectionally in a second direction between each power rail pair. The first transistor logic set is located between the second transistor logic set and the third transistor logic set. In one configuration, the power rails in one or more power rail pairs of the first transistor logic set and the third transistor logic set extend in a second direction between the first transistor logic set and the third transistor logic set. The power supply rails are shared power supply rails, providing either a power supply voltage or a ground voltage to at least one subset of the first transistor logic set and at least one subset of the third transistor logic set. In one configuration, subsets of the first transistor logic set, subsets of the second transistor logic set, and subsets of the third transistor logic set are located within a single logic unit. The height hm of said single logic unit is equal to (n3-1)h2 + (n1-1)h1 + (n2-1)h2, where n1 ≥ 2 and is the number of power supply rails within the subset of the first transistor logic set, n2 ≥ 2 and is the number of power supply rails within the subset of the second transistor logic set, and n3 ≥ 2 and is the number of power supply rails within the subset of the third transistor logic set, and where n1 + n2 + n3 - 2 is the total number of power supply rails within said single logic unit. In one configuration, subsets of the first transistor logic set, subsets of the second transistor logic set, and subsets of the third transistor logic set are coupled together within a single logic unit.

[0037] Referring to Figures 700, 720, 740, and 760 of FIG7, in one configuration, the MOS IC includes n transistor logic sets. The n transistor logic sets are adjacent to one of a first transistor logic set or a second transistor logic set in a first direction. Each of the n transistor logic sets has the same number of gate interconnects extending in the first direction. The gate interconnects have the same gate spacing, and each gate interconnect is collinear with a corresponding gate interconnect in a first plurality of gate interconnects and a second plurality of gate interconnects. Each of the n transistor logic sets has one or more power rail pairs that provide a power supply voltage and a ground voltage to the transistor logic between each corresponding power rail pair. Each of the n transistor logic sets has a first cell height h1 and a first number of Mx layer rails, or a second cell height h2 and a second number of Mx layer rails.

[0038] As discussed above, for the provided heterogeneous height-based logic cell architecture, the relatively high and relatively low logic architectures can be adjacent to each other, both having aligned gate interconnects with the same spacing. The higher logic architecture can provide a larger number of routing tracks compared to the lower logic architecture. The higher logic architecture can provide relatively high performance with lower area efficiency, while the lower logic architecture can provide relatively low performance with higher area efficiency. Logic cells can reside within the higher logic architecture, the lower logic architecture, or both. The heterogeneous height-based logic cell architecture allows for optimized area / performance while also allowing for easier program scaling to smaller technology program nodes.

[0039] It should be understood that the specific order or hierarchy of steps in the disclosed procedure is an illustration of exemplary methods. It should be understood that the specific order or hierarchy of steps in these procedures may be rearranged based on design preferences. Furthermore, some steps may be combined or omitted. The appended method request presents the elements of various steps in an illustrative order, and is not intended to limit one to the specific order or hierarchy presented.

[0040] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the scope of the claim is not intended to be limited to the aspects shown herein, but should be granted the full scope consistent with the linguistic scope of the claim, wherein, unless specifically stated otherwise, references to elements in the singular form are not intended to mean “one and only one,” but rather “one or more.” The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects. Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as "at least one of A, B, or C," "at least one of A, B, and C," and "A, B, C, or any combination thereof" can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements described throughout this disclosure, now or hereafter known to a person skilled in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be contributed to the public, whether or not such disclosure is expressly recorded in the claims. No claim element is to be construed as a component plus a function unless the element is expressly recorded using the phrase "component for...".

[0041] The following examples are merely illustrative and may be combined with other embodiments or teachings described herein without limitation.

[0042] Example 1 is a MOS IC including a first transistor logic set. The first transistor logic set has a first plurality of gate interconnects extending in a first direction. The first plurality of gate interconnects have a gate spacing. The first transistor logic set has one or more power rail pairs, which provide a power supply voltage and a ground voltage to the logic between each corresponding power rail pair. The first transistor logic set has a first cell height h1 and has a first number of Mx layer rails extending unidirectionally in a second direction between each power rail pair. The second direction is orthogonal to the first direction. The MOS IC also includes a second transistor logic set. The second transistor logic set is adjacent to the first transistor logic set in the first direction. The second transistor logic set has a second plurality of gate interconnects extending in the first direction. The second plurality of gate interconnects have the same gate spacing as the first plurality of gate interconnects, and each is collinear with a corresponding one of the first plurality of gate interconnects. The second transistor logic set has one or more power rail pairs, which provide the power supply voltage and the ground voltage to the logic between each corresponding power rail pair. The second transistor logic set has a second cell height h2 and a second number of Mx layer tracks extending unidirectionally in the second direction between each power supply track pair. The second cell height h2 is greater than the first cell height h1. The second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of the following is satisfied: the height ratio hR = h2 / h1 is a non-integer value, or a subset of the first transistor logic set and a subset of the second transistor logic set are within a single logic cell.

[0043] Example 2 is a MOS IC according to Example 1, wherein a power supply rail in one or more power supply rail pairs of the first transistor logic set and the second transistor logic set extends in the second direction between the first transistor logic set and the second transistor logic set. The power supply rail is configured to provide either the power supply voltage or the ground voltage to at least one subset of the first transistor logic set and at least one subset of the second transistor logic set.

[0044] Example 3 is a MOS IC according to any one of Example 1 and Example 2, wherein the spacing of the first number of Mx layer tracks of the first transistor logic set is the same as the spacing of the second number of Mx layer tracks of the second transistor logic set.

[0045] Example 4 is a MOS IC according to any one of Examples 1 to 3, wherein the Mx layer is the lowest metal layer extending unidirectionally in the second direction.

[0046] Example 5 is a MOS IC according to any one of Examples 1 to 4, wherein the height ratio hR=h2 / h1 is a non-integer value, and the first transistor logic set includes a first logic cell set, and the second transistor logic set includes a second logic cell set.

[0047] Example 6 is a MOS IC according to any one of Examples 1 to 5, wherein the subset of the first transistor logic set and the subset of the second transistor logic set are located within a single logic cell. The height hm of the single logic cell is equal to (n1-1)h1 + (n2-1)h2, where n1 ≥ 2 and is the number of power supply rails within the subset of the first transistor logic set, and n2 ≥ 2 and is the number of power supply rails within the subset of the second transistor logic set, and where n1 + n2 - 1 is the total number of power supply rails within the single logic cell.

[0048] Example 7 is a MOS IC according to Example 6, wherein the subset of the first transistor logic set and the subset of the second transistor logic set are coupled together within the one logic unit.

[0049] Example 8 is a MOS IC according to any one of Examples 1 to 7, further comprising a third transistor logic set. The third transistor logic set has a third plurality of gate interconnects extending in the first direction. The third plurality of gate interconnects has the same gate spacing as the first plurality of gate interconnects and the second plurality of gate interconnects, and each is collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects. The third transistor logic set has one or more power rail pairs, which provide the power supply voltage and the ground voltage to the logic between each corresponding power rail pair. The third transistor logic set has a first cell height h1 and has a first number of Mx layer rails extending unidirectionally in the second direction between each power rail pair. A second transistor logic set is located between the first transistor logic set and the third transistor logic set.

[0050] Example 9 is a MOS IC according to Example 8, wherein a power supply rail in one or more power supply rail pairs of the second transistor logic set and the third transistor logic set extends in the second direction between the second transistor logic set and the third transistor logic set. The power supply rail is configured to provide one of the power supply voltage or ground voltage to at least one subset of the second transistor logic set and at least one subset of the third transistor logic set.

[0051] Example 10 is a MOS IC according to any one of Examples 8 and 9, wherein a subset of the first transistor logic set, a subset of the second transistor logic set, and a subset of the third transistor logic set are located within a single logic cell. The height hm of the single logic cell is equal to (n1-1)h1 + (n2-1)h2 + (n3-1)h1, where n1 ≥ 2 and is the number of power supply rails within the subset of the first transistor logic set, n2 ≥ 2 and is the number of power supply rails within the subset of the second transistor logic set, and n3 ≥ 2 and is the number of power supply rails within the subset of the third transistor logic set, and where n1 + n2 + n3 - 2 is the total number of power supply rails within the single logic cell.

[0052] Example 11 is a MOS IC according to Example 10, wherein the subset of the first transistor logic set, the subset of the second transistor logic set, and the subset of the third transistor logic set are coupled together within the same logic unit.

[0053] Example 12 is a MOS IC according to any one of Examples 1 to 11, further comprising a third transistor logic set. The third transistor logic set has a third plurality of gate interconnects extending in the first direction. The third plurality of gate interconnects has the same gate spacing as the first plurality of gate interconnects and the second plurality of gate interconnects, and each is collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects. The third transistor logic set has one or more power rail pairs that provide the power supply voltage and the ground voltage to the logic between each corresponding power rail pair. The third transistor logic set has a second cell height h2 and has a second number of Mx layer rails extending unidirectionally in the second direction between each power rail pair. The first transistor logic set is located between the second transistor logic set and the third transistor logic set.

[0054] Example 13 is a MOS IC according to Example 12, wherein a power supply rail in one or more power supply rail pairs of the first transistor logic set and the third transistor logic set extends in the second direction between the first transistor logic set and the third transistor logic set. The power supply rail is configured to provide either the power supply voltage or the ground voltage to at least one subset of the first transistor logic set and at least one subset of the third transistor logic set.

[0055] Example 14 is a MOS IC according to any one of Examples 12 and 13, wherein a subset of the first transistor logic set, a subset of the second transistor logic set, and a subset of the third transistor logic set are located within a single logic cell. The height hm of the single logic cell is equal to (n3-1)h2 + (n1-1)h1 + (n2-1)h2, where n1 ≥ 2 and is the number of power supply rails within the subset of the first transistor logic set, n2 ≥ 2 and is the number of power supply rails within the subset of the second transistor logic set, and n3 ≥ 2 and is the number of power supply rails within the subset of the third transistor logic set, and where n1 + n2 + n3 - 2 is the total number of power supply rails within the single logic cell.

[0056] Example 15 is a MOS IC according to Example 14, wherein the subset of the first transistor logic set, the subset of the second transistor logic set, and the subset of the third transistor logic set are coupled together within the same logic unit.

[0057] Example 16 is a MOS IC according to any one of Examples 1 to 15, further comprising n transistor logic sets. The n transistor logic sets are adjacent to one of the first transistor logic sets or the second transistor logic sets in the first direction. Each of the n transistor logic sets has the same number of gate interconnects extending in the first direction. The gate interconnects have the same gate spacing and each gate interconnect is collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects. Each of the n transistor logic sets has one or more power rail pairs that provide the power supply voltage and the ground voltage to the logic between each corresponding power rail pair. Each of the n transistor logic sets has a first cell height h1 and the first number of Mx layer rails, or has a second cell height h2 and the second number of Mx layer rails. [Simplified Explanation of the Diagram]

[0006] Figure 1 is a first view showing the side view of the standard cell and various layers within the IC.

[0007] Figure 2 is a second view showing the side view of the standard cell and various layers within the IC.

[0008] Figure 3 is the first figure of a top view conceptually illustrating a heterogeneous high logic unit architecture.

[0009] Figure 4 is the second figure, a top view conceptually illustrating a heterogeneous high logic unit architecture.

[0010] Figure 5 is the third figure of a top view conceptually illustrating a heterogeneous high logic unit architecture.

[0011] Figure 6 is the fourth figure, a top view conceptually illustrating a heterogeneous high logic unit architecture.

[0012] Figure 7 is a collection of top views that conceptually illustrate different configurations of a heterogeneous high-order logic unit architecture.

Claims

1. A metal-oxide-semiconductor (MOS) integrated circuit (IC), comprising: A first transistor logic set has a first plurality of gate interconnects extending in a first direction, the first plurality of gate interconnects having a gate spacing, the first transistor logic set having one or more power rail pairs providing power supply voltage and ground voltage to the logic between each corresponding power rail pair, the first transistor logic set having a first cell height h1 and having a first number of metal x (Mx) layer rails extending unidirectionally in a second direction between each power rail pair, the second direction being orthogonal to the first direction; and a second transistor logic set adjacent to the first transistor logic set in the first direction, the second transistor logic set having a first number of metal x (Mx) layer rails extending in the first direction. The second plurality of gate interconnects extend, the second plurality of gate interconnects having the same gate spacing as the first plurality of gate interconnects, and each being collinear with a corresponding gate interconnect in the first plurality of gate interconnects; the second transistor logic set has one or more power rail pairs providing the power supply voltage and the ground voltage to the logic between each corresponding power rail pair; the second transistor logic set has a second cell height h2 and has a second number of Mx layer rails extending unidirectionally in the second direction between each power rail pair; the second cell height h2 is greater than the first cell height h1; the second number of Mx layer rails is greater than the first number of Mx layer rails; wherein at least one of the following is satisfied: the height ratio hR = h2 / h1 is a non-integer value, or a subset of the first transistor logic set and a subset of the second transistor logic set are within a single logic cell.

2. The MOS IC according to claim 1, wherein a power supply rail in one or more power supply rail pairs of the first transistor logic set and the second transistor logic set extends in the second direction between the first transistor logic set and the second transistor logic set, and the power supply rail is configured to provide one of the power supply voltage or the ground voltage to at least one subset of the first transistor logic set and at least one subset of the second transistor logic set.

3. The MOS IC according to claim 1, wherein the spacing of the first number of Mx layer tracks of the first transistor logic set is the same as the spacing of the second number of Mx layer tracks of the second transistor logic set.

4. The MOS IC according to claim 1, wherein the Mx layer is the lowest metal layer extending unidirectionally in the second direction.

5. The MOS IC according to claim 1, wherein the height ratio hR=h2 / h1 is a non-integer value, and the first transistor logic set includes a first logic cell set, and the second transistor logic set includes a second logic cell set.

6. The MOS IC according to claim 1, wherein the subset of the first transistor logic set and the subset of the second transistor logic set are located in a single logic cell, wherein the height hm of the single logic cell is equal to (n1-1)h1+(n2-1)h2, where n1≥2 and is the number of power supply rails in the subset of the first transistor logic set, and n2≥2 and is the number of power supply rails in the subset of the second transistor logic set, and where n1+n2-1 is the total number of power supply rails in the single logic cell.

7. The MOS IC according to claim 6, wherein the subset of the first transistor logic set and the subset of the second transistor logic set are coupled together within the same logic unit.

8. The MOS IC according to claim 1, further comprising: A third transistor logic set has a third plurality of gate interconnects extending in the first direction, the third plurality of gate interconnects having the same gate spacing and each being collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects, the third transistor logic set having one or more power rail pairs providing the power supply voltage and the ground voltage to the logic between each corresponding power rail pair, the third transistor logic set having a first cell height h1 and having a first number of Mx layer rails extending unidirectionally in the second direction between each power rail pair, the second transistor logic set being located between the first transistor logic set and the third transistor logic set.

9. The MOS IC of claim 8, wherein a power supply rail in one or more power supply rail pairs of the second transistor logic set and the third transistor logic set extends in the second direction between the second transistor logic set and the third transistor logic set, the power supply rail being configured to provide one of the power supply voltage or the ground voltage to at least one subset of the second transistor logic set and at least one subset of the third transistor logic set.

10. The MOS IC according to claim 8, wherein a subset of the first transistor logic set, a subset of the second transistor logic set, and a subset of the third transistor logic set are located within a single logic cell, wherein the height hm of the single logic cell is equal to (n1-1)h1 + (n2-1)h2 + (n3-1)h1, where n1 ≥ 2 and is the number of power supply rails within the subset of the first transistor logic set, n2 ≥ 2 and is the number of power supply rails within the subset of the second transistor logic set, and n3 ≥ 2 and is the number of power supply rails within the subset of the third transistor logic set, and where n1 + n2 + n3 - 2 is the total number of power supply rails within the single logic cell.

11. The MOS IC according to claim 10, wherein the subset of the first transistor logic set, the subset of the second transistor logic set, and the subset of the third transistor logic set are coupled together within the same logic unit.

12. The MOS IC according to claim 1, further comprising: A third transistor logic set has a third plurality of gate interconnects extending in the first direction, the third plurality of gate interconnects having the same gate spacing and each being collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects, the third transistor logic set having one or more power rail pairs providing the power supply voltage and the ground voltage to the logic between each corresponding power rail pair, the third transistor logic set having a second cell height h2 and having a second number of Mx layer rails extending unidirectionally in the second direction between each power rail pair, the first transistor logic set being located between the second transistor logic set and the third transistor logic set.

13. The MOS IC of claim 12, wherein a power supply rail in one or more power supply rail pairs of the first transistor logic set and the third transistor logic set extends in the second direction between the first transistor logic set and the third transistor logic set, the power supply rail being configured to provide one of the power supply voltage or the ground voltage to at least one subset of the first transistor logic set and at least one subset of the third transistor logic set.

14. The MOS IC according to claim 12, wherein a subset of the first transistor logic set, a subset of the second transistor logic set, and a subset of the third transistor logic set are located within a single logic cell, wherein the height hm of the single logic cell is equal to (n3-1)h2+(n1-1)h1+(n2-1)h2, where n1≥2 and is the number of power supply rails within the subset of the first transistor logic set, n2≥2 and is the number of power supply rails within the subset of the second transistor logic set, and n3≥2 and is the number of power supply rails within the subset of the third transistor logic set, and where n1+n2+n3-2 is the total number of power supply rails within the single logic cell.

15. The MOS IC according to claim 14, wherein the subset of the first transistor logic set, the subset of the second transistor logic set, and the subset of the third transistor logic set are coupled together within the same logic unit.

16. The MOS IC according to claim 1, further comprising: n transistor logic sets, adjacent to one of the first transistor logic sets or the second transistor logic sets in the first direction, each of the n transistor logic sets having the same number of gate interconnects extending in the first direction, the gate interconnects having the same gate spacing and each gate interconnect being collinear with a corresponding gate interconnect in the first plurality of gate interconnects and the second plurality of gate interconnects, each of the n transistor logic sets having one or more power rail pairs providing the power supply voltage and the ground voltage to the logic between each corresponding power rail pair, each of the n transistor logic sets having a first cell height h1 and the first number of Mx layer rails, or having a second cell height h2 and the second number of Mx layer rails.

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