General-purpose graphics processing unit and data processing system for compute optimizations for low precision machine learning operations

Abstract

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Description

[Technical Field]

[0001] The embodiments generally relate to data processing, and more specifically to data processing via a general graphics processing unit. [Previous Technology]

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, and depth testing. Traditionally, graphics processors (GPUs) use fixed-function computing units to process graphics data; however, recently, some GPUs have become programmable, enabling them to support a wider range of operations to process vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipeline operations, which attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel graphics processors with a Single Instruction Multithreaded (SIMT) architecture aim to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to synchronize the execution of program instructions as often as possible to improve processing efficiency. A general overview of the software and hardware used in the SIMT architecture can be found in Shane Cook, CUDA Programming, Chapter 3, pp. 37-51 (2013) and / or Nicholas Wilt, CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 to 3.1.2 (June 2013). [Summary of the Invention]

[0004] and

Implementation Method

[0042] In some embodiments, the graphics processing unit (GPU) is communicatively coupled to the host / processor core to accelerate graphics processing, machine learning processing, pattern analysis processing, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated with the core on the same package or die and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or die). Regardless of the GPU connection method, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0043] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of this embodiment. System Overview

[0044] FIG1 is a block diagram illustrating a computing system 100 configured to implement one or more embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104, which communicates via interconnect paths including a memory hub 105. The memory hub 105 may be a standalone component within a chipset assembly or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, which enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 enables a display controller, which may be included in one or more processors 102, to provide output to one or more display devices 110A. In one embodiment, one or more display devices 110A coupled to I / O hub 107 may include local, internal or embedded display devices.

[0045] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 may be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In one embodiment, the one or more parallel processors 112 form a computationally centralized parallel or vector processing system, including a large number of processing cores and / or processing clusters, such as a number of integrated core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem capable of outputting pixels to one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) enabling direct connection to one or more display devices 110B.

[0046] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism enabling connection between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more add-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other networking devices including one or more wireless radios.

[0047] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 107. The communication paths that interconnect the various components in Figure 1 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol, such as NV-Link high-speed interconnect, or interconnect protocols known in the art.

[0048] In one embodiment, one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while retaining the underlying computing architecture, which is described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to form a modular computing system.

[0049] It should be understood that the computing system 100 shown herein is exemplary, and variations and modifications are possible. The connectivity topology can be modified as needed, including the number and configuration of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, system memory 104 is connected directly to processor 102 instead of via bridges, while other devices communicate with system memory 104 via memory hub 105 and processor 102. In other alternative topologies, parallel processors 112 are connected to I / O hub 107 or directly to one or more processors 102, rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors 102 attached via multiple sockets, which may be coupled to two or more instances of parallel processors 112.

[0050] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, many add-in cards or peripherals may be supported, or some components may be omitted. Furthermore, some architectures may use different terminology to describe components similar to those shown in Figure 1. For example, in some architectures, memory hub 105 may be referred to as the Northbridge, while I / O hub 107 may be referred to as the Southbridge.

[0051] FIG2A illustrates a parallel processor 200 according to an embodiment. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is a variation of one or more parallel processors 112 shown in FIG1.

[0052] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 enabled to communicate with other devices including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices using a hub or switch interface, such as a memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, wherein the host interface 206 receives commands to perform processing operations, and the memory crossbar 216 receives commands to perform memory operations.

[0053] When the host interface 206 receives a command buffer through the I / O unit 204, the host interface 206 can direct the work operations used to execute those commands to the front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and is active before tasks are distributed to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented through firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, enabling fast preemption and context switching of threads executing on the processing array 212. In one embodiment, the host software can check the workload scheduled on the processing array 212 through one of a plurality of graphics processing doorbells. The workload can then be automatically distributed to the processing array 212 through the scheduler 210 logic in the scheduler microcontroller.

[0054] The processing cluster array 212 may include up to "N" processing clusters (e.g., clusters 214A, 214B, to clusters 214N). Each cluster 214A-214N of the processing cluster array 212 can execute a large number of parallel threads. The scheduler 210 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload generated by each type of program or computation. Scheduling may be handled dynamically by the scheduler 210 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0055] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformation.

[0056] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic to support the performance of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Furthermore, the processing cluster array 212 may be configured to perform graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from system memory for processing via I / O unit 204. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory.

[0057] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable graphics processing operations to be distributed across multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A-214N may be stored in a buffer to allow intermediate data to be transferred between the clusters 214A-214N for further processing.

[0058] During operation, the processing cluster array 212 can receive processing tasks to be executed via a scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, processing tasks may include indexes of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data will be processed (e.g., what program will be executed). The scheduler 210 may be configured to retrieve the index corresponding to the task, or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to be active before initiating the workload specified by an input command buffer (e.g., a batch buffer, a push buffer, etc.).

[0059] Each of one or more instances of the parallel processing unit 202 may be coupled to the parallel processor memory 222. The parallel processor memory 222 may be accessed through a memory cross 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory cross 216 may access the parallel processor memory 222 through a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, to partition unit 220N), each partition unit may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 222. In one embodiment, the number of segmentation units 220A-220N is configured to be equal to the number of memory units, such that the first segmentation unit 220A has a corresponding first memory unit 224A, the second segmentation unit 220B has a corresponding memory unit 224B, and the Nth segmentation unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of segmentation units 220A-220N may not be equal to the number of memory devices.

[0060] In various embodiments, memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will understand that the specific implementation of memory units 224A-224N can vary and can be selected from one of a variety of conventional designs. Rendering targets, such as frame buffers or texture maps, may be stored in memory units 224A-224N, allowing partitioning units 220A-220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be excluded to facilitate a unified memory design that co-utilizes system memory and local cache memory.

[0061] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any memory cell 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 via the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204, and a connection to a local instance of the parallel processor memory 222, enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory not local to the parallel processing unit 202. In one embodiment, memory cross 216 may use virtual channels to separate traffic streams between clusters 214A-214N and segmentation units 220A-220N.

[0062] Although a single instance of the parallel processing unit 202 is shown within the parallel processor 200, any number of instances of the parallel processing unit 202 may be included. For example, multiple instances of the parallel processing unit 202 may be located on a single card or multiple cards may be interconnected. Different instances of the parallel processing unit 202 may be configured to inter-operate even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, and in one embodiment, some instances of the parallel processing unit 202 may include higher precision floating-point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit 202 or the parallel processor 200 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0063] FIG2B is a block diagram of the partitioning unit 220 according to an embodiment. In one embodiment, the partitioning unit 220 is an example of one of the partitioning units 220A-220N of FIG2A. As shown, the partitioning unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from memory cross 216 and ROP 226. Read misses and urgent write-back requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer for processing through the frame buffer interface 225. In one embodiment, the frame buffer interface 225 is connected via an interface to one of the memory cells in the parallel processor memory, such as memory cells 224A-224N of FIG2A (e.g., within parallel processor memory 222).

[0064] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, and color mixing. ROP 226 then outputs processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic may be one or more lossless compression logics utilizing a variety of compression algorithms. The type of compression performed by ROP 226 may vary depending on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0065] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2A) rather than within segmentation unit 220. In this embodiment, read and write requests for pixel data are transmitted via memory crossover 216, rather than pixel fragment data. The processed graphic data can be displayed on a display device, such as one or more display devices 110 of FIG. 1, routed by processor 102 for further processing, or routed for further processing by one of the processing entities within parallel processor 200 of FIG. 2A.

[0066] FIG2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an example of one of the processing clusters 214A-214N of FIG2A. The processing cluster 214 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, Single Instruction, Multiple Data (SIMD) instruction issue technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, Single Instruction, Multiple Thread (SIMT) technology is used to support the parallel execution of a large number of substantially synchronous threads, using common instruction units configured to issue instructions to a set of processing engines within each processing cluster. Unlike a SIMD execution regime where all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow different execution paths within a given thread program. Those skilled in the art will understand that a SIMD processing regime represents a functional subset of a SIMT processing regime.

[0067] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which assigns processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2A and manages the execution of those instructions via the graphics multiprocessor 234 and / or texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, the processing cluster 214 may include various types of SIMT parallel processors with different architectures. The processing cluster 214 may include one or more instances of the graphics multiprocessor 234. The graphics multiprocessor 234 can process data, and the data cross 240 can be used to distribute the processed data to one of several possible destinations, including other shader units. The pipeline manager 232 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross 240.

[0068] Each graphics multiprocessor 234 within the processing cluster 214 may include the same set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipelined manner, in which new instructions can be issued before previous instructions are completed. The functional execution logic supports a variety of operations, including integer and floating-point operations, comparison operations, Boolean operations, bit shifting, and various algebraic function calculations. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0069] Instructions sent to the processing cluster 214 constitute threads. A group of threads executing on this set of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the processing cycle of the thread group. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed in consecutive clock cycles. In one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 234.

[0070] In one embodiment, the graphics multiprocessor 234 includes internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and use cache memory within the processing cluster 214 (e.g., L1 cache 248). Each graphics multiprocessor 234 may also access L2 cache within partitioned units (e.g., partitioned units 220A-220N of FIG. 2A) shared among all processing clusters 214 and used to transfer data between threads. The graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 202 may be used as global memory. Embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 may share common instructions and data, which may be stored in the L1 cache 248.

[0071] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2A. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of the graphics tiles, and optionally a cache line index. The MMU 245 may include a translation lookaside buffer (TLB) or may reside within the graphics multiprocessor 234 or the L1 cache or a cache within the processing cluster 214. Processing physical addresses distributes surface data access locality to allow efficient request interleaving between segmented units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0072] In graphics and computing applications, the processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to the texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. The texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234, and may be retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs the processed task to a data cross 240 to provide the processed task to another processing cluster 214 for further processing, or stores the processed task in an L2 cache, local parallel processor memory, or system memory via a memory cross 216. The preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to a ROP unit, which may be located alongside segmentation units as described herein (e.g., segmentation units 220A-220N of FIG. 2A). The preROP 242 unit may perform color mixing optimization, organize pixel color data, and perform address translation.

[0073] It should be understood that the core structure shown herein is exemplary, and variations and modifications are possible. Processing cluster 214 may include any number of processing units, such as a graphics multiprocessor 234, a texture unit 236, a preROP 242, etc. Furthermore, although only one processing cluster 214 is shown, parallel processing units as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0074] Figure 2D illustrates a graphics multiprocessor 234 according to one embodiment. In this embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline, including but not limited to an instruction cache 252, an instruction unit 254, an address mapping unit 256, a temporary register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to cache memory 272 and shared memory 270 via memory and cache interconnect 268.

[0075] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. These instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 may dispatch instructions into thread groups (e.g., execution warps), with each thread of the thread group assigned to a different execution unit within GPGPU core 262. Instructions may access any of the local, shared, or global address spaces by specifying an address within a unified address space. Address mapping unit 256 may be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 266.

[0076] The register file 258 provides a set of registers to the functional units of the graphics multiprocessor 234. The register file 258 provides temporary storage for computational units connected to the data paths of the functional units of the graphics multiprocessor 234 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, the register file 258 is partitioned between each functional unit such that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned between different execution packages executed by the graphics multiprocessor 234.

[0077] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions of the graphics multiprocessor 234. Depending on the embodiment, the GPGPU core 262 may be structurally similar or structurally different. For example, in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or enable variable-precision floating-point operations. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0078] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core may be generated by a color compiler at compile time, or automatically generated when a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture is executed. Multiple threads of a program configured for a SIMT execution model can be executed through a single SIMD instruction. For example, and in one embodiment, eight SIMD threads may be executed in parallel through a single SIMD8 logic unit, the eight SIMD threads performing the same or similar operations.

[0079] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 234 to the scratchpad file 258 and to the common memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the common memory 270 and the scratchpad file 258. The scratchpad file 258 can operate at the same frequency as the GPGPU core 262, so the data transfer latency between the GPGPU core 262 and the scratchpad file 258 is very low. The common memory 270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 234. The cache memory 272 can be used as a data cache, for example, to cache texture data communicated between functional units and texture units 236. The common memory 270 can also be used as a program to manage the cache. In addition to automatically caching the data already stored in cache memory 272, threads executing on GPGPU core 262 can also programmatically store data in shared memory.

[0080] Figures 3A-3B illustrate another graphics multiprocessor according to an embodiment. The graphics multiprocessors 325 and 350 shown are variations of the graphics multiprocessor 234 of Figure 2C. The graphics multiprocessors 325 and 350 shown can be configured as streaming multiprocessors (SM) capable of executing a large number of execution threads simultaneously.

[0081] FIG3A illustrates a graphics multiprocessor 325 according to another embodiment. The graphics multiprocessor 325 includes multiple additional instances of the execution resource units of the graphics multiprocessor 234 of FIG2D. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, temporary register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple sets of graphics or computing execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0082] Multiple components can communicate via interconnect fabric 327. In one embodiment, interconnect fabric 327 includes one or more crossbar switches to enable communication between various components of the graphics multiprocessor 325. In one embodiment, interconnect fabric 327 is a separate high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via interconnect fabric 327. For example, each of the GPGPU cores 336A-336B, 337A-337B, and 338A-338B can communicate with shared memory 346 via interconnect fabric 327. Interconnect fabric 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0083] Figure 3B illustrates a graphics multiprocessor 350 according to another embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, each set of execution resources including multiple instruction units, temporary register files, GPGPU cores, and load storage units, as shown in Figures 2D and 3A. Execution resources 356A-356D can cooperate with texture units 360A-360D for texture operations, while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D can share instruction cache 354 and shared memory 362, as well as multiple instances of texture and / or data cache memory 358A-358B. Various components can communicate through interconnect structure 352, similar to interconnect structure 327 of Figure 3A.

[0084] Those skilled in the art will understand that the structures described in Figures 1, 2A-2D, and 3A-3B are descriptive and not limiting of the scope of this embodiment. Therefore, the techniques described herein can be implemented on any suitably configured processing unit, including but not limited to, one or more mobile application processors, one or more desktop or server CPUs including multi-core central processing units (CPUs), one or more parallel processing units, such as parallel processing unit 202 of Figure 2A, and one or more graphics processors or dedicated processing units, without departing from the scope of the embodiments described herein.

[0085] In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics processing, machine learning processing, pattern analysis processing, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In other embodiments, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the GPU connection method, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions. GPU-to-Host Processor Interconnect Technology

[0086] Figure 4A illustrates an exemplary architecture in which a plurality of GPUs 410-413 are communicatively coupled to a plurality of multi-core processors 405-406 via high-speed links 440A-440D (e.g., bus, point-to-point interconnect, etc.). In one embodiment, the high-speed links 440A-440D support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput.

[0087] Furthermore, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 442A-442B, which may use the same or different protocols / links as those used for high-speed links 440A-440D. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 443, which may be a symmetric multiprocessor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocols / links (e.g., via common interconnect structures) may be used to accomplish all communication between the various system components shown in FIG. 4A. However, as stated above, the basic principles of the invention are not limited to any particular type of interconnect technology.

[0088] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430A-430B, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450A-450D. Memory interconnects 430A-430B and 450A-450D may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or nano-RAM. In one embodiment, some portions of the memory may be volatile memory, while other portions may be non-volatile memory (e.g., using a second-order memory (2LM) hierarchy).

[0089] As described below, although the various processors 405-406 and GPUs 410-413 can be physically coupled to specific memories 401-402 and 420-423 respectively, a unified memory structure can also be implemented, in which the same virtual system address space (also known as the "effective address" space) is distributed across all the various physical memories. For example, each of the processor memories 401-402 can contain 64GB of system memory address space, and each of the GPU memories 420-423 can contain 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0090] Figure 4B illustrates additional details of the interconnection between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated with the processor 407 on the same package or chip. The processor 407 shown in

[0091] includes a plurality of cores 460A-460D, each core having a translation back buffer 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the invention (e.g., instruction fetching unit, branch prediction unit, decoder, execution unit, reordering buffer, etc.). The caches 462A-462D may include first-order (L1) and second-order (L2) caches. Furthermore, one or more shared caches 456 may be included in the cache hierarchy and shared by multiple sets of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator module 446 are connected to the system memory 441, which may include the processor memory 401-402.

[0092] Data and instructions stored in various caches 462A-462D, 456 and system memory 441 are maintained in consistency through inter-core communication on the consistency bus 464. For example, each cache may have associated cache consistency logic / circuit to communicate on the consistency bus 464 in response to detected reads or writes to a specific cache line. In one embodiment, a snooping protocol is implemented on the consistency bus 464 to monitor cache access. Cache snooping / consistency technology is fully understood by those skilled in the art, and will not be described in detail here to avoid obscuring the basic principles of the invention.

[0093] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to consistency bus 464, allowing graphics acceleration module 446 to participate in cache consistency protocols as a core peer. Specifically, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to high-speed link 440.

[0094] In one embodiment, the accelerator integration circuit 436 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 431, 432, N of the graphics acceleration module 446. Each of the graphics processing engines 431, 432, N may include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU with a plurality of graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be individual GPUs integrated on a common package, line card, or chip.

[0095] In one embodiment, the accelerator integration circuitry 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) for accessing system memory 441 and memory access protocols. MMU 439 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translation. In one embodiment, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, N. In one embodiment, the data stored in cache 438 and graphics memories 433-434, M are consistent with core caches 462A-462D, 456 and system memory 411. As described above, this can be accomplished by proxy circuitry 425 representing cache 438 and memories 433-434, M participating in the cache coherency mechanism (e.g., sending updates about modifications / accesses to cache lines on processor caches 462A-462D, 456 to cache 438 and receiving updates from cache 438).

[0096] A set of registers 445 stores context data of threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages the thread context. For example, context management circuitry 448 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., saving a first thread and storing a second thread so that it can be executed by the graphics processing engine). For example, during context switching, context management circuitry 448 can store the current register value to a designated area in memory (e.g., identified by a context indicator). Then, when returning to the context, it can restore the register value. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0097] In one embodiment, the MMU 439 translates the virtual / valid address from the graphics processing engine 431 into a real / physical address in the system memory 411. One embodiment of the accelerator integration circuitry 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on the processor 407, or it may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0098] Therefore, the accelerator integrated circuitry acts as a bridge between the graphics acceleration module 446 and the system, and provides address translation and system memory caching services. In addition, the accelerator integrated circuitry 436 can provide virtualization facilities to the main processor to manage the virtualization, interrupts, and memory management of the graphics processing engine.

[0099] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the main processor 407, any main processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integration circuit 436 is to physically separate the graphics processing engines 431-432, N, so that they appear as independent units in the system.

[0100] As described, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of graphics processing engines 431-432, N. Graphics memories 433-434, M store instructions and data to be processed by each of graphics processing engines 431-432, N. Graphics memories 433-434, M can be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories, such as 3D XPoint or nano-random access memory.

[0101] In one embodiment, to reduce data traffic on the high-speed link 440, a biasing technique is used to ensure that the data stored in the graphics memory 433-434, M is data that the graphics processing engines 431-432, N will use most frequently, and preferably will not be used (at least infrequently) by the cores 460A-460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 431-432, N) within the core caches 462A-462D, 456 and system memory 411.

[0102] Figure 4C illustrates another embodiment in which the accelerator integration circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integration circuit 436 via high-speed link 440 through interfaces 437 and 435 (which may also utilize any form of bus or interface protocol). The accelerator integration circuit 436 can perform the same operations as described with respect to Figure 4B, but may operate at higher throughput due to its proximity to the consistency bus 464 and caches 462A-462D, 456.

[0103] One embodiment supports different programming models, including a dedicated-process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integration circuitry 436 and a programming model controlled by graphics acceleration module 446.

[0104] In one embodiment of the dedicated application model, graphics processing engines 431-432, N are dedicated to a single application or program under a single operating system. The single application can import requests from other applications into graphics processing engines 431-432, N to provide virtualization within a VM / partition.

[0105] In a dedicated program design model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a system supermanager to virtualize graphics processing engines 431-432, N to allow access by each operating system. For single-partition systems without a supermanager, the operating system owns the graphics processing engines 431-432, N. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each program or application.

[0106] For a common programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a handle to select a processing element. In one embodiment, the processing element is stored in system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The handle may be an implementation-specific value provided to the main program when the main program registers its context with the graphics processing engines 431-432, N (i.e., calling system software to add the program element to the program element linking list). The lower 16 bits of the handle may be an offset of the program element within the program element linking list.

[0107] Figure 4D illustrates an exemplary accelerator integration slice 490. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integration circuitry 436. Application effective address space 482 within system memory 411 stores program elements 483. In one embodiment, program element 483 is stored in response to a GPU invocation 481 from an application 480 executing on processor 407. Program element 483 contains the program state of the corresponding application 480. The job descriptor (WD) 484 included in program element 483 may be a single job requested by the application or may contain an index pointing to a job queue. In the latter case, WD 484 is an index pointing to a job request queue in the application's address space 482.

[0108] The graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all programs or subsets of programs in the system. Embodiments of the present invention include infrastructure for establishing program states and sending WD 484 to the graphics acceleration module 446 to begin operation in a virtual environment.

[0109] In one embodiment, the dedicated program design model is implementation-specific. In this model, a single program has a graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 belongs to a single program, the hypervisor initializes the accelerator integration circuitry 436 for its partition, and the operating system initializes the accelerator integration circuitry 436 for its program when the graphics acceleration module 446 is allocated.

[0110] In operation, the WD fetch unit 491 in the accelerator integration chip 490 fetches the next WD 484, which includes instructions for the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 can be stored in a register 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 448, as shown. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the valid address 493 generated by the graphics processing engines 431-432, N is translated into a real address via the MMU 439.

[0111] In one embodiment, the same group of registers 445 are copied for each graphics processing engine 431-432, N and / or graphics acceleration module 446, and can be initialized by the super manager or the operating system. Each of these copied registers may be included in the accelerator integration chip 490. Table 1 shows exemplary registers that can be initialized by the super manager. Table 1 – Registers initialized by the super manager 1 Slice control register 2 Real Address (RA) Area Indicator via Scheduling Process 3 Permission mask replacement register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 State register 7 Logical partition ID 8 Real Address (RA) super manager accelerator utilizes recording indicators 9 Storage description register

[0112] Table 2 shows exemplary temporary registers that can be initialized by the operating system. Table 2 – Temporary Registers Initialized by the Operating System 1 Program and thread identifiers 2 Effective address (EA) context save / restore indicator 3 Virtual address (VA) accelerators utilize recording indicators 4 Virtual Address (VA) storage segmentation table index 5 Permission masking 6 Job descriptor

[0113] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required for the graphics processing engine 431-432, N to complete its work, or it may be an index to the memory location of a command queue that the application has created to complete the work.

[0114] Figure 4E illustrates additional details of one embodiment of the shared model. This embodiment includes a super manager real address space 498, in which a program element table 499 is stored. The super manager real address space 498 is accessible through a super manager 496, which is a virtualized graphics acceleration module for the operating system 495.

[0115] The shared programming model allows all programs or subsets of programs from all segments or subsets of segments in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple programs and segments: sharing of time-sliced ​​data and sharing of graphics pointers.

[0116] In this model, the system super manager 496 possesses the graphics acceleration module 446 and makes its functionality available to all operating systems 495. For the graphics acceleration module 446 that supports virtualization through the system super manager 496, the graphics acceleration module 446 may meet the following requirements: (1) The application's work requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 446 must provide a context saving and recovery mechanism. (2) The application's work requests are guaranteed by the graphics acceleration module 446 to be completed within a specified time, including any translation errors, or the graphics acceleration module 446 provides the ability to preempt job processing. (3) When operating in a shared programming model, the graphics acceleration module 446 must guarantee fairness between programs.

[0117] In one embodiment, for a common model, application 480 is required to make a system call to operating system 495 using a graphics acceleration module 446 type, a working descriptor (WD), an access control mask register (AMR) value, and a context save / restore region index (CSRP). The graphics acceleration module 446 type describes the target acceleration function used for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446 and can be a graphics acceleration module 446 command, a valid address index pointing to a user-defined structure, a valid address index pointing to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current program. This value passed to the operating system is similar to that of an application setting the AMR. If the implementation of the accelerator integration circuit 436 and graphics acceleration module 446 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value during a super manager call before transmitting the AMR. The super manager 496 can optionally apply the current UAMOR value before placing the AMR into program element 483. In one embodiment, CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This indicator is optional if saving state between jobs is not required or when a job is preempted. The context save / restore region can be pinned system memory.

[0118] Once a system call is received, the operating system 495 verifies that the application 480 has been registered and authorized to use the graphics acceleration module 446. Then, the operating system 495 calls the super manager 496 using the information shown in Table 3. Table 3 – OS to Super Manager Call Parameters 1 Working Descriptor (WD) 2 Permission Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Recovery Region Indicator (CSRP) 4 Program ID (PID) and optional Thread ID (TID) 5 Virtual Address (VA) accelerators utilize the Authenticator Reference Point (AURP). 6 Virtual address of Storage Segmentation Table Indicator (SSTP) 7 Logical Interruption Service Number (LISN)

[0119] Upon receiving a call from the super manager, the super manager 496 verifies that the operating system 495 has been registered and authorized to use the graphics acceleration module 446. Then, the super manager 496 places the program element 483 into the program element link table for the corresponding graphics acceleration module 446 type. The program element may include the information shown in Table 4. Table 4 – Program Element Information 1 Working Descriptor (WD) 2 Permission Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Recovery Region Indicator (CSRP) 4 Program ID (PID) and optional Thread ID (TID) 5 Virtual Address (VA) accelerators utilize the Authenticator Reference Point (AURP). 6 Virtual address of Storage Segmentation Table Indicator (SSTP) 7 Logical Interruption Service Number (LISN) 8 Interrupt vector table, derived from super manager call parameters 9 Status Register (SR) value 10 Logical Partition ID (LPID) 11 Real Address (RA) super manager accelerator utilizes recording indicators 12 Storage Descriptor Register (SDR)

[0120] In one embodiment, the super manager initializes temporary registers 445 of a plurality of accelerator integration chips 490.

[0121] As shown in FIG4F, one embodiment of the present invention employs a unified memory that can be addressed through a common virtual memory address space used to access physical processor memories 401-402 and GPU memories 420-423. In this embodiment, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective memory address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access any physical memory through virtual addresses mapped to that memory.

[0122] In one embodiment, the bias / coherence management circuitry 494A-494E within one or more of the MMUs 439A-439E ensures cache coherence between the caches of the main processor (e.g., 405) and the GPUs 410-413, and implements biasing techniques that indicate physical memory where certain types of data should be stored. Although multiple instances of the bias / coherence management circuitry 494A-494E are shown in FIG4F, the bias / coherence circuitry may be implemented within the MMU of one or more main processors 405 and / or within the accelerator integration circuitry 436.

[0123] One embodiment allows GPU-attached memories 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without suffering the typical performance drawbacks associated with full system cache coherence. The ability of GPU-attached memories 420-423 to be accessed as system memory without incurring a heavy cache coherence burden provides a favorable operating environment for GPU offloading. This configuration allows the main processor 405 to software-set up operands and access computation results without the burden of conventional I / O DMA data copying. This conventional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) access, which are inefficient compared to simple memory access. Simultaneously, the ability to access GPU-attached memories 420-423 without a cache coherence burden is critical for offloading computation execution time. For example, in cases with significant streaming write memory traffic, a cache coherence burden can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setup, result retrieval, and GPU computation all play a role in determining the benefits of GPU offloading.

[0124] In one embodiment, the selection between GPU bias and main processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure comprising 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of memory pages). The bias table may be implemented in the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in GPUs 410-413 (e.g., for caching frequently / recently used entry points of the bias table). Alternatively, the entire bias table may be kept within the GPU.

[0125] In one embodiment, before actually accessing the GPU memory, the bias table entry point associated with each access to the GPU-attached memory 420-423 is accessed, resulting in the following operations: First, local requests from GPUs 410-413 to find their pages in the GPU bias are directly forwarded to the corresponding GPU memory 420-423. Local requests from GPUs to find their pages in the host bias are forwarded to processor 405 (e.g., via the high-speed link described above). In one embodiment, a request from processor 405 to find the requested page in the host processor bias is performed as a normal memory read. Alternatively, a request to a GPU bias page can be forwarded to GPUs 410-413. Then, if the GPU is not currently using the page, the page can be moved to the host processor bias.

[0126] The bias state of a page can be changed through software-based mechanisms, hardware-assisted software-based mechanisms, or, for limited situations, through purely hardware-based mechanisms.

[0127] One mechanism for changing the bias state uses an API call (e.g., OpenCL) that sequentially calls the GPU's device driver, which in turn sends messages to the GPU (or queues command descriptors) to guide it in changing the bias state. For certain transitions, a flushing operation is performed in the host machine. The flushing operation is necessary for transitions from the main processor 405 bias to the GPU bias, but not for the reverse transition.

[0128] In one embodiment, cache consistency is maintained by temporarily presenting GPU bias pages that the main processor 405 cannot cache. To access these pages, the processor 405 may request access from the GPU 410, depending on the implementation, whether or not immediate authorization of access is possible. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the main processor 405, and vice versa. Graphics Processing Pipeline

[0129] FIG5 illustrates a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem described herein, such as the parallel processor 200 of FIG2A, which in one embodiment is a variation of the parallel processor 112 of FIG1. ​​Various parallel processing systems may implement the graphics processing pipeline 500 through one or more instances of parallel processing units as described herein (e.g., parallel processing unit 202 of FIG2A). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG2C) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of data combiner 502, primitive combiners 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 2A) and corresponding partitioning units (e.g., partitioning units 220A-220N of FIG. 2A). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 can be performed by parallel processing logic within a general-purpose processor (e.g., CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 can access on-chip memory (e.g., parallel processor memory 222 as shown in FIG. 2A) through a memory interface 528, which can be an instance of memory interface 218 of FIG. 2A.

[0130] In one embodiment, the data combiner 502 is a processing unit that collects vertex data for surfaces and primitives. The data combiner 502 then outputs vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data specified by the vertex shader program. The vertex processing unit 504 reads data stored in cache, local, or system memory for processing vertex data and can be programmed to convert vertex data from object-based coordinate representation to world space coordinate space or normalized device coordinate space.

[0131] The first instance of the primitive combiner 506 receives vertex attributes from the vertex processing unit 504. The primitive combiner 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., as supported by various graphics processing application programming interfaces (APIs).

[0132] The tessellation control processing unit 508 treats the input vertices as control points for geometric repair. These control points are transformed from the input representation of the repair (e.g., the basis of the repair) into a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate the tessellation factor for the edges used for geometric repair. The tessellation factor is applied to a single edge and quantifies the level of detail dependent on the viewpoint associated with that edge. The tessellation unit 510 is configured to receive the tessellation factor for the edges used for repair and subdivide the repaired surface into multiple geometric primitives, such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parametric coordinates of the subdivided repair to generate a surface representation and vertex attributes associated with each geometric primitive.

[0133] A second instance of the primitive combiner 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive combiner 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 may be programmed to subdivide the graphics primitives into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0134] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry flow. The geometry processing unit 516 outputs the parameters and vertices of the specified new graphics primitive to the primitive combiner 518. The primitive combiner 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for processing geometric data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0135] Rasterizer 522 can perform depth culling and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphics primitives to generate fragments and outputs those fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, color mixing, texture correction, and perspective correction to produce shaded fragments or pixels output to raster operation unit 526. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at samples, pixels, tiles, or other granularities according to a sampling rate configured for the processing unit.

[0136] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stenciling, z-testing, and color mixing, and outputs pixel data as processed graphic data for storage in graphics memory (e.g., parallel processor memory 222 in FIG. 2A and / or system memory 104 in FIG. 1) for display on one or more display devices 110 or for further processing by one or more processors 102 or parallel processors 112. In some embodiments, the raster operation unit 526 is configured to compress z- or color data written to memory and decompress z- or color data read from memory. Machine Learning Overview

[0137] Machine learning algorithms are algorithms that can learn from a set of data. Implementations of machine learning algorithms can be designed to model high-order abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value for a given input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0138] One exemplary type of machine learning algorithm is the neural network. There are many types of neural networks; a simple type is the feedforward network. A feedforward network can be implemented as an acyclic graph, where nodes are arranged in hierarchical layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for producing an output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within a single layer. Data received at the nodes in the input layer of the feedforward network is fed forward (i.e., “feedforward”) to the nodes in the output layer via an activation function, which calculates the state of each node in the network based on coefficients (“weights”) associated with each edge connecting the layers. Depending on the specific model represented by the algorithm being executed, the output of the neural network algorithm can take various forms.

[0139] Before a machine learning algorithm can be used to model a specific problem, a training dataset is used to train the algorithm. Training a neural network involves selecting a network topology, using a set of training data to represent the problem modeled by the network, and adjusting the weights until the network model performs with minimum error for all instances in the training dataset. For example, during supervised learning training of a neural network, the output generated by the network in response to inputs representing instances in the training dataset is compared with the labeled "correct" output of that instance, an error signal representing the difference between the output and the labeled output is calculated, and as the error signal is backpropagated through the layers of the network, the weights associated with those connections are adjusted to minimize the error. The network is considered "trained" when the error of each output generated from instances in the training dataset is minimized.

[0140] The quality of the dataset used to train algorithms significantly affects the accuracy of machine learning algorithms. The training process can be computationally intensive and may take a considerable amount of time on traditional general-purpose processors. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed when adjusting the coefficients in the neural network are naturally suited for parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to utilize parallel processing hardware within general-purpose graphics processing units.

[0141] Figure 6 is a generalized diagram of the machine learning software stack 600. The machine learning application 602 can be configured to train neural networks using training datasets or to implement machine intelligence using trained deep neural networks. The machine learning application 602 may include training and inference functions for neural networks and / or dedicated software that can be used to train neural networks prior to deployment. The machine learning application 602 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0142] Hardware acceleration for the machine learning application 602 can be enabled via the machine learning framework 604. The machine learning framework 604 provides a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms would need to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when developing new parallel processors. Instead, the machine learning application can be configured to use the primitives provided by the machine learning framework 604 to perform the necessary computations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 may also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0143] The machine learning framework 604 can process the input data received from the machine learning application 602 and generate appropriate inputs for the computing framework 606. The computing framework 606 can abstract the low-level instructions provided to the GPGPU driver 608, enabling the machine learning framework 604 to utilize hardware acceleration through the GPGPU hardware 610 without requiring the machine learning framework 604 to have in-depth knowledge of the GPGPU hardware 610 architecture. Furthermore, the computing framework 606 can enable hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610. GPGPU Machine Learning Acceleration

[0144] Figure 7 illustrates a highly parallel general-purpose graphics processing unit 700 according to an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 may be configured to be particularly effective in handling the types of computational workloads associated with training deep neural networks. Furthermore, the GPGPU 700 may be directly linked to other instances of GPGPUs to create multi-GPU clusters to improve training speed, particularly for deep neural networks.

[0145] The GPGPU 700 includes a host interface 702 for connection to the host processor. In one embodiment, the host interface 702 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or communication structure. The GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute the execution threads associated with those commands to a set of compute clusters 706A-706H. The compute clusters 706A-706H share a cache memory 708. The cache memory 708 can act as a higher-order cache of the cache memory within the compute clusters 706A-706H.

[0146] The GPGPU 700 includes memory 714A-714B coupled to the compute cluster 706A-H via a set of memory controllers 712A-712B. In various embodiments, memory 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory, or 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0147] In one embodiment, each compute cluster 706A-706H includes a set of graphics multiprocessors, such as the graphics multiprocessor 234 of FIG. 2C. The graphics multiprocessors of the compute cluster include various types of integer and floating-point logic units that can perform computations within a precision range suitable for machine learning computations. For example, in one embodiment, at least a subset of the floating-point units in each of the compute clusters 706A-H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0148] Multiple instances of the GPGPU 700 can be configured to operate as a compute cluster. The communication mechanisms used for synchronization and data exchange in the compute cluster differ between embodiments. In one embodiment, multiple instances of the GPGPU 700 communicate via a host interface 702. In one embodiment, the GPGPU 700 includes an I / O hub 709 that couples the GPGPU 700 to a GPU link 710 that enables direct connections to other instances of the GPGPU. In one embodiment, the GPU link 710 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 700. In one embodiment, the GPU link 710 is coupled to a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of the GPGPU 700 reside in separate data processing systems and communicate via a network device accessible via the host interface 702. In one embodiment, the GPU link 710 can be configured to enable a connection to the main processor, either in addition to or as an alternative to the host interface 702.

[0149] While the configuration shown for the GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration of the GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 700 includes fewer compute clusters 706A-H compared to the training configuration. Furthermore, the memory technology associated with the memories 714A-714B may differ between the inference and training configurations. In one embodiment, the inference configuration of the GPGPU 700 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer-point product instructions, which are typically used during inference operations of a deployed neural network.

[0150] FIG8 illustrates a multi-GPU computing system 800 according to an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI Express switch device that couples the processor 802 to a PCI Express bus through which the processor 802 can communicate with the group of GPGPUs 806A-D. Each of the plurality of GPGPUs 806A-806D may be an example of the GPGPU 700 of FIG7. The GPGPUs 806A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU links may be connected to each of the GPGPUs 806A-806D via dedicated GPU links, such as GPU link 710 in FIG7. The P2P GPU link 816 enables direct communication between the GPGPUs 806A-806D without requiring communication through the host interface bus to which the processor 802 is connected. Through GPU-to-GPU traffic routed to the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 800, for example, through one or more network devices. While in the illustrated embodiment the GPGPUs 806A-806D are connected to the processor 802 via the host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-806D. Machine Learning Neural Network Implementation

[0151] The computational structures provided in the embodiments described herein can be configured to perform parallel processing particularly suitable for training and deploying neural networks for machine learning. Neural networks can be broadly categorized as function networks with graphical relationships. As is well known in the art, various types of neural network implementations are used in machine learning. As previously mentioned, an exemplary type of neural network is a feedforward network.

[0152] A second exemplary type of neural network is the Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network used to process data with a known, grid-like topology, such as image data. Therefore, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors are inspired by the receptive fields found in the retina), and the output of each set of filters is passed to nodes in subsequent layers of the network. The computation for a CNN involves applying convolutional mathematical operations to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional matrix of data defining various color components of an input image. The convolution kernel can be a multidimensional matrix of parameters, which are tuned through the training process of the neural network.

[0153] Recursive Neural Networks (RNNs) are a family of feedforward neural networks that include feedback connections between layers. RNNs enable the modeling of sequential data by sharing parameter data across different parts of the neural network. The structure used in RNNs includes a cycle. A cycle represents the influence of the current value of a variable on its value at future time, because at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to their ability to represent the variability of linguistic data.

[0154] The diagrams described below illustrate exemplary feedforward, CNN, and RNN networks, and describe the general process of training and deploying those types of networks respectively. It should be understood that these descriptions are exemplary and non-limiting for any particular embodiment described herein, and the concepts shown are generally applicable to general deep neural networks and machine learning techniques.

[0155] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning that uses deep neural networks. The deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers, rather than shallow neural networks that only include a single hidden layer. Deeper neural networks typically require more computational training. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in a reduction in output errors compared to shallow machine learning techniques.

[0156] Deep neural networks used in deep learning typically include a front-end network coupled to a back-end network that performs feature recognition. The back-end network represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on feature representations provided to that model. Deep learning enables machine learning to be performed without requiring hand-crafted feature engineering on the model. Instead, deep neural networks can learn features based on the statistical structure or correlations in the input data. The learned features can be fed to a mathematical model, which can output the detected feature maps. The mathematical models used by the network are typically specific to the task to be performed, and different models will be used to perform different tasks.

[0157] Once a neural network is structured, a learning model can be applied to the network to train it to perform specific tasks. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of error is a common method used to train neural networks. The input vector is presented to the network for processing. The network's output is compared to the expected output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then use algorithms, such as stochastic gradient descent, to learn from these errors to update the neural network's weights.

[0158] Figures 9A-9B illustrate an exemplary convolutional neural network. Figure 9A illustrates various layers within a CNN. As shown in Figure 9A, the exemplary CNN used to model image processing can receive input 902 describing the red, green, and blue (RGB) components of an input image. Input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 908. Neurons in fully connected layers are fully connected to all activations in the previous layer, as previously described for feedforward networks. The output from fully connected layers 908 can be used to produce the output from the network. Matrix multiplication can be used instead of convolution to compute the activations within fully connected layers 908. Not all CNN implementations utilize fully connected layers 908. For example, in some implementations, convolutional layers 906 can be used to produce the output for the CNN.

[0159] Convolutional layers are sparsely connected, unlike the traditional neural network configuration seen in fully connected layers 908. Traditional neural network layers are fully connected, allowing each output unit to interact with each input unit. However, convolutional layers are sparsely connected because the output of the convolution of a field is input (rather than the individual state values ​​of each node in the field) to nodes in subsequent layers, as shown in the figure. The kernels associated with the convolutional layers perform convolution operations, and their outputs are sent to the next layer. The dimensionality reduction performed within convolutional layers is one way that enables CNNs to scale to handle large images.

[0160] Figure 9B illustrates an exemplary computational stage within a convolutional layer of a CNN. The output of the convolutional layer 912 to the CNN can be processed in three stages of the convolutional layer 914. The three stages may include a convolutional stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 can then output data to subsequent convolutional layers. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate classification values ​​for the input to the CNN.

[0161] Several convolutions are performed in parallel in convolution stage 916 to produce a set of linear activations. Convolution stage 916 may include affine transformations, which are any transformations that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron computes the dot product between the neuron's weights and the region in the local input to which the neuron is connected. The output of convolution stage 916 defines a set of linear activations processed by subsequent stages of convolutional layer 914.

[0162] Linear excitations can be processed by the detector stage 918. In the detector stage 918, each linear excitation is processed by a nonlinear excitation function. The nonlinear excitation function adds nonlinearity to the overall network without affecting the receptive fields of the convolutional layer. Several types of nonlinear excitation functions can be used. One particular type is the rectified linear unit (ReLU), which uses an excitation function defined as such that the excitation threshold is zero.

[0163] Pooling stage 920 uses a pooling function that replaces the output of convolutional layer 906 with a summary statistic of neighboring outputs. Pooling functions can be used to introduce translation invariance into neural networks, ensuring that small translations of the input do not alter the pooled output. Invariance to local translation is particularly useful when features in the input data are more important than their precise location. Various types of pooling functions can be used during pooling stage 920, including max pooling, average pooling, and L2-norm pooling. Furthermore, some CNN implementations do not include a pooling stage. Instead, such implementations use an additional convolutional stage with a larger stride relative to the previous convolutional stage.

[0164] The output of convolutional layer 914 can then be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or a fully connected layer 908. For example, the first convolutional layer 904 in Figure 9A can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer of the fully connected layer 908.

[0165] Figure 10 illustrates an exemplary recurrent neural network 1000. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state. RNNs can be constructed in various ways using various functions. The use of RNNs typically revolves around using mathematical patterns to predict the future based on the previous input order. For example, an RNN can be used to perform statistical language modeling to predict the upcoming word based on the previous word order. The RNN 1000 shown can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 that implements a recurrent function, a feedback mechanism 1005 that enables a "memory" of previous states, and an output layer 1006 that outputs the result. The RNN 1000 operates on a time-step basis. The state of the RNN at a given time step is influenced by the feedback mechanism 1005 based on previous time steps. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) of the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by hidden layer 1004 using state information determined during the processing of the initial input (x1). A given state can be computed as , where and are parameter matrices. The function is typically a nonlinear function, such as a variation of the hyperbolic tangent function (Tanh) or a rectified function. However, the specific mathematical function used in hidden layer 1004 can vary depending on the specific implementation details of the RNN 1000.

[0166] In addition to the basic CNN and RNN networks described above, variations of those networks can also be enabled. An exemplary RNN variation is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are capable of learning the long-term dependencies required to process longer language sequences. A variation of CNN is the Convolutional Deep Belief Network (DBN), which has a similar structure to CNNs and is trained in a similar manner to DBNs. A Deep Belief Network (DBN) is a generative neural network consisting of multiple layers of random (random) variables. A greedy unsupervised learning approach can be used to train a DBN layer by layer. Then, by determining the optimal initial set of weights for the neural network, the learned weights of the DBN can be used to provide a pre-trained neural network.

[0167] Figure 11 illustrates the training and deployment of deep neural networks. Once a given network has been structured for a task, the neural network is trained using a training dataset 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, the machine learning framework 604 of Figure 6 can be configured as a training framework 604. The training framework 604 can be embedded with an untrained neural network 1106 and can be used with the parallel processing resources described herein to train the untrained neural network to produce a trained neural network 1108.

[0168] To begin the training process, initial weights can be randomly selected or pre-trained using a deep belief network. Training cycles can then be performed in a supervised or unsupervised manner.

[0169] Supervised learning is a learning method that uses training execution as an intermediary operation, such as when the training dataset 1102 includes inputs paired with expected outputs for those inputs, or the training dataset includes inputs with known outputs, and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting output with a set of expected or desired outputs. The error is then fed back through the system. The training framework 1104 can adjust the weights controlling the untrained neural network 1106. The training framework 1104 can provide tools to monitor the degree to which the untrained neural network 1106 converges toward a model suitable for producing correct answers based on known input data. As the network weights are adjusted to improve the outputs produced by the neural network, the training process is repeated. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0170] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training dataset 1102 will include input data without any associated output data. The untrained neural network 1106 can learn grouping within the unlabeled input and can determine how individual inputs relate to the entire dataset. Unsupervised learning can be used to generate self-organizing maps, which are trained neural networks 1108 capable of performing operations that benefit from reducing data dimensionality. Unsupervised learning can also be used to perform anomaly detection, allowing the identification of data points in the input dataset that deviate from the normal pattern of the data.

[0171] Variations of supervised and unsupervised training can also be used. Semi-supervised learning is a technique that includes a mixture of labeled and unlabeled data with the same distribution in the training dataset 1102. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled into the network during the initial training.

[0172] Whether supervised or unsupervised, the training process for particularly deep neural networks can be computationally too demanding for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to accelerate the training process.

[0173] Figure 12 is a block diagram illustrating distributed learning. Distributed learning is the training of a neural network model using multiple distributed computing nodes to perform supervised or unsupervised training. Each distributed computing node may include one or more host processors and one or more general-purpose processing nodes, such as the highly parallel general-purpose graphics processing unit 700 in Figure 7. As shown, distributed learning may be performed as model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1206.

[0174] In model parallel processing 1202, different computing nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes in a distributed system. The benefits of model parallel processing include the ability to scale to particularly large models. Separating the computations associated with different layers of a neural network makes it possible to train very large neural networks where the weights of all layers cannot fit into the memory of a single computing node. In some cases, model parallel processing may be particularly useful for performing unsupervised training of large neural networks.

[0175] In data parallel processing 1204, different nodes in a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then merged. While different methods of performing data parallel processing are possible, all data parallel training methods require techniques for merging results and synchronizing model parameters between nodes. Exemplary methods for combining data include parameter averaging and update-based data parallel processing. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallel processing is similar to parameter averaging, except that instead of transferring parameters from nodes to a parameter server, model updates are transferred. Furthermore, update-based data parallel processing can be performed in a distributed manner, where updates are compressed and transferred between nodes.

[0176] The combined model and data parallel processing 1206 can be performed, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, and individual GPUs within each node are used to train different parts of the model.

[0177] Distributed training increases the overhead compared to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques that enable high-bandwidth GPU-to-GPU data transfer and accelerate remote data synchronization. Exemplary Machine Learning Applications

[0178] Machine learning can be applied to a wide range of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from replicating human visual abilities, such as recognizing faces, to creating new categories of visual abilities. For example, computer vision applications can be configured to recognize sound waves that vibrate from visible objects in a video feed. Parallel processor-accelerated machine learning enables computer vision applications to be trained using significantly larger training datasets than previously feasible, and allows inference systems to be deployed using low-power parallel processors.

[0179] Parallel processor-accelerated machine learning has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described herein enable rapid training of increasingly complex neural networks for autonomous driving solutions and allow for the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0180] Parallel processor-accelerated deep neural networks have enabled machine learning methods to achieve automatic speech recognition (ASR). ASR involves establishing a function that considers a given input sound sequence and calculates the most likely language sequence. Accelerated machine learning using deep neural networks has been able to replace previously used Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) for ASR.

[0181] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can utilize statistical inference algorithms to generate robust models to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0182] Parallel processing platforms used for machine learning can be categorized into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate single-node multi-GPU training and multi-node, multi-GPU training. Exemplary parallel processors suitable for training include the highly parallel general-purpose graphics processing unit 700 of Figure 7 and the multi-GPU computing system 800 of Figure 8. Conversely, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0183] Figure 13 illustrates an exemplary inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model. The SOC 1300 may integrate processing components including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 may additionally include on-chip memory 1305, which enables a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power computing to enable deployment on various machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1300 may be used as part of the main control system of an autonomous vehicle. When the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards of the deployment jurisdiction.

[0184] During operation, the media processor 1302 and the vision processor 1304 can work together to accelerate computer vision computation. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in on-chip memory 1305. The vision processor 1304 can then analyze the decoded video and perform preliminary processing operations on the frames of the decoded video when ready to use a trained image recognition model to process the frames. For example, the vision processor 1304 can accelerate convolution operations for a CNN used to perform image recognition on high-resolution video data, while the back-end model computation is performed by the GPGPU 1306.

[0185] The multi-core processor 1308 may include control logic to assist in the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also function as an application processor to execute software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of the navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may either directly offload the computational workload to the GPGPU 1306 or offload the computational workload to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0186] The GPGPU 1306 may include compute clusters, such as low-power configurations of compute clusters 706A-706H within the highly parallel general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 may support instructions specifically optimized for performing inference computations on trained neural networks. For example, the GPGPU 1306 may support instructions for performing low-precision computations such as 8-bit and 4-bit integer vector operations. The precision of dynamic floating-point units used for machine learning is reduced.

[0187] The IEEE 754 single-precision binary floating-point format specifies a 32-bit binary representation with 1 bit for the sign, 8 bits for the exponent, and 24 bits for the significant number, of which 23 bits are explicitly stored. The IEEE 754 half-precision binary floating-point format specifies a 16-bit binary representation with 1 bit for the sign, 5 bits for the exponent, and 11 bits for the significant number, of which 10 bits are explicitly stored. For non-zero exponent values, the implicit significant number bits are defined as 1, and when all exponent bits are zero, the implicit significant number bits are defined as zero. Floating-point units capable of performing arithmetic operations in single-precision and half-precision are known in the art. For example, existing floating-point units can perform 32-bit single-precision floating-point operations (FP32) or dual 16-bit half-precision floating-point operations (FP16).

[0188] The embodiments described herein extend this capability to enable variable-precision arithmetic by providing support for instructions and associated logic. Floating-point instructions that allow variable-precision arithmetic can dynamically increase throughput by performing operations with the lowest possible precision. In one embodiment, a set of instructions and associated logic is provided, wherein throughput is increased by performing floating-point operations with the lowest possible precision without significant data loss. In another embodiment, a set of instructions and associated logic is provided, wherein the floating-point logic compares the result of execution with higher precision to verify the result with lower precision to determine whether any significant data loss has occurred.

[0189] FIG14 illustrates the components of a dynamic precision floating-point unit 1400 according to an embodiment. In one embodiment, the dynamic precision floating-point unit 1400 includes a control unit 1402, a set of internal registers 1404, an exponent block 1406, and a sign block 1408. In addition to floating-point control logic known in the art, in one embodiment, the control unit 1402 additionally includes precision tracking logic 1412 and a value transformation unit 1422.

[0190] In one embodiment, precision tracking logic 1412 is hardware logic configured to track the number of available precision bits for computed data relative to a target precision. Precision tracking logic 1412 may track precision registers within exponent block 1406 and significant number block 1408 to track precision metrics, such as the minimum number of precision bits required to store the computed values ​​generated by exponent block 1406 and significant number block 1408. In one embodiment, the precision metric includes a running average representing the numerical precision required to represent data across a set of computations. In one embodiment, the precision metric includes the maximum required precision within a set of given data. In one embodiment, dynamic precision floating-point unit 1400 supports instructions to read or reset register data used by precision tracking logic 1412 to produce the precision metric described herein. In one embodiment, the computational unit housing the dynamic precision floating-point unit supports instructions to set or reset register files used by precision tracking logic 1412. In one embodiment, precision tracking logic 1412 monitors an error accumulator 1434 within the set of internal registers 1404. An error accumulator can be used to track accumulated errors (e.g., rounding errors) in a set of floating-point operations. In one embodiment, the dynamic precision floating-point unit 1400 supports a set of instructions including instructions to reset the error accumulator 1434 and instructions to read the error accumulator 1434. In one embodiment, the error accumulator can be reset in response to a bit or flag provided as an operand to the instruction.

[0191] In one embodiment, the numerical transformation unit 1422 may be used to perform intermediate numerical transformations on data when performing lower-precision operations to prevent or mitigate the possibility of overflow or underflow during the operation. For example, when approaching the precision limit of a given data type, the numerical transformation unit 1422 may use logarithms to perform multiplication or division operations and transform the resulting values ​​through exponentiation. Further details regarding the precision tracking logic 1412 and the numerical transformation unit 1422 are provided in Figure 22.

[0192] The internal register 1404 includes a set of operand registers 1414 that store input values ​​for the dynamic precision floating-point unit 1400. In one embodiment, the operand registers 1414 include two operands (A, B). For floating-point input data, the input data value may be divided into an exponent part (EXA, EXB) and a significant part (SIGA, SIGB). In various embodiments, the operand registers 1414 are not limited to supporting two floating-point inputs. In one embodiment, the operand registers 1414 include three input operands, for example, to support fused multiplication-addition, multiplication-subtraction, product-accumulation, or correlation operations. In one embodiment, the operand registers 1414 may also store integer values, such as in one embodiment where the dynamic precision floating-point unit supports 32-bit, 16-bit, and 8-bit integer operations. In one embodiment, the specific data type and baseline precision can be configured via inputs to the control unit 1402.

[0193] In one embodiment, floating-point operations are performed with dynamic precision using an exponent block 1406 and a significant number block 1408. In one embodiment, integer operations can be performed using the significant number block 1408. In one embodiment, dual 8-bit integer operations can be performed using the exponent block 1406 and the significant number block 1408.

[0194] In one embodiment, the exponent block 1406 includes a comparator 1416 and a dynamic precision exponent adder 1426. The comparator determines the difference between the exponents and identifies the smaller of the two exponents. During floating-point addition, the exponent with the smaller value is adjusted to match the exponent with the larger value. The dynamic precision exponent adder 1426 can be used to add the exponent value to an FP16 or FP32 value. The significant number block 1408 includes a dynamic precision multiplier 1418, a shift unit 1428, a dynamic precision significant number adder 1438, and an accumulator register 1448.

[0195] In one embodiment, the FP16 or FP32 data type can be specified for the operation. When FP16 is specified, the dynamic precision floating-point unit 1400 can power gate elements that are not necessary for performing FP32 operations, while maintaining logic to track precision loss or errors (e.g., through the error accumulator 1434). For example, in one embodiment, the error accumulator 1434 can be used to track some rounding operations within an instruction cycle. In one embodiment, the error accumulator holds the total accumulated rounding error across a set of instructions. The dynamic precision floating-point unit 1400 can enable instructions that support clearing or reading the error accumulator 1434 from software. When FP32 is specified, the dynamic precision floating-point unit 1400 can attempt to perform FP32 operations with FP16 precision, while powering more gate elements and components than are required to perform operations with FP16 precision. Based on input or intermediate values, when the dynamic precision floating-point unit 1400 is required to perform operations in FP32, it can initially attempt to perform operations in FP16 and expand the precision up to FP32 as needed. When FP32 operations can be performed with FP16 precision, the power requirement per operation is reduced, allowing a larger number of computing elements to be enabled simultaneously. For example, the dynamic capacitance and / or power budget constraints of a given configuration, such as a battery-powered configuration or a passively cooled configuration only, may not allow all floating-point units or other computing elements within the GPGPU to be enabled simultaneously. By enabling dynamic lower-precision computation to reduce the dynamic power of a set of floating-point units, the overall throughput of the GPGPU's computing units within a given power envelope can be increased because a larger number of threads can be processed per cycle without exceeding the dynamic power limit.

[0196] FIG15 provides additional details regarding the dynamic precision floating-point unit 1400 of FIG14 according to an embodiment. In one embodiment, the dynamic precision multiplier 1418 includes a set of input buffers 1502 for storing significant number data. In one embodiment, the set of input buffers includes two buffers storing two input values ​​for multiplication or division operations. For aggregating operations (e.g., multiply-add, multiply-subtract), the product of the operation can be added to a third input via an adder and / or stored in an accumulator register.

[0197] In one embodiment, some configurations of the dynamic precision multiplier 1418 include a 24-bit input buffer that can explicitly store 24 bits of significant data for single-precision floating-point inputs, or 11 bits of significant data for half-precision floating-point values. In some configurations, the input buffer 1502 can also be a 32-bit buffer to implement multiplication of 32-bit integer values. In one embodiment, a single configuration of the input buffer 1502 is presented, which can be selected or configured between 32 bits and 24 bits. In one embodiment, the output buffer 1510 can similarly be configured or selected between 24 bits and 32 bits to selectively enable the storage of full-precision 32-bit integers or 24-bit and / or 11-bit significant values ​​for 32-bit or 16-bit floating-point numbers.

[0198] In one embodiment, the dynamic precision multiplier 1418 includes a multiplier 1506 and an overflow multiplier 1504. The multiplier 1506 is configured to perform multiplication or division operations with half precision for the data type. For example, the multiplier 1506 can perform 11-bit multiplication operations on the significant numbers of FP16 floating-point values ​​and / or 16-bit multiplication operations on 16-bit integer values. The multiplier 1506 can also perform 8-bit multiplication operations on INT8 integer values. For 32-bit floating-point values ​​or 32-bit integer values, the multiplier 1506 can perform multiplication operations with 11 bits (e.g., FP16 precision) on 24-bit significant numbers. If needed, the multiplier 1506 can perform multiplication with 16-bit precision on 24-bit FP32 significant numbers. In one embodiment, the precision required and the result of operations on a given set of inputs can be tracked through a precision register 1508. In one embodiment, the required and resulting precision can be represented within the precision register 1508 through precision loss, which would result if the output of multiplier 1506 were output through output buffer 1510. In this embodiment, the precision register 1508 can track precision loss associated with using lower precision data types and precision loss associated with performing operations with less precision than required.

[0199] In one embodiment, the control logic associated with the dynamic precision multiplier 1418 (e.g., within the control unit 1402 of FIG. 14) can monitor the precision loss associated with performing higher precision (e.g., FP32, INT32) operations at lower precision (e.g., FP16, INT16, INT8). If the precision loss would be significant, the control logic can enable the overflow multiplier 1504 to perform operations with additional bit precision. Furthermore, if the control logic determines, based on the current input, that an overflow or underbite will occur, it enables the overflow multiplier 1504 and uses the overflow multiplier 1504 and multiplier 1506 to perform multiplication operations.

[0200] Similar control operations are performed for the dynamic precision exponent adder 1426 and the dynamic precision significant number adder 1438. The dynamic precision exponent adder 1426 includes a set of 8-bit input buffers that can store exponent data of FP32 (8 bits) and FP16 (5 bits). The 8-bit input buffer 1512 can also store a set of INT-8 inputs. The output buffer 1520 for the dynamic precision exponent adder 1426 can be configured similarly. The dynamic precision significant number adder 1438 includes a set of input buffers 1522, which can be selected from one of a set of 24-bit and 32-bit buffers, or can be dynamically configured to store input data with 24 bits or 32 bits. In one embodiment, the input buffer 1522 is simply a 32-bit buffer, which can also store 24-bit input data. The output buffer 1530 for the dynamic precision significant number adder 1438 can be configured similarly. The precision register 1518 within the dynamic precision exponential adder 1426 and the precision register 1528 within the dynamic precision significant number adder 1438 can be configured to track the precision loss of the performed operation. The control logic can enable the overflow adder 1514 and / or the overflow adder 1524 as needed to prevent overflow or under-accuracy conditions or to prevent the precision loss from exceeding a threshold.

[0201] Referring back to Figure 14, in one embodiment, the dynamic precision floating-point unit 1400 can perform dual INT8 operations using a dynamic precision exponent adder 1426 and a dynamic precision significant adder 1438. For example, instead of disabling the exponent block 1406 during integer operations, the exponent block 1406 can be configured to operate on a first set of 8-bit integer operands, while the significant adder 1408 can be configured to operate on a second set of 8-bit operands. To support dual 8-bit multiplication, dual-sum multiplication-addition, dual-sum multiplication-subtraction, and / or other multiplication-based operations, in one embodiment, the exponent block 1406 may include an additional multiplier 1436. This multiplier may be a fixed 8-bit multiplier to enable simultaneous dual 8-bit multiplication operations using the exponent block 1406 and the significant adder 1408.

[0202] Figure 16 illustrates thread allocation for a dynamic precision processing system 1600 according to an embodiment. In one embodiment, the dynamic precision processing system 1600 includes a set of dynamic floating-point units 1608A-1608D. The dynamic floating-point units 1608A-1608D can execute a set of operation threads 1606A-1606D, which can perform mixed-precision arithmetic and produce output data with variable precision. In one embodiment, a first operation (e.g., addition, subtraction, multiplication, division, etc.) can be performed on the first dynamic floating-point unit 1608A by the first operation thread 1606A, wherein the first operation thread 1606A accepts two 16-bit floating-point values ​​1602A-1602B as input and outputs a 16-bit floating-point value FP16. The first operation can be executed as a double operation, wherein a single instruction executed by the GPGPU allows mixed-precision FP16 / FP32 double operation. The second operation of the dual-operation can be executed by a second operation thread 1606B, which is executed by the second dynamic floating-point unit 1608B. The second dynamic floating-point unit 1608B can generate a second output 1612, which is a 32-bit floating-point output. The second operation thread 1606B configures the second dynamic floating-point unit 1608B to receive two 32-bit floating-point input values ​​1603A-1603B. In one embodiment, the operation on the two 32-bit floating-point operations can be performed with 16-bit precision. If the operation can be performed without under-biting, overflowing, or excessive biting, performing the operation with lower precision will not result in a loss of precision.

[0203] In one embodiment, the dynamic precision processing system 1600 can execute a single instruction having 16-bit operands 1604A and 32-bit operands 1604B. An operation thread 1606C can be executed on the dynamic floating-point unit 1608C. The dynamic floating-point unit 1608C will attempt to perform mixed-precision 16-bit / 32-bit operations with 16-bit precision unless significant precision loss or error occurs. In one embodiment, the dynamic precision processing system 1600 can also be configured to perform integer operations. For example, an operation can be performed on a pair of 8-bit integer outputs 1605A-1605B via the dynamic floating-point unit 1608D through the operation thread 1606D to produce an 8-bit integer output 1616. In one embodiment, the dynamic floating-point unit 1608D is configured to perform dual 8-bit integer operations, wherein the two 8-bit integer operations can be executed in a single loop.

[0204] FIG17 illustrates logic 1700 performing numerical operations with less-than-required precision according to an embodiment. In one embodiment, logic 1700 is implemented via hardware integrated within dynamic precision floating-point unit 1400 of FIG14. In another embodiment, logic 1700 is partially executed via control unit 1402 within dynamic precision floating-point unit 1400 of FIG14.

[0205] In one embodiment, logic 1700 may receive a request to perform a numerical operation with a first precision, as shown in block 1702. The numerical operation may be a floating-point operation or an integer operation. The first precision may be, for example, 32-bit precision. In one embodiment, the numerical operation may be a first-precision operation performed while performing an operation with mixed precision. Logic 1700 may then perform the numerical operation using a number of bits associated with a second precision lower than the first precision, as shown in block 1704. For example, and in one embodiment, the number of bits used to perform the operation may be a number of bits associated with a 16-bit operation, while the first precision is 32-bit precision. Logic 1700 may produce an intermediate result with the second precision in block 1706. Logic 1700 may then determine the precision loss of the intermediate result relative to the first precision. The precision loss may be read from a register that stores an index of the precision loss stored during the operation.

[0206] Logic 1700 can determine in block 1709 whether the precision loss is less than a threshold. In one embodiment, the threshold associated with the precision loss can be software-configurable, although in some embodiments a hardware-preset threshold is used. In one embodiment, the degree of precision loss can also be determined by performing full-precision operations in parallel on unused computational units. The reduced precision result can then be compared with the full-precision result. If the precision loss is less than the threshold, logic 1700 can output the result with a second precision, as shown in block 1712. If the precision loss is not less than the threshold in block 1709, logic 1700 can compute the remaining bits of the result in block 1710 and output the result with a first precision, as shown in block 1714. In one embodiment, the remaining bits of the result computed in block 1710 can be performed through overflow logic units, such as overflow multiplier 1504, overflow adder 1514, and / or overflow adder 1524 in FIG. 15. Vertical stacking of operations for 16-bit floating-point arithmetic.

[0207] When performing Single Instruction Multiple Thread (SIMT) operations with lower precision, in some cases, it may be difficult to fully utilize the underlying SIMD logic due to the increased number of components required to fill all SIMD lanes. For example, a SIMD logic unit configured to run FP32 on a 128-bit output register can perform a single operation on four sets of input data. If this logic unit is configured to perform FP16 operations on the same four sets of input data, the underlying throughput of the operation may increase due to the lower precision, but the SIMD utilization will be halved. One solution to underutilizing SIMD is to perform the operation on eight sets of input data. However, the software executing on the logic unit may not require as much parallelism as the underlying hardware can provide.

[0208] For example, loops that perform iterative operations on an input array can be vectorized, so that each iteration of the array is executed in parallel as a separate SIMT thread. A single SIMT thread can be executed as a single operation on the underlying SIMD / vector logic within the computation unit. When executing parallel instructions derived through the compiler's loop vectorization logic, loops shorter than eight iterations will not fill all eight SIMD channels available for executing threads spawned for those operations, thus reducing the overall utilization of the computation unit. Furthermore, if the underlying hardware has N SIMD channels, any number of vectorized iterations that are not multiples of N will require the remaining iterations to be executed on an incomplete SIMD unit. Additionally, vectorization may require a separate peel loop execution before the main body of the vectorization operation is executed.

[0209] Some embodiments described herein can improve SIMD utilization by stacking multiple unrelated FP16 operations into a single SIMD unit for execution. With eight channels available for execution in the SIMD unit, thread scheduling logic can dispatch threads in units of N / 2 or N / 4, allowing several unrelated groups of threads performing the same or compatible operations to share a single SIMD unit. Additionally, one embodiment enables SIMD channel scheduling, which allows a mix of dynamically assembled SIMT thread groups and vectorized SIMD threads.

[0210] Figure 18 illustrates loop vectorization for a SIMD unit according to an embodiment. In one embodiment, the software logic may include loops automatically vectorized by compiler software executed on a data processing system. The loop may include a stripped loop 1802, a vectorized main loop 1804, and a residual loop 1806. In some configurations, loop vectorization is most efficient when performing data on access-aligned memory. For example, a GPGPU may be configured such that vector memory accesses can be performed most efficiently in 64-bit blocks 1801A-1801F. In this configuration, the stripped loop 1802 includes stripping a subset of loop iterations from the main loop so that unaligned memory accesses can be separated from the main loop. The vectorized main loop 1804 includes most of the loop iterations. Each iteration of the vectorized main loop can be executed in parallel, and memory accesses for each element are aligned on specific memory boundaries. Residual loop 1806 comprises a set of iterations following the vectorized main loop 1804. The iterations in residual loop 1806 may not typically be executed in parallel as efficiently as the main loop.

[0211] In one embodiment, the stripping loop 1802 and the remaining loop 1806 can also be vectorized. In one embodiment, each of the stripping loop 1802, the main loop 1804, and the remaining loop 1806 can be executed on an FP16 SIMD8 unit, wherein eight instances of the same operation can be executed in parallel. Loop iterations can be executed in parallel on SIMD hardware (e.g., FP16 SIMD8 units 1808A-1808C) using execution masks 1812, 1814, and 1816, each of which enables and disables SIMD channels for the operation cycle. For the illustrated stripping loop 1802 and the remaining loop 1806, a subset of elements is selected in execution masks 1812 and 1816. All channels are selected in the execution mask 1814 of the vectorized main loop 1804.

[0212] In one embodiment, for a SIMD unit with inactive channels, it can be configured to perform other operations on those inactive channels. For a given period, if the scheduling logic configures a set of inactive channels for a SIMD unit (e.g., FP16 SIMD8 1808A, FP16 SIMD8 1808C), instead of leaving those channels idle during the cycle, the scheduler can stack other multi-element SIMD threads or allocate SIMT threads to other idle SIMD channels.

[0213] Figure 19 illustrates a thread processing system 1900 according to an embodiment. In one embodiment, the thread processing system 1900 includes a SIMD computing unit, such as a SIMD8 floating-point unit 1920, which includes a plurality of dynamic floating-point units 1922A-1922H. Depending on the operation, the SIMD8 floating-point unit 1920 can perform eight or more identical or similar operations in a single loop. For example, in one embodiment, each of the eight dynamic floating-point units 1922A-1922H can perform a single operation with FP16 precision. In one embodiment, each of the eight dynamic floating-point units 1922A-1922H can perform two pairs of INT8 operations in a single loop.

[0214] In some cases, such as with stripping or residual loops as shown in Figure 18, not all channels of the SIMD floating-point unit will be active during the loop. To improve utilization, SIMD slots can be allocated at a smaller granularity so that other unused SIMD channels can be utilized. For example, the SIMD8 floating-point unit 1920 is typically allocated threads or operations at an eight-operation granularity, where fewer than eight operations can result in a potential loss of computational efficiency. In one embodiment, a SIMD channel can be occupied by a single-vector SIMD thread, which includes an execution mask selecting at least eight elements or a SIMT thread group with at least eight elements.

[0215] To improve SIMD utilization, one embodiment divides eight SIMD channels into two SIMD4 slots (e.g., SIMD4 slot 1910, SIMD4 slot 1912). The SIMD4 slots can be filled in various ways. In one embodiment, two separate SIMD threads (SIMD thread 1902, SIMD thread 1904) combined to cover a total of four SIMD channels are assigned to the SIMD4 slot (e.g., SIMD4 slot 1910). In another embodiment, a SIMT thread group 1906 can be assigned to the SIMD4 slot 1912. The SIMT thread group 1906 can include any number of threads that are multiples of four threads (e.g., 4, 8, 12, 16, etc.). Threads within the SIMT thread group 1906 can be processed in batches of four, and the number of loops required to process all threads within the SIMT thread group 1906 depends on the number of threads within the group.

[0216] Figure 20 illustrates logic 2000 for allocating threads for computation according to an embodiment. In one embodiment, logic 2000 is executed via thread processing system 1900 in Figure 19. In one embodiment, logic 2000 may receive a first group of threads at a SIMD unit having a first number of channels, as shown in block 2002. Logic 2000 may then determine whether the first group of threads fills all the SIMD channels of the SIMD unit, as shown in block 2003. If the first group of threads includes enough SIMT threads or the threads of the first group of threads include enough SIMD vector elements to fill all the SIMD channels, then logic 2000 may allocate the first group of threads to the SIMD unit, as shown in block 2004.

[0217] If the first group of threads does not fill all the SIMD channels, as determined in block 2003, then logic 2000 can allocate the first group of threads to a second number of channels, which is less than the first number of channels, in block 2006. This allocation can be performed by allocating SIMD threads to SIMD units and masking inactive channels. Allocation can also be performed by allocating a group of SIMD threads to SIMD units. The logic can then stack one or more additional groups of threads to fill all the SIMD channels, as shown in block 2008. The additional groups of threads can specify active SIMD channels that occupy channels not occupied by the initial threads. This enables systems for standardizing and transforming low-precision data.

[0218] When performing operations with low-precision data types, care must be taken to avoid data overflow or underbiting during numerical computation. This responsibility typically falls to the data scientists developing low-precision algorithms. Due to the limitations of low-precision arithmetic, many neural networks have been adapted to use binary and / or ternary values ​​where each element occupies only one or two bits. However, there is a need for integer and floating-point arithmetic logic units that can be enabled using guard logic to warn or attempt to prevent significant loss of precision during arithmetic operations. In one embodiment, the dynamic precision floating-point unit described herein includes logic that issues a warning when the numerical computation approaches the limits of low-precision computation.

[0219] As shown in FIG. 14, the dynamic precision floating-point unit 1400 may include precision tracking logic 1412 and a value transformation unit 1422. In one embodiment, the precision tracking logic 1412 tracks the available bits of the remaining precision of the computed data relative to a target precision. If precision can be tracked, the available bits of intermediate data are used to determine, in one embodiment, whether an intermediate data value computed with higher precision relative to the input or output data can be stored with output precision without significant precision loss or rounding error. For example, in one embodiment, a particular low-precision operation can be performed efficiently with higher precision, and the precision tracking logic 1412 can determine whether the result of the computation will overflow the given output precision. In one embodiment, the logic unit described herein can output status information indicating the degree of precision loss due to rounding error. In one embodiment, the logic unit can perform intermediate value transformations on the data to prevent significant data loss. The logic unit can then output the transformed value. In one embodiment, a full-precision or near-full-precision output value can be programmatically derived based on the output and status information provided by the output.

[0220] Figure 21 illustrates a deep neural network 2100 that can be processed using the computational logic provided by the embodiments described herein. A deep neural network (DNN) is an artificial neural network comprising multiple neural network layers 2102A-2102N. Each layer represents a set of non-linear computational operations that perform feature extraction and transformation in a manner consistent with the machine learning neural networks described herein. Each successive layer uses the output from the previous layer as input. In the case of a convolutional neural network, fusion multiply-accumulate logic (e.g., FMA logic 2104A, 2104B) can be used to compute the dot product between the feature map and the filtered data to generate activation map data, which is provided as input to the successive layers.

[0221] Low-precision neural networks can be implemented using binary or ternary weights combined with binary, ternary, or N-bit feature maps. Some neural networks can still benefit from the increased precision of computation using N-bit feature maps and N-bit filters. In some implementations, the N-bit features and weights of a neural network can be processed with low precision without significantly reducing output error. However, data scientists implementing low-precision N-bit neural networks (e.g., FP16, INT8) should generally be aware of the rounding errors or out-of-bounds data that may occur due to continuous computation with low precision. If the precision tracking logic in FMA logics 2104A-2104B (e.g., precision tracking logic 1412 in Figure 14) determines that the weights or feature map data are approaching the limits of the available precision for the data type, the state bits can be set by FMA logics 2104A-2014B. State bits can serve as an indicator for data scientists developing neural network models existing within neural network layers 2102A-2102N, suggesting that the model may require optimization or may need greater numerical precision.

[0222] In one embodiment, the normalization and transformation logics 2106A-2106B can be enabled to perform weight normalization or numerical transformation on the feature map data before providing the feature map data to the next neural network layer as input. The application of the normalization and transformation logics 2106A-2106B is optional at each stage and is only performed if significant loss of precision, overflow, or under-precision conditions may occur during the processing of the upcoming layer. In one embodiment, the weights or feature maps output from one layer of the neural network can be automatically normalized through instances of the normalization and transformation logics 2106A-2106B.

[0223] In one embodiment, the normalization and transformation logics 2106A-2106B can use the numerical transformation unit 1422 of FIG. 14 to transform feature map data or weight data. The feature map data output from the neural layer can be based on a set of data output from a set of functions. In this embodiment, a specific set of low-precision instructions is provided that can automatically adjust the N-bit neural network data to prevent catastrophic loss of precision. Exemplary transformations or normalizations that can be performed by the normalization and transformation logics 2106A-2106B include weight normalization to a range of values, or a set of permanent and reversible feature data transformations. In one embodiment, weight normalization can be performed to compress the dynamic range of a set of filter weights to a predetermined range. The weight data can be normalized in, for example, a range of [-1, 1], which can maintain the relative differences between weight values ​​while reducing the overall numerical value of the weight values. In one embodiment, the neural network weights or feature map data can be normalized by the average value of the dataset.

[0224] In one embodiment, neural network computation using data that is close to the range limit of the data type can be transformed before the data is used for computation. For example, multiplication using large values ​​that may cause overflow can be performed as logarithmic addition instead of multiplication. Although this transformation may result in some loss of precision, it will enable computation to be performed without overflowing the number of bits allocated to perform the operation. For example, a series of operations can be presented as in equation (1). (1)

[0225] If the precision tracking logic within the computation unit determines that such an operation may overflow or undershoot, the operation can be converted into equation (2). (2)

[0226] Equation (2) can be executed to produce a result without triggering a data type overflow. In one embodiment, the normalization and transformation logic 2106A-2016B can convert the output value into a logarithmic value for storage and transform the value by exponentiation before using the value in the machine learning computation described herein.

[0227] Figure 22 is a flowchart of logic 2200 according to an embodiment, which is used to prevent errors or significant loss of precision when performing low-precision calculations in machine learning. In one embodiment, logic 2200 can be executed through precision tracking logic 1412 and numerical transformation unit 1422 in the dynamic precision floating-point unit 1400 as shown in Figure 14.

[0228] In one embodiment, logic 2200 may compute an activation map based on filter and feature map data associated with layers of the neural network, as shown in block 2202. Then, logic 2200 may track the accuracy loss that occurs during the computation of the activation map for the layers of the neural network. Logic 2200 may then determine at block 2205 whether the accuracy loss is close to a threshold. If the accuracy loss is not close to a preset or configured threshold at block 2205, logic 2200 may continue to compute the activation map for the successor layer (and apply the activation function) until, and unless, an accuracy loss close to the threshold occurs at block 2205. When the accuracy loss is close to the threshold, logic 2200 may determine at block 2207 whether to enable automatic numerical transformation. If, at block 2207, automatic transformation is enabled, for example, through instructions used to perform the set of numerical operations, logic 2200 may transform the neural network data at block 2208 to reduce errors caused by accuracy loss. Logic 2200 can perform any numerical transformations described herein, including data normalization within a range or through averaging. Regardless of whether automatic transformation is enabled at block 2207, logic 2200 can output a state at block 2210 indicating that the accuracy loss is approaching a threshold. This state output can be a state flag, which is output from the computation unit as the result of the computation. Programmers can configure the software logic to respond to this state by adjusting the algorithm executed in the executor or by adjusting the neural network model used to perform machine learning. Additional exemplary graphics processing system.

[0229] Details of the above embodiments can be incorporated in the following graphics processing system and apparatus. The graphics processing system and apparatus of Figures 23 to 36 illustrate alternative systems and graphics processing hardware that can implement any and all of the above-described techniques. Additional exemplary graphics processing system overview

[0230] FIG23 is a block diagram of a processing system 2300 according to an embodiment. In various embodiments, the system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2302 or processor cores 2307. In one embodiment, the system 2300 is a processing platform incorporated into a system-on-a-chip (SoC) integrated circuit for mobile, handheld, or embedded devices.

[0231] One embodiment of system 2300 may include a server-based gaming platform, a game console including a game and media console, a mobile game console, a handheld game console, or an online game console, or incorporated thereof. In some embodiments, system 2300 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet access device. Data processing system 2300 may also include, be coupled to, or be integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0232] In some embodiments, one or more processors 2302 each include one or more processor cores 2307 to process instructions that, when executed, perform operations for the system and user software. In some embodiments, each of the one or more processor cores 2307 is configured to process a particular instruction set 2309. In some embodiments, the instruction set 2309 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). The multiple processor cores 2307 may each process different instruction sets 2309, which may include instructions that facilitate the emulation of other instruction sets. The processor cores 2307 may also include other processing devices, such as digital signal processors (DSPs).

[0233] In some embodiments, processor 2302 includes cache memory 2304. Depending on the architecture, processor 2302 may have a single internal cache or multiple levels of internal cache. In some embodiments, cache memory is shared among various components of processor 2302. In some embodiments, processor 2302 also uses external caches (e.g., Level 3 (L3) cache or Last Level (LLC) cache) (not shown), which can be shared among processor cores 2307 using known cache coherence techniques. Processor 2302 also includes a register file 2306, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction index registers) for storing different types of data. Some registers may be general-purpose registers, while others may be designed specifically for processor 2302.

[0234] In some embodiments, processor 2302 is coupled to processor bus 2310 to transmit communication signals such as addresses, data, or control signals between processor 2302 and other components in system 2300. In one embodiment, system 2300 uses an exemplary "hub" system architecture including memory controller hub 2316 and input / output (I / O) controller hub 2330. Memory controller hub 2316 facilitates communication between memory devices and other components of system 2300, while I / O controller hub (ICH) 2330 provides connectivity to I / O devices via local I / O buses. In one embodiment, the logic of memory controller hub 2316 is integrated within the processor.

[0235] The memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a cache memory device, a phase-change memory device, or some other memory device with suitable performance as processing memory. In one embodiment, the memory device 2320 may operate as system memory for the system 2300 to store data 2322 and instructions 2321 for use when one or more processors 2302 execute applications or processes. The memory controller hub 2316 is also coupled to an optional external graphics processor 2312, which may communicate with one or more graphics processors 2308 in the processors 2302 to perform graphics and media operations.

[0236] In some embodiments, ICH 2330 enables peripheral devices to be connected to memory device 2320 and processor 2302 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 2346, a firmware interface 2328, a wireless transceiver 2326 (e.g., Wi-Fi, Bluetooth), a data storage device 2324 (e.g., a hard drive, cache memory, etc.), and a legacy I / O controller 2340 for coupling legacy (e.g., a Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2342 connect input devices such as a keyboard and mouse 2344 combination. A network controller 2334 may also be coupled to ICH 2330. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 2310. It should be understood that the illustrated system 2300 is exemplary and not limiting, as other types of data processing systems with different configurations may also be used. For example, the I / O controller hub 2330 may be integrated within one or more processors 2302, or the memory controller hub 2316 and the I / O controller hub 2330 may be integrated into individual external graphics processors, such as external graphics processor 2312.

[0237] FIG24 is a block diagram of an embodiment of a processor 2400 having one or more processor cores 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408. The elements of FIG24, which have the same reference numerals (or names) as elements in any other figure herein, may operate or function in a manner similar to, but not limited to, any manner described elsewhere herein. The processor 2400 may include up to and including additional cores 2402N, indicated by dashed boxes. Each of the processor cores 2402A-2402N includes one or more internal cache units 2404A-2404N. In some embodiments, each processor core may also access one or more shared cache units 2406.

[0238] Internal cache units 2404A-2404N and shared cache unit 2406 represent cache memory hierarchies within processor 2400. A cache memory hierarchy may include at least one level of instruction and data cache within each processor core, and one or more levels of shared intermediate-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, wherein the highest-level cache preceding external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherence among the various cache units 2406 and 2404A-2404N.

[0239] In some embodiments, the processor 2400 may also include a group of one or more bus controller units 2416 and a system agent core 2410. The one or more bus controller units 2416 manage a group of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2410 provides management functions for various processor components. In some embodiments, the system agent core 2410 includes one or more integrated memory controllers 2414 to manage access to various external memory devices (not shown).

[0240] In some embodiments, one or more processor cores 2402A-2402N include support for simultaneous multithreading. In such an embodiment, system agent core 2410 includes components for coordinating and operating cores 2402A-2402N during multithreaded processing. System agent core 2410 may also include a power control unit (PCU), which includes logic and components for regulating the power state of processor cores 2402A-2402N and graphics processor 2408.

[0241] In some embodiments, the processor 2400 further includes a graphics processor 2408 to perform graphics processing operations. In some embodiments, the graphics processor 2408 is coupled to the shared cache unit 2406 and a system proxy core 2410 including one or more integrated memory controllers 2414. In some embodiments, a display controller 2411 is coupled to the graphics processor 2408 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2411 may be a separate module coupled to the graphics processor via at least one interconnect, or it may be integrated within the graphics processor 2408 or the system proxy core 2410.

[0242] In some embodiments, the ring-based interconnect unit 2412 is used to couple internal components of the processor 2400. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art, may be used. In some embodiments, the graphics processor 2408 is coupled to the ring interconnect 2412 via I / O link 2413.

[0243] The exemplary I / O link 2413 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2418 (such as an eDRAM module). In some embodiments, each of the processor cores 2402A-2402N and the graphics processor 2408 uses the embedded memory module 2418 as a shared last-order cache memory.

[0244] In some embodiments, processor cores 2402A-2402N are homogeneous cores executing the same instruction set architecture. In another embodiment, with respect to the instruction set architecture (ISA), processor cores 2402A-2402N are heterogeneous, wherein one or more of processor cores 2402A-2402N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, with respect to the microarchitecture, processor cores 2402A-2402N are heterogeneous, wherein one or more cores with relatively high power consumption are coupled to one or more cores with lower power consumption. Furthermore, processor 2400 may be implemented on one or more wafers, or implemented as a SoC integrated circuit having the components shown among other components.

[0245] Figure 25 is a block diagram of a graphics processor 2500, which may be a discrete graphics processing unit or a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and with commands placed into processor memory. In some embodiments, the graphics processor 2500 includes a memory interface 2514 for accessing memory. The memory interface 2514 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0246] In some embodiments, the graphics processor 2500 also includes a display controller 2502 to drive display output data to the display device 2520. The display controller 2502 includes one or more overlay plane hardware for displaying and combining multiple video layers or user interface elements. In some embodiments, the graphics processor 2500 includes a video codec engine 2506 for encoding media to one or more media encoding formats, decoding media from one or more media encoding formats, or transcoding media between one or more media encoding formats, including, but not limited to, Animation Experts Group (MPEG) format such as MPEG-2, Advanced Video Coding (AVC) format such as H.264 / MPEG-4 AVC, and Society of Animation and Television Engineers (SMPTE) 421M / VC-1, and Joint Group of Video Experts (JPEG) format such as JPEG, and Animation JPEG (MJPEG) format.

[0247] In some embodiments, the graphics processor 2500 includes a block image transfer (BLIT) engine 2504 for performing two-dimensional (2D) rasterization operations, including, for example, bit-boundary block transfer. However, in one embodiment, one or more components of a graphics processing engine (GPE) 2510 are used to perform 2D graphics operations. In some embodiments, the GPE 2510 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0248] In some embodiments, GPE 2510 includes a 3D pipeline 2512 for performing 3D operations, such as rendering 3D images and scenes using processing functions acting on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2512 includes programmable and fixed-function elements that perform various tasks within the elements and / or generate execution threads to the 3D / media subsystem 2515. While the 3D pipeline 2512 can be used to perform media operations, embodiments of GPE 2510 also include a media pipeline 2516, which is specifically used to perform media operations such as video post-processing and image enhancement.

[0249] In some embodiments, the media pipeline 2516 includes fixed-function or programmable logic units to perform one or more dedicated media operations, such as video decoding acceleration, video de-interlacing, and video encoding acceleration, in place of or on behalf of the video codec engine 2506. In some embodiments, the media pipeline 2516 also includes a thread spawning unit to generate threads for execution on the 3D / media subsystem 2515. The generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2515.

[0250] In some embodiments, the 3D / media subsystem 2515 includes logic for executing threads generated by the 3D pipeline 2512 and the media pipeline 2516. In one embodiment, the pipeline transmits thread execution requests to the 3D / media subsystem 2515, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2515 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, which includes registers and addressable memory for sharing data among threads and storing output data. Exemplary Additional Graphics Processing Engine

[0251] FIG26 is a block diagram of a graphics processing engine 2610 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2610 is a version of the GPE 2510 shown in FIG25. Elements of FIG26 having the same reference numerals (or names) as elements in any other figure herein may operate or function in a manner similar to, but not limited to, those described elsewhere herein. For example, the 3D pipeline 2512 and media pipeline 2516 of FIG25 are shown. The media pipeline 2516 is optional in some embodiments of the GPE 2610 and may not be explicitly included within the GPE 2610. For example, and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 2610.

[0252] In some embodiments, GPE 2610 is coupled to or includes command streamer 2603, which provides command streaming to 3D pipeline 2512 and / or media pipeline 2516. In some embodiments, command streamer 2603 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 2603 receives commands from memory and sends those commands to 3D pipeline 2512 and / or media pipeline 2516. These commands are directives extracted from a ring buffer that stores commands for 3D pipeline 2512 and media pipeline 2516. In one embodiment, the ring buffer may also include a batch command buffer that stores batches of multiple commands. Commands for the 3D pipeline 2512 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 2512 and / or image data and memory objects for the media pipeline 2516. The 3D pipeline 2512 and the media pipeline 2516 process commands and data by performing operations through logic within their respective pipelines or by dispatching one or more execution threads to the graphics core array 2614.

[0253] In various embodiments, the 3D pipeline 2512 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2614. The graphics core array 2614 provides a unified block of execution resources. The multipurpose execution logic (e.g., execution units) within the graphics core array 2614 includes support for various 3D API shader languages ​​and can execute multiple concurrent execution threads associated with multiple shaders.

[0254] In some embodiments, the graphics core array 2614 also includes execution logic for performing media functions, such as video and / or image processing. In one embodiment, the execution unit additionally includes general-purpose logic programmable to perform parallel general-purpose computing operations in addition to graphics processing operations. The general-purpose logic may perform processing operations in parallel or together with the general-purpose logic within the processor core 2307 of FIG. 23, the cores 2402A-2402N of FIG. 24, or any other processor described herein.

[0255] Output data generated by threads executing on the graphics core array 2614 can be output to memory in a unified return buffer (URB) 2618. The URB 2618 can store data for multiple threads. In some embodiments, the URB 2618 can be used to transfer data between different threads executing on the graphics core array 2614. In some embodiments, the URB 2618 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared-function logic 2620.

[0256] In some embodiments, the graphics core array 2614 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 2610. In one embodiment, the execution resources are dynamically scalable, such that execution resources can be enabled or disabled as needed.

[0257] The graphics core array 2614 is coupled to shared function logic 2620, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functions within the shared function logic 2620 are hardware logic units that provide dedicated auxiliary functions for the graphics core array 2614. In various embodiments, the shared function logic 2620 includes, but is not limited to, sampler 2621, math 2622, and inter-thread communication (ITC) 2623 logic. Furthermore, some embodiments implement one or more caches 2625 within the shared function logic 2620. Shared functions are implemented when the requirement for a given dedicated function is insufficient to be included within the graphics core array 2614. Instead, a single instance of the dedicated function is implemented as a separate entity within the shared function logic 2620 and shared among execution resources within the graphics core array 2614. The exact groups of functions shared among and included within the graphics core array 2614 differ between various embodiments.

[0258] FIG27 is a block diagram of another embodiment of the graphics processor 2700. Elements of FIG27 having the same reference numerals (or names) as elements in any other figure herein may operate or function in a manner similar to, but not limited to, those described elsewhere herein.

[0259] In some embodiments, the graphics processor 2700 includes a ring interconnect 2702, a pipeline front end 2704, a media engine 2737, and graphics cores 2780A-2780N. In some embodiments, the ring interconnect 2702 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0260] In some embodiments, the graphics processor 2700 receives a batch of commands via a ring interconnect 2702. The incoming commands are interpreted by a command streamer 2703 in the pipeline front end 2704. In some embodiments, the graphics processor 2700 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2780A-2780N. For 3D geometry processing commands, the command streamer 2703 provides commands to the geometry pipeline 2736. For at least some media processing commands, the command streamer 2703 provides commands to the video front end 2734, which is coupled to the media engine 2737. In some embodiments, the media engine 2737 includes a video quality engine (VQE) 2730 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2733 for providing hardware acceleration for media data encoding and decoding. In some embodiments, the geometry pipeline 2736 and the media engine 2737 each generate execution threads for thread execution resources provided by at least one graphics core 2780A.

[0261] In some embodiments, the graphics processor 2700 includes scalable thread execution resources, the primary portion of which is modular cores 2780A-2780N (sometimes referred to as slices), each having multiple sub-cores 2750A-2750N and 2760A-2760N (sometimes referred to as sub-slices). In some embodiments, the graphics processor 2700 may have any number of graphics cores 2780A to 2780N. In some embodiments, the graphics processor 2700 includes a graphics core 2780A having at least a first sub-core 2750A and a second sub-core 2760A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2750A). In some embodiments, the graphics processor 2700 includes multiple graphics cores 2780A-2780N, each including a set of first sub-cores 2750A-2750N and a set of second sub-cores 2760A-2760N. Each subcore in the first group of subcores 2750A-2750N includes at least a first set of execution units 2752A-2752N and media / texture samplers 2754A-2754N. Each subcore in the second group of subcores 2760A-2760N includes at least a second set of execution units 2762A-2762N and samplers 2764A-2764N. In some embodiments, each subcore 2750A-2750N and 2760A-2760N shares a set of shared resources 2770A-2770N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor. Exemplary additional execution units

[0262] Figure 28 illustrates thread execution logic 2800, which includes an array of processing elements employed in some embodiments of GPE. Elements of Figure 28 having the same reference numerals (or names) as elements in any other figure herein may operate or perform functions in a manner similar to, but not limited to, those described elsewhere herein.

[0263] In some embodiments, thread execution logic 2800 includes a shader processor 2802, a thread dispatcher 2804, an instruction cache 2806, a scalable execution unit array including a plurality of execution units 2808A-2808N, a sampler 2810, a data cache 2812, and a data port 2814. In one embodiment, the scalable execution unit array can be dynamically scaled according to the computational needs of the workload by enabling or disabling one or more execution units (e.g., any one of execution units 2808A, 2808B, 2808C, 2808D, to 2808N-1 and 2808N). In one embodiment, the included components are interconnected via an interconnect structure linking each component. In some embodiments, thread execution logic 2800 includes one or more connections connected to memory, such as system memory or cache memory, via one or more of instruction cache 2806, data port 2814, sampler 2810, and execution units 2808A-2808N. In some embodiments, each execution unit (e.g., 2808A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2808A-2808N is scalable to include any number of individual execution units.

[0264] In some embodiments, execution units 2808A-2808N are primarily used to execute shader programs. Shader processor 2802 can handle various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2804. In one embodiment, the thread dispatcher includes logic for arbitrating thread initiation requests from the graphics and media pipeline and instantiating the requesting thread on one or more execution units in execution units 2808A-2808N. For example, the geometry pipeline (e.g., 2736 of FIG. 27) can dispatch vertex, tessellation, or geometry shaders to thread execution logic 2800 (FIG. 28) for processing. In some embodiments, thread dispatcher 2804 can also handle thread-generated requests from the execution of an ongoing shader program.

[0265] In some embodiments, execution units 2808A-2808N support instruction sets including native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (e.g., Direct3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the execution units 2808A-2808N is capable of multi-issue single-instruction multiple-data (SIMD) execution, and multi-threaded operations provide an efficient execution environment in the face of high-latency memory access. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread states. Execution is multi-issued per clock cycle to a pipeline capable of performing integer, single-precision and double-precision floating-point operations, SIMD branching functions, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, the dependency logic within execution units 2808A-2808N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution unit can perform operations for pixel shaders, fragment shaders, or another type of shader program that includes different vertex shaders.

[0266] Each execution unit in the execution units 2808A-2808N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels used for instructions. An execution channel is a logic unit used for data element access, masking, and flow control within an instruction. The number of channels can be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) used for a particular graphics processor. In some embodiments, the execution units 2808A-2808N support integer and floating-point data types.

[0267] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements according to their data size. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit compressed data elements (four-word (QW) size data elements), eight separate 32-bit compressed data elements (double-word (DW) size data elements), sixteen separate 16-bit compressed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0268] One or more internal instruction caches (e.g., 2806) are included in thread execution logic 2800 to cache cached thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2812) are included to cache thread data during thread execution. In some embodiments, a sampler 2810 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2810 includes dedicated texture or media sampling functions to process texture or media data during sampling processing before providing sampled data to the execution unit.

[0269] During execution, the graphics and media pipeline sends thread start requests to thread execution logic 2800 via thread creation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2802 is invoked to further compute output data and write the results to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​of various vertex attributes that are interpolated onto the rasterized objects. In some embodiments, the pixel processor logic within shader processor 2802 then executes a pixel or fragment shader program provided by an application programming interface (API). To execute the shader program, shader processor 2802 dispatches threads to execution units (e.g., 2808A) via thread dispatcher 2804. In some embodiments, pixel shader 2802 uses texture sampling logic in sampler 2810 to access texture data in a texture map stored in memory. Arithmetic operations on texture data and input geometry data are used to calculate pixel color data for each geometric fragment, or to discard one or more pixels from further processing.

[0270] In some embodiments, data port 2814 provides a memory access mechanism for thread execution logic 2800 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2814 includes or is coupled to one or more cache memories (e.g., data cache 2812) to cache data for memory access via the data port.

[0271] FIG29 is a block diagram illustrating a graphics processor instruction format 2900 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having multiple instruction formats. Solid lines depict components typically included in the execution unit instructions, while dashed lines include optional components or components included only in a subset of the instructions. In some embodiments, the instruction format 2900 described and illustrated are macro instructions because they are instructions supplied to the execution unit, rather than micro-operations generated by instruction decoding after the instructions are processed.

[0272] In some embodiments, the graphics processor execution unit natively supports instructions of the 128-bit instruction format 2910. Depending on the selected instruction, instruction options, and the number of operands, the 64-bit compressed instruction format 2930 may be available for certain instructions. The native 128-bit instruction format 2910 provides access to all instruction options, while some options and operations are limited in the 64-bit format 2930. The native instructions available in the 64-bit format 2930 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in index field 2913. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions of the 128-bit format 2910.

[0273] For each format, the instruction opcode 2912 defines the operation to be performed by the execution unit. The execution unit executes the instructions in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across the color channels representing texture elements or picture elements. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2914 enables control over certain execution options such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For the 128-bit instruction format 2910, the execute-size field 2916 limits the number of data channels to be executed in parallel. In some embodiments, the execute-size field 2916 is not applicable in the 64-bit compressed instruction format 2930.

[0274] Some execution unit instructions have up to three operands, including two source operands src0 2920 and src1 2922 and a destination 2918. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2924), where the instruction opcode 2912 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0275] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926, which specifies, for example, whether to use a direct register addressing mode or an indirect register addressing mode. When using the direct register addressing mode, the register addresses of one or more operands are directly provided by bits in the instruction.

[0276] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926, which specifies the addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment of the instruction. Some embodiments support access modes including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction can use byte-aligned addresses for both source and destination operands, and in a second mode, the instruction can use 16-byte aligned addresses for all source and destination operands.

[0277] In one embodiment, the addressing mode portion of the access / addressing mode field 2926 determines whether the instruction uses direct or indirect addressing. When using direct register addressing mode, bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0278] In some embodiments, instructions are grouped based on the opcode 2912-bit field to simplify opcode decoding 2940. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2942 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2942 shares five most significant bits (MSBs), where the move (mov) instruction is in the form of 0000xxxxb and the logic instruction is in the form of 0001xxxxb. The flow control instruction group 2944 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2946 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction group 2948 includes component-wise arithmetic instructions (e.g., addition, multiplication (mul)) in the form of 0100xxxxb (e.g., 0x40). Parallel math group 2948 performs arithmetic operations in parallel across data channels. Vector math group 2950 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic such as dot product calculations on vector operands. Exemplary additional graphics pipeline.

[0279] FIG30 is a block diagram of another embodiment of the graphics processor 3000. Elements of FIG30 having the same reference numerals (or names) as elements in any other figure herein may operate or function in a manner similar to, but not limited to, those described elsewhere herein.

[0280] In some embodiments, the graphics processor 3000 includes a graphics pipeline 3020, a media pipeline 3030, a display engine 3040, thread execution logic 3050, and a rendering output pipeline 3070. In some embodiments, the graphics processor 3000 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by commands written to registers of one or more control registers (not shown) or issued to the graphics processor 3000 via a ring interconnect 3002. In some embodiments, the ring interconnect 3002 couples the graphics processor 3000 to other processing elements, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3002 are interpreted by a command streamer 3003, which provides instructions to individual elements of the graphics pipeline 3020 or the media pipeline 3030.

[0281] In some embodiments, the command streamer 3003 instructs the vertex extractor 3005 to operate, the vertex extractor 3005 reads vertex data from memory and executes vertex processing commands provided by the command streamer 3003. In some embodiments, the vertex extractor 3005 provides vertex data to the vertex shader 3007, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex extractor 3005 and the vertex shader 3007 execute vertex processing instructions by dispatching execution threads to execution units 3052A-3052B via the thread dispatcher 3031.

[0282] In some embodiments, execution units 3052A-3052B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 3052A-3052B have an additional L1 cache 3051 specifically for each array or shared between arrays. This cache may be configured as a data cache, an instruction cache, or a single cache, which is divided into different partitions containing data and instructions.

[0283] In some embodiments, the graphics pipeline 3020 includes tessellation elements for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable contour shader 3011 configures the tessellation operation. A programmable domain shader 3017 provides back-end evaluation of the tessellation output. A tessellation 3013 operates in the direction of the contour shader 3011 and includes dedicated logic to generate a set of fine geometric objects based on a coarse geometric model provided as input to the graphics pipeline 3020. In some embodiments, if tessellation is not used, the tessellation elements (e.g., contour shader 3011, tessellation 3013, and domain shader 3017) can be bypassed.

[0284] In some embodiments, the complete geometry object can be processed by the geometry shader 3019 via one or more threads dispatched to execution units 3052A-3052B, or it can proceed directly to the trimmer 3029. In some embodiments, the geometry shader operates on the entire geometry object, rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 3019 receives input from the vertex shader 3007. In some embodiments, the geometry shader 3019 can be programmed via a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0285] Prior to rasterization, clipper 3029 processes vertex data. Clipper 3029 may be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, rasterization and depth testing element 3073 in the render output pipeline 3070 dispatches pixel shaders to convert geometric objects into their pixel-by-pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 3050. In some embodiments, an application may bypass rasterization and depth testing element 3073 and access unrasterized vertex data via streaming output unit 3023.

[0286] The graphics processor 3000 has interconnect buses, interconnect structures, or other interconnect mechanisms that allow data and messages to be transferred between the main components of the processor. In some embodiments, execution units 3052A-3052B and associated caches 3051, texture and media samplers 3054, and texture / sampler cache 3058 are interconnected via data port 3056 to perform memory access and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 3054, caches 3051 and 3058, and execution units 3052A-3052B each have independent memory access paths.

[0287] In some embodiments, the rendering output pipeline 3070 includes rasterization and depth testing elements 3073, which convert vertex-based objects into associated pixel-based representations. In some embodiments, the rasterization logic includes windower / masker units to perform fixed-function triangle and line rasterization. Associated rendering caches 3078 and depth caches 3079 are also available in some embodiments. Pixel manipulation components 3077 perform pixel-based operations on the data; however, in some instances, pixel operations associated with 2D operations (e.g., bit-block image transfer with color mixing) are performed by the 2D engine 3041, or at display time by the display controller 3043 using an overlay display plane. In some embodiments, a shared L3 cache 3075 can be used across all graphics components, allowing data to be shared without using main system memory.

[0288] In some embodiments, the graphics processor media pipeline 3030 includes a media engine 3037 and a video front-end 3034. In some embodiments, the video front-end 3034 receives pipeline commands from a command streamer 3003. In some embodiments, the media pipeline 3030 includes a separate command streamer. In some embodiments, the video front-end 3034 processes the media commands before transmitting them to the media engine 3037. In some embodiments, the media engine 3037 includes spawning functionality to generate threads for dispatch to thread execution logic 3050 via a thread dispatcher 3031.

[0289] In some embodiments, the graphics processor 3000 includes a display engine 3040. In some embodiments, the display engine 3040 is external to the processor 3000 and coupled to the graphics processor via a ring interconnect 3002, or some other interconnect bus or structure. In some embodiments, the display engine 3040 includes a 2D engine 3041 and a display controller 3043. In some embodiments, the display engine 3040 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 3043 is coupled to a display device (not shown), which may be a system-integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0290] In some embodiments, the graphics pipeline 3020 and media pipeline 3030 may be configured to perform operations based on multiple graphics and media interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support for the Open Graphics Library (OpenGL), the Open Computing Language (OpenCL), and / or the Vulkan graphics and computing API is provided, all from the Khronos Group. In some embodiments, support for the Direct3D library from Microsoft Corporation may also be provided. In some embodiments, a combination of these libraries may be supported. Support for the Open Source Computer Vision Library (OpenCV) may also be provided. Future APIs with compatible 3D pipelines will also be supported, if the pipeline of the future API can be mapped to the graphics processor's pipeline. Threaded design of the graphics pipeline.

[0291] FIG31A is a block diagram illustrating a graphics processor command format 3100 according to some embodiments. FIG31B is a block diagram illustrating a graphics processor command sequence 3110 according to an embodiment. Solid lines in FIG31A depict elements typically included in a graphics command, while dashed lines include optional elements or elements only included in a subset of the graphics command. The exemplary graphics processor command format 3100 of FIG31A includes data fields for identifying the target client 3102 of the command, a command opcode 3104, and related data 3106 for the command. Sub-opcodes 3105 and command sizes 3108 are also included in some commands.

[0292] In some embodiments, client 3102 specifies a client unit for processing command data of a graphics device. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 3104 and, if present, reads sub-opcode 3105 to determine the operation to be performed. The client unit uses information in data field 3106 to execute the command. For some commands, an explicit command size 3108 is required to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of double words.

[0293] The flowchart in Figure 31B illustrates an exemplary graphics processor command sequence 3110. In some embodiments, software or firmware of a data processing system characterizing an embodiment of the graphics processor uses a version of the illustrated command sequence to set, execute, and terminate a set of graphics operations. The exemplary command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these particular commands or this command sequence. Furthermore, commands may be issued as a batch of commands in a command sequence, such that the graphics processor will process the command sequence at least partially simultaneously.

[0294] In some embodiments, the graphics processor command sequence 3110 may begin with a pipeline purge command 3112 to complete any currently pending commands for the active graphics pipeline. In some embodiments, the 3D pipeline 3122 and the media pipeline 3124 are not operated simultaneously. Pipeline purge is performed to complete any pending commands for the active graphics pipeline. In response to pipeline purge, the command parser for the graphics processor will pause command processing until the active graphics engine completes its pending operations, and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the rendering cache may be purged to memory. In some embodiments, the pipeline purge command 3112 may be used for pipeline synchronization or before placing the graphics processor in a low-power state.

[0295] In some embodiments, a pipeline selection command 3113 is used when a sequence of commands requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline selection command 3113 is required only once within the execution context before a pipeline command is issued, unless the context is for issuing commands for two pipelines. In some embodiments, a pipeline flushing command 3112 is required immediately before a pipeline switch via the pipeline selection command 3113.

[0296] In some embodiments, pipeline control command 3114 configures the graphics pipeline for operation and is used to program the 3D pipeline 3122 and the media pipeline 3124. In some embodiments, pipeline control command 3114 configures the pipeline state for the pipeline in operation. In one embodiment, pipeline control command 3114 is used for pipeline synchronization and is used to clear data from one or more caches within the pipeline in operation before processing a batch of commands.

[0297] In some embodiments, the return buffer state command 3116 is used to configure a set of return buffers for individual pipeline writes. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers, which write intermediate data into the one or more return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 3116 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0298] The remaining commands in the command sequence differ based on the pipeline used for the operation. Based on pipeline determination 3120, the command sequence is designed for 3D pipeline 3122 starting from 3D pipeline state 3130, or for media pipeline 3124 starting from media pipeline state 3140.

[0299] Commands for configuring 3D pipeline states 3130 include 3D state setting commands for vertex buffer states, vertex element states, constant color states, depth buffer states, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, 3D pipeline state 3130 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0300] In some embodiments, the 3D primitive 3132 command is used to submit 3D primitives for processing by the 3D pipeline. Commands and associated parameters passed to the graphics processor via the 3D primitive 3132 command are forwarded to the vertex extraction function in the graphics pipeline. The vertex extraction function uses the 3D primitive 3132 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 3132 command is used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 3122 dispatches shader execution threads to the graphics processor execution unit.

[0301] In some embodiments, the 3D pipeline 3122 is triggered by executing a command or event 3134. In some embodiments, a register is written to trigger command execution. In some embodiments, execution is triggered by a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered by using pipeline synchronization commands to clear the command sequence from the graphics pipeline. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized, and the pixel engine colors the resulting pixels. Additional commands controlling pixel shading and pixel backend operations may also be included for those operations.

[0302] In some embodiments, the graphics processor command sequence 3110 follows the media pipeline 3124 path when performing media operations. Generally, the specific purpose and manner of programming the media pipeline 3124 depends on the media or computational operation to be performed. Specific media decoding operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may also be bypassed, and media decoding may be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly associated with the rendering of graphics primitives.

[0303] In some embodiments, the media pipeline 3124 is configured in a manner similar to that of the 3D pipeline 3122. A set of commands configuring media pipeline states 3140 is assigned or placed before media object commands 3142 in a command sequence. In some embodiments, the media pipeline state commands 3140 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 3140 also support the use of one or more pointers to "indirect" state elements, which contain a set of state settings.

[0304] In some embodiments, media object command 3142 supplies indicators to media objects for media pipeline processing. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 3142. Once the pipeline states are configured and media object command 3142 is queued, media pipeline 3124 is triggered by executing command 3144 or an equivalent execution event (e.g., register write). The output from media pipeline 3124 can then be post-processed by operations provided by 3D pipeline 3122 or media pipeline 3124. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations. Graphics Software Architecture

[0305] FIG32 illustrates an exemplary graphics software architecture for a data processing system 3200 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 3210, an operating system 3220, and at least one processor 3230. In some embodiments, the processor 3230 includes a graphics processor 3232 and one or more general-purpose processor cores 3234. The graphics application 3210 and the operating system 3220 each execute in the system memory 3250 of the data processing system.

[0306] In some embodiments, the 3D graphics application 3210 includes one or more shader programs, which include shader instructions 3212. The shader language instructions may be a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 3214 in machine language form suitable for execution by a general-purpose processor core 3234. The application also includes graphics objects 3216 defined by vertex data.

[0307] In some embodiments, the operating system 3220 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary Unix-like operating system, or an open-source Unix-like operating system using a variant of the Linux kernel. The operating system 3220 may support graphics APIs 3222, such as the Direct3D API, OpenGL API, or Vulkan API. When using the Direct3D API, the operating system 3220 uses a front-end shader compiler 3224 to compile any shader instructions 3212 in the form of HLSL into a lower-level shader language. This compilation may be just-in-time (JIT) compilation or pre-compilation of the application executable shader. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 3210. In some embodiments, shader instructions 3212 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0308] In some embodiments, the user-mode graphics driver 3226 includes a back-end shader compiler 3227 to translate shader instructions 3212 into a hardware-specific representation. When using the OpenGL API, shader instructions 3212 in the form of the GLSL high-level language are passed to the user-mode graphics driver 3226 for compilation. In some embodiments, the user-mode graphics driver 3226 uses operating system kernel-mode functionality 3228 to communicate with the kernel-mode graphics driver 3229. In some embodiments, the kernel-mode graphics driver 3229 communicates with the graphics processor 3232 to dispatch commands and instructions. IP Core Implementation

[0309] One or more embodiments of at least one example may be implemented by representative program code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions may cause the machine to manufacture the logic to perform the techniques described herein. This representation, referred to as an "IP core," is a reusable logic unit for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities that load the hardware model onto a manufacturing machine that manufactures the integrated circuit. The manufacture of the integrated circuit causes the circuit to perform the operations described in association with any of the embodiments described herein.

[0310] Figure 33 is a block diagram illustrating an IP core development system 3300 that can be used to fabricate integrated circuits to perform operations according to an embodiment. The IP core development system 3300 can be used to generate modular, reusable designs that can be integrated into larger designs or used to construct entire integrated circuits (e.g., SOC integrated circuits). Design facility 3330 can generate software simulations 3310 of the IP core design using high-level programming languages ​​(e.g., C / C++). Software simulations 3310 can be used to design, test, and verify the behavior of the IP core using simulation models 3312. Simulation models 3312 can include functional, behavioral, and / or timing simulations. Register Transfer Level (RTL) designs 3315 can then be built or synthesized from simulation models 3312. RTL designs 3315 are abstractions of the behavior of integrated circuits modeling digital signal flows between hardware registers, including associated logic performed using modeled digital signals. In addition to the RTL design 3315, lower-order designs at the logic or transistor levels can also be built, designed, or synthesized. Therefore, the specific details of the initial design and simulation can differ.

[0311] The RTL design 3315 or its equivalent can be further synthesized by the design facility into a hardware model 3320, which may be in Hardware Description Language (HDL) format or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored in non-volatile memory 3340 (e.g., a hard drive, flash memory, or any non-volatile storage medium) for transfer to a third-party manufacturing facility 3365. Alternatively, the IP core design can be transferred via a wired connection 3350 or a wireless connection 3360 (e.g., via the Internet). The manufacturing facility 3365 can then manufacture an integrated circuit at least partially based on the IP core design. The manufactured integrated circuit can be configured to operate according to at least one embodiment described herein. Exemplary System-on-a-Chip Integrated Circuit

[0312] Figures 34-36 illustrate exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores, according to various embodiments described herein. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0313] FIG34 is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 3400 manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 3400 includes one or more application processors 3405 (e.g., CPU), at least one graphics processor 3410, and may additionally include an image processor 3415 and / or a video processor 3420, any of which may be modular IP cores from the same or more different design facilities. The integrated circuit 3400 includes peripheral or bus logic, including a USB controller 3425, a UART controller 3430, an SPI / SDIO controller 3435, and an I2S / I2C controller 3440. In addition, the integrated circuit may include a display device 3445 coupled to one or more of a high-resolution multimedia interface (HDMI) controller 3450 and a mobile industry processor interface (MIPI) display interface 3455. Storage may be provided by a flash memory subsystem 3460, which includes flash memory and a flash memory controller. A memory interface may be provided via a memory controller 3465 for accessing SDRAM or SRAM memory devices. Some integrated circuitry may also include an embedded security engine 3470.

[0314] FIG35 is a block diagram illustrating an exemplary graphics processor 3510 of a system-on-a-chip integrated circuit that can be manufactured using one or more IP cores according to an embodiment. The graphics processor 3510 may be a variation of the graphics processor 3410 of FIG34. The graphics processor 3510 includes a vertex processor 3505 and one or more fragment processors 3515A-3515N (e.g., 3515A, 3515B, 3515C, 3515D, to 3515N-1, and 3515N). The graphics processor 3510 may execute different shader programs through independent logic, such that the vertex processor 3505 is optimized to perform vertex shader program operations, while the one or more fragment processors 3515A-3515N perform fragment (e.g., pixel) shading operations or pixel shader programs. The vertex processor 3505 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. Fragment processors 3515A-3515N use primitive and vertex data generated by vertex processor 3505 to produce frame buffers that are displayed on a display device. In one embodiment, fragment processors 3515A-3515N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0315] The graphics processor 3510 further includes one or more memory management units (MMUs) 3520A-3520B, caches 3525A-3525B, and circuit interconnects 3530A-3530B. The one or more MMUs 3520A-3520B provide virtual-to-physical address mapping for the graphics processor 3510, including for the vertex processor 3505 and / or fragment processors 3515A-3515N, and can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 3525A-3525B. In one embodiment, one or more MMUs 3520A-3520B can be synchronized with other MMUs within the system, which includes one or more MMUs associated with one or more application processors 3405, image processor 3415, and / or video processor 3420 of FIG. 34, such that each processor 3405-3420 can participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3530A-3530B enable the graphics processor 3510 to interface with other IP cores within the SoC via the SoC's internal bus or via direct connections.

[0316] FIG36 is a block diagram illustrating another exemplary graphics processor 3610 of a system-on-a-chip integrated circuit that can be manufactured using one or more IP cores according to an embodiment. The graphics processor 3610 may be a variation of the graphics processor 3410 of FIG34. The graphics processor 3610 includes one or more MMUs 3520A-3520B, caches 3525A-3525B, and circuit interconnects 3530A-3530B of the integrated circuit 3510 of FIG35.

[0317] The graphics processor 3610 includes one or more shader cores 3615A-3615N (e.g., 3615A, 3615B, 3615C, 3615D, 3615E, 3615F, up to 3615N-1, and 3615N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader code implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shaders present in embodiments and implementations may vary. In addition, the graphics processor 3610 includes an inter-core task manager 3605, which acts as a thread dispatcher to assign execution threads to one or more shader cores 3615A-3615N and tiling units 3618 to accelerate tiling operations for tile-based rendering, where scene rendering operations are subdivided in image space, for example by utilizing local spatial consistency within the scene or optimizing the use of internal caches.

[0318] The following clauses and / or examples relate to specific embodiments or examples thereof. Details in the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with certain included features and others excluded features to suit a variety of different applications. Examples may include objects such as methods, mechanisms for performing the actions of the method, at least one machine-readable medium including instructions which, when executed by a machine, cause the machine to perform the actions of the method, or objects of apparatus or systems according to the embodiments and examples described herein. Various components may be mechanisms for performing the operations or functions.

[0319] The embodiments described herein refer to a special configuration of hardware, such as an application-specific integrated circuit (ASIC), configured to perform certain operations or have predetermined functions. Such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboard, touchscreen, and / or display), and network connectivity. The coupling of the collection of processors to other components is typically via one or more buses and bridges (also known as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on the collection of one or more processors of the electronic device.

[0320] Of course, different combinations of software, firmware, and / or hardware can be used to implement one or more parts of the embodiments. Throughout the detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these embodiments can be practiced without some of these specific details. In some cases, well-known structures and functions have not been described in detail to avoid obscuring the inventive subject matter of the embodiments. Therefore, the scope and spirit of the invention should be determined in accordance with the appended claims. [Simplified Explanation of the Diagram]

[0005] To gain a detailed understanding of the features of the present invention, it can be described in more detail with reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments and should not be considered as limiting the scope of all embodiments.

[0006] [Figure 1] is a block diagram illustrating one or more computer systems configured to implement the embodiments described herein;

[0007] [Figures 2A-2D] illustrate a parallel processor assembly according to an embodiment;

[0008] [Figures 3A-3B] are block diagrams of a graphics multiprocessor according to an embodiment;

[0009] [Figures 4A-4F] show an exemplary structure in which a plurality of GPUs are communicatively coupled to a plurality of multi-core processors;

[0010] [Figure 5] illustrates the graphics processing pipeline according to an embodiment;

[0011] [Figure 6] illustrates a machine learning software stack according to an embodiment;

[0012] [Figure 7] illustrates a highly parallel general-purpose graphics processing unit according to an embodiment;

[0013] [Figure 8] illustrates a multi-GPU computing system according to an embodiment;

[0014] [Figures 9A-9B] illustrate the layers of an exemplary deep neural network;

[0015] [Figure 10] illustrates an exemplary recursive neural network;

[0016] [Figure 11] illustrates the training and deployment of deep neural networks;

[0017] [Figure 12] is a block diagram illustrating distributed learning;

[0018] [Figure 13] illustrates an exemplary inference system single chip (SOC) suitable for performing inference using a trained model;

[0019] [Figure 14] shows the components of a dynamic precision floating-point unit according to an embodiment;

[0020] [Figure 15] provides additional details regarding the dynamic precision floating-point unit according to the embodiment;

[0021] [Figure 16] illustrates thread allocation for a dynamic precision processing system according to an embodiment;

[0022] [Figure 17] illustrates the logic for performing numerical calculations with less-than-required precision according to an embodiment;

[0023] [Figure 18] illustrates loop vectorization for a SIMD unit according to an embodiment;

[0024] [Figure 19] illustrates a thread processing system according to an embodiment;

[0025] [Figure 20] illustrates the logic for allocating threads for computation according to an embodiment;

[0026] [Figure 21] illustrates a deep neural network that can be processed using the computational logic provided by the embodiments described herein;

[0027] [Figure 22] is a flowchart of the logic according to the embodiment, which is used to prevent errors or significant loss of precision when performing low-precision calculations in machine learning;

[0028] [Figure 23] is a block diagram of the processing system according to an embodiment;

[0029] [Figure 24] is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor;

[0030] [Figure 25] is a block diagram of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with a plurality of processing cores;

[0031] [Figure 26] is a block diagram of the graphics processing engine of a graphics processor according to some embodiments;

[0032] [Figure 27] is a block diagram of a graphics processor provided by another embodiment;

[0033] [Figure 28] illustrates thread execution logic, which includes an array of processing elements employed in some embodiments;

[0034] [Figure 29] is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0035] [Figure 30] is a block diagram of a graphics processor according to another embodiment;

[0036] [Figures 31A-31B] illustrate the graphics processor command format and command sequence according to some embodiments;

[0037] [Figure 32] illustrates an exemplary graphical software structure for a data processing system according to some embodiments;

[0038] [Figure 33] is a block diagram showing an IP core development system according to an embodiment;

[0039] [Figure 34] is a block diagram illustrating an exemplary system single-chip integrated circuit according to an embodiment;

[0040] [Figure 35] is a block diagram illustrating another graphics processor according to an embodiment; and

[0041] [Figure 36] is a block diagram illustrating another exemplary graphics processor of a system-on-a-chip integrated circuit according to an embodiment.

Claims

1. A graphics processor, comprising: Memory devices; A compressor is used to compress data to be written to the memory device; The memory device is coupled to a streaming multiprocessor that executes multiple thread groups simultaneously. The streaming multiprocessor includes a single-instruction, multi-threaded (SIMT) architecture and is configured to execute multiple instructions in a multi-threaded manner. The multiple instructions include a first instruction that causes a first part of the streaming multiprocessor to perform floating-point operations on multiple floating-point input operands and a second instruction that causes a second part of the streaming multiprocessor to perform integer operations on multiple integer operands. The first instruction and the second instruction are executed simultaneously. as well as The streaming multiprocessor includes a mixed-precision core for executing the operation of the third instruction of the multi-instruction set. The mixed-precision core executes the first operation of the third instruction with a first precision and the second operation of the third instruction with a second precision.

2. The graphics processor of request item 1, wherein the first operation is performed on 16-bit floating-point input and the second operation is performed on 32-bit floating-point input.

3. The graphics processor as described in request item 2, wherein the 16-bit floating-point input includes half-precision floating-point input.

4. A graphics processor as described in request 2, wherein the first operation is multiplication and the second operation is accumulation.

5. The graphics processor of claim 1, wherein the mixed-precision core is configured to execute the operation of a fourth instruction of the multi-instruction, the fourth instruction causing the mixed-precision core to perform a third operation on an 8-bit integer input and a fourth operation on a 32-bit integer input.

6. The graphics processor of claim 1 also includes a second-order (L2) cache coupled to the compressor.

7. The graphics processor of claim 6, wherein the compressor is used to compress the data to be written to the memory device without distortion.

8. The graphics processor as described in claim 6, wherein the compressor is used to decompress data to be read from the memory device.

9. The graphics processor of claim 8, wherein the memory device is a high-bandwidth memory (HBM) device.

10. A method comprising: The first instruction is decoded by the instruction decoder of the graphics processor into a first decoded instruction, wherein the graphics processor includes a streaming multiprocessor coupled to a memory device and a compressor for compressing data to be written to the memory device, and the streaming multiprocessor includes Single Instruction, Multithreaded (SIMT); the multithreading associated with the first decoded instruction is executed via the streaming multiprocessor, wherein the first decoded instruction causes a first part of the streaming multiprocessor to perform floating-point operations on a plurality of floating-point input operands; the second instruction is decoded by the instruction decoder of the graphics processor into a second decoded instruction; the multithreading associated with the second decoded instruction is executed via the streaming multiprocessor, wherein the second decoded instruction causes a second part of the streaming multiprocessor to perform integer operations on a plurality of integer operands, and the first decoded instruction and the second decoded instruction are executed simultaneously; The third instruction is decoded into a third decoded instruction via the instruction decoder of the graphics processor; and multithreading associated with the third decoded instruction is executed via the mixed-precision core of the streaming multiprocessor, wherein the mixed-precision core performs a first operation of the third decoded instruction using the first bit and a second operation of the third decoded instruction using the second bit.

11. The method of request 10, wherein the third instruction is an integer instruction, the first bit number is associated with a first representable range of integer values, and the second bit number is associated with a second representable range of integer values.

12. The method of claim 11 further includes the first operation of performing the third decoding instruction on an 8-bit integer input, and the second operation of performing the third decoding instruction on a 32-bit integer input.

13. The method of request 10, wherein the third instruction is a floating-point instruction, the first bit is associated with a first floating-point precision, and the second bit is associated with a second floating-point precision.

14. The method of claim 13 further includes performing the first operation of the third decoding instruction on a 16-bit floating-point input and the second operation of the third decoding instruction on a 32-bit floating-point input.

15. The method of request item 14, wherein the 16-bit floating-point input includes half-precision floating-point input.

16. The method of request 14, wherein the first operation of the third decoding instruction is multiplication, and the second operation of the third decoding instruction is accumulation.

17. The method of claim 10 further includes compressing the data before writing the data associated with the first instruction, second instruction, or third instruction into the memory device.

18. The method of claim 17 further includes compressing the data without distortion before writing the data associated with the first instruction, second instruction or third instruction into the memory device.

19. The method of claim 10 further includes decompressing the data after reading the data associated with the first instruction, the second instruction, or the third instruction from the memory device.

20. A graphics processing system, comprising: System interface coupled to interconnect structure; A graphics memory device coupled to the interconnect structure; A compressor is used to compress the data to be written to the graphics memory device; The streaming multiprocessor coupled to the graphics memory device executes multiple thread groups simultaneously. The streaming multiprocessor includes a single instruction, multithreaded (SIMT) architecture and is configured to execute multiple instructions in a multithreaded manner. The multiple instructions include a first instruction for causing a first part of the streaming multiprocessor to perform floating-point operations on multiple floating-point input operands and a second instruction for causing a second part of the streaming multiprocessor to perform integer operations on multiple integer operands. The first instruction and the second instruction are executed simultaneously. as well as The streaming multiprocessor includes a mixed-precision core for executing the operation of the third instruction of the multi-instruction set. The mixed-precision core executes the first operation of the third instruction with a first precision or range and executes the second operation of the third instruction with a second precision or range.

21. The graphics processing system of claim 20, wherein the graphics memory device is a high-bandwidth memory (HBM) device.

22. The graphics processing system of claim 20, wherein the third instruction is an integer instruction, and the mixed-precision core is configured to perform the first operation with a first bit to represent the first range and to perform the second operation with a second bit to represent the second range, wherein the first range and the second range are representable ranges of integer values.

23. The graphics processing system of claim 22, wherein the mixed-precision core is configured to perform the first operation of the third instruction on an 8-bit integer input and the second operation of the third instruction on a 32-bit integer input.

24. The graphics processing system of claim 20, wherein the third instruction is a floating-point instruction, and the mixed-precision core is configured to perform the first operation with a first bit to achieve the first precision and to perform the second operation with a second bit to achieve the second precision, wherein the first precision and the second precision are floating-point precision.

25. The graphics processing system of claim 24, wherein the mixed-precision core is configured to perform the first operation of the third instruction on 16-bit floating-point input and the second operation of the third instruction on 32-bit floating-point input.

26. The graphics processing system of claim 25, wherein the 16-bit floating-point input includes half-precision floating-point input.

27. The graphics processing system of claim 26, wherein the first operation of the third instruction is multiplication, and the second operation of the third instruction is accumulation.

28. The graphics processing system of claim 20 further includes a second-order (L2) cache coupled to the compressor.

29. The graphics processing system of claim 28, wherein the compressor is used to compress the data to be written to the graphics memory device without distortion.

30. The graphics processing system of claim 28, wherein the compressor is used to decompress data to be read from the graphics memory device.

31. A machine-readable medium storing program code, which, when executed, causes the machine to perform the method of any one of claims 10 to 19.

32. An apparatus comprising a mechanism for performing the method as claimed in any one of claims 10 to 19.

Images