Interconnection structure

Abstract

An interconnect structure includes a dielectric layer, a conductive feature, a conductive layer, a capping layer, a support layer and an etch stop layer. The conductive feature is disposed in the dielectric layer. A first portion of the conductive layer is disposed over the first conductive feature, and a second portion of the conductive layer is disposed over the dielectric layer. A first portion of the capping layer is in contact with the first portion of the conductive layer, a second portion of the capping layer is in contact with the second portion of the conductive layer, and a third portion of the capping layer is in contact with the dielectric layer. An air gap is defined by the support layer and the capping layer. The etch stop layer is disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer.

Description

[Technical Field]

[0001] The present invention relates to an interconnect structure, and more particularly to an interconnect structure and a method thereof, which can reduce the risk of leakage current between wires and improve the electrical properties of the obtained interconnect structure. [Previous Technology]

[0002] As the semiconductor industry introduces a new generation of integrated circuits (ICs) with higher performance and more functions, the density of components forming ICs has increased, while the size, dimensions, and spacing of components or between components have decreased. In the past, this reduction in size, dimensions, and spacing was limited only by the ability of optical lithography to define structures; the geometry of devices with smaller dimensions has created new constraints. For example, for any two adjacent conductive components, as the distance between conductive components decreases, the resulting capacitance (a function of the dielectric constant (k value) of the insulating material divided by the distance between the conductive components) increases. This increased capacitance leads to increased capacitive coupling between conductive components, increased power consumption, and an increased resistive-capacitive (RC) time constant.

[0003] Therefore, there is a need in the art to provide an improved device that can solve the above problems. [Summary of the Invention]

[0004] Some embodiments of the present invention provide an interconnect structure. This interconnect structure includes a dielectric layer, a first conductive component, a conductive layer, a capping layer, a support layer, and an etch stop layer. The first conductive component is disposed in the dielectric layer. The conductive layer includes a first portion and a second portion. The first portion of the conductive layer is disposed above the first conductive component, and the second portion of the conductive layer is disposed above the dielectric layer. The capping layer includes a first portion, a second portion opposite to the first portion, and a third portion connecting the first and second portions. The first portion of the capping layer contacts the first portion of the conductive layer, the second portion of the capping layer contacts the second portion of the conductive layer, and the third portion of the capping layer contacts the dielectric layer. The support layer contacts the first and second portions of the capping layer. An air gap is defined by the support layer, the first portion of the capping layer, the second portion of the capping layer, and the third portion of the capping layer. The etch stop layer is disposed above the second portion of the conductive layer, the second portion of the capping layer, and the support layer.

[0005] Some embodiments of the present invention provide an interconnect structure. This interconnect structure includes a dielectric layer, a first conductive component, a conductive layer, a capping layer, a support layer, a dielectric filler, and a metal oxide layer. The first conductive component is disposed in the dielectric layer. The conductive layer is disposed above the first conductive component and the dielectric layer. The capping layer is embedded in the conductive layer. The sidewalls of the capping layer are in contact with the conductive layer, and a bottom surface of the capping layer is in contact with the dielectric layer. The support layer is in contact with the capping layer. An air gap is defined by the support layer and the capping layer. The dielectric filler is disposed above the air gap and in contact with the support layer. The metal oxide layer is disposed above the dielectric filler, the support layer, and the capping layer.

[0006] Some embodiments of the present invention provide a method for forming an interconnect structure. This method includes forming a conductive layer over a dielectric layer, forming one or more openings in the conductive layer to expose portions of the dielectric surface of the dielectric layer and portions of the conductive surface of the conductive layer, wherein the one or more openings divide the conductive layer into one or more portions, forming a capping layer on the exposed portions of the dielectric surface of the dielectric layer and the conductive surface of the conductive layer, forming a sacrificial layer in the one or more openings to recess the sacrificial layer, forming a support layer on each recessed sacrificial layer in the one or more openings, removing the sacrificial layer to form an air gap in each of the one or more openings, forming a dielectric filler on the support layer to recess the conductive layer, forming an etch stop layer on the recessed conductive layer, capping layer, support layer and dielectric filler, forming a dielectric material on the etch stop layer, forming a contact opening through the dielectric material and the etch stop layer to expose the top surface of a portion of the conductive layer, and forming a conductive component in the contact opening.

Implementation Method

[0008] The following provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions a first component formed above or on a second component, it may include embodiments where the first and second components are in direct contact, or it may include embodiments where an additional component is formed between the first and second components, such that the first and second feature components are not in direct contact. In addition, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatial terms such as "below," "under," "lower," "above," "above," "on," "top," "higher," and other similar terms may be used here to describe the relationship between one of the elements or components shown in the figure and other elements or components. These spatial terms include not only the orientation shown in the figure but also different orientations of the device in use or operation. If the device can be rotated to other orientations (rotated 90 degrees or other orientations), the spatial relative descriptions used here can also be interpreted according to the orientation after rotation.

[0010] Figures 1A to 1T illustrate exemplary sequential processes for manufacturing a semiconductor device structure 100 according to some embodiments. It should be understood that some additional steps may be performed before, during, and after the processes shown in Figures 1A to 1T, and for other embodiments of the processes, some steps described below may be replaced or eliminated. The order of steps / processes may also be interchanged.

[0011] Figure 1A is a perspective view of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1A, the semiconductor device structure 100 includes a substrate 502 on which at least a plurality of conductive features are formed (one conductive feature 106 is shown in Figure 1A). The conductive feature 106 is formed in a dielectric material 104. One or more devices (not shown), such as transistors, diodes, image sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices, may be formed between the substrate 502 and the conductive feature 106.

[0012] FIG. Line AA of FIG. As shown in FIGS. Substrate 502 may be a semiconductor base. In some embodiments, substrate 502 includes at least one single crystal semiconductor layer on the surface of substrate 502 . Substrate 502 may include single-crystal semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide, gallium (gallium) antimonide, GaSb, indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (gaSbP), gallium arsenide (gaSbP), gallium arsenide (gaSbP) phosphide, InP). For example, base 502 is made of silicon. In some embodiments, the substrate 502 is an insulating layer overlaid with a silicon-on-insulator (SOI) substrate comprising an insulating layer (not shown) disposed between two silicon layers. In one embodiment, the insulating layer is an oxygen-containing material, such as an oxide.

[0013] The substrate 502 may include one or more buffer layers (not shown) on the surface of the substrate 502 . The buffer layer can act as a gradual change of the lattice constant from the lattice constant at the base to the lattice constant at the source / draft region. The buffer layer may be formed from epicrystal-grown single-crystal semiconductor materials, such as, but not limited to, silicon, zirconia, zinc tin (GeSn), SiGe, gallium arsenide (GaAs), gallium arsenide (InSb), gallium phosphide (GaP), gallium phosphide (GaSb), aluminum arsenide (InAlAs) ), gallium arsenide (InGaAs), gallium phosphide (GaSbP), gallium arsenic arsenide (GaAsSb), gallium nitride (GaN), gallium phosphide (GaP) and indium phosphide (InP). In one embodiment, substrate 502 includes SiGe buffer layers on which epitaxial grows on silicon substrate 502 . The zinc concentration of the silicon zinc buffer layer can be increased from 30 atom percent zinc in the bottommost buffer layer to 70 atom percent zinc in the top buffer layer.

[0014] Substrate 502 may include various regions already suitably doped with impurities (e.g., p-type or n-type impurities). The doping is, for example, boron for n-type fin field effect transistors (FinFET) and phosphorus for p-type fin field effect transistors.

[0015] As described above, device 602 can be any suitable device, such as a transistor, diode, image sensor, resistor, capacitor, inductor, memory cell, or a combination thereof. In some embodiments, device 602 is a transistor, such as a planar field-effect transistor (FET), a FinFET, nanosheet transistors, or other suitable transistors. Nanosheet transistors can include nanowire transistors, gate-all-around (GAA), multi-bridge channel (MBC) transistors, or any transistor having gate electrodes surrounding the channel. An example of a device 602 formed between substrate 502 and conductive component 106 is a FinFET, shown in Figures 1B and 1C. Device 602 includes a source / drain (S / D) region 604 and a gate stack 606. Each gate stack 606 may be disposed between a source / drain region 604 serving as a source region and a source / drain region 604 serving as a drain region. For example, each gate stack 606 may extend along the Y-axis between a plurality of source regions 604 serving as source regions and a plurality of source regions 604 serving as drain regions. As shown in Figure 1B, two gate stacks 606 are formed on a substrate 502. In some embodiments, more than two gate stacks 606 are formed on a substrate 502. A channel region 608 is formed between the source / drain regions 604 serving as source regions and the source / drain regions 604 serving as drain regions.

[0016] The source / drain region 604 may include a semiconductor material, such as silicon or germanium (Ge), a III-V compound semiconductor, a II-VI compound semiconductor, or other suitable semiconductor materials. Exemplary source / drain regions 604 may include, but are not limited to, germanium, silicon-germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), silicon phosphide (SiP), indium arsenide (InAs), aluminum arsenide (AlAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium antimonide (GaSb), aluminum phosphide (AlP), gallium phosphide (GaP), or the like. The source / drain region 604 may include p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants including combinations of the foregoing. The source / drain region 604 can be formed using epitaxial growth methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The channel regions 608 can include one or more semiconductor materials, such as silicon, germanium, germanium-tin (GeSn), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony phosphide (GaAsSb), gallium nitride (GaN), gallium phosphide (GaP), or indium phosphide (InP). In some embodiments, the channel regions 608 include the same semiconductor material as the substrate 502. In some embodiments, the device 602 is a FinFET, and the channel regions 608 are a plurality of fins disposed below the gate stack 606. In some embodiments, device 602 is a nanosheet transistor, and channel region 608 is surrounded by gate stack 606.

[0017] Each gate stack 606 includes a gate electrode layer 610 disposed above (or around) the channel region 608 of the nanosheet transistor. The gate electrode layer 610 may be a metallic material, such as tungsten, cobalt, aluminum, ruthenium, copper, multiple layers of the aforementioned materials, or similar materials, and may be deposited by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam deposition (MBD), physical vapor deposition (PVD), or any suitable deposition technique. Each gate stack 606 may include an interfacial dielectric layer 612, a gate dielectric layer 614 disposed on the interfacial dielectric layer 612, and one or more conformal layers 616 disposed on the gate dielectric layer 614. The gate electrode layer 610 may be disposed on one or more conformal layers 616. The interface dielectric layer 612 may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, or multiple layers of the aforementioned materials, and may be formed by any suitable deposition method, such as chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The gate dielectric layer 614 may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, a dielectric material with a high dielectric constant (k) greater than about 7.0, or multiple layers of the aforementioned materials. The gate dielectric layer 614 may be formed by any suitable method, such as chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The aforementioned one or more conformal layers 616 may include one or more barrier layers and / or capping layers, such as nitrogen-containing materials, such as tantalum nitride (TaN), titanium nitride (TiN), or the like. The aforementioned one or more conformal layers 616 may also include one or more work function layers, such as aluminum titanium carbide, aluminum titanium oxide, aluminum titanium nitride, or the like. The term "conformal" as used herein may be used to describe a layer having substantially the same thickness over different regions.One or more of the aforementioned conformal layers 616 can be deposited by atomic layer deposition (ALD), plasma-assisted chemical vapor deposition (PECVD), molecular beam deposition (MBD), or any suitable deposition technique.

[0018] Gate spacers 618 are formed along the sidewalls of the gate stack 606 (e.g., the sidewalls of the gate dielectric layer 614). Gate spacers 618 may include silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, multiple layers of the aforementioned materials, or combinations thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition techniques.

[0019] A portion of the gate stack 606 and gate spacer 618 may be formed on isolation regions 603. Isolation regions 603 are formed on substrate 502. Isolation regions 603 may include an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination of the foregoing. The insulating material may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one example, isolation regions 603 comprise silicon oxide formed by a flowable chemical vapor deposition (FCVD) process.

[0020] A contact etch stop layer (CESL) 624 is formed on a portion of the source / drain region 604 and the isolation region 603, and a first interlayer dielectric (ILD) 626 is formed on the contact etch stop layer (CESL) 624. The contact etch stop layer 624 can provide the function of stopping an etch process when an opening is formed in the first interlayer dielectric 626. The contact etch stop layer 624 can be conformally deposited on the surfaces of the source / drain region 604 and the isolation region 603. The contact etch stop layer 624 can include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, the like, or combinations thereof, and can be deposited by chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any suitable deposition technique. The first interlayer dielectric 626 may include tetraethoxysilane (TEOS) oxide, undoped silicate glass, or materials such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), organosilicate glass (OSG), silicon oxide (SiOC) doped silicon oxide, and / or any suitable low dielectric constant dielectric material (e.g., materials with a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, chemical vapor deposition (CVD), flow chemical vapor deposition (FCVD), plasma-assisted chemical vapor deposition (PECVD), physical vapor deposition (PVD), or any suitable deposition technique.

[0021] A silicide layer 620 is formed on at least a portion of each source / drain region 604, as shown in Figures 1B and 1C. The silicide layer 620 may comprise one or more materials selected from tungsten silicide (WSi), cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi), molybdenum silicide (MoSi), and tantalum silicide (TaSi). In some embodiments, the silicide layer 620 comprises a metal or metal alloy silicide, and the aforementioned metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof. A conductive contact 622 is provided on each silicide layer 620. The conductive contact 622 may comprise one or more of the following materials: ruthenium (Ru), molybdenum (Mo), cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), titanium nitride (TiN), or tantalum nitride (TaN). The conductive contact 622 may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition (PVD). The silicate layer 620 and the conductive contact 622 may be formed by first forming openings in the first interlayer dielectric 626 and the contact etch stop layer 624 to expose at least a portion of the source / drain region 604, then forming the silicate layer 620 on the exposed portion of the source / drain region 604, and finally forming the conductive contact 622 on the silicate layer 620.

[0022] As shown in Figures 1B and 1C, a dielectric material 104 may be formed over the device 602. This dielectric material 104 may include an etch stop layer. Conductive components 106 are formed in the dielectric material 104, and each conductive component 106 may contact a corresponding conductive contact 622.

[0023] Figures 1D-1T are cross-sectional side views of various stages of fabricating the interconnect structure 100 along line AA of Figure 1A according to some embodiments. The interconnect structure 100 can be formed on various devices of a semiconductor structure. For example, the interconnect structure 100 can be formed on one or more devices, such as transistors, diodes, image sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices. In some embodiments, the interconnect structure 100 can be formed on a transistor, such as a nanostructure field-effect transistor having multiple channels enclosed by a gate electrode layer.

[0024] As shown in Figure 1D, the interconnect structure 100 includes a layer 102, which may be an interlayer dielectric layer or an intermetallic dielectric (IMD) layer. Layer 102 includes a dielectric layer 104, one or more conductive components 106 (only one shown) disposed in the dielectric layer 104, and a selective capping layer 108 disposed on each conductive component 106. The dielectric layer 104 may include an insulating material made of an oxygen-containing material, such as silicon oxide or fluorosilicate glass (FSG); made of a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), silicon oxynitride (SiOCN), or silicon carbonitride (SiCN); made of a dielectric material with a low dielectric constant (e.g., a material whose dielectric constant is lower than that of silicon oxide); or made of any suitable dielectric material. In some embodiments, the dielectric layer 104 includes silicon oxide. The dielectric layer 104 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, or other suitable processes. The conductive component 106 and the capping layer 108 can each comprise a conductive material, such as copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), aluminum (Al), the aforementioned alloys, or other suitable materials. In some embodiments, the conductive component 106 and the capping layer 108 each comprise a metal. The conductive component 106 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. The capping layer 108 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the thickness of the conductive component 106 along the z-axis is in the range of approximately 50 angstroms to approximately 500 angstroms, and the thickness of the cover layer 108 is in the range of approximately 2 angstroms to approximately 50 angstroms. The conductive component 106 may be electrically connected to conductive contacts beneath the interconnect structure 100.

[0025] As shown in Figure 1E, a glue layer 110, a conductive layer 112, and a hard mask 114 are formed over layer 102. In some embodiments, the glue layer 110 is formed on layer 102, the conductive layer 112 is formed on the glue layer 110, and the hard mask 114 is formed on the conductive layer 112. In some embodiments, the glue layer 110 is absent, and the conductive layer 112 is formed on layer 102. The glue layer 110 may include a nitride, such as a metal nitride, and may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the glue layer 110 includes titanium nitride (TiN), tantalum nitride (TaN), tin nitride (WN), or other suitable metal nitrides. The thickness of the glue layer 110 may be in the range of approximately 2 angstroms to approximately 100 angstroms. The adhesive layer 110 provides adhesion between the conductive layer 112 and the conductive component 106 and the capping layer 108. The conductive layer 112 may comprise the same material as the conductive component 106 and may be formed using the same process as the conductive component 106. The conductive layer 112 may have the same thickness along the z-axis as the conductive component 106. The hard mask 114 may comprise titanium nitride (TiN), tantalum nitride (TaN), tin nitride (WN), or other suitable metal nitrides and may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. The thickness of the hard mask 114 may range from approximately 2 angstroms to approximately 100 angstroms.

[0026] As shown in Figure 1F, after forming the adhesive layer 110, the conductive layer 112, and the hard mask 114, an opening 116 is formed in the hard mask 114, the conductive layer 112, and the adhesive layer 110. The opening 116 can be formed by first patterning the hard mask 114, and then transferring the pattern of the hard mask 114 to the conductive layer 112 and the adhesive layer 110 to form the opening 116. The opening 116 can also be formed by any suitable process, such as wet etching, dry etching, or a combination of the aforementioned etching processes. In some embodiments, the opening 116 is formed by one or more etching processes. The opening 116 divides the conductive layer 112 into one or more portions, for example, into multiple portions.

[0027] Figure 1F shows an ideal case where the sidewalls of opening 116 are vertical. It is understood that in actual operation, the sidewalls of opening 116 may not be vertical, and the sidewalls of opening 116 may have a profile angle between approximately 70 and 90 degrees.

[0028] As shown in Figure 1G, a capping layer 118 is then formed on the exposed surfaces of portions of the rigid mask 114, conductive layer 112, adhesive layer 110, and dielectric layer 104. The capping layer 118 may at least provide adhesion to the rigid mask 114, conductive layer 112, and adhesive layer 110. The capping layer 118 may be made of a dielectric material. In some embodiments, the capping layer 118 includes silicon carbide (SiCO), silicon carbide (SiCN), silicon nitride (SiN), silicon carbide (SiCON), silicon oxide (SiOx), silicon carbide (SiC), silicon oxynitride (SiON), or other suitable dielectric materials. The capping layer 118 can be formed by any suitable process, such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted atomic layer deposition (PEALD), or any suitable conformal process. The term "conformal" as used herein can be used simply to describe a layer having substantially the same thickness in different regions. The capping layer 118 can have a thickness ranging from approximately 5 angstroms to approximately 200 angstroms.

[0029] As shown in Figure 1H, after forming the capping layer 118, a sacrificial layer 120 is formed in the opening 116 (Figure 1G) and on the capping layer 118. The sacrificial layer 120 may comprise a polymer, such as an organic layer having carbon (C), oxygen (O), nitrogen (N), and / or hydrogen (H). In some embodiments, the sacrificial layer 120 is a degradable gap-fill material, such as polyurea. Polyurea can be synthesized by reacting diisocyanate and diamine, as shown below.

[0030] The sacrificial layer 120 can be formed by any suitable process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular layer deposition (MLD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted atomic layer deposition (PEALD), or spin coating.

[0031] As shown in Figure 1I, the sacrificial layer 120 is recessed to a level below the top surface 121 of the conductive layer 112. The recess of the sacrificial layer 120 can be achieved by any suitable process, such as thermal baking, UV curing, etch-back (e.g., plasma etching), or any combination thereof. In some embodiments, a UV curing process can be used to recess the sacrificial layer 120 by exposing it to UV energy having an energy density in the range of approximately 10 mJ / cm² to approximately 100 J / cm². The recess of the sacrificial layer 120 can partially open the opening 116. In some embodiments, the recess of the sacrificial layer 120 can expose at least a portion of the capping layer 118 in the opening 116. The remaining sacrificial layer 120 can have a height H1 ranging from approximately 10 angstroms to approximately 1000 angstroms.

[0032] As shown in Figure 1J, a support layer 122 is formed on the exposed surface of the interconnect structure 100. In some embodiments, the support layer 122 is formed on the sacrificial layer 120 and the capping layer 118. The support layer 122 can provide the mechanical strength required to maintain an air gap (e.g., air gap 124 in Figure 1K) subsequently formed between the support layer 122 and the capping layer 118. The support layer 122 may include silicon (Si), oxygen (O), nitrogen (N), or any combination thereof. In some embodiments, the support layer 122 includes silicon oxide (SiOx), silicon carbide (SiCO), silicon oxynitride (SiON), silicon carbide (SiCN), or silicon oxynitride (SiCON). The support layer 122 may be porous to allow ultraviolet energy, thermal energy, or plasma to reach the sacrificial layer 120 disposed beneath the support layer 122. The support layer 122 may have a thickness ranging from approximately 2 angstroms to approximately 100 angstroms. The support layer 122 can be formed by any suitable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-assisted chemical vapor deposition (PECVD), or plasma-assisted atomic layer deposition (PEALD). In some embodiments, the support layer 122 is a conformal layer formed by atomic layer deposition (ALD) or plasma-assisted atomic layer deposition (PEALD).

[0033] As shown in Figure 1K, the sacrificial layer 120 is removed, forming an air gap 124 in each opening 116 between the support layer 122 and the cover layer 118. The removal of the sacrificial layer 120 may be due to degradation or decomposition of the sacrificial layer 120. Decomposition or degradation of the sacrificial layer 120 can be performed by any suitable process, such as thermal baking and / or UV curing. In some embodiments, a UV curing process is performed to remove the sacrificial layer 120. UV energy can penetrate the porous support layer 122 to reach and remove the sacrificial layer 120. The UV energy may have an energy density ranging from approximately 10 mJ / cm² to approximately 100 J / cm². The removal of the sacrificial layer 120 does not substantially affect the other layers of the interconnect structure 100. The air gap 124 may have a height H2 ranging from approximately 10 angstroms to approximately 1000 angstroms, which is substantially the same as the height H1 of the sacrificial layer 120 shown in Figure 1I. Air gap 124 can reduce capacitive coupling between adjacent portions of conductive layer 112. If the height H2 is less than approximately 10 angstroms, air gap 124 may not reduce capacitive coupling between adjacent portions of conductive layer 112. On the other hand, if the height H2 is greater than approximately 1000 angstroms, support layer 122 may not have sufficient contact with capping layer 118 to prevent material subsequently formed on support layer 122 from collapsing into air gap 124.

[0034] As shown in Figure 1L, a dielectric fill 126 is formed on the support layer 122. The dielectric fill 126 can improve the isolation of the air gap 124 and provide adhesion between the support layer 122 and the subsequently formed etch stop layer. The dielectric fill 126 can be a silicon-containing material, such as silicon carbide (SiCO), silicon carbide (SiCN), silicon nitride (SiN), silicon oxynitride (SiCON), silicon oxide (SiOx), silicon carbide (SiC), or silicon oxynitride (SiON). In some embodiments, the dielectric fill 126 comprises a low dielectric constant dielectric material, such as SiCOH, with a dielectric constant (k) in the range of about 2 to about 3.6. The low dielectric constant dielectric material may have a porosity in the range of about 0.1% to about 40%. The dielectric filler 126 may partially fill the opening 116 (Figure 1K) and be located above the rigid mask 114, as shown in Figure 1L. The dielectric filler 126 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted atomic layer deposition (PEALD), or other suitable processes.

[0035] As shown in Figure 1M, a planarization process can be performed to remove a portion of the dielectric filler 126 formed above the rigid mask 114. A portion of the capping layer 118 and support layer 122 disposed above the rigid mask 114 are also removed due to this planarization process. This planarization process can be any suitable process, such as chemical-mechanical polishing (CMP). As a result of the planarization process, the top surface 128 of the rigid mask 114 can be substantially coplanar with the top surface 130 of the dielectric filler 126. The remaining dielectric filler 126 can have a thickness ranging from approximately 2 angstroms to approximately 1000 angstroms. Together, the support layer 122 and the dielectric filler 126 can prevent materials introduced during the planarization process, such as slurry, from entering the air gap 124.

[0036] As shown in Figure 1N, the hard mask 114 is removed by an etching process. The etching process may include one or more selective etching processes, such as dry etching, wet etching, or a combination thereof, to selectively remove the hard mask 114. After the hard mask 114 is removed, the top surface 121 of the conductive layer 112 may be substantially lower than the top surface 130 of the dielectric filler 126, and the capping layer 118 and the support layer 122 may each have a top surface substantially coplanar with the top surface 130 of the dielectric filler 126.

[0037] As shown in Figure 10, an etch stop layer 132 is formed on the exposed surfaces of the conductive layer 112, the capping layer 118, the support layer 122, and the dielectric filler 126. The etch stop layer 132 can be a single layer or a multilayer structure. The etch stop layer 132 can include metal oxides such as aluminum (Al), zirconium (Zr), yttrium (Y), hafnium (Hf) or other suitable metal oxides, or silicon-containing materials such as silicon carbide (SiCO), silicon carbide (SiCN), silicon nitride (SiN), silicon oxynitride (SiCON), silicon oxide (SiOx), silicon carbide (SiC), or silicon oxynitride (SiON) or similar materials. The etch stop layer 132 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, or any suitable deposition process. The etch stop layer 132 can have a thickness ranging from about 1 angstrom to about 100 angstroms.

[0038] As shown in Figure 1P, a dielectric material 134 is formed on the etch stop layer 132, and a hard mask 136 is formed on the dielectric material 134. The dielectric material 134 may include the same material as the dielectric filler 126 and can be formed by the same process as the dielectric filler 126. The etch stop layer 132 and the dielectric material 134 may have different etch selectivity. The hard mask 136 may include the same material as the hard mask 114 and can be formed by the same process as the hard mask 114.

[0039] As shown in Figure 1Q, contact openings 138 and 140 are formed in the hard mask 136 and the dielectric material 134. Contact openings 138 and 140 can be formed by any suitable etching / patterning process, such as a dual-damascene process. For example, contact opening 138 can be formed by first patterning the hard mask 136 and transferring the pattern to a portion of the dielectric material 134. Contact opening 140 is then formed by removing the dielectric material 134 from a portion of the bottom of contact opening 138. Therefore, contact opening 140 has a smaller dimension than contact opening 138. In some embodiments, contact opening 140 is a via, and contact opening 138 is a trench. When the contact opening 140 is formed, the etching process may be stopped by the etching stop layer 132 because the etching stop layer 132 and the dielectric material 134 have different etching selectivity. The conductive layer 112, the cover layer 118, the support layer 122 and the dielectric filler 126 located below the contact opening 140 are protected by the etching stop layer 132 to prevent damage caused by over-etching.

[0040] As shown in Figure 1R, an etching process can be performed to remove a portion of the etch stop layer 132 exposed by the contact opening 140, such that the contact opening 140 exposes at least a portion of the top surface 121 of the conductive layer 112. In some embodiments, the etch stop layer 132 can be removed by a wet etching process or a dry etching process. In some embodiments, the cover layer 118, the support layer 122, and the etch stop layer 132 can be formed of the same material. When the etching process is performed to remove a portion of the etch stop layer 132, portions of the cover layer 118 and the support layer 122 can also be removed.

[0041] In most embodiments, the contact opening 140 is aligned with a portion of the conductive layer 112, for example, the contact opening 140 is aligned with a portion of the conductive layer 112 disposed between two adjacent air gaps 124. However, in some embodiments, the contact opening 140 may be slightly misaligned with a portion of the conductive layer 112, as shown in Figure 1R. Since the etch stop layer 132 and the dielectric filler 126 have different etch selectivity, the dielectric filler 126 can be retained when the etch stop layer 132 is removed.

[0042] The misalignment of the via is referred to as an edge placement error (EPE). If the etch stop layer 132 is not present, since the dielectric material 134 and the dielectric filler 126 can comprise the same material, the contact opening 140 can also be formed in the dielectric filler 126. As a result, subsequently formed conductive components may be formed in the dielectric filler 126 and between adjacent portions of the conductive layer 112, which may lead to line-to-line leakage. Due to the leakage current between the wires, reliability issues may arise, such as poor breakdown voltage or time-related dielectric breakdown. Since the etch stop layer 132 is disposed on the dielectric filler 126, the etching process used to form the contact opening 140 will not substantially affect the etch stop layer 132, because the dielectric material 134 and the etch stop layer 132 have different etch selectivity. Therefore, by setting the etch stop layer 132, the risk of leakage current between conductors can be reduced when edge setting error (EPE) occurs.

[0043] As shown in Figure 1S, a barrier layer 142 and a conductive feature 144 are formed in the contact openings 138 and 140. The barrier layer 142 may include cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium silicon (TiSi), cobalt silicon (CoSi), nickel silicon (NiSi), copper (Cu), tantalum nitride (TaN), nickel (Ni), or TiSiNi, and can be formed by any suitable process, such as physical vapor deposition (PVD), atomic layer deposition (ALD), or plasma-assisted chemical vapor deposition (PECVD). In some embodiments, the barrier layer 142 may be a conformal layer formed, for example, by a conformal process such as atomic layer deposition (ALD), on or in contact with the exposed surfaces of the hard mask 136, dielectric material 134, etch stop layer 132, support layer 122, capping layer 118, and conductive layer 112. The conductive component 144 may include a conductive material, such as a metal. For example, the conductive component 144 may include copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), molybdenum (Mo), the aforementioned alloys, or other suitable materials. The conductive component 144 can be formed on the barrier layer 142 by any suitable process, such as electrochemical plating (ECP), physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma-assisted chemical vapor deposition (PECVD).

[0044] As shown in Figure 1T, a planarization process is performed to remove a portion of the barrier layer 142 and a portion of the conductive component 144 disposed above the rigid mask 136, and the rigid mask 136 can also be removed by a planarization process. The aforementioned planarization process can be any suitable process, such as a chemical mechanical polishing (CMP) process. After the planarization process is completed, the top surfaces of the dielectric material 134, the barrier layer 142, and the conductive component 144 are substantially coplanar.

[0045] Subsequently, a cap layer 146 may be selectively formed on the conductive component 144 and the barrier layer 142. The metal surfaces of the conductive component 144 and the barrier layer 142 may promote selective growth of the cap layer 146 on the conductive component 144 and the barrier layer 142, rather than on the dielectric material 134. Alternatively, the cap layer 146 may comprise a conductive material, such as copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), aluminum (Al), alloys thereof, or other suitable materials. In some embodiments, the cap layer 146 comprises a metal. The cap layer 146 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. The capping layer 146 may have a thickness ranging from about 2 angstroms to about 50 angstroms.

[0046] As shown in Figure 1T, the interconnect structure 100 includes a dielectric layer 104, a conductive component 106 disposed in the dielectric layer 104, a conductive layer 112 including a first portion and a second portion, a cover layer 118 having a first portion, a second portion opposite to the first portion, and a third portion connecting the first portion and the second portion, a support layer 122 in contact with the first and second portions of the cover layer, and an etch stop layer 132 disposed above the second portion of the conductive layer 112, the second portion of the cover layer 118, and the support layer 122. The first portion of the conductive layer 112 is disposed above the first conductive component 106, and the second portion of the conductive layer 112 is disposed above the dielectric layer 104. The first portion of the cover layer 118 is in contact with the first portion of the conductive layer 112, the second portion of the cover layer 118 is in contact with the second portion of the conductive layer 112, and the third portion of the cover layer 118 is in contact with the dielectric layer 104. The air gap 124 is defined by the support layer 122, the first part of the cover layer 118, the second part of the cover layer 118, and the third part of the cover layer 118, and the air gap 124 is disposed between the first part of the conductive layer 112 and the second part of the conductive layer 112.

[0047] An inter-inter-metal dielectric layer (ILD layer) or an inter-metal dielectric layer (IMD layer) can be formed on the capping layer 146 and the dielectric material 134, and the process discussed above with respect to Figures 1D-1T can be repeated until the required number of back-end-of-line (BEOL) interconnect structures are achieved.

[0048] Figures 2A-2S are cross-sectional side views of various stages of fabricating another interconnect structure 200 according to some embodiments. The interconnect structure 200 can be formed on various devices of a semiconductor structure. For example, the interconnect structure 200 can be formed on one or more devices, such as transistors, diodes, image sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices. In some embodiments, the interconnect structure 200 can be formed on a transistor, for example on a nanostructure field-effect transistor (FET) having multiple channels surrounded by a gate electrode layer.

[0049] As shown in Figure 2A, the interconnect structure 200 includes a layer 202, which may be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. Layer 202 includes a dielectric layer 204, one or more conductive members 206 (only one shown) disposed in the dielectric layer 204, and a selective capping layer 208 disposed on each conductive member 206. The materials and processes used to form the dielectric layer 204 may be similar to those used to form the dielectric layer 104. In some embodiments, the dielectric layer 204 includes silicon oxide. The materials, thicknesses, and processes used to form the conductive members 206 and the capping layer 208 may be similar to those used to form the conductive members 106 and the capping layer 108. The conductive members 206 may be electrically connected to conductive contacts beneath the interconnect structure 200.

[0050] As shown in Figure 2B, an adhesive layer 210, a conductive layer 212, and a rigid mask 214 are formed over layer 202. In some embodiments, the adhesive layer 210 is formed on layer 202, the conductive layer 212 is formed on the adhesive layer 210, and the rigid mask 214 is formed on the conductive layer 212. In some embodiments, the adhesive layer 210 is absent, and the conductive layer 212 is formed on layer 202. The material, thickness, and process for forming the adhesive layer 210 can be similar to those for forming the adhesive layer 110. The adhesive layer 210 provides adhesion between the conductive layer 212 and the conductive component 206 and the cover layer 208. The conductive layer 212 may include the same material as the conductive component 206 and can be formed by the same process as the conductive component 206. The conductive layer 212 may have the same thickness as the conductive component 206. The hard mask 214 may include titanium nitride (TiN), tantalum nitride (TaN), tin nitride (WN), or other suitable metal nitrides, and may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable processes. The thickness of the hard mask 214 may range from approximately 2 angstroms to approximately 100 angstroms.

[0051] As shown in Figure 2C, after forming the adhesive layer 210, the conductive layer 212, and the rigid mask 214, an opening 216 is formed in the rigid mask 214, the conductive layer 212, and the adhesive layer 210. The process for forming the opening 216 can be similar to the process for forming the opening 116. The opening 216 divides the conductive layer 212 into one or more portions, for example, into multiple portions.

[0052] Figure 2C shows an ideal case where the sidewalls of opening 216 are vertical. It is understood that in actual operation, the sidewalls of opening 216 may not be vertical, and the sidewalls of opening 216 may have a profile angle between approximately 70 and 90 degrees.

[0053] As shown in Figure 2D, a capping layer 218 is then formed on the exposed surfaces of portions of the rigid mask 214, conductive layer 212, adhesive layer 210, and dielectric layer 204. The capping layer 218 can at least provide adhesion to the rigid mask 214, conductive layer 212, and adhesive layer 210. The material, thickness, and process for forming the capping layer 218 can be similar to those of the capping layer 118.

[0054] As shown in Figure 2E, after the capping layer 218 is formed, a sacrificial layer 220 is formed in the opening 216 (Figure 2D) and on the capping layer 218. The materials and processes for forming the sacrificial layer 220 can be similar to those for forming the sacrificial layer 120.

[0055] As shown in Figure 2F, the sacrificial layer 220 is recessed to a height below the top surface 221 of the conductive layer 212. This recess in the sacrificial layer 220 can partially open the opening 216. In some embodiments, the recess in the sacrificial layer 220 can expose at least a portion of the cover layer 218 in the opening 216. The recess in the sacrificial layer 220 can be performed using a process similar to that used for the recess in the sacrificial layer 120, and the remaining sacrificial layer 220 can have a height similar to that of the remaining sacrificial layer 120.

[0056] As shown in Figure 2G, a support layer 222 is formed on the exposed surface of the interconnect structure 200. In some embodiments, the support layer 222 is formed on the sacrificial layer 220 and the cover layer 218. The support layer 222 can provide the mechanical strength required to maintain the air gap (e.g., air gap 224 in Figure 2H) subsequently formed between the support layer 222 and the cover layer 218. The material, thickness, and process for forming the support layer 222 can be similar to those for forming the support layer 122.

[0057] As shown in Figure 2H, the sacrificial layer 220 is removed, and an air gap 224 is formed in each opening 216 between the support layer 222 and the cover layer 218. The sacrificial layer 220 can be removed by a process similar to that used to remove the sacrificial layer 120, and the air gap 224 can have a similar height to the air gap 124.

[0058] As shown in Figure 2I, a dielectric fill 226 is formed on the support layer 222. The dielectric fill 226 can enhance the isolation of the air gap 224 and provide adhesion between the support layer 222 and the subsequently formed etch stop layer 232. The material, thickness, and process for forming the dielectric fill 226 can be similar to those for forming the dielectric fill 126.

[0059] As shown in Figure 2J, a planarization process can be performed to remove a portion of the dielectric filler 226 formed above the rigid mask 214. A portion of the capping layer 218 and support layer 222 disposed above the rigid mask 214 are also removed due to this planarization process. This planarization process can be any suitable process, such as a chemical mechanical polishing (CMP) process. As a result of the planarization process, the top surface 228 of the rigid mask 214 can be substantially coplanar with the top surface 230 of the dielectric filler 226. The remaining dielectric filler 226 can have a thickness ranging from approximately 10 angstroms to approximately 700 angstroms. Together, the support layer 222 and the dielectric filler 226 can prevent materials introduced during the planarization process, such as slurry, from entering the air gap 224.

[0060] As shown in Figure 2K, a processing step can be performed to selectively form a blocking layer 252 on the top surface 228 of the rigid mask 214. This processing step can be atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, or a dipping process. The blocking layer 252 can include a compound having head groups of phosphorus, sulfur, silicon, or nitrogen to bond to the top surface 228 of the rigid mask 214. Since the rigid mask 214 is a metallic material, but the dielectric filler 226, support layer 222, and capping layer 218 are dielectric materials, the head groups of the blocking layer 252 can be bonded only to the metallic material during the processing step, such as a chemical vapor deposition (CVD) process. The blocking layer 252 is not formed on the top surface of the dielectric filler 226, support layer 222, and capping layer 218. In some embodiments, the barrier layer 252 may include 1-octadecylthiol, 1-dodecanethiol, stearic acid, 4-dodecylbenzenesulfonic acid, dimethyl octadecylphosphonate, Bi(dodecyl)dithiophosphinic acid, diethyl-n-octadecylphosphonate, octadecylphosphonic acid, decylphosphonic acid, and tetradecylphosphonic acid. acid), 2-mercaptobenzothiazole, 2-mercaptobenzoxazole, 2-mercaptobenzimidazole, benzothiazole, Benzoxazole, Benzimidazole, 2-methylbenzimidazole, 5,6-dimethylbenzimidazole, 2-(Methylthio)benzimidazole, 1,2,3-Triazole (1,2,3-triazole), 1,2,4-Triazole (1,2,4-triazole), 3-Amino-1,2,4-triazole (3-Amino-1,2,4-triazole), 1-Hydroxybenzotriazole hydrate (1-Hydroxybenzotriazole hydrate), 4-Methyl-1H-benzotriazole (4-Methyl-1H-benzotriazole), 5-Methyl-1H-benzotriazole (5-Methyl-1H-benzotriazole), 5,6-Dimethyl-1H-benzotriazole (5,6-Dimethyl-1H-benzotriazole), 4-Hydroxy-1H-benzotriazole (4-Hydroxy-1H-benzotriazole), Benzotriazole-1-carboxamide (Benzotriazole-1-carboxamide) amide), 2-methylbenzothiazole, imidazole, methimazole, 5-phenyl-1H-tetrazole, benzotriazole, 5-(3-aminophenyl)tetrazole, 4-amino-4H-1,2,4-triazole, 3-amino-5-thiol-1,2,4-triazole, 3-amino-5-methylthio-1H-1,2,4-triazole 2-Aminopyrimidine, 2-mercaptopyrimidine, adenine, hypoxanthine, morpholine, 5-Amino-1,3,4-thiadiazole-2-thiol, tryptophan, histidine, 5-(trifluoromethyl)-1H-1,2,3-benzotriazole3-benzotriazole), 1H-benzotriazole, 1-(4-morpholinylmethyl), phenothiazine, purine, melamine, trithiocyanuric acid, 1,3,4-thiadiazole-2,5-diamine, 3,5-diamino-1,2,4-triazole, 5-aminotetrazole, 3,6-bis(methylthio)-1,2,4,5-tetrazine, aminophylline, or other suitable compounds. In some embodiments, the barrier layer 252 may have a thickness ranging from about 2 angstroms to about 50 angstroms.

[0061] As shown in Figure 2L, a metal oxide layer 254 is formed on the exposed top surface of the dielectric filler 226, the support layer 222, and the capping layer 218. Since the barrier layer 252 can block the precursor while forming the metal oxide layer 254, the metal oxide layer 254 is grown on the dielectric filler 226, the support layer 222, and the capping layer 218, but not on the top surface of the barrier layer 252. In some embodiments, the metal oxide layer 254 may be composed of an oxide formed from aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), yttrium (Y), or other metal oxide precursors, and the metal oxide layer 254 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating processes. In some embodiments, the metal oxide layer 254 may have a thickness ranging from about 1 angstrom to about 100 angstroms.

[0062] As shown in Figure 2M, a removal process is performed to selectively remove the barrier layer 252 and retain the metal oxide layer 254. The removal process of the barrier layer 252 can be performed by any suitable process, such as wet etching, dry etching, or a combination thereof. After removing the barrier layer 252, as shown in Figure 2N, an etching process is performed to remove the hard mask 214. The etching process may include one or more selective etching processes, such as dry etching, wet etching, or a combination thereof, to selectively remove the hard mask 214. Once the hard mask 214 is removed, the top surface 221 of the conductive layer 212 may be substantially lower than the top surface 230 of the dielectric filler 226, and the top surface 221 of the conductive layer 212 may be substantially lower than the top surface of the metal oxide layer 254.

[0063] As shown in Figure 20, an etch stop layer 232 is formed on the exposed surfaces of the conductive layer 212, the capping layer 218, and the metal oxide layer 254. The etch stop layer 232 can be a single layer or a multilayer structure. The material, thickness, and process for forming the etch stop layer 232 can be similar to those for forming the etch stop layer 132.

[0064] As shown in Figure 2P, a dielectric material 234 is formed on the etch stop layer 232, and a hard mask 236 is formed on the dielectric material 234. The dielectric material 234 may include the same material as the dielectric filler 226 and can be formed by the same process as the dielectric filler 226. The etch stop layer 232 and the dielectric material 234 may have different etch selectivity or similar etch selectivity. The hard mask 236 may include the same material as the hard mask 214 and can be formed by the same process as the hard mask 214.

[0065] As shown in Figure 2Q, contact openings 238 and 240 are formed in the hard mask 236, the dielectric material 234, and the etch stop layer 232. Contact openings 238 and 240 can be formed by any suitable etch / patterning process, such as a dual-damascene process. For example, contact opening 238 can be formed first by patterning the hard mask 236 and transferring the pattern to a portion of the dielectric material 234. Then, contact opening 240 is formed by etching through the dielectric material 234 from a portion of the bottom of contact opening 238. Therefore, contact opening 240 has a smaller size than contact opening 238. In some embodiments, contact opening 240 is a via, and contact opening 238 is a trench. In some embodiments, when forming the contact opening 240, if the etch stop layer 232 and the dielectric material 234 have different etch selectivity, the etching process may be stopped by the etch stop layer 232, and another etching process is required to remove a portion of the etch stop layer 232. In some embodiments, when forming the contact opening 240, if the etch stop layer 232 and the dielectric material 234 have similar etch selectivity, the etching process can be stopped by the metal oxide layer 254. The conductive layer 212, capping layer 218, support layer 222, and dielectric filler 226 below the contact opening 240 are protected by the metal oxide layer 254 to prevent damage caused by over-etching.

[0066] In most embodiments, the contact opening 240 is aligned with a portion of the conductive layer 212, for example, this portion of the conductive layer 212 is disposed between two adjacent air gaps 224. However, in some embodiments, the contact opening 240 may be slightly misaligned with a portion of the conductive layer 212. Since the metal oxide layer 254 is formed on the dielectric filler 226, the dielectric filler 226 can be retained when removing the dielectric material 234 and the etch stop layer 232. Because of the metal oxide layer 254 disposed on the dielectric filler 226, the etching process used to form the contact opening 240 has virtually no impact on the dielectric filler 226. Therefore, the use of the metal oxide layer 254 can reduce the risk of leakage current between conductors when edge setting error (EPE) occurs.

[0067] As shown in Figure 2R, a barrier layer 242 and a conductive feature 244 are formed in contact openings 238 and 240. The materials and forming processes of the barrier layer 242 and the conductive feature 244 can be similar to those of the barrier layer 142 and the conductive feature 144.

[0068] As shown in Figure 2S, a planarization process is performed to remove a portion of the barrier layer 242 and a portion of the conductive component 244 disposed above the rigid mask 236, and the rigid mask 236 can also be removed by the planarization process. The aforementioned planarization process can be any suitable process, such as a chemical mechanical polishing (CMP) process. After the planarization process is completed, the top surfaces of the dielectric material 234, the barrier layer 242, and the conductive component 244 are substantially coplanar. Subsequently, a cap layer 246 can be selectively formed on the conductive component 244 and the barrier layer 242. The material and process for forming the cap layer 246 can be similar to the material and process for forming the cap layer 146.

[0069] As shown in Figure 2S, the interconnect structure 200 includes a dielectric layer 204, a first conductive member 206 disposed in the dielectric layer 204, a conductive layer 212 including a first portion and a second portion, a cover layer 218 having a first portion, a second portion opposite to the first portion, and a third portion connecting the first portion and the second portion, a support layer 222 in contact with the first and second portions of the cover layer 218, a dielectric filler 226 disposed above an air gap 224 and in contact with the support layer 222, and a metal oxide layer 254 disposed above the dielectric filler 226, the support layer 222, the first portion of the cover layer 218, and the second portion of the cover layer 218. The first portion of the conductive layer 212 is disposed above the first conductive member 206, and the second portion of the conductive layer 212 is disposed above the dielectric layer 204. A first portion of the capping layer 218 contacts a first portion of the conductive layer 212, a second portion of the capping layer 218 contacts a second portion of the conductive layer 212, and a third portion of the capping layer 218 contacts the dielectric layer 204. An air gap 224 is defined by the support layer 222, the first portion of the capping layer 218, the second portion of the capping layer 218, and the third portion of the capping layer 218, and is disposed between the first portion and the second portion of the conductive layer 212.

[0070] An inter-inter-metal dielectric layer (ILD layer) or an inter-metal dielectric layer (IMD layer) may be formed on the capping layer 246 and the dielectric material 234, and the process discussed above with respect to Figures 2A-2S may be repeated until the required number of back-end-of-line (BEOL) interconnect structures are achieved.

[0071] Figure 3 is a flowchart illustrating a method 300 for forming an interconnect structure 100 or 200 according to some embodiments. It should be noted that the operation of method 300, including any descriptions given with reference to the accompanying drawings, is exemplary only and is not intended to limit the scope beyond the specific statements in the appended claims. Additional steps may be performed before, during, and after method 300, and some steps may be replaced, eliminated, or rearranged in any desired order according to various embodiments of method 300.

[0072] Method 300 begins at step 302, where a conductive layer is formed over the dielectric layer. This conductive layer may be the aforementioned conductive layer 112 or conductive layer 212, and the dielectric layer may be the aforementioned dielectric layer 104 or dielectric layer 204. In some embodiments, the conductive layer may further include a conductive masking layer, such as masking layer 114 or masking layer 214 formed over conductive layer 112 or conductive layer 212. Dielectric layer 104 or 204 may have one or more conductive components (e.g., conductive component 106 or conductive component 206) formed therein. The aforementioned conductive layer and dielectric layer may be formed by the processes discussed above with respect to Figures 1A-1B and 2A-2B.

[0073] In step 304, one or more openings are formed in the conductive layer to expose portions of the dielectric surface of the dielectric layer and portions of the conductive surface of the conductive layer, wherein the one or more openings divide the conductive layer into one or more portions. The aforementioned one or more openings may be one or more openings 116 or 216, the portions of the dielectric surface of the dielectric layer may be the exposed surfaces of dielectric layer 104 or dielectric layer 204, and the conductive surface may be the conductive surface of conductive layer 112 or conductive layer 212. The aforementioned openings may be formed by the processes discussed above with respect to Figures 1C and 2C.

[0074] In step 306, a capping layer is formed on the exposed portions of the dielectric surface of the dielectric layer and the conductive surface of the conductive layer. This capping layer may be capping layer 118 or capping layer 218. The aforementioned capping layer may be formed by the process discussed above with respect to Figure 1D and Figure 2D.

[0075] In step 308, a sacrificial layer is formed in one or more openings. This sacrificial layer may be sacrificial layer 120 or sacrificial layer 220. In step 310, this sacrificial layer is recessed to have a height in the opening (e.g., height H1 shown in Figure 1F). The aforementioned sacrificial layer may be formed by the processes discussed above with respect to Figures 1E-1F and 2E-2F.

[0076] In step 312, a support layer is formed on the recessed sacrificial layer in each of the one or more openings, and in step 314, the sacrificial layer is removed to form an air gap in each of the one or more openings. The aforementioned support layer may be support layer 122 or support layer 222, and the aforementioned air gap may be air gap 124 or air gap 224. The support layer and the air gap may be formed by the processes discussed above with respect to Figures 1G-1H and 2G-2H.

[0077] In step 316, a dielectric fill is formed on the support layer. The aforementioned dielectric fill may be dielectric fill 126 or dielectric fill 226. The dielectric fill may be formed by the process discussed above with respect to Figures 1I-1J and 2I-2J.

[0078] In some embodiments, after step 316, a metal oxide layer is selectively formed on the capping layer, the support layer, and the dielectric filler. The aforementioned metal oxide layer may be metal oxide layer 254, and the metal oxide layer may be formed by the process discussed above with respect to Figures 2K-2M.

[0079] In step 318, the aforementioned conductive layer is recessed. The removed conductive layer may be a hard mask 114 or a hard mask 214. The aforementioned conductive layer may be recessed using the process discussed above with respect to Figure 1K and Figure 2N.

[0080] In step 320, an etch stop layer is formed on the recessed conductive layer, capping layer, support layer, and dielectric filler. When a metal oxide layer is formed on the capping layer, support layer, and dielectric filler, this etch stop layer is formed on the recessed conductive layer, capping layer, and metal oxide layer. The aforementioned etch stop layer can be etch stop layer 132 or etch stop layer 232. The etch stop layer can be formed using the processes discussed above with respect to Figures 1L and 2O.

[0081] In step 322, a dielectric material is formed on the etch stop layer. The aforementioned dielectric material may be dielectric material 134 or dielectric material 234. The aforementioned dielectric material may be formed by the process discussed above with respect to Figure 1M and Figure 2P.

[0082] In step 324, a contact opening is formed through the dielectric material and the etch stop layer to expose a portion of the top surface of the conductive layer. The aforementioned contact opening may be contact opening 140 or contact opening 240. The contact opening may be formed by the processes discussed above with respect to Figures 1N-1O and Figures 2Q-2R.

[0083] In step 326, a conductive feature is formed in the contact opening. The aforementioned conductive feature may be conductive feature 144 or conductive feature 244. The conductive feature may be formed by the process discussed above with respect to Figures 1P-1Q and 2R-2S.

[0084] The various embodiments disclosed herein provide an etch stop layer 132 with a different etch selectivity than the dielectric filler 126, or a metal oxide layer 254 formed on the dielectric filler 226. The aforementioned etch stop layer or metal oxide layer can serve as a barrier layer when an etching process is performed to remove a portion of the dielectric material 134 or 234. With the etch stop layer 132 or metal oxide layer 254 disposed on the dielectric filler 126, the etching process for forming the contact opening 140 or contact opening 240 will not substantially affect the dielectric filler 126 or dielectric filler 226. Therefore, the risk of wire-to-wire leakage current can be reduced when edge setting error (EPE) occurs.

[0085] One embodiment provides an interconnect structure. This interconnect structure includes a dielectric layer, a first conductive component, a conductive layer, a capping layer, a support layer, and an etch stop layer. The first conductive component is disposed in the dielectric layer. The conductive layer includes a first portion and a second portion. The first portion of the conductive layer is disposed above the first conductive component, and the second portion of the conductive layer is disposed above the dielectric layer. The capping layer includes a first portion, a second portion opposite to the first portion, and a third portion connecting the first and second portions. The first portion of the capping layer contacts the first portion of the conductive layer, the second portion of the capping layer contacts the second portion of the conductive layer, and the third portion of the capping layer contacts the dielectric layer. The support layer contacts the first and second portions of the capping layer. An air gap is defined by the support layer, the first portion of the capping layer, the second portion of the capping layer, and the third portion of the capping layer. The etch stop layer is disposed above the second portion of the conductive layer, the second portion of the capping layer, and the support layer.

[0086] In some embodiments, the aforementioned air gap is disposed between the aforementioned first portion of the aforementioned conductive layer and the aforementioned second portion of the aforementioned conductive layer.

[0087] In some embodiments, the exemplary interconnect structure further includes a dielectric filler disposed above the aforementioned air gap and in contact with the aforementioned support layer.

[0088] In some embodiments, the aforementioned etch stop layer is further disposed above the aforementioned dielectric filler.

[0089] In some embodiments, a top surface of the first portion of the aforementioned conductive layer is lower than a top surface of the aforementioned dielectric filler, and a top surface of the second portion of the aforementioned conductive layer is lower than the top surface of the aforementioned dielectric filler.

[0090] In some embodiments, the exemplary interconnect structure further includes a dielectric material disposed above the aforementioned second portion of the aforementioned conductive layer, the aforementioned second portion of the aforementioned cover layer, and the aforementioned support layer; and a second conductive member disposed in the aforementioned dielectric material and in contact with the aforementioned first portion of the aforementioned conductive layer and the aforementioned first portion of the aforementioned cover layer.

[0091] In some embodiments, the exemplary interconnect structure further includes a barrier layer disposed between the aforementioned second conductive component and the aforementioned first portion of the aforementioned conductive layer, and in contact with the aforementioned second conductive component, the aforementioned first portion of the aforementioned conductive layer and the aforementioned first portion of the aforementioned cover layer.

[0092] In some embodiments, the aforementioned second conductive component is in contact with the aforementioned support layer.

[0093] Another embodiment proposes an interconnect structure. This interconnect structure includes a dielectric layer, a first conductive component, a conductive layer, a capping layer, a support layer, a dielectric filler, and a metal oxide layer. The first conductive component is disposed in the dielectric layer. The conductive layer is disposed above the first conductive component and the dielectric layer. The capping layer is embedded in the conductive layer. The sidewalls of the capping layer are in contact with the conductive layer, and a bottom surface of the capping layer is in contact with the dielectric layer. The support layer is in contact with the capping layer. An air gap is defined by the support layer and the capping layer. The dielectric filler is disposed above the air gap and in contact with the support layer. The metal oxide layer is disposed above the dielectric filler, the support layer, and the capping layer.

[0094] In some embodiments, the exemplary interconnect structure further includes an etch stop layer disposed over the aforementioned conductive layer, the aforementioned capping layer and the aforementioned metal oxide layer.

[0095] In some embodiments, the exemplary interconnect structure further includes a dielectric material disposed above the aforementioned etch stop layer; and a second conductive component disposed in the aforementioned dielectric material and in contact with the aforementioned conductive layer, the aforementioned capping layer and the aforementioned metal oxide layer.

[0096] In some embodiments, a top surface of the aforementioned conductive layer is lower than a top surface of the aforementioned dielectric filler.

[0097] In some embodiments, a top surface of the aforementioned conductive layer is lower than a top surface of the aforementioned metal oxide layer.

[0098] In some embodiments, the exemplary interconnect structure further includes a barrier layer disposed between the aforementioned second conductive component and the aforementioned conductive layer, and in contact with the aforementioned second conductive component, the aforementioned conductive layer, the aforementioned cover layer and the aforementioned metal oxide layer.

[0099] Another embodiment is a method for forming an interconnect structure. This method includes forming a conductive layer over a dielectric layer, forming one or more openings in the conductive layer to expose portions of the dielectric surface of the dielectric layer and portions of the conductive surface of the conductive layer, wherein the one or more openings divide the conductive layer into one or more portions, forming a capping layer on the exposed portions of the dielectric surface of the dielectric layer and the conductive surface of the conductive layer, forming a sacrificial layer in the one or more openings to recess the sacrificial layer, forming a support layer on each recessed sacrificial layer in the one or more openings, removing the sacrificial layer to form an air gap in each of the one or more openings, forming a dielectric filler on the support layer to recess the conductive layer, forming an etch stop layer on the recessed conductive layer, capping layer, support layer and dielectric filler, forming a dielectric material on the etch stop layer, forming a contact opening through the dielectric material and the etch stop layer to expose the top surface of a portion of the conductive layer, and forming a conductive component in the contact opening.

[0100] In some embodiments, in the aforementioned exemplary interconnection structure formation method, recessing the aforementioned conductive layer includes: removing a hard masking layer of the aforementioned conductive layer.

[0101] In some embodiments, in the aforementioned exemplary interconnection structure formation method, before recessing the aforementioned conductive layer, a metal oxide layer is further formed on the aforementioned cover layer, the aforementioned support layer and the aforementioned dielectric filler.

[0102] In some embodiments, in the aforementioned exemplary interconnection structure formation method, forming the aforementioned etch stop layer system on the aforementioned recessed conductive layer, the aforementioned capping layer, the aforementioned support layer and the aforementioned dielectric filler includes: forming the aforementioned etch stop layer on the aforementioned recessed conductive layer, the aforementioned capping layer and the aforementioned metal oxide layer.

[0103] In some embodiments, in the aforementioned exemplary interconnection structure formation method, forming the aforementioned dielectric filler includes: disposing the aforementioned dielectric filler in the aforementioned support layer; and performing a planarization step to remove a portion of the aforementioned cover layer, the aforementioned support layer and the aforementioned dielectric filler, wherein the aforementioned cover layer, the aforementioned support layer and the aforementioned dielectric filler substantially have a coplanar top surface.

[0104] In some embodiments, in the aforementioned exemplary interconnection structure formation method, a top surface of the aforementioned recessed conductive layer is lower than the coplanar top surface of the aforementioned cover layer, the aforementioned support layer and the aforementioned dielectric filler.

[0105] The components of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0007] The embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased. Figure 1A is a perspective view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 1B to 1T are cross-sectional side views of various stages of manufacturing an interconnect structure according to some embodiments. Figures 2A to 2S are cross-sectional side views of various stages of manufacturing another interconnect structure according to some embodiments. Figure 3 is a flowchart illustrating a method for forming an interconnect structure according to some embodiments.

Claims

1. An interconnection structure, comprising: One dielectric layer; A first conductive component is disposed in the dielectric layer; a conductive layer includes a first portion and a second portion, wherein the first portion of the conductive layer is disposed above the first conductive component, and the second portion of the conductive layer is disposed above the dielectric layer; a capping layer has a first portion, a second portion opposite to the first portion, and a third portion connecting the first portion and the second portion, wherein the first portion of the capping layer is in contact with the first portion of the conductive layer, the second portion of the capping layer is in contact with the second portion of the conductive layer, and the third portion of the capping layer is in contact with the dielectric layer; a support layer is in contact with the first portion and the second portion of the capping layer, wherein an air gap is defined by the support layer, the first portion of the capping layer, the second portion of the capping layer, and the third portion of the capping layer; and an etch stop layer is disposed above the second portion of the conductive layer, the second portion of the capping layer, and the support layer.

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