Stacked RF circuit topology using transistor die with through silicon carbide vias on gate and / or drain

Abstract

A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and / or harmonic termination circuitry.

Description

[Technical Field]

[0001] The present invention relates to integrated circuit devices, and more particularly to structures for packaging integrated circuit devices. [Previous Technology]

[0002] RF power amplifiers are used in a variety of applications, such as base stations for wireless communication systems. The signal amplified by an RF power amplifier typically contains a signal with a modulated carrier having a frequency in the range of megahertz (MHz) to gigahertz (GHz). The baseband signal modulating the carrier is typically at a relatively low frequency, and depending on the application, the carrier can be as high as 300 MHz or higher. Many RF power amplifier designs utilize semiconductor switching devices as amplification devices. Examples of such switching devices include power transistor devices, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), DMOS (Double-Diffused Metal-Oxide-Semiconductor) transistors, HEMT (High Electron Mobility Transistor), MESFET (Metal-Oxide-Semiconductor Field-Effect Transistor), LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) transistors, etc.

[0003] RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented in silicon or using wide-bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV) such as silicon carbide (“SiC”) and group III nitride materials. As used herein, the term “group III nitride” refers to a semiconducting compound formed between nitrogen and elements in group III of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have an empirical formula for a combination of one mole of nitrogen and a total of one mole of group III elements.

[0004] Silicon-based RF amplifiers are typically implemented using LDMOS transistors and can achieve high-level linearity with relatively inexpensive fabrication. Group III nitride-based RF amplifiers are typically implemented using HEMTs and are primarily used in applications requiring high power and / or high-frequency operation, where LDMOS transistor amplifiers may have inherent performance limitations.

[0005] An RF transistor amplifier may include one or more amplification stages, each of which is typically implemented as a transistor amplifier. To increase output power and current handling capability, RF transistor amplifiers are typically implemented in a "unit cell" configuration, in which a large number of individual "unit cell" transistors are electrically configured in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include a plurality of dies. When multiple RF transistor amplifier dies are used, the multiple RF transistor amplifier dies may be connected in series and / or in parallel.

[0006] RF amplifiers typically include: matching circuitry, such as impedance matching circuitry, designed to improve impedance matching between the active transistor chip (e.g., including MOSFETs, HEMTs, LDMOS, etc.) and the transmission lines connected to the active transistor chip for RF signals at the basic operating frequency; and harmonic termination circuitry, designed to at least partially terminate harmonic products, such as second- and third-order harmonic products, that can be generated during device operation. The termination of harmonic products also affects the generation of intermodulation distortion products.

[0007] The RF amplifier transistor chip, impedance matching, and harmonic termination circuitry can be enclosed in a device package. A chip or wafer can refer to a small block of semiconducting material or other substrate on which electronic circuitry is fabricated. Integrated circuit packaging can refer to encapsulating one or more chips in a support housing or package that protects the chip from physical damage and / or corrosion and supports electrical contacts for connection to external circuitry. The input and output impedance matching circuitry in an integrated circuit device package typically includes an LC network providing at least a portion of an impedance matching circuit configured to match the impedance of the active transistor chip to a fixed value. Electrical leads can extend from the package to electrically connect the RF amplifier to external circuitry elements such as input and output RF transmission lines and bias voltage sources.

[0008] Many functional blocks, such as impedance matching circuits, harmonic filters, couplers, baluns, and power combiners / distributors, can be implemented using integrated passive devices (IPDs). IPDs contain passive electrical components and are generally fabricated using standard wafer fabrication techniques such as thin-film and photolithography. IPDs can be designed as flip-chip mounted or wire-bonded components. The substrates used for IPDs are typically thin-film substrates such as silicon, alumina, or glass, which allows for easy manufacturing and packaging using active transistor chips.

[0009] Certain conventional methods for assembling RF power devices may involve assembling some of a transistor die and some of a matching network component (e.g., a pre-matched capacitor, such as a MOS capacitor) in a ceramic or overmolded package on a CPC (copper, copper-molybdenum, copper laminate structure) or copper flange. The transistor die, capacitor, and input / output leads may be interconnected with wires such as gold wires and / or aluminum wires. This assembly process may be slow and continuous (e.g., one package at a time), and the assembly cost may be high (e.g., due to the cost of gold wires and expensive wire bonding machines). [Summary of the Invention]

[0010] According to certain embodiments of the present invention, a radio frequency (RF) power amplifier device package includes: a substrate; and a first die attached to the substrate at a bottom surface of the first die. The first die includes: a plurality of transistor cells; and top gate or drain contacts, which are located on a top surface of the first die opposite to the bottom surface. At least one of the top gate or drain contacts is electrically connected to at least one bottom gate or drain contact on the bottom surface of the first die via at least one respective conductive via structure. An integrated interconnect structure is provided on the first die opposite to the substrate. The integrated interconnect structure includes: a first contact pad located on the top gate contact or the top drain contact of the first die; and at least one second contact pad connected to a package lead, a contact of a second die, an impedance matching circuit system, and / or a harmonic termination circuit system.

[0011] In some embodiments, the package lead may be a first package lead, and the respective bottom gate or drain contacts on the bottom surface of the first die may be electrically connected to a second package lead.

[0012] In some embodiments, the integrated interconnect structure may include at least a portion of the impedance matching circuit system for a circuit defined by the isoelectric cells of the first die.

[0013] In some embodiments, conductive wiring may be provided on the substrate defining at least a portion of the harmonic termination circuit system for the circuit defined by the transistor cells of the first die. The respective bottom gate or drain contacts may be coupled to the second package lead via the conductive wiring.

[0014] In some embodiments, the top gate contact or the top drain contact of the first contact pad having the integrated interconnect structure can be electrically connected to the respective bottom gate or drain contact via the respective conductive via structure.

[0015] In some embodiments, the integrated interconnect structure may be an integrated passive device (IPD) comprising one or more passive electronic components.

[0016] In some embodiments, the first contact pad may be an electrical connection on one surface of the IPD to one of the bonding pads of one or more passive electronic components, the surface of which faces the top surface of the first die. The bonding pad may be connected to the top gate or drain contact via a conductive bump between the bonding pad and the top gate or drain contact.

[0017] In some embodiments, the circuit defined by the transistor cells of the first die may be a first stage of a radio frequency (RF) amplifier circuit, and the second die may contain transistor cells defining a second stage of the RF amplifier circuit.

[0018] In some embodiments, the IPD may include an insulating material between its conductive elements to define at least one capacitor integrated in the IPD.

[0019] In some embodiments, the second die may include one or more capacitors that define at least a portion of the impedance matching circuit system.

[0020] In some embodiments, the first die may be attached to the substrate at a source contact on the bottom surface of the first die adjacent to the at least one bottom gate or drain contact.

[0021] In some embodiments, the at least one respective bottom gate or drain contact may include both a bottom gate contact and a bottom drain contact. The source contact may be located on the bottom surface of the first die between the bottom gate contact and the bottom drain contact.

[0022] In some embodiments, the first grain may comprise a group III nitride-based material.

[0023] In some embodiments, the first grain may comprise a group III nitride-based material on silicon carbide (SiC), and the respective conductive via structure may be a through-silicon carbide (TSiC) via.

[0024] According to certain embodiments of the present invention, a radio frequency (RF) power amplifier device package includes: a substrate; and a first die attached to the substrate at a source contact on a bottom surface of the first die. The first die includes: a plurality of transistor cells; and top gate and drain contacts, which are located on a top surface of the first die opposite to the bottom surface. At least one of the top gate or drain contacts is electrically connected to a bottom gate or drain contact on the bottom surface via a separate conductive via structure. The top gate contact or the top drain contact is connected at the top surface of the first die to one of an impedance matching circuit system or a harmonic termination circuit system, and the separate bottom gate or drain contacts are connected at the bottom surface of the first die to the other of the impedance matching circuit system or the harmonic termination circuit system.

[0025] In some embodiments, the first grain may comprise a group III nitride-based material.

[0026] In some embodiments, an integrated interconnect structure may be provided on the first die, the integrated interconnect structure including at least a portion of the impedance matching circuit system opposite the substrate. The top gate contact or the top drain contact is coupled via the integrated interconnect structure to a second die attached to the substrate and / or a first package lead.

[0027] In some embodiments, the integrated interconnect structure may be an integrated passive device (IPD) comprising one or more passive electronic components.

[0028] In some embodiments, the integrated interconnect structure may include: a first contact pad located on one surface of the first die facing the top surface of the first die, wherein the first contact pad is located on the top gate contact or the top drain contact; and at least one second contact pad located on the surface of the second die, wherein the at least one second contact pad is located on one contact of the second die and / or coupled to one of the package leads by a conductive bump between the at least second contact pad and one of the package leads.

[0029] In some embodiments, conductive wiring may be provided on the substrate defining at least a portion of the harmonic termination circuit system. The respective bottom gate or drain contacts may be coupled to a second package lead via the conductive wiring.

[0030] In some embodiments, the top gate contact or the top drain contact of the first contact pad having the integrated interconnect structure can be electrically connected to the respective bottom gate or drain contact via the respective conductive via structure.

[0031] In some embodiments, the second die may include at least one contact on one surface of the second die opposite to the substrate, and the at least one second contact pad of the integrated interconnect structure may be located on the at least one contact. In some embodiments, the second die may include one or more capacitors. In some embodiments, the second die may include a plurality of transistor units defining a stage of an RF amplifier circuit.

[0032] Other apparatus, devices, and / or methods according to certain embodiments will become readily apparent to those skilled in the art upon review of the accompanying drawings and detailed description. All such additional embodiments, in addition to any and all combinations thereof, are intended to be included within this specification, fall within the scope of this invention, and are protected by the appended claims.

Implementation Method

[0049] Priority Statement

[0050] This application claims priority to U.S. Provisional Application No. 63 / 004,766, filed on April 3, 2020, with the United States Patent and Trademark Office. The disclosure of this application is incorporated herein by reference.

[0051] Certain embodiments of the present invention may present difficulties in assembling and optimizing the parameters of the various components included in an integrated circuit device package. For example, some conventional group III nitride-based RF amplifiers may use bonding wires to connect transistor chips to package leads, impedance matching circuits, and / or harmonic termination circuits. These bonding wires have inherent inductance that can be used to implement some of the inductors in the impedance matching and / or harmonic termination circuits of the RF amplifier. The amount of inductance provided may vary with the length and / or cross-sectional area (e.g., diameter) of the bonding wire. When the application moves to higher frequencies, the inductance of the bonding wire may exceed an inductance expected by the impedance matching and / or harmonic termination circuit. Very short and / or bonding wires with large cross-sectional areas may be used in an effort to reduce the inductance of these bonding wires to a suitable level. However, very short bonding wires may be difficult to solder in place or may violate manufacturability design rules, which may increase manufacturing costs and / or may lead to a higher device failure rate. Large cross-sectional area bonding wires may require larger gate and / or drain bonding pads on the RF amplifier die, which can increase the overall size of the RF amplifier die. Moreover, in some higher frequency applications, even very short bonding wires with large cross-sectional areas can have excessive inductance, making it impossible for the matching network to properly terminate higher-order (e.g., second or third-order) harmonics (for example).

[0052] Moreover, the performance of certain passive RF devices (e.g., IPDs containing passive electronic components such as inductors or capacitors, generally referred to herein as passive devices) can be affected based on their proximity to a ground plane. Specifically, the quality factor Q of an inductor coil can decrease when the distance between the winding of an inductor coil and a grounded flange (or other grounded structure) of a device package is reduced. However, since the die typically has a flat structure on one surface of such a die for electrically connecting to external dies or devices via conductive contact elements (also referred to herein as contact pads, bonding pads, mats, or contacts), increasing the distance between the passive component and the ground plane can increase the length of the bonding wires that connect the passive component to one or more active electronic components (e.g., transistors, such as power transistor devices containing transistor units) contained in an active transistor die (also referred to herein as a transistor die or active die). The increased connection length can reduce or offset the effectiveness of the impedance matching network provided by the passive component, especially at higher frequencies.

[0053] Compared to certain conventional RF power devices that can use wire bonding loops to implement input and output pre-matching, embodiments of the present invention provide a configuration of components for high-power applications (e.g., for 5G or base station applications) in packaged RF power products, wherein, without the use of wire bonding, connections are implemented between components (e.g., between circuit level components, such as between bonding pads of one or more active transistor dies and / or between bonding pads of active transistor dies and the gate and / or drain leads of the package) by including one or more structures of conductive components on a layer or substrate (generally referred to herein as integrated interconnect structures).

[0054] Generally, an integrated interconnect structure or device (or "integrated interconnect") can refer to a structure that includes an integrated circuit system such as resistors (including transmission lines), vias, inductors, and / or capacitors on a layer or substrate. For example, a dielectric substrate structure having integrated traces, vias, and / or circuit systems can be used to replace bonding wires to reduce and / or avoid associated parasitic inductance and manufacturing problems. In some embodiments described herein, the integrated interconnect can be implemented as a passive device (including an IPD having a thin-film substrate such as silicon, alumina, or glass) and / or a conductive wiring structure (including conductive wires on a passivation layer (RDL) structure or other substrate). As stated above, an IPD includes inductors and / or other passive electrical components and can be fabricated using standard semiconductor processing techniques such as thin-film and / or photolithography. An IPD can be a flip-chip mounted or wire-bonded component and can include a thin-film substrate such as silicon, alumina, or glass. An RDL structure refers to a substrate or layer having a conductive layer pattern and / or conductive vias. RDL structures can be fabricated using semiconductor processing techniques by depositing conductive and insulating layers and / or patterns on a substrate material and by forming vias and copper wiring patterns within the structure for transmitting signals via the RDL structure.

[0055] Integrated interconnects can be used, as described herein, to provide connections between input, output, and / or transistor stages, and to provide circuitry useful and / or necessary for the operation of the transistors. For example, an integrated interconnect can provide an impedance configured to reduce an impedance mismatch between active transistors and / or between an external device connected to a package lead. In certain instances, an integrated interconnect, such as an IPD, can be used to implement input and / or output pre-matching network circuitry for an active transistor, resulting in minimal or no wire connections. In some embodiments, a flip-chip IPD including individual contacts facing one or more transistors can be used to interconnect multiple transistors, for example, in a multi-stage amplifier implementation. That is, in some embodiments, an integrated interconnect can provide an interconnect function and an impedance matching / harmonic termination function, allowing for the reduction or elimination of wire connections in the package. In some embodiments, an IPD as described herein may not have active components.

[0056] In some embodiments, the IPDs providing impedance matching networks for active dies (also referred to herein as pre-matched IPDs) are placed directly or stacked on top of the gate and / or drain contact pads of the transistor die and / or capacitor die, thus reducing or minimizing interconnect-related losses by means of zero-wire or minimal-wire bonding. Furthermore, multiple wafers can be assembled in a batch process, further reducing assembly time and cost. The increased height or distance between passive components and one attachment surface of a grounded flange, such as a device package die pad (as provided by, for example, a stacked configuration on top of a 100 µm thick active transistor die), reduces capacitance coupled to ground, thus reducing or minimizing (and in some cases increasing) the negative effects on the quality factor Q, reducing or minimizing passive component losses, and resulting in better RF performance.

[0057] Additional passive components (e.g., for a specific application) may be included in the passive device and / or located on an attachment surface of the package, which is directly beneath the passive device. For example, in some embodiments, a capacitor (e.g., a MOS capacitor) for pre-matching and / or harmonic termination may be placed between the input pre-matching IPD and the attachment surface. Similarly, a high-density output capacitor may be placed between the output pre-matching IPD and the attachment surface to improve the video bandwidth (VBW), thereby providing a larger area for accommodating a high-density VBW capacitor. In some embodiments, the passive device may include a capacitor integrated therein, such as a MIM (metal-insulator-metal) capacitor.

[0058] Embodiments of the present invention further provide transistor die configurations in which one or more of the contacts or bonding pads of an active transistor die can be simultaneously connected from one side of the die via an integrated interconnect structure or device (e.g., a flip-chip IPD) and from the other side of the die using a conductive via connection structure also referred to herein as a conductive via (e.g., a silicon carbide (TSiC) via when extending through a SiC-based transistor die). For example, a bottom contact or bonding pad on the bottom side of one of the transistor chips (e.g., adjacent to the attachment surface of the package substrate) may be connected to a matching element (e.g., for harmonic termination) in or on the package substrate (e.g., an RDL layer), while a top contact or bonding pad on the top side of the transistor chip (e.g., opposite to the attachment surface of the package substrate) may be connected to one or more structures containing conductive components on a layer or substrate (e.g., an integrated interconnect structure), or vice versa, wherein individual TSiC vias extend between the top and bottom contacts.

[0059] Conductive vias providing contact points on different surfaces of the transistor die (e.g., extending on the top surface between individual gate contacts and / or individual drain contacts and the bottom surface of the transistor die) eliminate the need for additional IPDs, copper pads, and / or wire bonding to the gate / drain leads of the package. Furthermore, the conductive vias provide multiple paths to contact the package gate / drain leads, simultaneously allowing (e.g., via stacked IPDs) impedance matching at the top surface of the transistor die, while also allowing (e.g., via conductive wiring on the RDL) at least some impedance matching contribution in / on the substrate at the bottom surface of the transistor die to further pre-match the fundamental frequency and / or harmonics. The combination of matching contributions at the top and bottom of the transistor die allows for the integration of pre-matching circuitry into a smaller space and reduces or eliminates performance degradation due to the need to share pad space between multiple functionalities.

[0060] That is, compared to some conventional packages in which transistor pad space is shared between the drain and tuning leads or between the leads and / or IPDs for pre-matching the fundamental frequency and the leads and / or IPDs for harmonic termination, embodiments of the present invention can dedicate an entire side (e.g., the top side) of the transistor pad to one function and an entire other side (e.g., the bottom side, through a TSiC via) to other functions. For example, the top pad of the active die can be dedicated to impedance matching at the fundamental frequency f0, while the bottom pad can provide connections for input / output and harmonic termination, as illustrated in the figures, or vice versa. In a particular embodiment, harmonic termination for the input and output can be achieved via wiring to a TSiC via and trace on a bottom-side RDL, while the top side is connected via flip-chip IPDs for pre-matching the fundamental frequency. Alternatively, instead of series and shunt leads sharing space on the same bonding pad, the shunt tuning leads can be implemented from the top side in a flip-chip IPD, and the series drain can be directly connected to the drain lead from the bottom side. More generally, pre-matching, harmonic termination, and / or device interconnects can be achieved from each top, bottom, or both sides of the transistor bonding pad using a combination of conductive via connections and integrated interconnects as described herein.

[0061] Therefore, embodiments of the present invention can use a combination of stacked wafer topology and transistor dies containing through-hole interconnect structures to significantly reduce the problem of coupling between gate junction wires and drain junction wires, which can cause gain loss and instability. In some embodiments, gate and / or drain junction wires can be eliminated or reduced, and thin, low-profile conductive traces in integrated interconnects (e.g., pre-matched IPDs) can provide minimal coupling between gate junction wires and drain junction wires and / or lower coupling to output wires or traces.

[0062] Embodiments of the present invention can be used in RF power products for 5G and base station applications, as well as in radar and / or monolithic microwave integrated circuit ("MMIC") type applications. For example, a group III nitride-based RF amplifier can be implemented as an MMIC device, wherein one or more transistors are implemented in a single integrated circuit die together with the associated impedance matching and harmonic termination circuitry of the transistors.

[0063] FIG1A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and through-hole interconnect structure according to certain embodiments of the present invention. As shown in FIG1A, certain embodiments of the present invention provide an RF power device package 100, which includes: an active transistor die 105 including at least one conductive through-hole structure 105v; and a capacitor chip or die 104 (e.g., a MOS capacitor) mounted on an attachment surface 101s of a package substrate 101, wherein an integrated interconnect device (illustrated as an IPD or other passive device 110i) is opposite to the attachment surface 101s.

[0064] The active die 105 may include power transistor devices, for example, defining an RF power amplifier. In some embodiments, the active die 105 may include discrete multi-stage MMICs and / or multipath (e.g., Doherty) transistor devices. A conductive via structure 105v may extend substantially through the semiconductor layer structure of the active die 105 to electrical connection contacts 105p (such as bonding pads) on different sides or surfaces of the active die 105. In some embodiments, the via structure 105v may include conductive gate vias 262, conductive drain vias 264, and / or conductive power vias 266 extending through a group III nitride-based semiconductor layer structure 230, as described in more detail below with reference to the active die 705 of Figures 7A to 7C.

[0065] The active transistor grains described herein may be implemented in silicon or using wide-bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. In a particular embodiment, the active grains may be based on group III nitrides (such as gallium nitride (GaN) and / or silicon carbide (SiC)), which include unit cell transistors connected in parallel in an upper portion of a semiconductor layer structure and a gate contact and / or a drain contact adjacent to a source contact on a lower or bottom surface of the semiconductor layer structure, the lower or bottom surface being adjacent to an attachment surface. The term “semiconductor layer structure” may refer to a structure comprising one or more semiconductor layers such as a semiconductor substrate and / or a semiconductor epitaxial layer. In Figure 1A, the active die 105 includes an RF GaN on a SiC die, and one of the contacts 105p (in this example, a drain contact) includes a drain via structure 105v (in this example, a through silicon carbide (TSiC) via structure). The drain via structure 105v provides electrical connection and signal routing between the drain contact 105p on the top side or top surface of the die 105 and the bottom side or bottom surface of the die 105, which is adjacent to the attachment surface 101s.

[0066] In the example of FIG1A, substrate 101 is a passivation layer (RDL) structure. RDL 101 may include a conductive layer fabricated using semiconductor processing techniques. However, it will be understood that substrate 101 is not limited thereto; for example, substrate 101 may be a printed circuit board (e.g., a multilayer printed circuit board with metal traces), a ceramic substrate including conductive vias and / or conductive pads, or any other suitable mounting surface for active die 105. The bottom side of RDL 101 includes package leads (specifically, gate 102g, drain 102d, and source 102s leads, collectively referred to as package leads 102) that conduct electrical signals between components on attachment surface 101s and an external device (not shown), such as an external circuit board. Attachment surface 101s may include one or more conductive die pads 103, which in some embodiments may provide an electrical ground for components of package 100. RDL 101 includes vias and / or multilayer conductive wiring for transmitting signals from the bottom-side drain pad 105p to the external drain lead 102d of package 100. The signal traces in RDL 101 may have sufficient spacing (e.g., greater than about 5 µm) away from the source lead 102s to avoid shorting the signal to ground and / or introducing harmful parasitic coupling.

[0067] Because RF amplifiers are typically used in high-power and / or high-frequency applications, high levels of heat can be generated within the transistor die during operation. If the transistor die becomes overheated, the performance of the RF amplifier (e.g., output power, efficiency, linearity, gain, etc.) can deteriorate and / or the transistor die may be damaged. Thus, RF amplifiers are typically housed in packages that can be optimized or otherwise configured for thermal removal. In the example of FIG1A, the source lead 102 includes or is attached to a conductive heat dissipation structure 103 (e.g., a heat sink) that provides thermal conductivity (illustrated as an embedded conductive block or via). Specifically, a section of RDL 101 beneath the transistor die 105 may be filled (e.g., more than about 85% filled, fully filled, or almost fully filled) with a high-density conductive array 103 of copper vias to transfer heat away from the transistor of the transistor die 105. For example, in an embedded package process, the conductive structure 103 may also be filled with an embedded copper block or coin. The transistor die 105 and capacitor chip 104 are attached to the attachment surface 101s of RDL 101 using die attachment material 107 and techniques (such as eutectic material, pre-coating (e.g., AuSn pre-coating), preforming, sintering (e.g., Ag-sintering)).

[0068] Referring again to FIG1A, in the absence of a wire connection between the active transistor 105 and the package lead 102, one or more connections between the active transistor 105 (specifically, between contacts or bonding pads 105p on one of the top sides or surfaces of the transistor 105) and the package lead 102 are implemented by an integrated interconnect 110i (in this example, an IPD 110i) and / or a through-hole structure 105v. The connection provided by the through-hole structure 105v may further include one or more conductive elements (e.g., conductive traces or vias) in the substrate 101. The connection provided by the passive device 110i is opposite to (but not in) the attachment surface 101s to which the bottom side or surface of the active transistor 105 is attached or to the substrate 101. More specifically, a bonding pad 105p on the top surface of one of the transistor chips 105 is connected to a bonding pad 110p on one of the surfaces facing the IPD 110i, and the bonding pad 110p of the IPD 110i is connected to the gate lead 102g via a conductive wiring structure 114. As stated above, the passive device 110i may include passive electronic components on a semiconductor or other substrate, such as resistors / transmission lines, inductors, and / or capacitors. The through-hole structure 105v may also provide some series inductance and / or resistance.

[0069] In Figure 1A, the components of the passive device 110i are configured to provide an input impedance matching network for a circuit (e.g., an RF amplifier circuit) defined by the transistor units of the active chip 105, and are illustrated as an IPD, but the passive device described herein is not limited to this. The input impedance matching circuit system matches the impedance of the basic components of the RF signal input to the RF power device package 100 with the impedance at the input of the active chip 105. In the example of Figure 1A, the IPD 110i incorporates an inductor and a transmission line configuration for pre-matching the fundamental frequency f0 and also for terminating harmonics (e.g., 2f0) that may exist at the input of the fundamental RF signal.

[0070] In the example of FIG1A, the IPD 110i for inputting the pre-matching network is a flip-chip device that includes bonding pads 110p on one surface of the IPD 110i. Therefore, the IPD 110i is "flip-chipped" on top of the transistor die 105 and a capacitor chip 104, such that the bonding pads 110p of the IPD 110i are aligned with the bonding pads 105p of the transistor die 105 and the bonding pads 104p of the capacitor chip 104, respectively. The IPD 110i may include conductive bumps 111 (e.g., conductive epoxy patterns or solder bumps pre-attached to the IPD 110 in some embodiments) for connecting the bonding pads 110p to the bonding pads 105p and 104p. Alternatively, a conductive bump 111 can be pre-placed on the bottom drain pad 105p of the transistor die 105 to connect the drain pad 105p to the package drain lead 102d through conductive traces and / or vias in the RDL 101.

[0071] By grinding the wafer (for a die or capacitor chip) and / or by using preforms 107 of different thicknesses to align the heights of elements 104 and 105 below IPD 110i, the top surfaces of capacitor chip 104 and transistor die 105 can be aligned to the same height. Thus, package 100 includes a stacked structure having one of elements 104 and 105 attached to attachment surfaces 101s (which provide electrical connection to ground) between substrate 101 and integrated interconnect 110i. Without individual bonding wires extending between elements 104 and 105 and lead 102, integrated interconnect 110i, combined with at least one through-hole structure 105v, provides electrical connection between elements 104, 105 and lead 102. An encapsulation material (illustrated as a plastic outer molding part (OMP) 113) encapsulates or otherwise protects the dies 105, 110 while providing access to the leads 102 for connection to circuitry or devices outside the package 100, generally referred to herein as external devices. The outer molding part 113 may substantially surround the dies 105, 110 and may be formed of a plastic or a plastic polymer compound, thereby providing protection against external environmental influences. Advantages of the outer molding part type of package include a reduced overall height or thickness of the package and design flexibility in the configuration and / or spacing between the leads 102. In some embodiments, the outer molding part type package as described herein may have a height or OMP thickness of approximately 400 micrometers (µm) to approximately 700 µm. In other embodiments, the grains 105, 110 may be contained in an open-cavity package (e.g., a thermally enhanced package (TEPAC or T3PAC)) comprising a ceramic material, the open-cavity package defining a cavity surrounding the grains 105, 110 and having a height or thickness of about 1400 micrometers (µm) to about 1700 µm.

[0072] Figure 1B is an equivalent circuit diagram of one embodiment of Figure 1A. The input pre-matching network is implemented by IPD 110i and input capacitor 104 to provide an LC matching circuit (e.g., a low-pass LC) at the fundamental frequency f0 and a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for the optimal termination harmonic frequency (e.g., 2f0). The series transmission line 110r in the input IPD 110i can be selected to provide a suitable impedance transformation from transistor die 105 to gate lead 102g. The series transmission line (e.g., provided by conductive structure 110r) can be considered as an extension of the board transmission line matching network, and the electrical width can be selected or configured to achieve the desired characteristic impedance for impedance matching. The drain via 105v provides a series drain connection from the drain contact 105p on the bottom side of the transistor die 105 to the drain lead 102d, and it contains some internal inductance.

[0073] The series inductance injected through the gate and / or drain via 105V as described herein can be a small fraction of the series inductance injected through comparable gate and drain junction wires (e.g., approximately 15% to 20% of the inductance injected through conventional gate and drain junction wires). This ensures an optimal amount of series inductance for various matching circuits of group III nitride-based RF amplifiers. Thus, the gate and / or drain via 105V as described herein can contribute to impedance matching and / or harmonic termination circuitry at the input and / or output of transistor die 105. Further contributions can be made within the package substrate 101, as shown in Figures 2A and 2B.

[0074] FIG2A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and through-hole structure according to certain embodiments of the present invention. As shown in FIG2A, an RF power device package 200 includes: an active transistor die 105 including a plurality of through-hole structures 105v; and a capacitor chip or die 104 (e.g., a MOS capacitor) mounted on an attachment surface 101s of a package substrate 101, wherein an integrated interconnect (illustrated as an IPD or other passive device 110i) is opposite to the attachment surface 101s. Package 200 includes components and connections similar to those shown in Figure 1A, but in the example of Figure 2A, both the gate and drain contacts 105p include separate through-hole structures 105v (in this example, separate TSiC through-hole structures), which provide electrical connections and signal routing between the gate and drain contacts 105p on the top side or surface of die 105 and the bottom side or surface of die 105 adjacent to attachment surface 101s.

[0075] In Figure 2A, harmonic termination is implemented on the input side using the gate contact 105p on the bottom side of the transistor die 105. The bottom gate contact 105p contacts the conductive trace wiring 101lci configured to provide additional inductance and shunt capacitance on the RDL 101. Since the amount of inductance and / or capacitance that may be required for input harmonics can be relatively small, the desired impedance for input harmonic termination can be achieved by combining the inductance provided by the gate-side via 105v with the additional conductive trace wiring 101lci (e.g., conductive traces and open shunt stubs) on and / or in the RDL 101. Therefore, more specifically, the flip-chip IPD 110i and capacitor die 104 used for input pre-matching can be configured to provide impedance matching at the fundamental frequency f0, for example, by using a smaller capacitor die 104 with fewer capacitors (shown as a single capacitor C in FIG. 2B) under the flip-chip IPD 110i. That is, due to the gate via 105v, the top gate contact 105p can be dedicated to impedance matching through the IPD 110i, while the bottom gate contact 105p can provide a connection for the input harmonic termination 101lci (where the impedance of the gate via 105v defines a portion of the input harmonic termination). Moreover, compared to FIG. 1A, in the case where there is an independent connection between the capacitor die 104 and the source lead 102s in RDL 101, the conductive structure 103 (e.g., a copper block) is reduced in size and confined below the transistor die 105.

[0076] Figure 2B is an equivalent circuit diagram of one embodiment of Figure 2A. Similar to that shown in Figure 1B, the input pre-matching network is implemented by IPD 110i and input capacitor 104 to provide an LC matching circuit (e.g., a low-pass LC) at the fundamental frequency f0. In Figure 2B, the input harmonic termination is provided in the package substrate 101 by the inductance L and capacitance C of the conductive trace wiring 101lci. The connection between the gate lead 102g and the drain lead 102d is provided by the series transmission line 110r in IPD 110i and the series inductance of the drain via 105v, respectively.

[0077] FIG3A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and through-hole structure according to certain embodiments of the present invention. As shown in FIG3A, certain embodiments of the present invention provide an RF power device package 300, which includes an active die 105 and capacitor chips or dies 104, 106 mounted on an attachment surface 101s of a package substrate 101. As shown in FIG2A, the gate and drain contacts 105p of the transistor die 105 both include separate conductive through-hole connection structures 105v (in this example, separate TSiC through-hole structures), which provide electrical connections and signal routing between the top side of the die 105 adjacent to the attachment surface 101s and the gate and drain contacts 105p.

[0078] The package 300 of Figure 3A further includes individual integrated interconnects (illustrated as passive devices 110i, 110o; collectively referred to as 110) opposite the attachment surface 101s and connected to the gate and drain contacts or pads 105p at the top side of the transistor die 105. Specifically, the components of the passive device 110 are configured to provide an impedance matching network for the input 110i and output 110o of a circuit (e.g., an RF amplifier circuit) defined by the transistor of the active die 105, and are illustrated as a high-Q IPD, but the passive device as described herein is not limited thereto. The input impedance matching circuit can match the impedance of the basic components of the RF signal input to the RF power device package 300 with the impedance at the gate pad 105p on the top side of the transistor 105, and the output impedance matching circuit can match the impedance of the basic components of the RF signal output from the RF power device package 300 with the impedance of the circuit system connected to the drain pad 105p on the top side of the transistor 105. In the example of Figure 3A, the IPD 110 for the input and output pre-matching network includes flip-chip devices with individual bonding pads 110p on one surface of the IPD 110. These flip-chip devices are "flipped" onto the top of the transistor die 105 and capacitor chips 104, 106, such that the bonding pads 110p of the IPD 110 are aligned with the bonding pads 105p of the transistor die 105 and the bonding pads 104p, 106p of the capacitor chips 104, 106, respectively, and are connected to the bonding pads 105p and 104p, 106p by conductive bumps 111. As stated above, the top surfaces of the capacitor chips 104, 106 and the transistor die 105 can be aligned to the same height by grinding the wafer (for the die or capacitor chip) and / or by using preforms 107 of different thicknesses to align the heights of the components 104, 105 and 106.

[0079] Referring again to FIG3A, harmonic termination at both the input and output of transistor 105 is implemented by gate and drain vias 105v, bottom contacts or bonding pads 105p, and trace wirings 101lci and 101lco on RDL 101. Specifically, the gate via 105v and gate contacts 105p at the bottom of transistor 105 are connected to the conductive trace wirings 101lci on RDL 101. The conductive trace wirings 101lci are configured to provide additional inductance and shunt capacitance to short-circuit ground harmonics (e.g., 2f0) of the basic RF signal, which may be present at the input of active transistor 105. Similarly, the drain via 105v and drain contact 105p on the bottom side of transistor 105 are connected to the conductive trace wiring 101lco on RDL 101. The conductive trace wiring 101lco is configured to provide additional inductance and shunt capacitance for short-circuiting ground harmonics of the basic RF signal, which can be presented at the output of active chip 105.

[0080] Therefore, the flip-chip IPDs 110i and 110o on the gate and drain pads 105p at the top side of the transistor die 105 are dedicated to pre-matching the fundamental frequency f0 at the input and output of the transistor die 105. As in the example of FIG2A, a single capacitor 104 (e.g., a MOS capacitor) can be connected to the input at the top side of the transistor die 105 to provide an impedance matching circuit system, since the input harmonic termination circuit system is implemented by trace wiring 101lci connected to the input at the bottom side of the transistor die 105 via the gate via 105v. Similarly, a single capacitor 106 (e.g., a MOS capacitor or high-density capacitor for improved video bandwidth (VBW)) can be connected to the output at the top side of transistor die 105 to provide an impedance matching circuit system, since the output harmonic termination circuit system is implemented by trace wiring 101lco connected to the output at the bottom side of transistor die 105 via drain via 105v. That is, by using the bottom contact 105p for harmonic termination, the top contact 105p can be used only for fundamental frequency pre-matching, which is configured to achieve lower losses and thus provide higher RF performance. As shown in Figure 2A, with independent connections between capacitor dies 104, 106 and source leads 102s in RDL 101, the conductive structure 103 (e.g., a copper block) is reduced in size and confined below transistor die 105.

[0081] Thus, package 300 includes a stacked structure of elements 104, 105, and 106 having attachment surfaces 101s (which provide electrical connections to ground) attached to substrate 101 and integrated interconnects 110i, 110o. Where the individual bonding wires do not extend between elements 104, 105, and 106 and lead 102, one of the integrated interconnects 110i, 110o and a through-hole structure 105v provides electrical connections between elements 104, 105, and 106 and lead 102. Specifically, the through-hole structure 105v provides additional signal routing paths for gate and / or drain contacts 105p, thereby allowing greater flexibility in incorporating frequency-matched topologies at the inputs and outputs of transistor die 105.

[0082] Figure 3B is an equivalent circuit diagram of one embodiment of Figure 3A. Impedance matching at the fundamental frequency f0 is provided at the top side of transistor die 105, wherein the input pre-matching network is implemented by IPD 110i and input capacitor 104 to provide an LC matching circuit (e.g., a low-pass LC), and the output pre-matching network is implemented by output capacitor 106 and IPD 110o to provide a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls). Harmonic frequency (e.g., 2f0) termination is provided at the bottom side of transistor die 105, wherein the input harmonic termination is provided by the inductance and capacitance of conductive trace wiring 101lci in the package substrate 101 combined with gate via 105v, and the output harmonic termination is provided by the inductance and capacitance of conductive trace wiring 101lco in the package substrate 101 combined with drain via 105v. The series transmission line 110r in each of the input 110i and output 110o IPDs can be selected to provide suitable impedance transformation from the gate and drain pads 105p at the top side of the transistor die 105 to the gate 102g or drain 102d leads, respectively. The series transmission line (e.g., provided by the conductive structure 110r) can be considered as an extension of a board transmission line matching network, wherein the electrical width is selected or configured to achieve the desired characteristic impedance for impedance matching.

[0083] FIG4A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and conductive through-hole connection structure according to certain embodiments of the present invention. As shown in FIG4A, the RF power device package 400 includes active transistors 405i, 405o and an integrated interconnect (illustrated as an IPD or other passive device 410) mounted on a substrate 101. As in FIG1A, the substrate 101 is implemented as a conductive structure 103 (e.g., a copper block) providing an attachment surface 101s, source leads 102s, and thermal conductivity (e.g., a heat sink) for transferring heat away from the transistors 405i, 405o, and the connection provided by the passive device 410 is opposite to the attachment surface 101s or the substrate 101 (rather than in the attachment surface 101s or the substrate 101).

[0084] In the embodiment of FIG4A, active dies 405i and 405o define a multi-stage packaged RF power amplifier device (shown by way of example as two stages), such as a secondary GaN-based RFIC product. For example, active die 405i may be a smaller transistor die used to implement a driver stage, and active die 405o may be a larger transistor die 405o used to implement the output stage or final stage of the amplifier (e.g., approximately 6 to 8 or 7 to 10 times larger peripherally than the driver stage transistor die 405i). Transistor chips 405i and 405o are attached to the attachment surface 101s of the substrate 101 / conductive structure 103 providing source / hot leads 102s, wherein an interstage capacitor chip or chip 404 (e.g., a MOS or MIM capacitor chip having one or more independent capacitors integrated in a single chip) is provided on the attachment surface 101s between the chips 405i and 405o. An interstage passive device (refer to IPD 410) is attached to the two transistor chips 405i and 405o and the capacitor chip 404, and an electrical connection is provided between the two transistor chips 405i and 405o and the capacitor chip 404.

[0085] Specifically, in FIG4A, IPD 410 is die-mounted on top of transistor dies 405i, 405o and interstage matching capacitor wafer 404, such that the bonding pad 410p of IPD 410 is aligned with the bonding pads 405p and 404p of transistor dies 604i, 604o and capacitor wafer 404. The bonding pad 410p of IPD 410 may contact one or more drain pads 405p located on the top side of the driver stage transistor die 405i providing a driver drain lead 405d and one or more gate pads 605p located on the top side of the final stage transistor die 405o providing a final gate lead 405g. IPD 410 may include conductive bumps 111 (e.g., conductive epoxy patterns or solder bumps pre-attached to IPD 410 in some embodiments) for connecting bonding pad 410p to bonding pads 405p and 404p when there is no wire bonding between bonding pad 410p and bonding pads 405p and 404p. The top surfaces of capacitor wafer 404 and transistor dies 405i and 405o can be aligned to the same height by grinding the wafer (for a die or capacitor chip) and / or by using preforms 107 of different thicknesses for aligning the heights of elements 404, 405i, and 405o connected using IPD 410.

[0086] In the multistage amplifier 400, IPD 410 includes a passive component defining an interstage matching circuit system configured to provide impedance matching between the output of the driver stage transistor 405i and the input of the output stage transistor 405o, that is, matching the load of the driver transistor 405i to the input of the final transistor 405o. Although illustrated with reference to two stages 405i and 405o, it will be understood that multiple input or output transistors may be presented on the attachment surface 101s, with the output of one stage connected to the input of the next stage via individual IPDs 410.

[0087] Conductive via structures 405v (in this example, TSiC via structures) are used to implement connections from package leads 102g and 102d to gate and drain pads 405p on the bottom side (adjacent to attachment surface 101s) of dies 405i and 405o, respectively. Specifically, the driver-level transistor die 405i includes a gate via 405v extending from the gate pad 405p on the top side of die 405i to the gate pad 405p on the bottom side of die 405i, thereby providing connections from the bottom side of die 405i to conductive traces 414 on RDL 101 and external gate leads 102g. Similarly, the final transistor die 405o includes a drain via 405v extending from the drain pad 405p on the top side of the die 405o to the drain pad 405p on the bottom side of the die 405o, thereby providing a connection from the bottom side of the die 405o to the conductive trace 414 on the RDL 101 and the external drain lead 102d.

[0088] Conductive through-hole connection 405V provides low-inductance and low-loss connections to the input and output of the multi-stage packaged RF power amplifier 400. In some embodiments, connection or bonding pads 405p on the bottom side of dies 405i and 405o can be used for RF input leads 102g and RF output leads 102d, while connection or bonding pads 405p on the top side of die 405i and on the top side of the final die 405o can be connected to a high-inductance element (e.g., a DC choke) and can be used for DC bias feed of the RF power amplifier device 400.

[0089] Figure 4B is an equivalent circuit diagram of one embodiment of Figure 4A. As shown in Figure 4B, the interstage matching network is implemented by capacitor 404 and passive device 410 to provide a shunt-L pre-matching network Ls at the output of driver stage transistor 405i and at the input of final stage transistor 405o, and to provide a series LCL network connecting one of the driver stage transistor 405i and the final stage transistor 405o. This topology can provide a wideband response for a multistage RF power amplifier product. It will be understood that the interstage impedance matching network between transistor 405i and transistor 405o is shown in Figure 4B only by way of example, and the interstage passive device 410 providing electrical connection between two or more active chips according to an embodiment of the present invention may include or implement other network topologies.

[0090] Furthermore, in some embodiments, the capacitor 404 may not be located below the output IPD 410, but rather the capacitor (for example) may be integrated into the IPD 410 as a MIM capacitor C. In some embodiments, the MIM capacitor C may be formed by providing an insulating material between one of the conductive elements of the IPD 410 and one or more of the bonding pads 410p, as illustrated in the examples of Figures 5A and 5B.

[0091] FIG5A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and conductive through-hole connection structure according to certain embodiments of the present invention. As shown in FIG5A, the RF power device package 500 includes an active die 105 and an integrated interconnect (illustrated as IPD or other passive device 110ic, 110o; collectively referred to as 110) mounted on a package substrate 101 to provide electrical connections between the input and output of the transistor die 105 and package leads 102g and 102d, respectively. Specifically, in FIG5A, the IPD 110o is flip-chip mounted on top of the transistor die 105 and the capacitor chip 106, such that the bonding pad 110p of the IPD 110o is aligned and in contact with the drain pad 105p and the bonding pad 106p via conductive bumps 111 (on the top side of the transistor die 105 and the capacitor chip 106).

[0092] A drain pad 105p on the top side of transistor die 105 is dedicated to impedance matching and connected to a flip-chip IPD 110o containing passive electronic components configured to implement an impedance matching circuit system at the output of transistor die 105 (illustrated as a shunt-L inductor Ls pre-matching circuit). A drain via 105v (e.g., a TSiC via) connects the drain pad 105p on the top and bottom sides of transistor die 105. The drain pad 105p on the bottom side of transistor die 105 is connected to RDL 101 and external drain lead 102d, and the drain pad 105p exits the package 500 adjacent to the source / hot lead 102s. The other end of the flip-chip IPD 110o is connected to an output capacitor die 106 (e.g., a MOS capacitor or a high-density capacitor used to improve video bandwidth (VBW)) (and is supported by the output capacitor die 106). Since the entire drain pad 105p on the top side of the transistor die 105 and the flip-chip IPD 110o is used to provide a connection to the shunt-L inductor Ls, a lower loss inductance is achieved. The ground terminal of the output capacitor 106 is connected to the output ground lead G.

[0093] The transistor die 105 also includes a gate via 105v (e.g., a TSiC via) connecting the gate pads 105p on the top and bottom sides of the transistor die 105. The gate pads 105p on the bottom side of the transistor die 105 are connected to RDL 101, which includes conductive traces providing connections to the bonding pads 110p of the flip-chip IPD 110ic. The other end of the IPD 110ic is connected to the gate lead 102g. The IPD 110ic includes passive electronic components configured to implement an impedance matching circuit at the input of the transistor die 105. In the example of FIG5A, for example, a capacitor C (e.g., a MIM capacitor) is integrated into the IPD 110ic by providing an insulating material between one of the conductive elements of the IPD 110ic and one or more of the bonding pads 110p. Similar to Figure 2A, the conductive structure 103 (e.g., a copper block) is reduced in size and confined below the transistor grain 105, wherein the integrated capacitor C in the IPD 110ic in RDL 101 is separately connected to the source lead 102s.

[0094] Figure 5B is an equivalent circuit diagram of one embodiment of Figure 5A. The input pre-matching network is implemented by a flip-chip IPD 110ic, which provides an LC matching circuit (e.g., a low-pass LC) at the fundamental frequency f0 and a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for optimal termination of the harmonic frequency (e.g., 2f0) by means of the input capacitor C integrated therein. The output pre-matching network is implemented by a flip-chip IPD 110o, which provides a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) with an output capacitor C, which is provided by capacitor die 106 and connected to the ground lead G. The gate via 105V provides additional inductance between the gate pad 105P and the IPD 110IC, while the drain via 105V provides additional inductance between the drain pad 105P and the drain lead 102D.

[0095] As shown in Figures 5A and 5B, since the drain lead 102d exits the package 500 between the conductive structure 103 and the output ground lead G, the embodiments described herein provide a package footprint 500f and PCB circuit designs 515i, 515o to support this topology. Figure 5C is a plan view illustrating a package footprint 500f for the embodiment of Figure 5A. As shown in Figure 5C, with the drain lead 102d between the source / hot lead 102s and the smaller ground lead G, the ground connection to the output capacitor die 106 is implemented by a plurality (shown as three) of smaller ground leads G opposite to the source / hot lead 102s. The output ground lead G can be aligned with or corresponding to a ground via 515v in an external circuit board 515, such as an RF circuit board shown in Figure 5D.

[0096] Specifically, FIG5D has a top plan view of a transparent package 500, which illustrates the package area 500f of FIG5C and further illustrates the connection to an input matching circuit board 515i and an output matching circuit board 515o of an external circuit board 515. In some embodiments, the input matching circuit board 515i and the output matching circuit board 515o may include additional active and / or passive electrical components. The ground lead G may be large (e.g., relative to the surface area of ​​the area 500f) to create a constraint, but not so small as to substantially degrade the performance of the output matching circuit board 515o.

[0097] Figures 6A and 6B are plan and perspective views, respectively, illustrating examples of IPDs 110 and 410 providing impedance matching and integrated interconnects according to certain embodiments of the present invention. In the examples of Figures 6A and 6B, the precise value of the shunt-L inductance required for proper transistor pre-matching is implemented using a coil inductor Ls. The shape, width, and general design of the coil inductor Ls can be optimized to reduce losses. One end of the coil inductor Ls terminates on a bump or contact pad 110pl, which may be pre-attached with conductive bumps (e.g., 111) for attachment to a capacitor (e.g., 104) for pre-matching or a high-density capacitor (e.g., 106) for improving video bandwidth. The width of the series connection strip L used to implement the series inductor can be configured to provide the desired impedance transformation from the transistor die to the drain lead. Series connection strips L may extend between bumps or contact pads 110p and can be considered as an extension of a board transmission line matching network, and the width of each series connection strip L can be configured to provide a desired characteristic impedance. More generally, any of the passive devices described herein may include or be implemented using series connection strips L, which couple between contact pads 110p to provide electrical connectivity in addition to providing impedance transformation between contact pads 105p of one or more active dies 105 and / or between contact pads 105p of an active die 105 and a package lead 102. Similarly, any of the passive devices described herein may include or be implemented using coil inductors Ls, which are configured to be connected to capacitors (e.g., capacitors integrated into the passive device or external capacitors via contact pads 110p1).

[0098] Figures 8 and 9 are cross-sectional views illustrating examples of thermally enhanced integrated circuit device packages including stacked topologies and conductive through-hole connections according to further embodiments of the present invention. For ease of illustration, the feature sizes in Figures 8 and 9 are enlarged. As shown in Figures 8 and 9, RF power device packages 1100, 1200 include components 104, 105, 106, 110 and connections similar to packages 100a, 100b, and 100c of Figure 3A, but these connections are mounted on a conductive substrate or flange 1101, 1201 or protected by a cover member 1113, 1213 of the thermally enhanced package instead of a plastic outer molded part 113. Specifically, Figure 8 illustrates a first embodiment (referred to as a TEPAC package 1100), and Figure 9 illustrates a second embodiment of a thermally enhanced package according to an embodiment of the present invention (referred to as a T3PAC package 1200).

[0099] The TEPAC package 1100 of Figure 8 may be a ceramic-based package comprising a substrate 1101 and an upper housing, the upper housing comprising a cover member 1113 and a sidewall member 1104. The cover member 1113 and / or the sidewall 1104 may comprise a ceramic material (e.g., alumina) and may be defined on the conductive substrate or flange 1101 surrounding one of the open cavities of the components 104, 105, 106, 110. The conductive substrate or flange 1101 provides both an attachment surface 1101s for the components 104, 105, 106, 110 and thermal conductivity (e.g., a heat sink) for dissipating or otherwise transferring heat generated by components outside the package 1100.

[0100] The T3PAC package 1200 of Figure 9 can also be a ceramic-based package, comprising a substrate 1201 and an upper housing having a cover member 1213 and sidewall members 1204. Similarly, the cover member 1213 and sidewalls 1204 define an open cavity surrounding components 104, 105, 106, and 110 on the conductive substrate and flange 1201. Likewise, the conductive substrate and flange 1201 provide an attachment surface 1201s and thermal conductivity (e.g., a heat sink) for dissipating or otherwise transferring heat to the exterior of the package 1200. In the package 1200, the cover member 1213 may be a ceramic material (e.g., alumina), while the sidewall members 1204 are illustrated as a printed circuit board (PCB).

[0101] In Figures 8 and 9, flanges 1101 and 1201 may be a conductive material, for example, a copper layer / laminate or an alloy or metal matrix composite thereof. In some embodiments, flange 1101 may comprise a copper-molybdenum (CuMo) layer, CPC (Cu / MoCu / Cu), or other copper alloys (such as copper-tungsten CuW) and / or other laminate / multilayer structures. In the example of Figure 8, flange 1101 is illustrated as a CPC-based structure to which sidewall 1104 and / or cover member 1113 are attached. In the example of Figure 9, flange 1201 is illustrated as a copper-molybdenum (RCM60)-based structure to which sidewall 1204 and / or cover member 1213 are attached (e.g.) by a conductive adhesive 1208. To prevent the bottom gate and drain contact pads 105p of the active die 105 from short-circuiting the conductive flanges 1101 and 1201, a dielectric or other insulating material layer 101 is deposited or otherwise provided on the flanges 1101 and 1201, and conductive traces 101lci and 101lco are deposited or otherwise provided on the layer 101 (which are configured to provide additional inductance and / or shunt capacitance for input and output harmonic termination, respectively).

[0102] In Figures 8 and 9, active dies 105, passive devices (e.g., capacitor chips 104 and 106), and integrated interconnects (collectively referred to as 110) are attached to the attachment surfaces 1101s and 1201s of flanges 1101 and 1201 by respective conductive die attachment material layers 107. Flanges 1101 and 1201 also provide source leads 102s for packages 1100 and 1200. Gate leads 102g and drain leads 102d are provided by respective conductive wiring structures 1114 and 1214, which are attached to flanges 1101 and 1201 and supported by respective sidewall components 1104 and 1204.

[0103] The thickness of the sidewall components 1104, 1204 can result in a height difference between the components 104, 105, 106, 110 and the package leads 102g, 102d relative to the attachment surfaces 1101s, 1201s. For example, the combined height of the active die 105 and its integrated interconnects 110i, 110o relative to the attachment surface 1101s can be approximately 100 µm, while the gate lead 102g and drain lead 102d can be separated from the attachment surface 1101s by a distance of approximately 635 µm. In the examples of Figures 8 and 9, the individual wire connections 14 are therefore used to connect the package leads 102g, 102d to the contact pads 104p, 106p of the passive RF components 104, 106 on the attachment surfaces 1101s, 1201s. Thus, an RF signal input on a lead 102g can be transmitted via wire connection 14 to an input matching circuit 110i, 104 and a gate terminal 105p of the RF transistor amplifier chip 105, and the amplified output RF signal can be transmitted from the drain terminal 105p of the RF transistor amplifier chip 105 to the output matching circuit 110o, 106, and via lead 102d from the output matching circuit 110o, 106 to the connection wire 14 for output. However, it will be understood that the wire connection 14 can be omitted in other embodiments and different electrical connections can be used.

[0104] Compared to certain conventional designs, the integrated circuit device package incorporating a stacked topology according to embodiments of the present invention offers further advantages: the stacked interconnect structure allows for thinner or reduced-height packages. In external molding package embodiments (e.g., as shown in Figures 1 to 5), the wiring of the package leads at the bottom of the package also allows for package flexibility. For example, based on a modified package footprint, changes in the height and / or spacing of the package leads can be accommodated by modifying the layout of the traces on the circuit board / PCB. Thermally enhanced package embodiments (e.g., as shown in Figures 8 to 9) offer similar advantages, but may require changes in package dimensions (e.g., flange height and / or package lead spacing) relative to standardized dimensions.

[0105] Accordingly, in embodiments of the present invention, electrical connections between components (e.g., between circuit level components, such as between contact pads of one or more active transistors, and / or between contact pads of active transistors and the gate and / or drain leads of the package) are implemented by means of one or more integrated interconnect structures (e.g., conductive wiring structures and / or passive devices, such as IPDs) that are physically extended between the components, rather than by wire bonding. That is, the integrated interconnects can provide both an interconnect and an impedance matching / harmonic termination function, thereby reducing or eliminating the use of wire bonding in the package.

[0106] As described herein, certain embodiments of the present invention use an IPD "inverted" on top of the transistor and capacitor. The additional facade of the IPD, located above the ground plane of the package (e.g., provided by a conductive structure that may also define the attachment surface of the active die), provides higher Q and lower loss pre-matching. Much of the space beneath the inverted IPD can be used for capacitors, such as high-density capacitors typically used in outputs. Larger capacitance values ​​can be used in the available space, thus improving the video bandwidth of the device. To connect RF signals from the IPD back to the RDL and gate / drain leads, a copper pad or IPD with a TSV can be used. The IPD can be configured for both fundamental frequency pre-matching and optimal termination of harmonic frequencies.

[0107] Additionally, the transistor die described herein may include conductive via structures providing additional signal routing paths on multiple sides or surfaces of the active transistor die. According to a specific embodiment of the invention, a group III nitride-based RF amplifier is provided, comprising a transistor die having gate contacts, drain contacts, and / or source contacts on the same side of the transistor die (e.g., the bottom surface of the die adjacent to the attachment surface of the package substrate). The transistor die may include one or more gate vias and one or more drain vias for connecting a gate bus and / or a drain bus located on the top side of the transistor die to respective gate and drain contacts located on the back side of the transistor die. The length of the conductive vias may be a small fraction (e.g., 10% to 30%) of the length of conventional bonding conductors, and thus the inductance of the connection between the gate and drain buses and the carrier substrate can be significantly reduced.

[0108] Figures 7A, 7B, and 7C are cross-sectional views illustrating examples of group III nitride-based transistor grains 705a, 705b, and 705c (collectively referred to as 705) comprising conductive through-hole connections between bonding pads on opposing surfaces, according to certain embodiments of the present invention. Transistor grain 705 may represent transistor grains 105 and / or 405 as described herein.

[0109] Referring now to Figures 7A to 7C, the group III nitride-based transistor die 705 includes a semiconductor layer structure 230. A plurality of unit cell transistors are provided in an upper portion of the semiconductor layer structure 230, and a source contact 226 is provided on a lower or bottom surface 214 configured to be attached to a carrier substrate (e.g., an attachment surface 101s of a package substrate 101).

[0110] In the examples of Figures 7A to 7C, the transistor die 705 is a HEMT RF transistor amplifier die based on group III nitride, having an upper side or top surface 212 and a lower side or bottom surface 214. The RF amplifier die 705 includes a bottom-side metallization structure 220a, 220b, 220c (collectively referred to as 220), a semiconductor layer structure 230, and a top-side metallization structure 240a, 240b, 240c (collectively referred to as 240) stacked sequentially. The semiconductor layer structure 230 may include at least one channel layer 234 and a barrier layer 236 formed on a semiconductor or insulating substrate 232 (such as a SiC or sapphire substrate). The substrate 232 may be a growth substrate, and even if formed of a non-semiconductor material, the substrate 232 may be considered as part of the semiconductor layer structure 230. Due to the bandgap difference between the barrier layer 236 and the channel layer 234, and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced in the channel layer 234 at a junction between the channel layer 234 and the barrier layer 236.

[0111] As shown in Figures 7A to 7C, the top-side metallization structure 240 includes a top gate contact or bonding pad 242 and a top drain contact or bonding pad 244 on the top surface 212 of the die 705. The bottom-side metallization structure 220 may include a source contact 226 and one or more additional contacts 222 and / or 224. Each of these contacts 242, 244, 222, 224, and 226 may include, for example, an exposed copper pad. Specifically, in Figure 7A, the bottom-side metallization structure 220a includes a bottom gate contact 222, a bottom drain contact 224, and a bottom source contact 226 between the bottom gate contact 222 and the bottom drain contact 224 on the bottom surface 214. In Figure 7B, the bottom-side metallization structure 220b includes a bottom gate contact 222 and a bottom source contact 226 on the bottom surface 214. In Figure 7C, the bottom-side metallization structure 220c includes a bottom drain contact 224 and a bottom source contact 226 on the bottom surface 214. That is, in some embodiments (as shown in Figure 7A), when the source contact 226 is present between the gate contact 222 and the drain contact 224, the gate contact 222 and the drain contact 224 can be provided on the bottom surface 214 of the die, while in other embodiments (as shown in Figures 7B and 7C), only one of the gate contact 222 or the drain contact 224 is provided on the bottom surface of the die 705 adjacent to the source contact 226.

[0112] A plurality of conductive vias 262, 264, 266 (e.g., metal-plated or metal-filled vias) extend from the top metallization structure 240 through portions of the semiconductor layer structure 230 to provide electrical connections to the bottom metallization 220. For example, a source contact 226 on the bottom surface 214 of die 705 may be electrically connected to a source contact 256 via one or more source vias 266. Die 705 may further include conductive vias 262 and 264 extending between one or more of the top gate contact 242 and the top drain contact 244 to respective bottom gate contacts 222 and respective bottom drain contacts 224. Specifically, in Figures 7A and 7B, the top gate contact 242 may be physically connected and electrically connected to the bottom gate contact 222 via one or more conductive gate vias 262. In Figures 7A and 7C, the top drain contact 244 can be physically connected and electrically connected to the bottom drain contact 224 via one or more conductive drain vias 264.

[0113] Although conductive vias 262, 264, and 266 are illustrated as visible in the same cross-sectional view in Figures 7A to 7C, in some embodiments, one or more of vias 262, 264, and 266 may be offset from each other. For example, the three illustrated source vias 266 may be aligned along a common axis, while the gate via 262 and / or drain via 264 may be offset relative to the three source vias 266 along their aligned axis, as is more readily seen along line A-A' in the view of Figure 7D. Offsetting the conductive gate via 262 and the conductive drain via 264 from the conductive source via 266 increases the distance between the conductive vias 262, 264, and 266, which reduces the likelihood of cracks in the grain 705 due to mechanical weaknesses. This configuration also reduces parasitic gate-to-source and / or parasitic source-to-drain coupling that can occur between the various vias 262, 264, and 266, which can otherwise lead to gain loss and / or instability. In some embodiments, the conductive vias 262, 264, and / or 266 may be metal-plated (e.g., having an air-filled center instead of a metal-filled center) to reduce stress that can occur during thermal cycling.

[0114] In some embodiments, the top-side metallization structure 240 may include a plurality of gate, drain, and / or source "fingers" that can be connected via one or more separate buses on the upper surface of one of the semiconductor layer structures 230. FIG7D is a cross-sectional view taken along line D-D' of a portion of the top-side metallization structure 240 of the die 705a of FIG7A. Gate fingers 252, drain fingers 254, and source fingers 257 (and the connecting buses) define a portion of the electrodes of the die 705a that are respectively connected via gate, drain, and source. Gate fingers 252 may be formed of a material capable of forming a Schottky contact with a group III nitride-based semiconductor material (such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN). The drain fingers 254 and / or source fingers 257 may comprise a metal, such as TiAlN, capable of forming an ohmic contact with a group III nitride-based material. Gate fingers 252 may be electrically connected to each other via gate bus 243 and connected to the bottom gate contact 222 via one or more conductive gate vias 262, and drain fingers 254 may be electrically connected to each other via drain bus 245 and connected to the bottom drain contact 224 via one or more conductive drain vias 264. For better illustration of these components, one or more dielectric layers that help isolate the structures connecting the gate, drain, and source are not shown.

[0115] Figure 7D also shows one of the unit cell transistors 216. As shown, the unit cell transistor 216 includes a gate finger 252, a drain finger 254, and a source finger 257 together with the underlying portion of the semiconductor layer structure 230. Since the gate finger 252 is electrically connected to a common gate bus 243, the drain finger 254 is electrically connected to a common drain bus 245, and the source finger 257 is electrically connected together via a conductive power electrode via 266 and source pads 226 / 256, it can be seen that all the unit cell transistors 216 are electrically connected together in parallel.

[0116] Embodiments of the present invention can be built on a substrate or layer (e.g., a passivation layer (RDL) layer) and can be mass-assembled using modern enhanced wafer-level packaging technologies. Multiple parts can be built immediately, thereby reducing assembly time, cost, and yield issues. Additionally, wire bonding processes can be reduced or eliminated, saving time and cost. Heat generated by the transistor die can be effectively removed and conducted outside the package to a heat sink, for example, using a high-density copper-filled array or embedded copper block to effectively remove the heat (because for high-power RF applications, typical hollow or partially filled vias are not sufficiently effective at removing the heat). Embodiments of the present invention can be used in various Cellular Infrastructure (CIFR) RF power products (including but not limited to 5 W, 10 W, 20 W, 40 W, 60 W, 80 W, and different frequency bands), for example, for 5G and base station applications. Embodiments of the present invention are also applicable to radar and monolithic microwave integrated circuit (MMIC) type applications.

[0117] Various embodiments have been described herein with reference to the accompanying drawings, in which exemplary embodiments are shown. However, these embodiments may be embodied in different forms and should not be considered as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention is thorough and complete, and fully conveys the concept of the invention to those skilled in the art. Various modifications to the exemplary embodiments and general principles and features set forth herein will be readily apparent. In the drawings, the sizes and relative sizes of layers and regions are not shown to scale and may be enlarged in some instances for clarity.

[0118] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, such elements should not be limited by such terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any or all combinations of one or more of the associated listed items.

[0119] The terminology used herein is for the purpose of illustrating particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0120] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms used herein (e.g., those as defined in a common dictionary) shall be interpreted as having the meaning consistent with the meaning of such terms in the context of this specification and in the relevant art, and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0121] It will be understood that when an element (e.g., a layer, region, or substrate) is referred to as being "on," "attached," or extending "to" another element, the element may be directly on the other element, or an intervening element may be present. In contrast, when an element is referred to as being "directly on," "directly attached," or "directly" extending "to" another element, no intervening element is present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or an intervening element may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening element is present.

[0122] Relative terms (such as “below” or “above”, or “upper” or “lower”, or “horizontal” or “lateral” or “vertical”) may be used herein to describe a relationship between one element, layer or region and another element, layer or region as illustrated in the figures. It will be understood that, in addition to the orientations shown in the figures, these terms are also intended to encompass different orientations of the apparatus.

[0123] Embodiments of the present invention are illustrated herein by reference to cross-sectional views illustrating idealized embodiments (and intermediate structures). In the drawings, the thickness of layers and regions may be enlarged for clarity. Furthermore, it will be anticipated that the shapes illustrated may vary due to (for example) manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be considered as limited to the specific shapes of the regions illustrated herein, but will include shape deviations due to (for example) manufacturing processes. In the illustrated embodiments, elements illustrated by dashed lines may be optional.

[0124] Throughout this document, similar symbols refer to similar elements. Therefore, other diagrams may be consulted to illustrate the same or similar symbols, even if such same or similar symbols are not mentioned or illustrated in the corresponding diagrams. Moreover, other diagrams may be consulted to illustrate elements not represented by element symbols.

[0125] Typical embodiments of the present invention have been disclosed in the drawings and description, and although specific terms have been used, they are used only in a general and illustrative sense and not for limiting purposes. The scope of the present invention is set forth in the following claims. [Simplified Explanation of the Diagram]

[0033] FIG1A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and conductive through-hole connection structure according to certain embodiments of the present invention.

[0034] Figure 1B is an equivalent circuit diagram of one embodiment of Figure 1A.

[0035] FIG2A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and conductive through-hole connection structure according to certain embodiments of the present invention.

[0036] Figure 2B is an equivalent circuit diagram of one embodiment of Figure 2A.

[0037] FIG3A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and conductive through-hole connection structure according to certain embodiments of the present invention.

[0038] Figure 3B is an equivalent circuit diagram of one embodiment of Figure 3A.

[0039] FIG4A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and conductive through-hole connection structure according to certain embodiments of the present invention.

[0040] Figure 4B is an equivalent circuit diagram of one embodiment of Figure 4A.

[0041] FIG5A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology and conductive through-hole connection structure according to certain embodiments of the present invention.

[0042] Figure 5B is an equivalent circuit diagram of one embodiment of Figure 5A.

[0043] FIG5C is a bottom plan view illustrating one of the package occupies the area of ​​one embodiment of FIG5A according to certain embodiments of the present invention.

[0044] FIG5D is a top plan view illustrating one of the packaging areas of the embodiment of FIG5C according to certain embodiments of the present invention.

[0045] Figures 6A and 6B are plan and perspective views illustrating examples of IPDs according to certain embodiments of the present invention, respectively.

[0046] Figures 7A to 7C are cross-sectional views illustrating examples of active transistor grains with conductive through-hole connections between bonding pads on opposite surfaces according to certain embodiments of the present invention.

[0047] Figure 7D is a cross-sectional view taken through a portion of the top metallized structure of Figure 7A.

[0048] Figures 8 and 9 are cross-sectional views illustrating examples of thermally enhanced integrated circuit device packages including stacked topology and conductive through-hole connection structures according to further embodiments of the present invention.

Claims

1. A power amplifier device package comprising: One substrate; A first transistor chip includes a bottom surface on the substrate and a top gate contact and a top drain contact on a top surface of the first transistor chip opposite to the bottom surface, wherein at least one of the top gate contact or the top drain contact is electrically connected to a separate bottom gate contact or bottom drain contact on the bottom surface via a separate conductive via structure; and wherein the top gate contact or the top drain contact is connected to a first circuit configured to provide a first function on the top surface of the first transistor chip, and wherein the separate bottom gate contact or bottom drain contact is connected to a second circuit configured to provide a second function on the bottom surface of the first transistor chip.

2. The power amplifier device package of claim 1, wherein the top gate contact or the top drain contact is connected to the first circuit and there is no wire connection at the top surface of the first transistor die; and / or wherein the respective bottom gate contact or bottom drain contact is connected to the second circuit and there is no wire connection at the bottom surface of the first transistor die.

3. The amplifier device package of claim 1, wherein the first circuitry includes an inductor and the second circuitry includes a package lead.

4. The power amplifier device package of claim 3, wherein the inductor includes an integrated interconnect structure having a first contact pad on the top gate contact or the top drain contact.

5. The power amplifier device package of claim 4 further includes: conductive wiring on the substrate, wherein the respective bottom gate contact or drain contact is coupled to the package lead via the conductive wiring.

6. The power amplifier device package of claim 5, wherein the top gate contact or the top drain contact of the first contact pad having the integrated interconnect structure is electrically connected to the respective bottom gate or drain contact via the respective conductive via structure.

7. The power amplifier device package of claim 4, wherein the integrated interconnect structure includes an integrated passive device (IPD) of one or more passive electronic components.

8. The power amplifier device package of claim 7, wherein the integrated passive device (IPD) is configured to provide a parallel inductor.

9. The power amplifier device package of claim 7, wherein the first contact pad is electrically connected to a bonding pad of one or more passive electronic components on one surface of the IPD, the surface facing the top surface of the first transistor die, wherein the bonding pad is connected to the top gate or drain contact by a conductive bump between the bonding pad and the top gate or drain contact.

10. The power amplifier device package of claim 7, wherein the IPD includes an insulating material between its conductive elements to define at least one capacitor integrated in the IPD.

11. The power amplifier device package of claim 1, wherein the transistor unit of the first transistor die includes a first stage of a radio frequency (RF) amplifier circuit, and further includes: a second transistor die on the substrate, which includes a transistor unit defining a second stage of the RF amplifier circuit.

12. The power amplifier device package of claim 11, wherein the first transistor is attached to the substrate at a source contact on the bottom surface of the first transistor adjacent to the respective bottom gate contact or drain contact.

13. The power amplifier device package of claim 12, wherein each of the respective bottom gate or drain contacts comprises both a bottom gate contact and a bottom drain contact, and wherein the source contact is located on the bottom surface of the first transistor die between the bottom gate contact and the bottom drain contact.

14. The power amplifier device package of claim 1, wherein the first transistor die comprises a group III nitride-based material on silicon carbide (SiC), and wherein each conductive via structure comprises a through-silicon carbide (TSiC) via.

15. A power amplifier device package comprising: One substrate; A first transistor chip includes a top gate contact and a top drain contact on a bottom surface on the substrate and on a top surface of the first transistor chip opposite to the bottom surface, wherein at least one of the top gate contact or the top drain contact is electrically connected to a separate bottom gate contact or bottom drain contact on the bottom surface via a separate conductive via structure; and wherein the top gate contact or the top drain contact is connected to a first circuit that has no wire connection at the top surface of the first chip; and / or wherein the separate bottom gate contact or bottom drain contact is connected to a second circuit without wire connection at the bottom surface of the first chip.

16. The power amplifier device package of claim 15, wherein the first circuitry includes an inductor and the second circuitry includes a package lead. The integrated interconnect structure includes one or more passive electronic components, namely an integrated passive device (IPD).

17. The power amplifier device package of claim 16, wherein the inductor includes an integrated interconnect structure having a first contact pad on the top gate contact or the top drain contact.

18. The power amplifier device package of claim 17, wherein the integrated interconnect structure includes an integrated passive device (IPD) comprising one or more passive electronic components, wherein the first contact pad is electrically connected to the one or more passive electronic components and is connected to the top gate or drain contact via a conductive bump between the first contact pad and the top gate or drain contact.

19. The power amplifier device package of claim 17, wherein the top gate contact or the top drain contact of the first contact pad having the integrated interconnect structure is electrically connected to the respective bottom gate or drain contact via the respective conductive via structure.

20. The power amplifier device package of claim 17 further includes: a second die mounted on the substrate; and wherein the top gate contact or the top drain contact is coupled to the second die via the integrated interconnect structure.

21. The power amplifier device package as described in claim 20, wherein: The second die includes one or more capacitors; or the second die includes a plurality of transistor units defining a stage of an RF amplifier circuit.

Images