Integrated circuit structures with gate cuts above buried power rails

Abstract

An example IC structure includes a plurality of elongated channel structures (e.g., fins or nanoribbons) and one or more metal gate lines crossing over the fins / nanoribbons. A buried power rail (BPR) is formed between a pair of adjacent fins / nanoribbons. Once a BPR has been formed, an opening is formed above the BPR. The opening has an elongated shape that extends horizontally along the length of the BPR and extends vertically from the top of the BPR to the top of the IC structure, cutting through the metal gate lines. Portions of the opening between cut portions of metal gate lines may be filled with a dielectric material, thus forming metal gate cuts. A portion of the opening that is not between cut portions of a metal gate line is filled with an electrically conductive material and coupled to a source / drain contact of a transistor, thus forming a conductive via.

Description

[Technical Field]

[0001] This disclosure generally relates to the field of semiconductor devices, and more specifically, to integrated circuit (IC) structures. [Previous Technology]

[0002] A field-effect transistor (FET), such as a metal-oxide-semiconductor (MOS) FET (MOSFET), is a three-terminal device that includes a source, a drain, and a gate terminal, and uses an electric field to control the current flowing through the device. An FET typically includes a semiconductor channel material, source and drain regions disposed within the channel material, and a gate stack that includes at least a gate electrode material and may also include a gate dielectric material, disposed on a portion of the channel material between the source and drain regions. Because the gate electrode material typically includes a metal, the gate of a transistor is often referred to as a "metal gate."

[0003] Recently, FETs with non-planar architectures, such as FinFETs (sometimes also called "all-around gate transistors" or "triple gate transistors") and nanoband / nanowire transistors (sometimes also called "fully all-around gate transistors"), have been extensively explored as alternatives to transistors with planar architectures. [Summary of the Invention]

[0004] and

Implementation Method

[0016] Overview

[0017] The systems, methods, and apparatuses disclosed herein each have several inventive aspects, none of which alone is responsible for all the desired properties disclosed herein. Details of one or more embodiments of the subject matter described herein are set forth in the following description and figures.

[0018] To illustrate the IC structure with a gate cutout above the BPR presented herein, it may be helpful to first understand the phenomena that may function in such structures. The following basic information can be considered as the basis for correctly interpreting this disclosure. Such information is provided for illustrative purposes only and should not be construed in any way as limiting the broad scope of this disclosure and its potential applications. Although some of the descriptions below may be provided as examples of transistors implemented as FinFETs, the embodiments of this disclosure are equally applicable to IC structures employing other transistor architectures, such as nanoband or nanowire transistors, and planar transistors.

[0019] As mentioned above, recently, FETs with non-planar architectures, such as FinFETs and nanoband / nanowire transistors, have been extensively explored as alternatives to transistors with planar architectures.

[0020] In a FinFET, a fin-shaped semiconductor structure extends from a substrate (e.g., from a semiconductor substrate), and a gate stack may surround the upper part of the fin (that is, the part furthest from the substrate), possibly forming gates on three sides of the fin. The fin portion surrounded by the gate stack is called the "channel" or "channel portion" of the FinFET. The semiconductor material of the channel portion is usually referred to as the "channel material" of the transistor. Source and drain regions are disposed in the fins on both sides of the gate stack, forming the source and drain of the FinFET, respectively.

[0021] In nano-charged crystals, gate stacks can be arranged around a portion of an elongated semiconductor structure called a "nanoband," forming gates on all sides of the nanoband. The "channel" or "channel portion" of the nano-charged crystal is the portion of the nanoband around which the gate stack surrounds. Source and drain regions are formed in the nanoband on each side of the gate stack, respectively, constituting the source and drain of the nano-charged crystal. In some contexts, the term "nanoband" has been used to describe elongated semiconductor structures having a substantially rectangular cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" has been used to describe similar structures but with a substantially circular cross-section.

[0022] Taking FinFET as an example, the fabrication of an IC device with a FinFET array typically involves first providing a plurality of fins (usually parallel to each other), followed by providing metal gate lines spanning the fins. Typically, but not always, the metal gate lines are arranged substantially perpendicular to the length or longitudinal axis of the fins, and are arranged substantially parallel to the plane forming the support structure with the fins. The metal gate line spanning the first fin of the plurality of fins can form the gate of the transistor in the first fin, while the metal gate line spanning the adjacent second fin can form the gate of the transistor in the second fin. Because the metal gate lines span the first and second fins, the metal gate lines are electrically continuous on the first and second fins, thereby providing electrical coupling between the gates of the transistors in the first and second fins. Later in the fabrication process, it may be necessary to disrupt this continuity, for example, if the design requires decoupling of the gates of the transistors in the first and second fins. Furthermore, in the later stages of the manufacturing process, trench contacts are formed. The term "trench contact" as used here refers to a structure that provides electrical connectivity (i.e., a contact) to the source or drain (S / D) contacts of the transistor. Additionally, gate contacts are formed, where the term "gate contact" refers to a structure that provides electrical connectivity (i.e., a contact) to the gate of the transistor (i.e., the gate metal wire).

[0023] Over the past few decades, the expansion of features in ICs has been a driving force for the continuous development of the semiconductor industry. Shrinking features to increasingly smaller sizes allows for increased density of functional units within the limited space of a semiconductor wafer. For example, shrinking transistor size allows for the integration of a greater number of memory or logic devices on a wafer, thus facilitating the manufacture of products with larger capacities. However, this drive for ever-increasing capacity is not without its problems. The necessity of optimizing the performance of each device becomes increasingly important, and such optimization is by no means trivial.

[0024] As the size of IC devices continues to shrink, it is no easy task to disrupt the electronic continuity of metal gate lines (a procedure commonly referred to as "metal gate nicking") in a sufficiently accurate way to decouple the gates of transistors on adjacent fins cost-effectively without unintentionally impairing the performance of the IC device. A conventional approach involves using a combination of a mask and a material with sufficient etch selectivity to selectively etch the gate electrode material in the area where the metal gate line will be disrupted. Sufficient etch selectivity can be described between two materials if the etchant used to etch one material does not substantially etch the other, and vice versa. Selective etching is typically isotropic etching, meaning that a given material is etched substantially in all directions, and can cause the actual gate nick to expand significantly relative to the desired shape. In extreme cases, the lateral intrusion of such a gate nick can disable one or more fins.

[0025] This document describes an IC structure having a gate cutout above the BPR. An exemplary IC structure includes a plurality of elongated channel structures (e.g., fins or nanoribbons) of one or more semiconductor materials disposed on a support structure (e.g., substrate, wafer, die, or chip) that is substantially parallel to each other. One or more metal gate lines, substantially parallel to each other, may span the channel structures such that the metal gate lines are substantially perpendicular to the channel structures. The metal gate lines are elongated structures of one or more gate electrode materials disposed on portions of the channel structures (e.g., surrounding at least a portion of the channel structures) to form the gates of transistors within the structure. Power rails may be formed between a pair of adjacent channel structures. The power rails are referred to as "rails" because the one or more conductive materials of the power rails are shaped into elongated structures, for example, elongated structures substantially parallel to the channel structures. The power rails are referred to as "power" rails because they are configured to provide power to various portions of the transistors formed along the channel structures (e.g., for the source regions or contacts of various transistors). Furthermore, because one or more conductive materials of the power rail are lower than one or more gate electrode materials of the metal gate line (that is, the top of one or more conductive materials of the power rail is closer to the support structure than the bottom of one or more gate electrode materials of the metal gate line), the power rail can be referred to as a "buried" power rail. Once the BPR is formed, an opening with an elongated shape can be formed above the BPR, extending horizontally along the length of the power rail and vertically from the top of the BPR to the top of the IC structure (e.g., to the top of the metal gate line). Because the BPR and the opening are substantially parallel to the elongated channel structure, they are substantially perpendicular to the metal gate line, meaning that the opening will cut through the metal gate line. The opening portions between the cut portions of the metal gate line can be filled with one or more dielectric materials to form a metal gate cut, hereinafter referred to as a "BPR gate cut" or "gate cut above the BPR". The opening between the cut portions of the metal gate lines, such as the opening opposite the source contact of the transistor formed in the adjacent channel structure, can be filled with one or more conductive materials, which can be further coupled to the source contact of the transistor, thereby forming a conductive via that electrically couples the BPR to the source contact of the transistor, hereinafter referred to as a "BPR via".

[0026] As described herein, an IC structure having a gate cutout above the BPR can provide several advantages. Forming the BPR metal gate cutout and BPR via in the same opening above the BPR helps reduce the area required to form the gate cutout and BPR via, as well as the number of masking and process steps for forming the metal gate cutout and the electrical connection from the BPR to the transistor portion, thus reducing the complexity and cost of the manufacturing process. Providing the conductive material of the power rail in the opening between the channel structures, in contrast to providing it above the channel structures, can provide improvements in reducing metal line resistance and voltage drop. Ensuring that the top of the power rail is below the metal gate line (i.e., ensuring that the power rail is embedded) can provide further improvements in reducing parasitic capacitance. In some embodiments, the BPR can extend all the way through the support structure, thereby advantageously providing the electrical connection to the power rail from the back of the support structure. Furthermore, in some embodiments, when depositing one or more conductive materials for the BPR via, the mask for electrically coupling the BPR to the source region of the transistor can also be used as a mask. Using such a mask will result in the formation of BPR vias that are self-aligned to the trench contacts in at least one direction (e.g., in a direction parallel to the length of the BPR). BPRs with self-aligned BPR vias to trench contacts, as described herein, can be used to address the miniaturization challenges of conventional transistor arrangements and achieve high-density arrangements compatible with advanced complementary metal-oxide-semiconductor (CMOS) processes. Other technical effects will become apparent from the various embodiments described herein.

[0027] Elongated structures are referred to throughout this specification. As used herein, a structure is described as elongated if its length (measured individually along one axis of the exemplary coordinate system) is greater than its width (measured individually along another axis of the exemplary coordinate system) and its height (measured individually along a third axis of the exemplary coordinate system). For example, an elongated channel structure as described herein may be a fin or nanoribbon having a length measured along the x-axis of the coordinate system shown in the drawings, a width measured along the y-axis of the coordinate system shown in the drawings, and a height measured along the z-axis of the coordinate system shown in the drawings. Because the BPRs described herein and the openings above them are substantially parallel to the channel structure, their length, width, and height are also measured along the x-axis, y-axis, and z-axis of the xyz coordinate system shown in the drawings, respectively. On the other hand, when the metal gate lines are substantially perpendicular to the channel structure, as shown in the embodiments of the drawings, their length, width, and height are measured along the y-axis, x-axis, and z-axis of the illustrated xyz coordinate system, respectively.

[0028] Although the description provided herein relates to FinFET, such description is equally applicable to any other nonplanar FET embodiments besides FinFET, such as nanoband transistors, nanowire transistors, or transistors such as nanoband / nanowire transistors but having a cross-section of any geometry (e.g., elliptical or polygonal with rounded corners).

[0029] The IC structure described herein, particularly the IC structure with a gate cutout above the BPR as described herein, can be used to provide electrical connectivity between one or more IC-related components and / or various such components. In various embodiments, IC-related components include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. IC-related components may include components mounted on the IC or connected to the IC. The IC can be analog or digital and can be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the IC-related components. The IC can be used as part of a chipset for performing one or more related functions in a computer.

[0030] For illustrative purposes, specific figures, materials, and configurations have been set forth to provide a thorough understanding of the illustrative implementation. However, it will be apparent to those skilled in the art that this disclosure may be practiced without specific details, or / and may be practiced using only some of the described states. In other instances, well-known features have been omitted or simplified so as not to obscure the illustrative implementation.

[0031] Furthermore, reference has been made to the drawings that form part of this specification, in which illustrative embodiments that can be implemented are shown. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as limiting. For convenience, if there exists a set of drawings represented by different letters, such as Figures 7A-7B, such a set may be referred to herein without the letters, for example, "Figure 7".

[0032] In the figures, some schematic diagrams of exemplary structures of the various devices and components described herein may be shown with precise right angles and straight lines for ease of illustration only, and embodiments of these components may be curved, circular, or otherwise irregular in shape, determined by the manufacturing processes used to manufacture semiconductor device components, and sometimes unavoidably. Therefore, it should be understood that such schematic diagrams do not reflect actual process constraints, and features may appear less than "ideal" when examined using, for example, scanning electron microscopy (SEM) or transmission electron microscopy (TEM) images. Possible manufacturing defects may also be visible in images of such actual structures, such as imperfectly straight edges of material, tapered vias or other openings, unintentional rounded corners or variations in the thickness of different material layers, accidental spirals, compound dislocations at edges or within crystal regions, and / or accidental dislocation defects of single atoms or clusters of atoms. Other defects not listed herein but common in the field of device manufacturing may also exist. Furthermore, while a given number of components may be shown in some diagrams (e.g., a number of fins, a number of metal gate lines, a number of gate cutouts, a number of stacked trench contacts, etc.), this is merely for illustrative purposes, and an IC structure having at least one gate cutout above at least one BPR as described herein may include more or fewer of those numbers. Additionally, the various views shown in some diagrams are intended to illustrate the relative arrangement of the various components therein. In other embodiments, various IC structures or portions thereof having gate cutouts above the BPR as described herein may include other components or elements not shown (e.g., transistor portions that may be in electronic contact with any metal lines, etc., various other components). Examining layout and masking data, as well as reverse engineering components of the device to reconstruct the circuit using, for example, optical microscopy, TEM, or SEM, and / or examining cross-sections of the device to detect the shape and location of the various device components described herein, using, for example, physical failure analysis (PFA), will allow the determination of the presence of an IC structure having a gate cutout above the BPR as described herein.

[0033] Various operations can be described sequentially as a plurality of discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequential. These operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0034] For the purposes of this invention, the phrase "A and / or B" represents (A), (B), or (A and B). For the purposes of this invention, the phrase "A, B, and / or C" represents (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to refer to a measurement range, the term "between" includes the end of the measurement range.

[0035] The description uses the phrases "in embodiments" or "in multiple embodiments," which may each refer to one or more of the same or different embodiments. Terms such as "comprising," "including," "having," etc., used with respect to embodiments of the invention are synonymous. The invention may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side," to interpret various features of the figures; these terms are used only for ease of discussion and do not imply desired or required directions. The figures are not necessarily drawn to scale. Unless otherwise stated, ordinal adjectives such as "first," "second," and "third" are used to describe common objects, indicating only different instances of similar objects and not intended to imply that the objects described in this way must be in a given order in time, space, sequence, or any other manner.

[0036] In the following detailed description, various forms of the illustrative implementation may be described using terms commonly used by those skilled in the art in order to convey the essence of its operation to others skilled in the art.

[0037] For example, some descriptions may refer to a specific source region or drain region or contact as a source region / contact or a drain region / contact. However, unless otherwise stated, it is not important which region / contact of a transistor is considered a source region / contact and which region / contact is considered a drain region / contact, because under certain operating conditions, the names source and drain are often interchangeable. Therefore, the descriptions provided herein may use the term "S / D" region / contact to indicate that the region / contact can be a source region / contact or a drain region / contact.

[0038] In another example, if used, the terms "package" and "IC package" are synonyms, as are the terms "die" and "IC die," the term "insulating" means "electrically insulating," and the term "conducting" means "conducting," unless otherwise stated. Although some elements may be referred to in the singular herein, these elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials.

[0039] In another example, if used, the terms "oxide", "carbide", "nitride", etc. refer to compounds including oxygen, carbon, nitrogen, etc., respectively, the term "high k dielectric constant" refers to a material with a dielectric constant (k) higher than that of silicon oxide, and the term "low k dielectric constant" refers to a material with a dielectric constant lower than that of silicon oxide.

[0040] In another example, the term "interconnect" can be used to describe any element formed of conductive material for providing electrical connections to one or more elements associated with the IC and / or between various such elements. Typically, "interconnect" can refer to wires / wiring (sometimes also called "lines," "metal wires," or "trenches") and conductive vias (sometimes also called "vias" or "metal vias"). Typically, the term "conductor" can be used to describe conductive elements isolated by a dielectric material, which typically comprises an interlayer low-k dielectric disposed within the plane of the IC wafer. Such conductors are typically arranged in several layers of a metallized stack. On the other hand, the term "conducting via" can be used to describe conductive elements that interconnect two or more conductors of different layers of a metallized stack. For this purpose, vias can be provided substantially perpendicular to a plane of the IC wafer or on which a support structure for the IC structure is provided, and two conductors in adjacent layers or two conductors in non-adjacent layers can interconnect. The term "metallized stack" can be used to refer to one or more interconnected stacks for providing connectivity to different circuit elements of the IC wafer.

[0041] Furthermore, the term "connection" refers to a direct electrical or magnetic connection between connected things without any intermediate means, while the term "coupled" refers to a direct electrical or magnetic connection between connected things or an indirect connection through one or more passive or active intermediate means. The term "circuit" refers to one or more passive and / or active elements arranged to cooperate with each other to provide the required function.

[0042] The terms "substantially," "nearly," "approximately," "nearby," and "about" generally refer to within + / -20% of the target value in the context of a specific value as described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to within + / -5 to 20% of the target value in the context of a specific value as described herein or known in the art. Example: FinFET

[0043] FIG1 is a perspective view of an exemplary FinFET 100 according to some embodiments of the present disclosure. FinFET 100 shows an example of a transistor that can be implemented in various IC structures described herein, such as an IC structure with a gate cutout above the BPR as shown in FIG3-5. The FinFET 100 shown in FIG1 is intended to show the relative arrangement of some of these components. In various embodiments, FinFET 100 or portions thereof may include other components not shown (e.g., any additional material around the gate stack of FinFET 100, such as spacer material, electrical contacts with the S / D region of FinFET 100, etc.).

[0044] As shown in FIG1, the FinFET 100 may be disposed on a support structure 102, wherein the term "support structure" (which may also be referred to as "base") may refer to any suitable support structure on which a transistor may be constructed, such as a substrate, die, wafer, or chip. Also as shown in FIG1, the FinFET 100 may include a fin 104 extending from the support structure 102. The portion of the fin 104 closest to the support structure 102 may be surrounded by an insulating material 106, commonly referred to as "shallow trench" isolation (STI). The portion of the fin 104 surrounded on its sides by the STI 106 is commonly referred to as a "sub-fin portion" or simply "sub-fin". As further shown in FIG1, a gate stack 108 comprising at least one layer of gate electrode material 112 and selectively comprising one layer of gate dielectric 110 may be disposed on the top and sides of the remaining upper portion of the fin 104 (e.g., the portion above the STI 106 and not surrounded by the STI 106), thus surrounding the uppermost portion of the fin 104. The portion of fin 104 surrounding the gate stack 108 may be referred to as the "channel portion" (or simply "channel") of fin 104 because this is where a conductive channel can be formed during the operation of FinFET 100. The channel portion of fin 104 is part of the active region of fin 104. The first S / D region 114-1 and the second S / D region 114-2 (also commonly referred to as "diffusion regions") are located on opposite sides of the gate stack 108, forming the source and drain terminals of FinFET 100.

[0045] Typically, implementations of this disclosure can be formed or implemented on a support structure such as a semiconductor substrate composed of a semiconductor material system (including, for example, an N-type or P-type material system). In one implementation, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or silicon-on-insulator structures. In other implementations, the semiconductor substrate may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-V, II-VI, or IV group materials. Although several examples of materials that can form the substrate are described herein, any material that can be used as the basis for an IC structure with a gate cut-out above the BPR as described herein falls within the spirit and scope of this disclosure. In various embodiments, the support structure 102 may include any such substrate material that provides a suitable surface for forming the FinFET 100.

[0046] As shown in FIG. 1, the fin 104 may extend away from the support structure 102 and may be substantially perpendicular to the support structure 102. The fin 104 may include one or more semiconductor materials, such as a stack of semiconductor materials, such that the uppermost fin (i.e., the portion of the fin 104 surrounded by the gate stack 108) can be used as a channel region of the FinFET 100. Therefore, as used herein, the term "channel material" for a transistor may refer to this uppermost portion of the fin 104, or more generally, any portion of one or more semiconductor materials, wherein a conductive channel may be formed between the source and drain regions during transistor operation.

[0047] As shown in Figure 1, the STI material 106 may surround the sides of the fin 104. A portion of the fin 104 surrounded by the STI 106 forms a sub-fin. In various embodiments, the STI material 106 may be a low-k or high-k dielectric, including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Other examples of dielectric materials that can be used in STI material 106 include, but are not limited to, silicon nitride, silicon oxide, silicon dioxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0048] Above the sub-fin portion of fin 104, gate stack 108 may surround fin 104, as shown in FIG1. ​​Specifically, gate dielectric 110 may surround the uppermost part of fin 104, and gate electrode 112 may surround gate dielectric 110. The interface between the channel portion of fin 104 and the sub-fin portion of fin 104 is located near the end of gate electrode 112.

[0049] The gate electrode 112 may include one or more gate electrode materials, wherein the selection of the gate electrode material may depend on whether the FinFET 100 is a P-type metal-oxide-semiconductor (PMOS) transistor or an N-type metal-oxide-semiconductor (NMOS) transistor. For a PMOS transistor, gate electrode materials that can be used for different portions of the gate electrode 112 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that can be used for different portions of the gate electrode 112 may include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode 112 may include a stack of a plurality of gate electrode materials, wherein zero or more of the stacked materials are work function materials, and at least one of the stacked materials is a filler metal layer. Other materials / layers may be included alongside the gate electrode 112 for other purposes, such as serving as a diffusion barrier layer or / and an adhesive layer.

[0050] If used, the gate dielectric 110 may comprise a stack of one or more gate dielectric materials. In some embodiments, the gate dielectric 110 may comprise one or more high-k dielectric materials. In various embodiments, the high-k dielectric material of the gate dielectric 110 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for the gate dielectric 110 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the gate dielectric 110 may be annealed during the manufacture of the FinFET 100 to improve the quality of the gate dielectric 110.

[0051] In some embodiments, the gate stack 108 may be surrounded by dielectric spacers, not specifically shown in FIG1. ​​The dielectric spacers may be configured to provide separation between gate stacks 108 of different FinFETs 100 that may be provided along a single fin (e.g., different FinFETs provided along fin 104, although FIG1 shows only one such FinFET) and between the gate stack 108 and source / drain contacts disposed on each side of the gate stack 108. Such dielectric spacers may include one or more low-k dielectric materials. Examples of low-k dielectric materials that may be used as dielectric spacers include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, fused silica glass (FSG), and organosilicones such as sesquioxanes, siloxanes, and organosilicon glasses. Other examples of low-k dielectric materials that can be used as dielectric spacers include organic polymers such as polyimide, polynorbornene, benzocyclobutene, perfluorocyclobutane, or polytetrafluoroethylene (PTFE). Other examples of low-k dielectric materials that can be used as dielectric spacers include silicon-based polymer dielectrics such as silsesquioxane (HSQ) and methylsesquioxane (MSQ). Other examples of low-k materials that can be used as dielectric spacers include various porous dielectric materials, such as porous silicon dioxide or porous carbon-doped silicon dioxide, wherein large voids or pores are created in the dielectric to reduce the overall dielectric constant of the layer, since the voids can have a dielectric constant close to 1. When such dielectric spacers are used, the lower portion of fin 104, such as a sub-fin portion of fin 104, can be surrounded by STI material 106, which can include, for example, any high-k dielectric material described herein.

[0052] In some embodiments, the fin 104 may be composed of a semiconductor material system, including, for example, an N-type or P-type material system. In some embodiments, the fin 104 may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the fin 104 may include a combination of semiconductor materials, wherein one semiconductor material is used for the channel portion, and another material, sometimes referred to as a "barrier material," is used for at least a portion of the sub-fin portion of the fin 104. In some embodiments, the sub-fin and channel portion of the fin 104 are each formed of a single-crystal semiconductor, such as Si or Ge. In a first embodiment, the sub-fin and channel portion of the fin 104 are each formed of a compound semiconductor having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). The fin can be a binary, ternary, or quaternary III-V compound semiconductor, which is an alloy of two, three, or even four elements from Groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

[0053] For some exemplary N-type transistor embodiments (that is, for FinFET 100, which is an NMOS embodiment), the channel portion of fin 104 may advantageously comprise a III-V material with high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel portion of fin 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with the highest mobility, the channel portion of fin 104 may be an intrinsic III-V material, i.e., a III-V semiconductor material unintentionally doped with any electroactive impurities. In alternative embodiments, a nominal level of impurity doping may be present within the channel portion of fin 104, for example, to further fine-tune the critical voltage Vt, or to provide HALO bag-like implantation, etc. However, even in impurity-doped embodiments, the degree of impurity doping within the channel portion of fin 104 can be relatively low, for example, below 10¹⁵ dopant atoms per cubic centimeter (cm⁻³), and advantageously below 10¹³ cm⁻³. The sub-fin portion of fin 104 can be a III-V material having a band shift relative to the channel portion (e.g., a conduction band shift for N-type devices). Exemplary materials include, but are not limited to, GaAs, GaSb, GaAsSb, GaP, InAlAs, GaAsSb, AlAs, AlP, AlSb, and AlGaAs. In some N-type transistor embodiments of FinFET 100 where the channel portion of fin 104 is InGaAs, the sub-fin can be GaAs, and at least a portion of the sub-fin can also be doped with impurities (e.g., P-type) at a higher degree of impurity than the channel portion. In alternative heterojunction embodiments, both the sub-fin and the channel portion of fin 104 comprise a group IV semiconductor (e.g., Si, Ge, SiGe). The sub-fins of fin 104 may be first element semiconductors (e.g., Si or Ge) or first SiGe alloys (e.g., having a wide bandgap).

[0054] For some exemplary P-type transistor embodiments (that is, for the FinFET 100, which is a PMOS embodiment), the channel portion of fin 104 may advantageously be a group IV material with high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some exemplary embodiments, the channel portion of fin 104 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with the highest mobility, the channel portion may be an intrinsic III-V (or IV for P-type devices) material and is not intentionally doped with any electrically active impurities. In alternative embodiments, one or more nominal impurity doping levels may be present within the channel portion of fin 104, for example, to further set the threshold voltage Vt, or to provide HALO bag implantation, etc. However, even for impurity-doped embodiments, the impurity doping level within the channel portion is relatively low, for example, below 10¹⁵ cm⁻³, and advantageously below 10¹³ cm⁻³. The sub-fins of fin 104 can be group IV materials having a band shift relative to the channel portion (e.g., a valence band shift in a p-type device). Exemplary materials include, but are not limited to, Si or Si-rich SiGe. In some p-type transistor embodiments, the sub-fins of fin 104 are Si, and at least a portion of the sub-fins may also be doped with impurities (e.g., N-type) to a higher degree of impurity than the channel portion.

[0055] Turning to the first S / D region 114-1 and the second S / D region 114-2 on different sides of the gate stack 108, in some embodiments, the first S / D region 114-1 may be a source region and the second S / D region 114-2 may be a drain region. In other embodiments, the designation of the source and drain may be interchanged, i.e., the first S / D region 114-1 may be a drain region and the second S / D region 114-2 may be a source region. Although not specifically shown in FIG. 1, the FinFET 100 may also include S / D electrodes (often also referred to as "S / D contacts") formed of one or more conductive materials for providing electrical connectivity to the S / D region 114, respectively. Such S / D contacts are shown as S / D contact 408 in FIG. 4B and 5B. In some embodiments, the S / D region 114 of the FinFET 100 may be a doped semiconductor region, such as a doped channel material region of fin 104, to provide charge carriers for the transistor channel. In some embodiments, the S / D region 114 may be highly doped, for example, with a doping concentration of approximately 1.1021 cm⁻³, to advantageously form an ohmic contact with the corresponding S / D electrode, although these regions may also have lower doping concentrations and, in some implementations, form Schottky contacts. Regardless of the exact doping level, the S / D region 114 of the FinFET 100 is a region with a higher doping concentration than other regions, for example, higher than the doping concentration in the semiconductor channel material region between the first S / D region 114-1 and the second S / D region 114-2, and therefore may be referred to as a "highly doped" (HD) region.

[0056] In some embodiments, the S / D region 114 can typically be formed using a planting / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be planted into one or more semiconductor materials on the upper part of the fin 104 to form the S / D region 114. An annealing process to enable the dopant and allow them to diffuse further into the fin 104 can be performed after the ion planting process. In the latter process, one or more semiconductor materials of the fin 104 can first be etched to form grooves at locations for future source and drain regions. An epitaxial deposition process can then be performed to fill the grooves using the material used to fabricate the S / D region 114 (which may include combinations of different materials). In some implementations, a silicon alloy such as germanium silicon or silicon carbide can be used to fabricate the S / D region 114. In some implementations, the epitaxially deposited silicon alloy can be in-situ doped with dopant such as boron, arsenic, or phosphorus. In a further embodiment, the S / D region 114 may be formed using one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys. Although not specifically shown in the perspective view of FIG1, in a further embodiment, one or more layers of metal and / or metal alloys may be used to form the source and drain contacts (that is, the electrical contacts for each S / D region 114). Such S / D contacts are shown, for example, in FIG4B and 5B of the present invention.

[0057] The FinFET 100 may have a gate length GL (e.g., the distance between the first S / D region 114-1 and the second S / D region 114-2), a dimension measured along the fin 104 in the x-axis direction of the exemplary reference coordinate system xyz shown in FIG1. ​​In some embodiments, it may be between about 5 and 40 nanometers, including all values ​​and ranges therein (e.g., between about 10 and 35 nanometers, or between about 15 and 25 nanometers). The fin 104 may have a thickness, i.e., a dimension measured in the y-axis direction of the reference coordinate system xyz shown in FIG1. ​​In some embodiments, it may be between about 4 and 15 nanometers, including all values ​​and ranges therein (e.g., between about 5 and 10 nanometers, or between about 7 and 12 nanometers). Fin 104 may have a height, a dimension measured in the z-axis direction of the reference coordinate system xyz shown in Figure 1, which in some embodiments may be between about 30 and 350 nanometers, including all values ​​and ranges therein (e.g., between about 30 and 200 nanometers, between about 75 and 250 nanometers, or between about 150 and 300 nanometers).

[0058] Although the fin 104 shown in FIG. 1 is depicted as having a rectangular cross-section in the zy plane of the reference coordinate system shown in FIG. 1, the fin 104 may alternatively have a circular or angled cross-section at the "top" of the fin 104, and the gate stack 108 (including different portions of the gate dielectric 110) may conform to the circular or angled fin 104. In use, the FinFET 100 may form conductive channels on up to three "sides" of the channel portion of the fin 104, thereby potentially improving performance relative to single-gate transistors (which may form conductive channels on one "side" of the channel material or substrate) and dual-gate transistors (which may form conductive channels on both "sides" of the channel material or substrate).

[0059] Although Figure 1 shows a single FinFET 100, in some embodiments, multiple FinFETs may be arranged adjacent to each other along fin 104 (with some spacing between them). An example IC structure with a gate cutout above the BPR.

[0060] According to various embodiments of the present disclosure, Figures 2 and 3 provide top views of exemplary IC structures (that is, views of the xy plane of the exemplary reference coordinate system shown in Figure 1), wherein at least one gate cutout above at least one BPR can be implemented. In particular, according to some embodiments of the present disclosure, Figure 2 shows an IC structure 200 without any gate cutout above the BPR, while Figure 3 shows an IC structure 300 with a gate cutout above the BPR.

[0061] The legends provided in the dashed boxes at the bottom of Figures 2 and 3 show colors / patterns used to indicate the colors or patterns of some portions or materials of some of the elements shown in Figures 2 and 3, so that these diagrams are not confused by too many reference symbols (the same applies to the subsequent diagrams of this disclosure, which include legends at the bottom of the diagrams). For example, Figures 2 and 3 use different colors / patterns to identify channel material 204 (e.g., channel material of fin 104), dielectric material 206, and metal gate line 212. Furthermore, Figure 3 further uses different colors / patterns to identify dielectric material 306 of the BPR gate cutout, first trench contact (TCN1) material 312, second trench contact (TCN2) material 314, and dielectric material 316 of the gate cutout, which is not the BPR gate cutout (that is, not above the gate cutout of the BPR). Since it is not visible below dielectric materials 306 and 206, the BPR is not shown in Figure 3.

[0062] The IC structures shown in Figures 2 and 3, and in some subsequent figures, are examples of how a plurality of FinFETs 100 can be arranged in an IC device. Therefore, the IC structures shown in Figures 2-3 and some subsequent figures illustrate elements labeled with the same reference symbols used in Figure 1 to represent similar or analogous elements in these figures. For the sake of brevity, the description of a given element provided with reference to one figure need not be repeated for other figures. For example, Figures 2 and 3 show fins 104 (in particular, a plurality of such fins), and an example S / D region 114 for an example FinFET used in the IC structure of Figures 2 and 3. The same applies to the subsequent figures of this disclosure: elements with reference symbols used in one figure and shown again in another refer to similar or analogous elements, and therefore their description need not be repeated for each figure.

[0063] The IC structures shown in Figures 2 and 3 are intended to illustrate the relative arrangement of some of the components to explain some details of implementing the gate cut above the BPR. The IC structures shown in Figures 2 and 3 are not true top views, and if the IC structures were to be cut along the xy plane, they would not show some materials to avoid obscuring the illustration of the gate cut details above the BPR. For example, Figures 2 and 3 show the channel material 204 of fin 104, although fin 104 would not be visible in the actual cross-section of the xy plane above (e.g., at the top) the metal gate line 212 because they would be covered by a dielectric material, for example, dielectric material 206 and / or dielectric material 306. In another example, Figure 3 shows TCN2 material 314, although TCN2 material 314 is seen in the top view as can be seen, for example, in Figure 4B, other parts of the IC structure could be covered by dielectric material 306 (that is, dielectric material 306 would only extend beyond the filler of the BPR gate cut, but this is not shown in Figure 3). Therefore, in various embodiments, the IC structure (or portions thereof) shown in Figures 2 and 3 may include other components not shown (e.g., any other materials such as spacer material, STI, S / D area, or their electrical contacts, etc.). This also applies to the subsequent figures of this disclosure.

[0064] As shown in Figure 2, the IC structure 200 may include channel material 204 shaped into a plurality of elongated channel structures, such as fins 104. In some embodiments, the fins 104 may extend substantially parallel to each other, with their lengths measured along the x-axis. Figure 2 shows different examples of fins 104, with a dash and different reference symbols following the reference numerals for the fins 104 (the same symbols are used for other elements in other figures). An example of IC structure 200 showing four fins 104 is labeled fins 104-1 to 104-4, but in other embodiments, any other number of two or more fins 104 may be implemented in the IC structure 200. Furthermore, in other embodiments, the channel material 204 may be shaped into elongated channel structures other than fins, such as nanoribbons or nanowires, but such other elongated channel structures may also be represented by a top view of the channel material, as shown in Figures 2 and 3.

[0065] Once the fins 104 are fabricated, metal gate lines 212 can be provided above the fins 104 through multiple fins 104. In some embodiments, the metal gate lines 212 may extend substantially perpendicular to the fins 104. For example, if the fins 104 extend in the x-axis direction of the exemplary coordinate system used in this figure, as shown in FIG2 (that is, if each fin 104 may have a long axis substantially parallel to the support structure (e.g., support structure 102) on which they are provided and the different fins 104 may extend substantially parallel to each other), then the metal gate lines 212 may extend in the y-axis direction, as shown in FIG2. In some embodiments, the metal gate lines 212 may be shaped as ridges, substantially perpendicular to the length of the fins 104 and surrounding different portions of the fins 104. At least a portion of the metal gate lines 212 are disposed above the fins 104, that is, where the gates of the FinFET can be formed, as described with reference to FIG1, one or more gate electrode materials 112 may be included to form the gate stack 108 as described above. In some embodiments, all metal gate lines 212 (i.e., also between fins 104) are formed of one or more gate electrode materials 112. In some embodiments, the gate electrode material 112 used in a portion of a given metal gate line 212 may have a different material composition than the gate electrode material 112 used in another portion of said particular metal gate line 212. For example, the material composition of a portion of a given metal gate line 212 through a fin 104 in which an NMOS transistor will be formed may be different from the material composition of a portion of a metal gate line 212 through a fin 104 in which a PMOS transistor will be formed. For example, fins 104-1 and 104-4 may be fins in which an NMOS transistor can be formed, while fins 104-2 and 104-3 may be fins in which a PMOS transistor can be formed.

[0066] The dashed outline shown in Figure 2 illustrates an example of a transistor 202 formed in / along one of the fins 104 (therefore, transistor 202 is a FinFET), specifically in fin 104-3. FinFET 202 can be an example of FinFET 100 as described above. Figure 2 shows the S / D regions 114-1 and 114-2 of FinFET 202, while the portion of the metal gate line 212 traversing fin 104-3 forms the gate stack 108 of FinFET 202. Several other such FinFETs are also shown in Figure 2, although they are not specifically labeled with reference symbols to avoid confusion in the diagram.

[0067] In some embodiments, a plurality of FinFETs 202 may be arranged to form cell units (or simply "cells") 210 with specific logic functions / functionalities (the approximate outline of cell unit 210 shown in FIG. 2 has a dashed outline), and such cells may then be provided multiple times in the IC structure 200, for example, in an array. Of course, in other embodiments of the IC structure 200, the FinFETs 202 may be arranged in a manner that does not include repeating cell units and / or the cell units 210 may include portions of the IC structure 200 other than those shown in FIG. 2.

[0068] Figure 2 further illustrates that the portion of the IC structure 200 surrounding the upper part of the fin 104 may be surrounded by a dielectric material 206, which may include one or more of the dielectric spacer materials or interlayer dielectric (ILD) materials described herein. Although the top view of Figure 2 shows the top of the fin 104 in the portion where the metal gate line 212 does not cross the fin, in some embodiments, the dielectric material 206 may cover the top of the fin 104 in those portions (in which case the fin 104 will not be visible in the top view of the IC structure 200).

[0069] As described above, a given design may require cutting some metal gate lines 212 to accommodate the BPR. In some further embodiments, a given design may require cutting some metal gate lines 212 to disrupt the electrical continuity between different portions of the IC structure 200 and to decouple the gates of different FinFETs 202. FIG3 is a top view of an IC structure 300 similar to the IC structure 200 of FIG2, further showing an exemplary gate cut above the BPR according to some embodiments of the present disclosure. In particular, FIG3 shows the outline of the opening 310 above the BPR and the dielectric material 306 and TCN1 material 312 and TCN2 material 314 of the BPR gate cut. The outline of the opening 310, as shown in FIG3, is a thick black rectangular outline surrounding all dielectric material 306 and a portion of TCN2 material 314. The portion of opening 310 filled with dielectric material 306 provides a BPR gate cutout because these portions cut one or more metal gate lines 212 and are provided above the BPR (the BPR itself is not shown in FIG. 3 because it is located below opening 310, but can be seen in the cross-sectional views of FIG. 4A-4C). However, the outline of opening 310 as shown in FIG. 4A-4C is not necessarily a material boundary. For example, in FIG. 4A, dielectric material 306 may be a single material continuously inside and outside the outline of opening 310. In another example, in FIG. 4B and 4C, conductive material 314 may be a single material continuously inside and outside the outline of opening 310. FIG. 3 further shows an opening 308 filled with dielectric material 316. Opening 308 also provides a gate cutout because it cuts one of the metal gate lines 212, but it is not a BPR gate cutout because it is not provided above the BPR (which can be better seen from the cross-sectional views of FIG. 4A-4C). According to some embodiments of this disclosure, Figures 4A-4C provide cross-sectional side views of the IC structure 300 of Figure 3, having cross-sections taken along various planes. Specifically, Figure 4A shows a cross-section of the IC structure 300 taken along plane AA of Figure 3 (i.e., a cross-section along the yz plane of one of the metal gate lines 212), Figure 4B shows a cross-section of the IC structure 300 taken along plane BB of Figure 3 (i.e., a cross-section along the BPR via in the yz plane between adjacent metal gate lines 212), and Figure 4C shows a cross-section of the IC structure 300 taken along plane CC of Figure 3 (i.e., a cross-section along the BPR and the xz plane opening above the BPR, where the opening BPR gate notch and the BPR via are formed). Together, the various views of Figures 3 and 4A-4C provide a comprehensive illustration of the IC structure 300. Therefore, details of the IC structure 300 will now be described with reference to elements that can be seen in one of the views of Figures 3 and 4 but not in the other figures.

[0070] Figures 4A and 4B show a BPR 320 disposed between two adjacent fins, for example, between fin 104-2 and fin 104-3. The BPR 320 may include one or more conductive materials. In some embodiments, the various conductive materials described herein, such as one or more conductive materials of the BPR 320, may include one or more metals or metal alloys having metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, molybdenum, tungsten, and aluminum. In some embodiments, the conductive materials described herein may include one or more conductive alloys, oxides (e.g., conductive metal oxides), carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), or nitrides of one or more metals (e.g., hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, and aluminum nitride).

[0071] BPR 320 may have a length measured along the x-axis and be substantially parallel to fin 104. Therefore, in the horizontal direction, BPR 320 is substantially parallel to two adjacent fins 104-2 and 104-3 and extends between two adjacent fins 104-2 and 104-3. BPR 320 is "buried" because the top of BPR 320 (that is, the boundary of BPR 320 furthest from the support structure 102) is located below the metal gate line 212, as seen in the view of FIG4A. For example, in some embodiments, the top of BPR 320 may be a distance 402 below the bottom of the metal gate line 212, as shown in FIG4A, where distance 402 may be at least 5 nanometers, including all values ​​and ranges, such as at least 7 nanometers or at least 10 nanometers. Therefore, in the vertical direction, the BPR 320 can extend from a plane below the metal gate line 212 (e.g., a plate at a distance 402 from the metal gate line 212) and downward toward the support structure 102, possibly extending through the support structure. This is shown, for example, in Figure 4A, where the BPR 320 extends from a first surface 404-1 of the support structure 102 to a second surface 404-2 of the support structure 102. Thus, the BPR 320 can be electrically connected on the back side of the support structure 102 (i.e., on the first surface 404-1). A fin 104 is then provided on the second surface 404-2 of the support structure 102.

[0072] Analysis of the opening 310 in the various views provided in Figures 3 and 4A-4C shows that the opening 310 extends horizontally parallel to and above the BPR 320 (that is, the bottom of the opening 310 completely overlaps with the top of the BPR 320), while in the vertical direction, the opening 310 extends from the top of the BPR 320 (that is, the bottom of the opening 310 is a distance 402 from the bottom of the metal gate line 212 and is coplanar with the top of the BPR 320) to the top of the gate electrode material of the metal gate line 212. Since the opening 310 extends from the top of the dielectric material 306 all the way to the BPR 320, the opening 310 cuts through the metal gate line 212, effectively separating the gate electrode material of each metal gate line 212 into two parts. This can be seen in the view of Figure 4A, where the opening 310 divides the gate electrode material of the metal gate line 212 into a first part 412-1 and a second part 412-2. A portion of the opening 310 between the first and second portions 412-1 and 412-2 of the gate electrode material 212, labeled as portion 410-1 of the opening 310 in FIG. 4A, may be filled with one or more dielectric materials, such as dielectric material 306. Although the cross-section of FIG. 4A shows portion 410-1 of the opening 310 completely filled with dielectric material 306, in other embodiments, the filling of portion 410-1 may be partial (e.g., only at the sidewalls and / or bottom of the opening 310). Dielectric material 306 may include any of the aforementioned dielectric materials, such as any ILD material or spacer dielectric material. Thus, portion 410-1 of the opening 310 between the first and second portions 412-1 and 412-2 of the gate electrode material 212 forms the gate cutout of the gate electrode material 212 (that is, it electrically isolates the first and second portions 412-1 and 412-2 from each other) and is a so-called BPR gate cutout. Therefore, in the following text, portion 410-1 is referred to as "BPR gate cutout 410-1". The top view of Figure 3 illustrates several examples of BPR gate cutout 410-1 (that is, a metal gate cutout provided by portion 410-1 of opening 310 cuts through and electrically isolates portions of the single gate metal wire 212 from each other). However, generally, a BPR gate cutout can be formed as long as a portion of opening 310 electrically isolates the first and second portions 412-1 and 412-2 of a given gate electrode material of the gate metal wire 212. The first portion 412-1 of the gate electrode material of the gate metal wire 212 may then at least partially surround a portion of a channel structure (e.g., fin 104-2 in the example of IC structure 300), while the second portion 412-2 of the gate electrode material of the gate metal wire 212 may at least partially surround a portion of another channel structure (e.g., fin 104-3 in the example of IC structure 300).

[0073] The top view of Figure 3 shows that the opening 310 extends along the x-axis, such that, in addition to having a BPR gate cutout 410-1 each time the opening 310 cuts through another metal gate line 212, there are also portions of the opening 310 between adjacent gate metal lines 212, i.e., along the x-axis direction. Some of these portions may be at least partially filled with dielectric material 306, as can be seen in Figure 3, where the portion of the opening 310 is marked as portion 410-2. However, at least a portion of the opening 310 between a pair of adjacent gate metal lines 212 may be filled with one or more conductive materials, the portion of the opening 310 marked as portion 410-3 in Figure 3 and can be seen in the cross-sectional view of Figure 4B. Portion 410-3 forms a BPR via, which can be configured to electrically couple the BPR 320 to the S / D contact of the transistor 202. Therefore, in the following, portion 410-3 is referred to as "BPR via 410-3".

[0074] Compared to the BPR gate cutout 410-1, the BPR via 410-3 is not located between the first and second portions 412-1, 412-2 of the gate electrode material of any metal wire 212. In some embodiments, the BPR via 410-3 may be opposite to the S / D contact of a transistor formed in an adjacent channel structure, for example, the S / D contact opposite to the first S / D region 114-1. This is shown in the view of FIG4B, where the BPR via 410-3 may be opposite to the S / D contact 408, which is coupled to the S / D region 114 of one of the fins 104 (that is, the S / D contact 408 is coupled to the S / D region 114 of the fin 104-3 shown in FIG4B and FIG3). As shown in Figure 4B, the S / D contact 408 of fin 104-3 can be coupled to TCN1 312 (e.g., in conductive contact with it), and TCN1 312 can be coupled to TCN2 314 (e.g., in conductive contact with it), which in turn is coupled to BPR via 410-3 (e.g., in conductive contact with it). BPR via 410-3 is then coupled to BPR 320 (e.g., in conductive contact with it). However, in other embodiments, the electrical connections between BPR 320 and various components of the IC structure therein can be achieved in many other ways, all of which are within the scope of this disclosure. For example, even though Figure 3 illustrates BPR 320 coupled to the source region 114 of transistor 202 provided along fin 104-3, in other embodiments, BPR 320 can be coupled to the source region 114 of transistor provided along fin 104-2 of Figure 3.

[0075] Each of the BPR via 410-3, S / D contact 408, TCN1 312, and TCN2 314 may be composed of one or more conductive materials, such as those described above (e.g., refer to BPR 320), and in various embodiments, their respective material compositions may be the same or different. In some embodiments, the material compositions of BPR via 410-3 and TCN2 314 may be substantially the same (as shown in FIG. 4B, having the same pattern used to display these elements), for example, if the method of manufacturing BPR via 410-3 and TCN2 314 is to first form openings for BPR via 410-3 and TCN2 314, and then fill the openings with conductive material in a single metallization process.

[0076] FIG4C provides another illustrative cross-section of the IC structure 300, which depicts the different metal gate lines 212 on the planar back side of FIG4C with dashed outlines. The different metal gate lines 212 are labeled as metal gate lines 212-1 to 212-6 in FIG4C, corresponding to the illustration in FIG3, although FIG3 only shows the labels of metal gate lines 212-1 and 212-2 and does not show the remaining lines to avoid cluttering the diagram. In some embodiments, the BPR via 410-3 may be self-aligned to the TCN2 314 to which it is coupled in the x-axis direction of the exemplary coordinate system, which can be inferred from the top view of the IC structure 300 (i.e., FIG3) and can be seen in the cross-sectional view of FIG4C. In other words, one or more conductive materials of the BPR via 410-3 may be self-aligned to one or more conductive materials of the TCN2 314 in a direction parallel to the length of the BPR 320 (i.e., in the x-axis direction of the exemplary coordinate system). In this context, self-alignment might mean that one sidewall of BPR via 410-3 (e.g., sidewall 422-1 shown in FIG. 4C) can be in a single plane, with one sidewall of TCN2 314 coupled to said plane (e.g., sidewall 426-1, as shown in FIG. 4C), and the other sidewall of BPR via 410-3 (e.g., sidewall 422-2, as shown in FIG. 4C) can be in a single plane, with the other sidewall of TCN2 314 coupled to said plane (e.g., sidewall 426-2, as shown in FIG. 4C). This can be inferred from FIG. 3, where BPR via 410-3 is not visible because it is below TCN2 314 to which it is coupled. For the ideal case where the sidewalls of BPR via 410-3 and TCN2 314 are perpendicular to the support structure 102, the first pair of self-aligned (i.e., single-plane) sidewalls can be sidewalls along the first yz plane, and the second pair of self-aligned (i.e., single-plane) sidewalls can be sidewalls along the second yz plane, the distance of which is equal to the dimension of BPR via 410-3 in the x-axis direction. However, similar self-alignment considerations also apply to the non-ideal case where the sidewalls of BPR via 410-3 and TCN2 314 are not 100% perpendicular to the support structure 102. The self-alignment of BPR via 410-3, in the x-axis direction of the exemplary coordinate system, coupled to TCN2 314, may be the result of using a masking filler of TCN2 314 within the dielectric material 306 to form the opening for BPR via 410-3.

[0077] In this embodiment, TCN2 314 may completely overlap with BPR via 410-3 in the y-axis direction. However, in other embodiments (not specifically shown in this embodiment), TCN2 314 may only partially overlap with BPR via 410-3. In other words, in some embodiments, one or more conductive materials of TCN2 314 do not completely overlap one or more conductive materials of BPR via 410-3 in a direction perpendicular to the length of BPR 320 and parallel to the support structure 102 (that is, in the y-axis direction of the exemplary coordinate system). This may be due to the cut in TCN2 314 after the formation of BPR via 410-3.

[0078] Because both the BPR gate notch 410-1 and the BPR via 410-3 are formed within the opening 310, their widths (that is, the dimensions measured along the x-axis of the exemplary coordinate system) can be substantially the same. In some embodiments, their widths (and therefore the width of the opening 310) can be smaller than the width of the BPR 320, as shown in the embodiments of Figures 4A and 4B. However, in other embodiments, the width of the opening 310 can be substantially the same as the width of the BPR 320, for example, as shown in Figures 5A and 5B and described below.

[0079] Figures 5A and 5B show an IC structure 500 similar to IC structure 300, except that in IC structure 500, the width of opening 310 can be substantially the same as the width of BPR 320. Apart from this difference, the description of other IC structures 300 applies to IC structure 500, and therefore will not be repeated for the sake of brevity. The embodiment shown in Figures 5A and 5B may be advantageous because an opening similar to opening 310 can be formed first, extending downwards into the support structure 102, possibly extending to the first surface 404-1 of the support structure 102. This opening can then be filled with one or more conductive materials to form BPR 320 as described herein, followed by filling with one or more dielectric materials to form BPR gate cutout 410-1, and then a portion of the opening can be filled with one or more conductive materials to form BPR via 410-3, as described herein. In this manner, each of the BPR gate cutout 410-1 and the BPR through-hole 410-3 can be self-aligned to the BPR 320 in a direction perpendicular to the length of the BPR 320 and parallel to the support structure 102 (that is, in the y-axis direction of the exemplary coordinate system). In this context, self-alignment may mean that the first sidewall 502-1 of the BPR 320 can be in a single plane with the first sidewall 504-1 of the BPR gate cutout 410-1 (as shown in FIG. 5A) and with the first sidewall 506-1 of the BPR through-hole 410-3 (as shown in FIG. 5B), while the second sidewall 502-2 of the BPR 320 can be in a single plane with the second sidewall 504-2 of the BPR gate cutout 410-1 (as shown in FIG. 5A) and with the second sidewall 506-2 of the BPR through-hole 410-3 (as shown in FIG. 5B). As described above, the BPR gate notch 410-1 and the BPR via 410-3 are formed within a common opening 310. For both IC structure 500 and IC structure 300, this means that for a given BPR gate notch 410-1, the first sidewall 504-1 of the BPR gate notch 410-1 and the first sidewall 506-1 of the BPR via 410-3 are in a single plane, and the second sidewall 504-2 of the BPR gate notch 410-1 and the second sidewall 506-2 of the BPR via 410-3 are also in a single plane. Therefore, for both IC structure 500 and IC structure 300, the sidewall of the BPR gate notch 410-1 can be self-aligned with the sidewall of the BPR via 410-3.

[0080] Returning to IC structure 300, but also applicable to IC structure 500, as shown in Figures 3, 4A, and 5A, in some embodiments, IC structure 300 may also include another metal gate cutout disposed in opening 308. Because opening 308 is not above BPR 320 (or any BPR), this metal gate cutout may be referred to as non-BPR gate cutout 308. Although Figure 3 shows non-BPR gate cutout 308 disposed between fins 104-1 and 104-2 and along a metal gate line 212, in other embodiments, the location of non-BPR gate cutout 308 may be different.

[0081] Similar to the BPR gate cut 410-1, the non-BPR gate cut 308 can cut through the gate electrode material of a given gate metal wire 212, thereby dividing the gate electrode material into two distinct portions (e.g., portions 412-1 and 412-3, as shown in Figures 4A and 5A), which are electrically insulated from each other. For this purpose, similar to the BPR gate cut 410-1, the non-BPR gate cut 308 can extend from the top of the gate electrode material it intends to cut below the bottom of the gate electrode material. In some embodiments, the width of the non-BPR gate cut 308 can be smaller than the width of the BPR gate cut 410-1 (e.g., a dimension measured along the y-axis of the exemplary coordinate system), as shown in Figures 3, 4A, and 5A. However, in other embodiments, the width of the non-BPR gate cut 308 can be equal to or greater than the width of the BPR gate cut 410-1.

[0082] Furthermore, in some embodiments, the depth of the BPR gate notch 410-1 may be less than the depth of the non-BPR gate notch 308 (e.g., the dimension measured along the z-axis of the exemplary coordinate system), as shown in Figures 3, 4A, and 5A. This is because the depth of the BPR gate notch 410-1 is defined by the groove depth of the BPR 320 located below the metal gate line 212 (that is, the BPR gate notch 410-1 is formed within the opening 310 and the opening 310 can be formed by an etching process that has etch selectivity relative to the conductive material of the BPR 320), while the depth of the non-BPR gate notch 308 may be defined by the etching process used to form the opening of the non-BPR gate notch 308, and therefore is generally not the same as the depth of the BPR gate notch 410-1. Although not specifically shown in the drawings, in some embodiments, the non-BPR gate cutout 308 may have a seam substantially located at the y-axis center of the non-BPR gate cutout 308 and extending vertically along the ab xz plane. If the non-BPR gate cutout 308 is a high aspect ratio opening, such a seam may occur due to the deposition of one or more dielectric materials into the opening for the non-BPR gate cutout 308. For example, such a seam may be characterized by using atomic layer deposition (ALD) to fill the opening of the non-BPR gate cutout 308 with a metallic gate cutout dielectric material.

[0083] Similar to the BPR gate cutout 410-1, the non-BPR gate cutout 308 may include one or more dielectric materials, such as any of the dielectric materials described above. In some embodiments, the BPR gate cutout 410-1 and the non-BPR gate cutout 308 may have substantially the same material composition. However, in other embodiments, the material composition of the non-BPR gate cutout 308 may differ from that of the BPR gate cutout 410-1, for example, when these gate cutouts are formed and filled in different processes during the manufacture of IC structures 300 or 500, as shown in Figures 3, 4A, and 5A, where different patterns are used to display the BPR gate cutout 410-1 and the non-BPR gate cutout 308. In particular, in some embodiments, for example, when the non-BPR gate cutout 308 is formed prior to the BPR gate cutout 410-1 and is (at least partially) filled with a dielectric material (e.g., silicon nitride) used as an etch stop during patterning, while the BPR gate cutout 410-1 is (at least partially) filled with a material such as silicon oxide, the dielectric constant of the dielectric material of the non-BPR gate cutout 308 may be higher than that of the dielectric material of the BPR gate cutout 410-1. Example Manufacturing Method

[0084] Figure 6 provides a flowchart of an exemplary method 600 for manufacturing an IC structure having one or more gate cutouts above the BPR according to an embodiment of the present disclosure. For example, method 600 can be used to manufacture an IC structure, such as IC structure 300 as described herein.

[0085] Although the operations of method 600 are shown once in a specific order, these operations can be performed in any suitable order and repeated as needed. For example, one or more operations can be performed in parallel to substantially simultaneously fabricate multiple IC structures having gate cutouts over the BPR as described herein. In another example, operations can be performed in different orders to reflect the structure of a particular device assembly, which will include one or more IC structures having gate cutouts over the BPR as described herein.

[0086] Furthermore, the exemplary manufacturing method 600 may include other operations not specifically shown in FIG. 6, such as various cleaning or planarization operations known in the art. For example, in some embodiments, layers of support structures and various other materials subsequently deposited thereon may be cleaned before, after, or during any procedure of the method 600 described herein, for example, to remove oxides, surface-bound organic and metallic contaminants, and subsurface contaminants. In some embodiments, cleaning may be performed using, for example, chemical solutions (such as peroxides) and / or ultraviolet (UV) radiation combined with ozone, and / or surface oxidation (e.g., using thermal oxidation) followed by removal of oxides (e.g., using hydrofluoric acid (HF)). In another example, the arrangement / apparatus described herein may be planarized before, after, or during any procedure of the method 600 described herein, for example, to remove capping layers or excess material. In some embodiments, planarization may be performed using wet or dry planarization procedures, for example, planarization is chemical mechanical planarization (CMP), which can be understood as a procedure that utilizes grinding surfaces, abrasives, and slurries to remove capping layers and planarize surfaces.

[0087] As shown in FIG. 6, method 600 may begin with procedure 602, which includes providing a first channel structure and a second channel structure (e.g., first and second fins or nanobands), the first channel structure and the second channel structure comprising one or more semiconductor materials. Method 600 may further include procedure 604, which includes providing a gate electrode material having a first portion at least partially surrounding a portion of the first channel structure and a second portion at least partially surrounding a portion of the second channel structure. Method 600 may further include procedure 606, which includes providing power rails extending in a horizontal direction parallel to and between the first and second channel structures, and extending in a vertical direction through the top of the power rails below the bottom of the first and second portions of the gate electrode material. Method 600 may further include procedure 608, which includes providing an opening extending horizontally parallel to and above the power rail, and vertically extending from the top of the power rail to the top of first and second portions of the gate electrode material, said opening having a first portion as an opening between the first and second portions of the gate electrode material, and also having a second portion as an opening not between the first and second portions of the gate electrode material. Method 600 may further include procedures 610 and 612, which respectively include filling the first portion of the opening at least partially with one or more dielectric materials, and filling the second portion of the opening at least partially with one or more conductive materials, wherein the one or more conductive materials are coupled to the power rail. Variations and Implementations

[0088] The IC structures shown and described with reference to Figures 1 to 6 do not represent an exhaustive set of components in which one or more IC structures with gate cutouts above the BPR as described herein can be integrated, but merely provide an example of such an arrangement. For example, while the descriptions and figures provided herein refer to FinFETs, these descriptions and figures are equally applicable to embodiments of any non-planar FET other than FinFETs formed based on elongated channel structures of suitable channel materials, such as nano-charged transistors, nano-wire transistors, or transistors such as nano-band / nano-wire transistors but with cross-sections of any geometry (e.g., elliptical or polygonal with rounded corners). In another example, although specific arrangements of materials are discussed with reference to Figures 1 to 6, intermediate materials may be included in various portions of these figures. Furthermore, while Figures 1 to 6 may illustrate various elements, such as the various openings shown in Figure 5, the gate electrode material of the metal gate line 212, etc., having a completely straight sidewall profile, i.e., a profile where the sidewalls extend perpendicularly to the support structure 102, these ideal profiles may not always be achievable in actual manufacturing processes. In other words, although designed to have straight sidewall profiles, real-world openings can be formed as part of the fabrication of various elements in the IC structures shown in Figures 1-6. Figures 1-6 may end up with so-called "non-recessed" profiles, where the width of the top of the opening is greater than the width of the bottom of the opening, or "recessed" profiles, where the width of the top of the opening is less than the width of the bottom of the opening. Typically, because real-world openings do not have perfectly straight sidewalls, defects may form within the material filling the opening. For example, typically with a recessed profile, a void may form at the center of the opening, where the growth of the given material filling the opening is pinched off at the top of the opening. Therefore, the description of various embodiments of IC structures with gate cutouts above the BPR as provided herein also applies to various elements of the IC structure that appear different from those shown in the figures due to the fabrication processes used to form them. Exemplary Electronic Devices

[0089] The IC structures with gate cutouts above the BPR disclosed herein can be included in any suitable electronic device. For example, the IC structure 300 according to any embodiment described herein can be part of at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communication device. Figures 7 to 10 show various examples of components and devices that may include one or more IC structures with gate cutouts above the BPR as disclosed herein.

[0090] Figures 7A-7B are top views of wafer 2000 and die 2002, which may include one or more IC structures having gate cutouts above the BPR according to any embodiment disclosed herein. In some embodiments, die 2002 may be included in an IC package according to any embodiment disclosed herein. For example, any die 2002 may be used as any die 2256 in the IC package 2200 shown in FIG8. Wafer 2000 may be made of semiconductor material and may include one or more dies 2002 having IC structures formed on the surface of wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product including any suitable IC (e.g., including ICs including one or more gate cutouts above the BPR as described herein). After the manufacture of a semiconductor product is completed (e.g., after the manufacture of one or more IC structures as described herein, having at least one gate cut-out over at least one BPR), wafer 2000 may undergo a dicing process, wherein the individual dies 2002 are separated from each other to provide discrete "wafers" of the semiconductor product. In particular, a device comprising one or more IC structures as disclosed herein, having gate cut-outs over a BPR, may take the form of wafer 2000 (e.g., not diced) or die 2002 (e.g., diced). Die 2002 may include support circuitry to route electrical signals to various memory cells, transistors, capacitors, and any other IC elements. In some embodiments, wafer 2000 or die 2002 may implement or include memory devices (e.g., static RAM (SRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be formed on the same die 2002 as a processing device (e.g., the processing device 2402 of FIG10) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0091] FIG8 is a side cross-sectional view of an exemplary IC package 2200, which may include one or more IC structures having a gate cutout above the BPR according to any embodiment disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0092] The packaging substrate 2252 may be formed of a dielectric material (e.g., ceramic, stacked film, epoxy film having filler particles, etc.) and may have a dielectric material extending through the space between the surfaces 2272 and 2274, or between different locations on the surface 2272 and / or between different locations on the surface 2274.

[0093] The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive paths 2262 through the package substrate 2252, thereby allowing circuitry within the die 2256 and / or interposer 2257 to be electrically coupled to various conductive contacts 2264 (or other devices (not shown) included in the package substrate 2252).

[0094] The IC package 2200 may include conductive contacts 2261 of the interposer 2257, a first-level interconnect 2265, and conductive contacts 2263 of the package substrate 2252 coupled to the interposer 2257 of the package substrate 2252. As shown in FIG8, the first-level interconnect 2265 is a solder bump, but any suitable first-level interconnect 2265 may be used. In some embodiments, the interposer 2257 may not be included in the IC package 2200; instead, the die 2256 may be directly coupled to the conductive contacts 2263 at face 2272 through the first-level interconnect 2265.

[0095] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, first-level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled through interposer 2257 to conductive paths (not shown) to allow circuitry within die 2256 to be electrically coupled to each of the conductive contacts 2261 (or coupled to other devices included in interposer 2257, not shown). The first-level interconnect 2258 shown in FIG8 is a solder bump, but any suitable first-level interconnect 2258 may be used. As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., metal) used as an interface between different components; conductive contacts may be recessed into, flush with, or extend away from the component surface, and may take any suitable form (e.g., conductive pad or socket).

[0096] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 surrounding the first-level interconnect 2265, while a molding compound 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding compound 2268. An example material that may be used for the underfill material 2266 and the molding compound 2268 is an epoxy molding compound, if suitable. The second-level interconnect 2270 may be coupled to the conductive contact 2264. The second-level interconnect 2270 shown in FIG8 is a solder ball (e.g., for a ball gate array arrangement), but any suitable second-level interconnect 2270 may be used (e.g., a pin in a pin gate array arrangement or a plane in a planar gate array arrangement). The second-level interconnect 2270 can be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and discussed below with reference to FIG9.

[0097] Die 2256 may take the form of any embodiment of die 2002 discussed herein (e.g., it may include any embodiment of an IC structure having a gate cutout over the BPR as described herein). In embodiments where IC package 2200 includes a plurality of dies 2256, IC package 2200 may be referred to as a multi-die package (MCP). Dies 2256 may include circuitry performing any desired function. For example, one or more of dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of dies 2256 may be memory dies (e.g., high-bandwidth memory). In some embodiments, any one of dies 2256 may include one or more IC structures having a gate cutout over the BPR as discussed above; in some embodiments, at least some of dies 2256 may not include any IC structure having a gate cutout over the BPR.

[0098] Although the IC package 2200 shown in FIG. 8 is a flip-chip package, other packaging architectures can be used. For example, the IC package 2200 can be a ball gate array (BGA) package, such as an embedded wafer-level ball gate array (eWLB) package. In another example, the IC package 2200 can be a wafer-level wafer-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200 in FIG. 8, the IC package 2200 can include any desired number of dies 2256. The IC package 2200 can include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252. More generally, the IC package 2200 can include any other active or passive components known in the art.

[0099] FIG9 is a cross-sectional side view of an IC device assembly 2300 that may include elements having one or more IC structures with gate cutouts above the BPR according to any embodiment disclosed herein. The IC device assembly 2300 includes a plurality of elements disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes elements disposed on a first surface 2340 and an opposing second surface 2342 of the circuit board 2302; typically, the elements may be disposed on one or both surfaces 2340 and 2342. In particular, any suitable elements of the IC device assembly 2300 may include any one or more IC structures having gate cutouts above the BPR according to any embodiment disclosed herein; for example, any IC package discussed below with reference to the IC device assembly 2300 may take the form of any embodiment of the IC package 2200 discussed above with reference to FIG8 (e.g., may include one or more IC structures having gate cutouts above the BPR disposed on a die 2256).

[0100] In some embodiments, the circuit board 2302 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by multiple layers of dielectric material and interconnected by conductive vias. Any one or more metal layers may be formed with a desired circuit pattern to route electrical signals between components coupled to the circuit board 2302 (selectively combined with other metal layers). In other embodiments, the circuit board 2302 may be a non-PCB substrate.

[0101] The IC device assembly 2300 shown in FIG9 includes an on-intermediate package structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling element 2316. The coupling element 2316 can electrically and mechanically couple the on-intermediate package structure 2336 to the circuit board 2302, and may include solder balls (as shown in FIG9), convex and concave portions of sockets, adhesive, underfill material and / or any other suitable electronic and / or mechanical coupling structures.

[0102] The interposer-on-package (IPC) structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling element 2318. The coupling element 2318 may take any suitable form for the application, such as the form discussed above with reference to coupling element 2316. The IC package 2320 may be, for example, or include a die (die 2002 of FIG. 7B), an IC device, or any other suitable element. In particular, the IC package 2320 may include one or more IC structures having a gate cutout over the BPR as described herein. Although a single IC package 2320 is shown in FIG. 9, multiple IC packages may be coupled to the interposer 2304; and in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an interposer substrate for bridging the circuit board 2302 and the IC package 2320. Typically, the interposer 2304 may extend connections to a wider pitch or reroute connections to different connections. For example, interposer 2304 can couple IC package 2320 (e.g., die) to the BGA of coupling element 2316 to couple to circuit board 2302. In the embodiment shown in FIG9, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304; in other embodiments, IC package 2320 and circuit board 2302 may be attached to the same side of interposer 2304. In some embodiments, three or more components may be interconnected via interposer 2304.

[0103] Interposer 2304 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymeric material such as polyimide. In some implementations, interposer 2304 may be formed of alternating rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials. Interposer 2304 may include any number of metal lines 2310, vias 2308, and through-silicon vias (TSVs) 2306. Interposer 2304 may also include embedded devices 2314 containing both passive and active devices. These devices may include (but are not limited to) capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on interposer 2304. The on-intermediate packaging structure 2336 can take the form of any on-intermediate packaging structure known in the art.

[0104] The IC device assembly 2300 may include an IC package 2324 coupled to a first side 2340 of the circuit board 2302 via a coupling element 2322. The coupling element 2322 may take the form of any embodiment discussed above with reference to the coupling element 2316, and the IC package 2324 may take the form of any embodiment discussed above with reference to the IC package 2320.

[0105] The IC device assembly 2300 shown in FIG9 includes a stacked package structure 2334 coupled to a second side 2342 of a circuit board 2302 via coupling element 2328. The stacked package structure 2334 may include IC packages 2326 and 2332 coupled together via coupling element 2330, such that IC package 2326 is disposed between the circuit board 2302 and IC package 2332. Coupling elements 2328 and 2330 may take the form of any embodiment of coupling element 2316 discussed above, while IC packages 2326 and 2332 may take the form of any embodiment of IC package 2320 discussed above. The stacked package structure 2334 may be configured according to any stacked package structure known in the art.

[0106] FIG10 is a block diagram of an exemplary computing device 2400 according to any embodiment disclosed herein, which may include one or more elements having one or more IC structures having a gate cutout over the BPR. For example, any suitable element of computing device 2400 may include a die (e.g., die 2002, as shown in FIG7B) implementing one or more IC structures having a gate cutout over the BPR according to any embodiment disclosed herein. Any element of computing device 2400 may include IC package 2200 (e.g., as shown in FIG8). Any element of computing device 2400 may include IC device assembly 2300 (e.g., as shown in FIG9).

[0107] Figure 10 shows many components as included in the computing device 2400, but any one or more of these components may be omitted or copied to suit the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-a-chip (SoC) die.

[0108] Furthermore, in various embodiments, computing device 2400 may not include one or more of the elements shown in FIG. 10, but computing device 2400 may include interface circuitry for coupling to one or more elements. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0109] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the terms "processing device" or "processor" may refer to any means or part of a means of processing electronic data from a register and / or memory to convert said electronic data into other electronic data that can be stored in the register and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing means. The computing device 2400 may include memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disks. In some embodiments, memory 2404 may include memory that shares a die with the processing device 2402.

[0110] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured to manage wireless communications for transmitting data to and from the computing device 2400. The term "wireless" and its derivatives can be used to describe circuits, apparatuses, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation over a non-fixed medium. This term does not imply that the related apparatus does not include any wiring, although in some embodiments they may not include any wiring.

[0111] The communication chip 2412 can implement any of a variety of wireless standards or protocols, including but not limited to the Institute of Electrical and Electronics Engineers (IEEE) standards, such as Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) projects, and any revisions, updates, and / or re-releases (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16 Compatible Broadband Radio Access (BWA) networks are commonly referred to as WiMAX networks, which represent global microwave connectivity interoperability and are certification symbols for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 can operate according to Global System for Mobile Communications (GSM), Universal Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2412 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, etc. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0112] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, a first communication chip 2412 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, while a second communication chip 2412 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, while the second communication chip 2412 may be dedicated to wired communications.

[0113] The computing device 2400 may include a battery / power circuit 2414. The battery / power circuit 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the computing device 2400 to an energy source (e.g., AC line power) separate from the computing device 2400.

[0114] The computing device 2400 may include a display device 2406 (or a corresponding interface circuit, as discussed above). The display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0115] The computing device 2400 may include an audio output device 2408 (or a corresponding interface circuit, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0116] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuit, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0117] The computing device 2400 may include a GPS device 2416 (or a corresponding interface circuit, as discussed above). The GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400, as is known in the art.

[0118] The computing device 2400 may include other output devices 2410 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2410 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0119] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include accelerometers, gyroscopes, compasses, image capturing devices, keyboards, cursor controls such as mice, styluses, touchpads, barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0120] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, smartphone, mobile internet device, music player, tablet computer, laptop, netbook, ultra-thin laptop, personal digital assistant (PDA), ultra-mobile PC, etc.), a desktop computing device, a server or other networked computing element, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device for processing data. Example of Selection

[0121] The following paragraphs provide various examples of the embodiments disclosed herein.

[0122] Example 1 provides an IC structure including a first channel structure and a second channel structure (e.g., first and second fins or nanobands), comprising one or more semiconductor materials; a gate electrode material having a first portion that at least partially surrounds a portion of the first channel structure and a second portion that at least partially surrounds a portion of the second channel structure; a power rail extending in a horizontal direction parallel to and between the first and second channel structures and in a vertical direction having a top of the power rail below the bottom of the first and second portions of the gate electrode material; and an opening extending in a horizontal direction parallel to and above the power rail and in a vertical direction extending from the top of the power rail to the top of the first and second portions of the gate electrode material, the opening having a first portion as a portion of the opening located between the first and second portions of the gate electrode material, and also having a second portion as a portion of the opening not located between the first and second portions of the gate electrode material. In this IC structure, the first portion of the opening is at least partially filled with one or more dielectric materials (that is, the first portion of the opening is a BPR gate cutout, also referred to herein as "gate cutout above BPR"), and the second portion of the opening is at least partially filled with one or more conductive materials (that is, the second portion of the opening is a BPR via).

[0123] Example 2 provides an IC structure according to Example 1, wherein the width of the first portion of the opening is substantially equal to the width of the second portion of the opening, wherein in this example, the width is a dimension measured along the support structure disposed thereon parallel to the first channel structure and the second channel structure and perpendicular to the length of the first channel structure and the second channel structure.

[0124] Example 3 provides an IC structure according to Example 1 or 2, wherein the width of the first portion and the second portion of the opening is smaller than the width of the power rail.

[0125] Example 4 provides an IC structure according to Example 1 or 2, wherein the widths of the first and second portions of the opening are substantially equal to the width of the power rail.

[0126] Example 5 provides an IC structure according to any of the foregoing examples, wherein the top of the power rail is at least 5 nanometers, for example at least 7 nanometers or at least 10 nanometers, below the bottom of the first and second portions of the gate electrode material.

[0127] Example 6 provides an IC structure according to any of the foregoing examples, wherein the one or more conductive materials of the second portion of the opening are in contact with the one or more conductive materials of the power rail.

[0128] Example 7 provides an IC structure according to any of the foregoing examples, wherein the one or more conductive materials of the second portion of the opening are electrically coupled to the power rail and electrically coupled to the S / D contact of the transistor, and wherein the transistor has a channel including a portion of the first channel structure and a gate including the first portion of the gate electrode material, or the transistor has the channel including a portion of the second channel structure and the gate including the second portion of the gate electrode material. In other words, even though FIG. 3 illustrates that BPR 320 is coupled to the S / D region 114 of the transistor 202 provided along fin 104-3, in other embodiments, BPR 320 may be coupled to the S / D region 114 of the transistor provided along fin 104-2 of FIG. 3.

[0129] Example 8 provides an IC structure according to Example 7, further comprising a first trench contact (TCN1) disposed above the S / D contact material of the transistor and electrically coupled (e.g., conductively contacting) the S / D contact material; and a second trench contact (TCN2) disposed above the first trench contact and electrically coupled (e.g., conductively contacting) the first trench contact, wherein the one or more conductive materials of the second portion of the opening are electrically coupled (e.g., conductively contacting) the second trench contact and self-aligned to the second trench contact in a direction parallel to the length of the power rail.

[0130] Each of the first channel structure, the second channel structure, and the power rail can be an elongated structure having a length measured in the direction of a first axis of the coordinate system (e.g., the x-axis of the exemplary coordinate system shown in the figures of this invention), a width measured in the direction of a second axis of the coordinate system (e.g., the y-axis of the exemplary coordinate system shown in the figures of this invention), and a height measured in the direction of a third axis of the coordinate system (e.g., the z-axis of the exemplary coordinate system shown in the figures of this invention), wherein the length is greater than the width and the height. The second portion of the opening self-aligns to the second groove contact in a direction parallel to the length of the power rail, which in turn means that the second portion of the opening self-aligns to the second groove contact in the direction of the x-axis.

[0131] Example 9 provides an IC structure according to Example 7 or 8, further comprising a first trench contact (TCN1) disposed above and electrically coupled (e.g., conductively contacted) to the S / D contact material of the transistor; and a second trench contact (TCN2) disposed above and electrically coupled (e.g., conductively contacted) to the first trench contact, wherein the one or more conductive materials of the second portion of the opening are electrically coupled (e.g., conductively contacted) to the second trench contact, and the second trench contact does not completely overlap with the second portion of the opening in a direction perpendicular to the length of the power rail and parallel to the support structure on which the IC structure is disposed. The fact that the second trench contact does not completely overlap with the second portion of the opening in a direction perpendicular to the length of the power rail and parallel to the support structure on which the IC structure is disposed may mean that the second trench contact does not completely overlap with the second portion of the opening in the y-axis direction.

[0132] Example 10 provides an IC structure according to any of the foregoing examples, wherein the first portion of the opening electrically isolates the first portion of the gate electrode material from the second portion of the gate electrode material.

[0133] Example 11 provides an IC structure according to any of the foregoing examples, wherein the gate electrode material is a first gate electrode material, the opening is a first opening, the one or more conductive materials are one or more first conductive materials, and the IC structure further includes a third channel structure (e.g., a third fin or nanoband) comprising the one or more semiconductor materials, a second gate electrode material having a first portion at least partially surrounding a portion of the third channel structure and a second portion at least partially surrounding a portion of the first channel structure, and a second opening located between the first portion and the second portion of the second gate electrode material and extending from the top of the first portion and the second portion of the second gate electrode material to below the bottom of the first portion and the second portion of the second gate electrode material, wherein the second opening is at least partially filled with one or more second dielectric materials.

[0134] Example 12 provides an IC structure according to Example 11, wherein the width of the second opening is smaller than the width of the first opening.

[0135] Example 13 provides an IC structure according to Example 11, wherein the width of the second opening is equal to or greater than the width of the first opening.

[0136] Example 14 provides an IC structure according to any one of Examples 11 to 13, further comprising a seam in one or more second dielectric materials.

[0137] Example 15 provides an IC structure according to any one of Examples 11 to 14, wherein the IC structure further includes a support structure (e.g., a substrate, wafer, die, or chip) having a first side and an opposing second side, wherein the first channel structure, the second channel structure, and the third channel structure are disposed on different portions of the second side of the support structure, and wherein the distance between the first side of the support structure and the bottom of the second opening is different from the distance between the first side of the support structure and the bottom of the first opening.

[0138] Example 16 provides an IC structure according to any one of Examples 11 to 15, wherein the material composition of the one or more second dielectric materials is different from the material composition of the one or more first dielectric materials.

[0139] Example 17 provides an IC structure according to any one of Examples 11 to 16, wherein the dielectric constant of the one or more first dielectric materials is less than the dielectric constant of the one or more second dielectric materials.

[0140] Example 18 provides an IC structure according to any one of Examples 11 to 17, wherein the second opening electrically isolates the first portion of the second gate electrode material from the second portion of the second gate electrode material.

[0141] Example 19 provides an electronic device comprising an IC die and other IC components coupled to the IC die, wherein the IC die comprises a plurality of channel structures of one or more semiconductor materials, substantially parallel to each other; a plurality of lines of one or more gate electrode materials, substantially parallel to each other, substantially perpendicular to the plurality of channel structures, and at least partially surrounding portions of the plurality of channel structures; a power rail, substantially parallel to a first channel structure and a second channel structure among the plurality of channel structures and located between the first channel structure and the second channel structure, wherein the top of the power rail is below the plurality of lines; a first gate cutout, wherein The device includes one or more first dielectric materials and is disposed above a portion of the power rail, such that a portion of the first line of the plurality of lines at least partially surrounding a portion of the first channel structure is electrically isolated from a portion of the first line of the plurality of lines at least partially surrounding a portion of the second channel structure; and a second gate cutout, which includes one or more second dielectric materials and is disposed between the first channel structure and the third channel structure of the plurality of channel structures, such that a portion of the second line of the plurality of lines at least partially surrounding a portion of the first channel structure is electrically isolated from a portion of the second line of the plurality of lines at least partially surrounding a portion of the third channel structure.

[0142] Example 20 provides an electronic device according to Example 19, wherein the dielectric constant of the one or more first dielectric materials is less than the dielectric constant of the one or more second dielectric materials.

[0143] Example 21 provides an electronic device according to Example 19 or 20, wherein the electronic device is a computing device or a memory device.

[0144] Example 22 provides an electronic device according to Example 19 or 20, wherein the electronic device is an IC package.

[0145] Example 23 provides an electronic device according to any one of Examples 19 to 22, wherein the other IC component includes one of a package substrate, an interposer, or other IC die.

[0146] Example 24 provides an electronic device according to any one of Examples 19 to 23, wherein the IC die includes at least one or a portion thereof of a memory device and a computing device.

[0147] Example 25 provides an electronic device according to any one of Examples 19 to 24, wherein the electronic device is a wearable electronic device (e.g., a smartwatch) or a handheld electronic device (e.g., a mobile phone).

[0148] Example 26 provides an electronic device as in any of Examples 19 to 25, wherein the electronic device further includes one or more communication chips and antennas.

[0149] Example 27 provides an electronic device according to any one of Examples 19 to 26, wherein the electronic device is an RF transceiver.

[0150] Example 28 provides an electronic device according to any one of Examples 19 to 27, wherein the other IC component is a motherboard.

[0151] Example 29 provides an electronic device according to any one of Examples 19 to 28, wherein the IC die includes an IC structure according to any one of Examples 1 to 18.

[0152] Example 30 provides a method for manufacturing an IC structure, the method comprising providing a first channel structure and a second channel structure (e.g., first and second fins or nanoribbons), the first channel structure and the second channel structure comprising one or more semiconductor materials; providing a gate electrode material having a first portion at least partially surrounding a portion of the first channel structure and a second portion at least partially surrounding a portion of the second channel structure; providing a power rail parallel to the first channel structure and the second channel structure and between the first channel structure and the second channel structure, and having the power rail below the bottom of the first portion and the second portion of the gate electrode material. The top portion of the gate electrode material is provided with an opening parallel to and above the power rail, extending from the top of the power rail to the top of the first and second portions of the gate electrode material. The opening has a first portion as the portion between the first and second portions of the gate electrode material and a second portion as the portion not located between the first and second portions of the gate electrode material. The first portion of the opening is at least partially filled with one or more dielectric materials, and the second portion of the opening is at least partially filled with one or more conductive materials, wherein the one or more conductive materials are coupled to the power rail.

[0153] Example 31 provides a method according to Example 30, further comprising providing a transistor having a channel including a portion of the second channel structure and a gate including the second portion of the gate electrode material, and electrically coupling the one or more conductive materials of the second portion of the opening to the source or drain (S / D) region of the transistor.

[0154] Example 32 provides a method according to Example 30 or 31, and further includes a procedure for forming an IC structure according to any of the foregoing examples (e.g., any of the foregoing examples 1 to 18) or an electronic device according to any of the foregoing examples (e.g., any of the foregoing examples 19 to 29).

[0155] The above description of the illustrated implementation of this disclosure, including the content described in the abstract, is not intended to be exhaustive or to limit this disclosure to its precise form. Although specific implementations and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications can be made within the scope of this disclosure, as will be understood by those skilled in the art. These modifications can be made to this disclosure based on the above detailed description. [Simplified Explanation of the Diagram]

[0005] The embodiments will be readily understood through the following detailed description in conjunction with the drawings. For ease of description, similar reference numerals denote similar structural elements. In the drawings, the embodiments are illustrated by way of example rather than limitation.

[0006] [Figure 1] is a perspective view of an exemplary FinFET according to some embodiments of the present disclosure.

[0007] [Figure 2] is a top-down view of an exemplary IC structure according to some embodiments of the present disclosure, wherein at least one gate cutout can be implemented above the embedded power rail (BPR).

[0008] [Figure 3] is a top-down view of the IC structure of Figure 2 according to some embodiments of the present disclosure, which has a gate cutout above the BPR.

[0009] [Figures 4A-4C] According to some embodiments of the present disclosure, a cross-sectional side view of the IC structure of FIG3 is provided, which has a cross-section taken along various planes.

[0010] [Figures 5A-5B] A cross-sectional side view of the IC structure of FIG3 is provided according to other embodiments of the present disclosure, having cross sections taken along various planes.

[0011] [Figure 6] provides a flowchart of an exemplary method for manufacturing an IC structure having a BPR and a gate cutout above the BPR according to an embodiment of the present disclosure.

[0012] [Figures 7A and 7B] are top views of a wafer and a die according to any embodiment disclosed herein, which may include one or more IC structures having a gate cutout above the BPR.

[0013] [Figure 8] is a cross-sectional side view of an IC package according to any embodiment disclosed herein, the IC package may include one or more IC structures having a gate cutout above the BPR.

[0014] [Figure 9] is a cross-sectional side view of an IC device assembly according to any embodiment disclosed herein, the IC device assembly may include one or more IC structures having a gate cutout above the BPR.

[0015] [Figure 10] is a block diagram of an exemplary computing device according to any of the embodiments disclosed herein, the exemplary computing device may include one or more IC structures having a gate cutout above the BPR.

Claims

1. An integrated circuit (IC) structure, comprising: a first channel structure and a second channel structure; a gate electrode material having a first portion that at least partially surrounds a portion of the first channel structure and a second portion that at least partially surrounds a portion of the second channel structure; The power rail is parallel to the first channel structure and the second channel structure and is located between the first channel structure and the second channel structure, and has a top of the power rail below the bottom of the gate electrode material; The opening is parallel to and above the power rail, extending from the top of the power rail to the top of the first and second portions of the gate electrode material. The opening has a first portion as the portion between the first and second portions of the gate electrode material, and a second portion as the portion not located between the first and second portions of the gate electrode material. The first portion of the opening is at least partially filled with one or more dielectric materials, and the second portion of the opening is at least partially filled with one or more conductive materials.

2. The IC structure of claim 1, wherein the width of the first portion of the opening is substantially equal to the width of the second portion of the opening.

3. The IC structure as claimed in claim 1, wherein the width of the first portion and the second portion of the opening is smaller than the width of the power rail.

4. The IC structure as claimed in claim 1, wherein the widths of the first and second portions of the opening are substantially equal to the width of the power rail.

5. An IC structure as claimed in any of claims 1 to 4, wherein the top of the power rail is at least 5 nanometers below the bottom of the gate electrode material.

6. An IC structure as claimed in any one of claims 1 to 4, wherein the one or more conductive materials of the second portion of the opening are in contact with the one or more conductive materials of the power rail.

7. An IC structure as claimed in any one of claims 1 to 4, wherein the one or more conductive materials of the second portion of the opening are electrically coupled to the power rail and electrically coupled to the source or drain (S / D) contact of the transistor, and wherein: The transistor has a channel comprising a portion of the first channel structure and a gate comprising the first portion of the gate electrode material, or the transistor has the channel comprising a portion of the second channel structure and the gate comprising the second portion of the gate electrode material.

8. The IC structure of claim 7 further comprises: a first trench contact that is above and coupled to the S / D contact material of the transistor; and a second trench contact that is above and coupled to the first trench contact, wherein the one or more conductive materials of the second portion of the opening are coupled to the second trench contact and self-aligned to the second trench contact in a direction parallel to the length of the power rail.

9. The IC structure of claim 7 further comprises: a first trench contact, which is above and coupled to the S / D contact material of the transistor; and a second trench contact, which is above and coupled to the first trench contact, wherein the one or more conductive materials of the second portion of the opening are coupled to the second trench contact, and the second trench contact does not completely overlap with the second portion of the opening in a direction perpendicular to the length of the power rail and parallel to the support structure on which the IC structure is disposed.

10. An IC structure as described in any of requests 1 to 4, wherein: The gate electrode material is a first gate electrode material, the opening is a first opening, the one or more conductive materials are one or more first conductive materials, and the IC structure further includes: a third channel structure comprising the one or more semiconductor materials, a second gate electrode material having a first portion that at least partially surrounds a portion of the third channel structure and a second portion that at least partially surrounds a portion of the first channel structure, and a second opening located between the first portion and the second portion of the second gate electrode material and extending from the top of the first portion and the second portion of the second gate electrode material to below the bottom of the first portion and the second portion of the second gate electrode material, wherein the second opening is at least partially filled with one or more second dielectric materials.

11. The IC structure of claim 10 further includes a seam in the one or more second dielectric materials.

12. The IC structure as described in request item 10, wherein: The IC structure further includes a support structure having a first surface and an opposing second surface, the first channel structure, the second channel structure and the third channel structure being on different portions of the second surface of the support structure, and the distance between the first surface of the support structure and the bottom of the second opening being different from the distance between the first surface of the support structure and the bottom of the first opening.

13. The IC structure of claim 10, wherein the material composition of the one or more second dielectric materials is different from the material composition of the one or more first dielectric materials.

14. The IC structure of claim 10, wherein the dielectric constant of the one or more first dielectric materials is less than the dielectric constant of the one or more second dielectric materials.

15. The IC structure of claim 10, wherein the second opening electrically isolates the first portion of the second gate electrode material from the second portion of the second gate electrode material.

16. An electronic device comprising: an integrated circuit (IC) die; and other IC components coupled to the IC die, wherein the IC die includes: A plurality of channel structures made of one or more semiconductor materials, substantially parallel to each other; a plurality of lines made of one or more gate electrode materials, substantially parallel to each other, substantially perpendicular to the plurality of channel structures, and at least partially surrounding a portion of the plurality of channel structures; a power rail, substantially parallel to a first channel structure and a second channel structure among the plurality of channel structures and between the first channel structure and the second channel structure, wherein the top of the power rail is below the plurality of lines; a first gate cut comprising one or more first dielectric materials, the first gate cut being above a portion of the power rail, such that a portion of a first line among the plurality of lines at least partially surrounding a portion of the first channel structure is electrically isolated from a portion of the first line at least partially surrounding a portion of the second channel structure; and a second gate cut comprising one or more second dielectric materials, the second gate cut being between the first channel structure and a third channel structure of the plurality of channel structures, such that a portion of a second line among the plurality of lines at least partially surrounding a portion of the first channel structure is electrically isolated from a portion of the second line at least partially surrounding a portion of the third channel structure.

17. The electronic device of claim 16, wherein the dielectric constant of the one or more first dielectric materials is less than the dielectric constant of the one or more second dielectric materials.

18. The electronic device of claim 16 or 17, wherein the electronic device is a computing device or a memory device.

19. A method of manufacturing an integrated circuit (IC) structure, the method comprising: providing a first channel structure and a second channel structure, the first channel structure and the second channel structure comprising one or more semiconductor materials; A gate electrode material is provided having a first portion that at least partially surrounds a portion of the first channel structure and a second portion that at least partially surrounds a portion of the second channel structure; a power rail is provided parallel to the first channel structure and the second channel structure and between the first channel structure and the second channel structure, and has a top of the power rail below the bottom of the first portion and the second portion of the gate electrode material; And providing an opening parallel to and above the power rail, extending from the top of the power rail to the top of the first and second portions of the gate electrode material, the opening having a first portion as the portion of the opening located between the first and second portions of the gate electrode material, and also having a second portion as the portion of the opening not located between the first and second portions of the gate electrode material; The first portion of the opening is at least partially filled with one or more dielectric materials; and the second portion of the opening is at least partially filled with one or more conductive materials, wherein the one or more conductive materials are coupled to the power rail.

20. The method of claim 19, further comprising: providing a transistor having a channel including a portion of the second channel structure and a gate including the second portion of the gate electrode material, and electrically coupling the one or more conductive materials of the second portion of the opening to a source or drain (S / D) region of the transistor.

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