Power management circuit and method for integrated circuit having multiple power domains

Abstract

A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

Description

[Technical Field]

[0001] This disclosure relates to power management, and more particularly to a power management circuit for an integrated circuit having a plurality of power domains, and a method for managing an integrated circuit having a plurality of power domains. [Previous Technology]

[0002] System-on-chip (SoC) design integrates different circuit blocks (including analog and digital circuits) onto a single chip to achieve multiple functions. To reduce power consumption, a SoC can be divided into different power domains, each capable of operating at different voltage levels. A power domain refers to a collection of hierarchical instances that share the same power supply. For example, each circuit block can operate at an appropriate voltage level to reduce dynamic and static power consumption. Furthermore, unused power domains can be shut down, disabling / disabling the circuit blocks located within them to reduce leakage power consumption. [Summary of the Invention]

[0003] The embodiments disclosed herein provide a power management circuit for an integrated circuit having a plurality of power domains, and a power management scheme that includes power-on control and power isolation in a circuit design having a plurality of power domains.

[0004] Certain embodiments of this disclosure include a power management circuit for an integrated circuit. The power management circuit includes an inverter circuit and a latching circuit. The inverter circuit has an inverter input terminal and an inverter output terminal. The inverter circuit is configured to receive a first control signal from the inverter input terminal and generate a second control signal at the inverter output terminal. The first control signal carries power status information of a first power supply voltage supplied to the integrated circuit. The latching circuit has a latch power supply terminal, a first latch input terminal, and a second latch input terminal. The latch power supply terminal is coupled to a second power supply voltage supplied to the integrated circuit, the second power supply voltage being ready before the first power supply voltage. The first latch input terminal is coupled to the inverter output terminal to receive the second control signal. The second latch input terminal is coupled to the inverter input terminal to receive the first control signal. The latching circuit is used to generate a third control signal based on the signal levels of the first control signal and the second control signal, and to perform power control of the integrated circuit accordingly.

[0005] Certain embodiments of this disclosure include a power management circuit for an integrated circuit. The power management circuit includes a level shifter and an output buffer. The level shifter is powered at least by a first power supply voltage usable in a first power domain of the integrated circuit. The level shifter is used to convert a first control signal into a second control signal usable in the first power domain. The first control signal indicates a power state of a second power supply voltage usable in a second power domain of the integrated circuit. The first power supply voltage is ready before the second power supply voltage, and the second power domain is different from the first power domain. The output buffer is coupled to the level shifter to buffer the second control signal to generate a third control signal, thereby performing power control of the integrated circuit.

[0006] Certain embodiments of this disclosure include a method for managing an integrated circuit. The method includes: operating a bit shifter at a first power supply voltage supplying a first power supply domain of the integrated circuit, wherein the first power supply domain is configured to receive an input signal from a second power supply domain of the integrated circuit, the second power supply domain being powered by a second power supply voltage; when the first power supply voltage is ready but the second power supply voltage is not ready, using the bit shifter to convert a first control signal into a second control signal having a first logic level to isolate the second power supply domain from the first power supply domain, wherein the first control signal at least indicates the power state of the second power supply voltage; and when both the first power supply voltage and the second power supply voltage are ready, using the bit shifter to convert the first control signal into the second control signal having a second logic level to allow the first power supply domain to receive the input signal from the second power supply domain.

[0007] The power management solution provided in this disclosure can perform power control operations on integrated circuits, such as power-on control operations or power isolation, while achieving zero quiescent current. Furthermore, the power management solution provided in this disclosure can use a single control signal to isolate different power domains, thereby reducing circuit chip area and power consumption. The physical layer of the integrated circuit allows for different power-on / off sequences.

Implementation Method

[0009] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of parameter values, components, and configurations described below are used to simplify this disclosure. It is understood that these descriptions are merely illustrative and are not intended to limit the scope of this disclosure. For example, component symbols and / or reference numerals may be reused in multiple embodiments. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0010] Furthermore, it is understood that if a component is described as being "connected to" or "coupled to" another component, then the two components may be directly connected or coupled, or there may be other intervening components between them.

[0011] In circuit systems with multiple power domains, power-supply sequencing is used to reduce transient inrush currents to a tolerable level. Incorrect power-supply sequencing can damage the circuit system. For example, in cases where unwanted signal propagation occurs between a power-down domain and a power-on domain, a functioning block in the power-on domain may receive input signals with an unknown state from the power-down domain, causing a large inrush current in the functioning block. To reduce leakage current, a dedicated control signal for the power-on domain is used for power isolation to disconnect the functioning block from the power-on domain. However, since each power domain requires its own dedicated control signal, circuit designs with multiple different power domains require a large number of control signals, thus increasing chip area and power consumption.

[0012] Another concern is the power consumption of power-on control (POC), which includes power-on reset (POR) and brownout detection (BOD). For example, after a circuit system powered by a supply voltage is started, the power-on control circuit (POC circuit) can put the circuit system in a reset state until the supply voltage stabilizes. When the supply voltage stabilizes, the power-on control circuit can release the circuit system from the reset state and initialize the circuit system. However, the power-on control circuit consumes non-zero quiescent current. In low-power applications, the power consumption caused by this non-zero quiescent current accounts for a large portion of the overall power consumption.

[0013] This disclosure provides a plurality of power management circuits for an integrated circuit, the integrated circuit having a plurality of power domains, including a first power domain powered by a first power supply voltage and a second power domain powered by a second power supply voltage. The plurality of power management circuits can perform power control of the integrated circuit according to the second power supply voltage and a control signal, wherein the control signal can carry power state information of the first power supply voltage. The second power supply voltage can be ready earlier than the first power supply voltage, or become available earlier than the first power supply voltage. In some embodiments, the power control includes (but is not limited to) power-on reset, power-down detection, and power isolation between different power domains. In some embodiments, the control signal can be a delayed version of the first power supply voltage, a power state signal indicating whether the first power supply voltage is ready, or other control signals that can carry power state information of the first power supply voltage.

[0014] In some embodiments, at least one power management circuit may include a latch circuit controlled by the control signal. In some embodiments, at least one power management circuit may include a level shifter controlled by the control signal. In some embodiments, the level shifter may be implemented using a latch-type level shifter, a single-ended level shifter, or other types of level shifters. In some embodiments, at least one power management circuit may use the same control signal to achieve power isolation between any two power domains in the plurality of power domains of the integrated circuit. Alternatively, at least one power management circuit may consume zero transient current during power control operation. Further explanation follows.

[0015] Please refer to Figure 1, which illustrates an integrated circuit 10 comprising a plurality of power domains 11 and 12 according to certain embodiments of the present disclosure. The plurality of power domains 11 and 12 are powered by different power supply voltages VCC1 and VCC2, respectively. When power domain 11 is powered up, it takes some time for power supply voltage VCC1 to become available or ready for use. Similarly, when power domain 12 is powered up, it takes some time for power supply voltage VCC2 to become available or ready for use. The plurality of power supply voltages VCC1 and VCC2 can both be provided by a power control module (PCM) 16 located in the always-on power domain. The power control module 16 can be an on-chip PCM in the integrated circuit 10 or an off-chip PCM outside the integrated circuit 10. In some embodiments, one of the plurality of power supply voltages VCC1 and VCC2 may be the core voltage at which the processor core operates, and the other of the plurality of power supply voltages VCC1 and VCC2 may be the input / output voltage at which the input / output circuit (I / O circuit) operates. The processor core can be used to control the input / output circuit.

[0016] The power management circuit 100 is coupled to a plurality of power domains 11 and 12 and can be used to perform power control of the integrated circuit 10 based on the power supply voltage VCC2 and a control signal CS, wherein the control signal CS carries power status information of the power supply voltage VCC1. The power control performed by the power management circuit 100 may include (but is not limited to) power-on reset, power-down detection, and power isolation between the plurality of power domains 11 and 12, wherein power isolation may be referred to as power gating or power shut-off (PSO). For example, in some embodiments where the power supply voltage VCC2 is ready earlier than the power supply voltage VCC1, the power management circuit 100 may detect whether the power supply voltage VCC1 is ready based on the power supply voltage VCC2 and the control signal CS, and perform power-on control operation on the integrated circuit 10 accordingly. Alternatively, in some embodiments where the power supply voltage VCC2 available for power domain 12 is ready earlier than the power supply voltage VCC1 available for power domain 11, the power management circuit 100 may selectively isolate power domain 11 and power domain 12 based on the power supply voltage VCC2 and the control signal CS.

[0017] The control signal CS may be implemented using (but is not limited to) a power supply voltage VCC1, a delayed version of the power supply voltage VCC1, or other power status signals that indicate whether the power supply voltage VCC1 is ready. For example, the power status signal may indicate whether the power supply voltage VCC1 has reached a threshold level. When the voltage level of the power supply voltage VCC1 is below the threshold level, the power supply voltage VCC1 is not yet ready. When the voltage level of the power supply voltage VCC1 reaches or exceeds the threshold level, the power supply voltage VCC1 is ready. In some embodiments, the control signal CS may be implemented using a power status signal that indicates whether both the power supply voltages VCC1 and VCC2 are ready. For example, the control signal CS may be implemented using a power status signal provided by a normally open power domain.

[0018] In this embodiment, the power management circuit 100 may be implemented as an on-chip circuit in the integrated circuit 10. However, this is not intended to limit the scope of protection of this disclosure. In some embodiments, the power management circuit 100 may be implemented as an off-chip circuit outside the integrated circuit 10. In some embodiments, the power management circuit 100 may be integrated into the power control module 16 without departing from the scope of protection of this disclosure.

[0019] Figure 2 is a functional block diagram of an embodiment of the power management circuit disclosed herein. The power management circuit 200 can be used to implement at least a portion of the power management circuit 100 shown in Figure 1. The power management circuit 200 includes (but is not limited to) an inverter circuit 210 and a latching circuit 220. The inverter circuit 210 has an inverter input terminal TI and an inverter output terminal TO. The inverter circuit 210 can be used to receive a control signal CS from the inverter input terminal TI and generate a control signal CSB at the inverter output terminal TO.

[0020] The latch circuit 220 has a latch supply terminal TSL, a latch input terminal TI1, and a latch input terminal TI2. The latch supply terminal TSL is coupled to the power supply voltage VCC2. The latch input terminals TI1 and TI2 are coupled to the inverter output terminal TO and the inverter input terminal TI, respectively. The latch circuit 220 can generate a control signal SOUTB based on the signal levels of the latch input terminals TI1 and TI2, and perform power control of the integrated circuit 10 shown in FIG. 1 accordingly. That is, the latch circuit 220 can generate the control signal SOUTB based on the control signal CSB input to the latch input terminal TI1 and the control signal CS input to the latch input terminal TI2. In some embodiments, the control signal SOUTB and the power supply voltage VCC2 can be used in the same power domain.

[0021] Since the control signal CS carrying power status information of one of the power supply voltages VCC1 is input to the latch circuit 220, the control signal SOUTB output from the latch circuit 220 can represent this power status information. For example, this power status information can indicate the voltage level of the power supply voltage VCC1 or the power supply state of the power supply voltage VCC1, such as whether the power supply voltage VCC1 is ready. In addition, when the power supply voltage VCC2 reaches a threshold level and thus becomes a ready power supply voltage, the latch circuit 220 can start to operate properly. Therefore, the control signal SOUTB can also indicate whether both the power supply voltages VCC1 and VCC2 are ready.

[0022] In some embodiments, when the power status information indicates that the power supply voltage VCC1 is not yet ready, one of the signal levels of the latch input terminals TI1 and TI2 will be higher than the other of the signal levels of the latch input terminals TI1 and TI2. The control signal SOUTB may have a first level, such as one of a logic high level and a logic low level. When the power status information indicates that the power supply voltage VCC1 is ready, the signal level of the latch input terminals TI1 and TI2 will be lower than the other of the signal levels of the latch input terminals TI1 and TI2. The control signal SOUTB may have a second level different from the first level, such as the other of the logic high level and the logic low level. Therefore, when the power supply voltage VCC2 is ready earlier than the power supply voltage VCC1, the control signal SOUTB can have different levels before and after the power supply voltage VCC1 becomes the ready power supply voltage.

[0023] For example, when the power status information indicates that the power supply voltage VCC1 is not yet ready, the signal level of the control signal CSB generated from the inverter circuit 210 may be higher than the signal level of the control signal CS. When the power status information indicates that the power supply voltage VCC1 is ready, the signal level of the control signal CSB may be lower than the signal level of the control signal CS. Again, for example, when the power status information indicates that the power supply voltage VCC1 is not yet ready, the signal level of the control signal CSB generated from the inverter circuit 210 may be lower than the signal level of the control signal CS. When the power status information indicates that the power supply voltage VCC1 is ready, the signal level of the control signal CSB may be higher than the signal level of the control signal CS.

[0024] In this embodiment, the power management circuit 200 may further include an output buffer 230, which can be used to buffer the control signal SOUTB to generate a control signal SOUT. The power management circuit 200 can perform power control of the integrated circuit 10 shown in FIG1 according to the control signal SOUT. In some embodiments, the output buffer 230 can be used to reduce the loading effect and / or change the signal level of the control signal SOUTB. The output buffer 230 can be implemented using (but not limited to) a buffer amplifier, a voltage follower, or an inverter circuit. In some embodiments, the output buffer 230 may be omitted. The power management circuit 200 can directly output the control signal SOUTB to perform power control of the integrated circuit 10 shown in FIG1 without departing from the scope of protection of this disclosure. In some embodiments, the operative power domain of the control signal SOUTB output from the latch circuit 220 may be different from the operative power domain of the control signal CS input to the inverter circuit 210. For example (but this disclosure is not limited thereto), the control signal CS can be implemented using a power supply voltage VCC1 or a delayed version of power supply voltage VCC1, wherein power supply voltage VCC1 is applicable to power domain 11 (i.e., power supply voltage VCC1 can be used in power domain 11), which is different from power domain 12 to which the control signal SOUTB is applicable (i.e., the control signal SOUTB can be used in power domain 12). As another example, the control signal CS can be implemented using a power state signal provided by a normally open power domain different from power domain 12. Therefore, inverter circuit 210 and latching circuit 220 can be implemented as at least a portion of a level shifter 202, wherein level shifter 202 can be used to convert the control signal CS into a control signal SOUTB that can be used in power domain 12. The control signal CS can be used in a power domain different from power domain 12. In this embodiment, level shifter 202 can be considered as a latch-up level shifter. In some embodiments, the power management scheme provided in this disclosure can utilize a single-ended level shifter or other types of level shifters to generate the control signal SOUTB without departing from the scope of protection of this disclosure. Further details will be provided later.

[0025] Please refer to Figures 1 and 2 together. In some embodiments, the power management circuit 200 can perform power-on control operation on the integrated circuit 10 according to the control signal SOUTB / SOUT. The latch circuit 220 operates at the power supply voltage VCC2, which can be ready earlier than the power supply voltage VCC1. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 is not yet ready, the latch circuit 220 can be used to generate the control signal SOUTB to keep the integrated circuit 10 in the reset mode. For example, the latch circuit 220 can generate the control signal SOUTB with a first criterion to keep at least one circuit block operating in the power domain 12 in the reset mode, and / or keep at least one circuit block operating in the power domain 11 in the reset mode. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 is ready, the latch circuit 220 can be used to generate the control signal SOUTB to release the integrated circuit 10 from the reset mode. For example, latch circuit 220 may generate a control signal SOUTB with a second level to release the at least one circuit block operating in power domain 12 from the reset mode, and / or release the at least one circuit block operating in power domain 11 from the reset mode.

[0026] In some embodiments, the power management circuit 200 may provide power isolation between different power domains in the integrated circuit 10 based on the control signal SOUTB / SOUT. For example, the latch circuit 220 may operate at power supply voltage VCC2, which may be ready earlier than power supply voltage VCC1. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 used by power domain 11 is not yet ready, the latch circuit 220 may be used to generate the control signal SOUTB to isolate power domain 11 from a portion of the integrated circuit 10. This portion of the integrated circuit 10 operates in power domain 12. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 used by power domain 11 is ready, the latch circuit 220 may be used to generate the control signal SOUTB to allow power domain 11 to be coupled to this portion of the integrated circuit 10.

[0027] It is worth noting that the power management scheme provided in this disclosure can perform power-on control operation or power isolation while achieving zero quiescent current. For example, when multiple power supply voltages VCC1 and VCC2 are ready or stable, both the inverter circuit 210 and the latch-up circuit 220 can consume zero transient current.

[0028] To facilitate understanding of the contents of this disclosure, the power management scheme provided by this disclosure is further illustrated below based on certain embodiments. First, the power management scheme provided by this disclosure is illustrated using the application of power-on control. Figure 3 illustrates a specific implementation of the power management circuit 200 shown in Figure 2. In this embodiment, the power management circuit 300 can be used to perform power-on control operation on the integrated circuit 10 shown in Figure 1. This power-on control operation may include (but is not limited to) power-on reset and power-down detection. The power management circuit 300 may include an inverter circuit 310, a latch circuit 320, an output buffer 330, a resistive element 340, and a delay element 350. The inverter circuit 310, latch circuit 320, and output buffer 330 can respectively serve as embodiments of the inverter circuit 210, latch circuit 220, and output buffer 230 shown in Figure 2.

[0029] In this embodiment, the inverter circuit 310 may be implemented using a plurality of transistors MPI and MNI. The gates of each of the plurality of transistors MPI and MNI are coupled to the inverter input terminal TI of the inverter circuit 310. The drains of each of the plurality of transistors MPI and MNI are coupled to the inverter output terminal TO of the inverter circuit 310. The source of the transistor MPI is coupled to the inverter power supply terminal TSI of the inverter circuit 310. The source of the transistor MNI is coupled to a reference voltage, such as ground voltage.

[0030] The latch circuit 320 can be configured as a comparator having a non-inverting input terminal and an inverting input terminal. In this embodiment, latch input terminal TI1 and latch input terminal TI2 can be configured as the non-inverting input terminal and the inverting input terminal, respectively. Therefore, when the signal level of latch input terminal TI1 is higher than the signal level of latch input terminal TI2, the control signal SOUTB output from latch output terminal TOL can have a high level or a logic high level. When the signal level of latch input terminal TI1 is lower than the signal level of latch input terminal TI2, the control signal SOUTB output from latch output terminal TOL can have a low level or a logic low level.

[0031] Output buffer 330 is coupled to latch circuit 320 to buffer control signal SOUTB to generate control signal SOUT. In this embodiment, output buffer 330 can be implemented using an inverter circuit operating at power supply voltage VCC2. Therefore, power management circuit 300 can use the inverted signal of control signal SOUTB, i.e., control signal SOUT, to perform power-on control operation.

[0032] Resistor unit 340 is coupled between power supply voltage VCC2 and inverter power supply terminal TSI to generate a voltage drop VD based on a current signal IR flowing through resistor unit 340. In some embodiments, resistor unit 340 may be implemented using at least one resistor, at least one diode, at least one diode-connected transistor, at least one circuit unit capable of providing electrical resistance, and combinations thereof.

[0033] The delay unit 350 is coupled to the inverter input terminal TI to receive the power supply voltage VCC1 and output a delayed version of the power supply voltage VCC1 to the inverter input terminal TI. The delayed version of the power supply voltage VCC1, hereinafter referred to as the power supply voltage VCCR1, can carry power state information indicating the voltage level of the power supply voltage VCC1. The power supply voltage VCCR1 can serve as an embodiment of the control signal CS shown in Figure 2. The voltage signal VCOM output from the inverter output terminal TO can serve as an embodiment of the control signal CSB shown in Figure 2.

[0034] Figure 4 illustrates a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit 300 shown in Figure 3. Referring to Figure 4 together with Figures 1 and 3, at time point t0, the power control module 16 can power up the power domain 12, and the power supply voltage VCC2 begins to rise. Since the power supply voltage VCC2 is not yet ready, the power management circuit 300 can keep the integrated circuit 10 in a reset mode. For example, the output buffer 330 can invert the control signal SOUTB to generate a control signal SOUT with a logic low level, so that the operation of one or more circuit blocks in the power domain 12 is in a reset mode.

[0035] Between time point t0 and time point t1, since the power supply voltages VCCR1 / VCC1 are at a low level, transistor MPI can be turned on, while transistor MNI can be turned off. The voltage signal VCOM applied to the latch input terminal TI1 can be equal to or approximately equal to (VCC2 - VD). When the power supply voltage VCC2 reaches a threshold level that allows the latch circuit 320 to operate correctly, since neither power supply voltages VCC1 nor VCC2 are ready, the control signal SOUT remains at this logic low level.

[0036] At time t1, the power supply voltage VCC2 reaches a nominal / rated level, such as 3.3V. The voltage signal VCOM may have a voltage level equal to or approximately equal to this rated level minus the voltage drop VD. Furthermore, the power control module 16 may activate the power domain 11, and the power supply voltage VCC1 / VCCR1 may begin to rise. Between time t1 and time t2, since the signal level of latch input terminal TI1 (the voltage level of voltage signal VCOM) is sufficiently high for the signal level of latch input terminal TI2 (the voltage level of power supply voltage VCCR1), the control signal SOUTB may have a logic high level, such as 3.3V. The control signal SOUT may be at this logic low level.

[0037] At time t2, the power supply voltage VCC1 reaches or exceeds a threshold level VCT1, enabling the transistor MNI to conduct. The voltage signal VCOM can be reduced to zero or approximately zero. For example (but not limited to this disclosure), when the power supply voltage VCCR1 ramps up to the threshold voltage of the transistor MNI, the power supply voltage VCC1 reaches the threshold level VCT1. Furthermore, the difference between the signal levels of the latch input terminals TI1 and TI2, such as |VCOM-VCCR1|, reaches or exceeds a transition threshold. The control signal SOUTB can transition from this logic high level to this logic low level, thereby indicating that the power supply voltage VCC1 is ready. The power management circuit 300 can release the integrated circuit 10 from the reset mode. For example, output buffer 330 can invert the control signal SOUTB to generate a control signal SOUT with the logic high level (such as 3.3V), thereby releasing the one or more circuit block integrated circuits 10 operating in power domain 12 from reset mode. Between time point t2 and time point t3, the control signal SOUTB can be at the logic low level, and the control signal SOUT can be at the logic high level. Transistor MPI can be turned off. During the period when both power supply voltages VCC1 and VCC2 are ready, power management circuitry 300 can consume zero transient current.

[0038] At time t3, for example, due to a power outage, the power supply voltage VCC1 drops below or reaches a threshold level VCT2. Transistor MNI can be turned off, while transistor MPI can be turned on. The voltage signal VCOM can be increased to a level equal to or approximately equal to the rated level of the power supply voltage VCC2 minus the voltage drop VD. For example (but not limited thereto), when the power supply voltage VCCR1 ramps down to the threshold voltage of transistor MNI, the power supply voltage VCC1 reaches the threshold level VCT2. The control signal SOUTB can transition from this logic low level to this logic high level, thereby indicating that the power supply voltage VCC1 is not yet ready. The power management circuit 300 can put the integrated circuit 10 into a reset mode. For example, the output buffer 330 can invert the control signal SOUTB to generate a control signal SOUT with the logic low level, thereby keeping the one or more circuit block integrated circuits 10 operating in the power domain 12 in reset mode.

[0039] The circuit structure and operation described above based on Figures 3 and 4 are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure. In some embodiments, the inverter power supply terminal TSI of the inverter circuit 310 can be directly coupled to a power supply voltage, wherein the power supply voltage is ready before the power supply voltage VCC1 and has a nominal / rated voltage level lower than the nominal / rated voltage level of the power supply voltage VCC2. In some embodiments, the latch input terminal TI1 and the latch input terminal TI2 can be used as the inverting input terminal and the non-inverting input terminal of the comparator, respectively. In some embodiments, the output buffer 330 can be implemented by other types of buffers (such as voltage follower). In some embodiments, the output buffer 330 can be omitted. The power management circuit 300 can directly output the control signal SOUTB to perform power-on control operation. In some embodiments, the delay unit 350 can be omitted. The power supply voltage VCC1 can be directly input to the inverter input terminal TI and the latch input terminal TI2. These changes and modifications are all covered by this disclosure.

[0040] In some embodiments, the delay unit 350 can be used to ensure that the power supply voltage VCC1 is in a stable state when the control signal SOUT transitions to the high logic level. For example, when the power supply voltage VCCR1 ramps up to a voltage level, since the power supply voltage VCCR1 is a delayed version of the power supply voltage VCC1, the power supply voltage VCC1 may have already risen above that voltage level. Therefore, when the control signal SOUT transitions from the low logic level to the high logic level to indicate that the power supply voltage VCC1 is ready, the power supply voltage VCC1 will be closer to the rated level of the power supply voltage VCC1, such as 1.2V, than the power supply voltage VCCR1.

[0041] Referring to FIG. 5, in some embodiments, the delay unit 350 shown in FIG. 3 can be implemented using a delay unit 550, wherein the delay unit 550 includes a resistor RD1 and a transistor MD1. In this embodiment, the resistor RD1 is coupled to the power supply voltage VCC1 to provide the power supply voltage VCCR1. The gate of the transistor MD1 is coupled to the power supply voltage VCCR1. The drain and source of the transistor MD1 are short-circuited to each other. Therefore, the transistor MD1 can act as a capacitor, coupled between the power supply voltage VCCR1 and a reference voltage VSS. The delay unit 550 can act as a resistive-capacitive delay element (RC delay element). In addition, the resistor unit 540 of the power management circuit 500 can be an embodiment of the resistor unit 340 shown in FIG. 3. The resistor unit 540 includes a plurality of transistors MR1 ​​to MR3 connected in series with each other in the form of diodes. When each of the multiple transistors MR1 ​​to MR3 configured as diodes is turned on, the voltage drop VD of the resistor unit 540 is approximately equal to the sum of the threshold voltages of each of the multiple transistors MR1 ​​to MR3 configured as diodes.

[0042] In this embodiment, the power management circuit 500 may further include a transistor ML, which can serve as a capacitor coupled between the latch power supply terminal TSL and the latch output terminal TOL of the latch circuit 320. During the ramp-up period of the power supply voltage VCC2, the signal level of the latch output terminal TOL can be pulled up to the power supply voltage VCC2 using the transistor ML.

[0043] Figure 6 illustrates a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit 500 shown in Figure 5. Referring to Figures 5 and 6 together, at time point tA1, the power supply voltage VCC1 begins to rise. For example, the power domain 11 shown in Figure 1 can be activated at time point tA1. Furthermore, since the power supply voltage VCC1 can be applied to the transistor MD1 (as a capacitor) via resistor RD1, the power supply voltage VCCR1 can begin to rise. After a period of time tP, the power supply voltage VCC1 can rise to the threshold level VCT1. The power supply voltage VCCR1 can rise to the threshold voltage of the transistor MNI. Therefore, the transistor MNI can be turned on at time point tA2. In addition, the voltage signal VCOM can decrease to zero or approximately zero.

[0044] At time point tA3, the power supply voltage VCCR1 can be higher than the voltage signal VCOM by a transition threshold, such that the difference between the signal levels of latch input terminals TI1 and TI2, such as |VCCR1-VCOM|, reaches this transition threshold. The control signal SOUTB can transition from this logic high level to this logic low level. Furthermore, the control signal SOUT can transition from this logic low level to this logic high level, thereby indicating that the power supply voltage VCC1 is ready. It is worth noting that when the control signal SOUT transitions from this logic low level to this logic high level, due to the provision of the delay unit 550, the voltage level of the power supply voltage VCC1 can be higher than the voltage level of the power supply voltage VCCR1. The power supply voltage VCC1 can become a sufficiently stable power supply voltage, allowing the device to operate correctly.

[0045] At time tA4, the power supply voltage VCC1 drops below or reaches the threshold level VCT2 (e.g., a power failure occurs). The power supply voltage VCC1 may drop to the threshold voltage of the transistor MNI. The control signal SOUTB may transition from this logic low level to this logic high level. Furthermore, the control signal SOUT may transition from this logic high level to this logic low level, thereby indicating that the power supply voltage VCC1 has become a power supply voltage that is not yet ready. In this embodiment, the threshold level VCT2 may be equal to the threshold level VCT1.

[0046] Since those skilled in the art should be able to understand the operational details of the power management circuit 500 after reading the relevant paragraphs in Figures 1 to 4, further explanation will not be repeated here.

[0047] Referring again to Figures 3 and 4, in some embodiments, the delay unit 350 may provide hysteresis to increase noise immunity and system stability. For example, the delay unit 350 may utilize a delay unit with hysteresis functionality, which can be used to generate a delayed version of the power supply voltage VCC1. During the ramp-up period of the power supply voltage VCC1, the delayed version of the power supply voltage VCC1 rises to a reference level when the VCC1 power supply voltage rises to a first threshold level. During the ramp-down period of the power supply voltage VCC1, the delayed version of the power supply voltage VCC1 falls to the reference level when the power supply voltage VCC1 falls to a second threshold level below the first threshold level. When the reference level is the voltage level of the threshold voltage of the transistor MNI, the first threshold level and the second threshold level may be threshold level VCT1 and threshold level VCT2, respectively. When the power supply voltage VCC1 slopes down to a level between threshold levels VCT1 and VCT2 due to noise interference, the control signal SOUT can still remain at this logic high level because the power supply voltage VCCR1 can still be higher than the threshold voltage level of the transistor MNI. This delay unit with hysteresis function reduces the possibility of false transitions in the control signals SOUTB / SOUT.

[0048] Referring to Figure 7, in some embodiments, the delay unit 350 shown in Figure 3 can be implemented using a delay unit 750. The circuit structure of the power management circuit 700 is similar to / the same as the circuit structure of the power management circuit 500 shown in Figure 5. The main difference is that the delay unit 750 further includes a resistor RD2 and a transistor MD2. In this embodiment, one end of the resistor RD2 is coupled to the inverter input terminal TI and the transistor MD2. The transistor MD2 is used to selectively couple the other end of the resistor RD2 to the reference voltage VSS according to the voltage signal VCOM.

[0049] Figure 8 illustrates a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit 700 shown in Figure 7. Referring to Figures 7 and 8 together, at time point tB1, the power supply voltage VCC1 begins to rise from a low voltage level. Transistor MPI can be turned on, while transistor MNI can be turned off. The voltage signal VCOM can have a sufficiently high level to turn on transistor MD2. Therefore, resistors RD1 and RD2 can act as a voltage divider to divide the power supply voltage VCC1. Since the power supply voltage VCC1 can be applied to transistor MD1 (which acts as a capacitor) via this voltage divider, the power supply voltage VCCR1 can begin to rise. The power supply voltage VCCR1 can be considered as a voltage divider associated with the power supply voltage VCC1.

[0050] After a period of time tQ, the power supply voltage VCC1 can rise to the threshold level VCT1. Furthermore, the power supply voltage VCCR1 can rise to the threshold voltage of the transistor MNI. Therefore, the transistor MNI can be turned on at time point tB2. In some embodiments, since the threshold level VCT1 shown in FIG8 can be higher than the threshold level VCT1 shown in FIG6, the length of this period tQ can be longer than the length of this period tP shown in FIG6. Between time points tB2 and tB3, the transistor MPI can be turned off. The voltage signal VCOM can have a low level, causing the transistor MD2 to be turned off. The voltage level of the power supply voltage VCCR1 can be approximately equal to the voltage level of the power supply voltage VCC1.

[0051] At time point tB3, the difference between the signal levels of the latch input terminals TI1 and TI2, such as |VCCR1-VCOM|, can reach a transition threshold. The control signal SOUTB can transition from this logic high level to this logic low level. Furthermore, the control signal SOUT can transition from this logic low level to this logic high level, thereby indicating that the power supply voltage VCC1 is ready.

[0052] At time point tB4, the power supply voltage VCC1 drops below or reaches the threshold level VCT2 (e.g., a power failure occurs). The power supply voltage VCCR1 may drop below or reach the threshold voltage of transistor MNI. Transistor MNI may be turned off, while transistor MPI may be turned on. The voltage signal VCOM may have a sufficiently high level to turn on transistor MD2. The power supply voltage VCCR1 may again become a voltage divider associated with the power supply voltage VCC1. The control signal SOUTB may transition from this logic low level to this logic high level. Furthermore, the control signal SOUT may transition from this logic high level to this logic low level, thereby indicating that the power supply voltage VCC1 has become a power supply voltage that is not yet ready. In this embodiment, the threshold level VCT2 shown in FIG8 may be equal to the threshold level VCT1 shown in FIG6.

[0053] Since those skilled in the art should be able to understand the operational details of the power management circuit 700 after reading the relevant paragraphs in Figures 1 to 6, further explanation will not be repeated here.

[0054] In some embodiments, the power management scheme provided by this disclosure can be applied to power isolation. FIG9 is a specific embodiment of the integrated circuit 10 shown in FIG1. ​​In this embodiment, the integrated circuit 90 has a plurality of power domains, including a power domain 13, a normally open power domain 14, and power domains 11 and 12 shown in FIG1. ​​The plurality of power domains 11 to 13 can be powered by a plurality of power voltages VCC1 to VCC3 transmitted by the normally open power domain 14. In some embodiments, the plurality of power voltages VCC1 to VCC3 can be switchable power domains.

[0055] The integrated circuit 90 may utilize one or more power gate mechanisms to perform power isolation between different power domains. For example, the integrated circuit 90 may include a power management circuit 900, which can be used for power isolation between a plurality of power domains 11 and 12. The power management circuit 900 may be an embodiment of the power management circuit 100 shown in FIG1. ​​As another example, the integrated circuit 90 may include an isolation cell 901, which can be used for power isolation between a plurality of power domains 11 and 13. The isolation cell 901 may be implemented using (but is not limited to) an OR gate. It is worth noting that in some embodiments, the power management circuit 900 can be used for power isolation between any two of the plurality of power domains 11 to 13 without departing from the scope of protection of this disclosure. Furthermore, the isolation cell 901 can be used for power isolation between any two of the plurality of power domains 11 to 13 without departing from the scope of protection of this disclosure. Furthermore, in some embodiments, the power management circuit 900 may be disposed in the physical medium attachment layer (PMA) 961, the physical coding sublayer (PCS) 962, or the power control module 16 without departing from the scope of protection disclosed herein.

[0056] For ease of explanation, the integrated circuit 90 is described below as at least a part of an application processor (AP) that supports the Mobile Industry Processor Interface (MIPI) specification. Those skilled in the art will understand that the integrated circuit 90 can be implemented as an integrated circuit capable of supporting other types of communication interface specifications without departing from the scope of this disclosure.

[0057] In this embodiment, the integrated circuit 90 may further include the power control module 16 shown in FIG. 1, an image signal processor (ISP) 92, a graphics processing unit (GPU) 94, and a receiver 96. The power control module 16 operates in the normally open power domain 14 and can be used to provide a plurality of power supply voltages VCC1 to VCC3 to a plurality of power domains 11 to 13, and control the power-on / off timing of the plurality of power domains 11 to 13. In addition, the power control module 16 can be used to generate a power status signal, such as a power good signal PWR_OK, to indicate that the plurality of power supply voltages VCC1 to VCC3 are all ready or available for use.

[0058] The image signal processor 92 operates in power domain 11 and can be started by a startup signal PWR_ON provided by the power control module 16. The graphics processing unit 94 operates in power domain 13 and can be controlled by the isolation unit 901 to selectively isolate it from the image signal processor 92. For example (but not limited thereto), when power domain 11 is not yet ready or available, the power control module 16 can transmit a control signal ISO_EN1 with a predetermined level (such as a high logic level). The isolation unit 901 can isolate the signal from power domain 11 and the graphics processing unit 94 in power domain 13 according to the control signal ISO_EN1.

[0059] Receiver 96, such as a Mobile Industry Processor Interface Differential Physical Receiver (MIPI D-PHY Receiver), may have a physical layer that may include a Physical Media Connection Layer (PMA) 961 and a Physical Coding Sublayer (PCS) 962. Using power management circuitry 900 coupled between the PMA and PCS layers 962, the physical layer of receiver 96 may allow for different power-on / off timings. For example (but not limited thereto), when power domain 11 is not ready or unavailable, power management circuitry 900 may disconnect the PMA layer 961 in power domain 11 from the PCS layer 962 in power domain 12 according to a control signal ISO_EN2 provided by power control module 16. In some embodiments, the control signal ISO_EN2 may carry power status information of power supply voltage VCC1, thereby indicating whether power supply voltage VCC1 is ready. In some embodiments, the control signal ISO_EN2 may carry power status information for a plurality of power supply voltages VCC1 and VCC2, thereby indicating whether the plurality of power supply voltages VCC1 and VCC2 are all ready. In some embodiments, the control signal ISO_EN2 may be a power status signal, such as the power good signal PWR_OK or the inverted signal of the power good signal PWR_OK.

[0060] Figure 10 is a specific embodiment of the power management circuit 200 shown in Figure 2. In this embodiment, the power management circuit 1000 shown in Figure 10 can be used to isolate different power domains of the integrated circuit 90 shown in Figure 9. The circuit structure of the power management circuit 1000 is similar to / the same as the circuit structure of the power management circuit 300 shown in Figure 3. The main difference is that the inverter power supply terminal TSI can be selectively coupled to one of a plurality of power supply voltages VCC1 and VCC2. In this embodiment, the power management circuit 1000 may include an inverter circuit 1010, a latch circuit 1020, a switch circuit 1060, an output buffer 1070, and the output buffer 330 shown in Figure 3. The inverter circuit 1010 and the latch circuit 1020 can be embodiments of the inverter circuit 210 and the latch circuit 220 shown in Figure 2, respectively.

[0061] The latch circuit 1020 may utilize (but is not limited to) a cross-coupled inverter pair, which may include a plurality of transistors MLU1, MLD1, MLU2, and MLD2. The latch input terminal TI1 is coupled to the gate of transistor MLD1 to receive a voltage signal PWRB generated by the inverter circuit 1010. The latch input terminal TI2 is coupled to the gate of transistor MLD2 to receive a control signal ISO_EN2 input to the inverter circuit 1010. The control signal ISO_EN2 may be an embodiment of the control signal CS shown in FIG2. The voltage signal PWRB may be an embodiment of the control signal CSB shown in FIG2. The latch power supply terminal TSL is coupled to the source of each of the plurality of transistors MLU1 and MLU2 to receive the power supply voltage VCC2. The latch output terminal TOL is coupled between the drains of the plurality of transistors MLU2 and MLD2 to output the control signal SOUTB. Another latch output terminal TOLC is coupled between the drains of the plurality of transistors MLU1 and MLD1 to output the inverted or complementary signal of the control signal SOUTB.

[0062] The switching circuit 1060 may include a resistor unit 1062, a switch 1064, and a switch 1066. The resistor unit 1062 is coupled between a circuit node NC and the inverter power supply terminal TSI. In this embodiment, the resistor unit 1062 may be implemented by a resistor RG. In some embodiments, the resistor unit 1062 may be implemented using at least one resistor, at least one diode, at least one transistor configured as a diode, at least one circuit unit capable of providing resistance, and combinations thereof, without departing from the scope of this disclosure. The switch 1064 may be selectively coupled between the power supply voltage VCC1 and the inverter power supply terminal TSI according to a control signal PWRS (i.e., the signal level of the latch output terminal TOLC). The switch 1066 may be selectively coupled between the power supply voltage VCC2 and the circuit node NC according to the control signal PWRS. When one of switches 1064 and 1066 is turned on, the other of switches 1064 and 1066 can be turned off. In this embodiment, switches 1064 and 1066 can be implemented using transistors MS1 and MS2, respectively. In some embodiments, switches 1064 and 1066 can be implemented using other types of switching units without departing from the scope of this disclosure.

[0063] The output buffer 1070 is coupled to the latch output terminal TOLC of the latch circuit 1020 and can be used to buffer the complementary signal of the control signal SOUTB to generate the control signal PWRS. In this embodiment, the output buffer 1070 can be implemented using a voltage follower operating at the power supply voltage VCC2.

[0064] Figure 11 illustrates a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit 1000 shown in Figure 10. Referring to Figure 11 together with Figures 9 and 10, before time point tC1, the control signal ISO_EN2 from the normally open power domain 14 has a logic low level (such as 0V). In this embodiment, the control signal ISO_EN2 can be implemented using the power good signal PWR_OK. The power good signal PWR_OK with this logic low level can indicate that a plurality of power supply voltages VCC1 and VCC2 are not yet ready. In addition, the voltage signal PWRB can rise in response to the power supply voltage VCC2 having a rated level V1 (such as 3.3V). For example, the inverter circuit 110 can be implemented using the inverter circuit 310 shown in Figure 3. Since the power good signal PWR_OK input to the gate of a p-channel transistor (such as the transistor MPI shown in Figure 3) has this logic low level, the power supply voltage VCC2 can be applied to the inverter output terminal TO via resistor unit 1062 and the p-channel transistor.

[0065] At time point tC1, because the voltage signal PWRB reaches or exceeds a threshold level, the difference between the signal levels of the latch input terminals TI1 and TI2 (e.g., |PWRB-VCCR1|) will reach or exceed a transition threshold (e.g., 0.9V). The control signal PWRS may have a logic low level, such as 0V, which is valid in power domain 12. The control signal SOUTB may have a logic high level, such as 3.3V, which is valid in power domain 12. Therefore, the control signal SOUT applicable to power domain 12 may have this logic low level to indicate that the plurality of power supply voltages VCC1 and VCC2 are not yet ready. Furthermore, since the control signal PWRS may be at this logic low level in response to the power good signal PWR_OK, switch 1064 is open and switch 1066 is on before power supply voltage VCC1 is ready.

[0066] At time tC2, the power supply voltage VCC1 reaches its rated level V2, such as 1.2V. After a delay, the power good signal PWR_OK transitions to a logic high level V3, such as 1.2V, at time tC3. At time tC4, the voltage signal PWRB may drop to voltage level V4, which may be equal to or approximately equal to the power supply voltage VCC2 minus the voltage drop VDG. The voltage drop VDG is generated based on a current signal flowing through resistor RG. For example (but not limited to this disclosure), voltage level V4 may be close to 0V, such as 0.2V.

[0067] At time tC5, because the difference between the signal levels of latch input terminals TI1 and TI2 (e.g., |PWR_OK-PWRB|) reaches or exceeds a transition threshold (e.g., 0.9V), both control signals PWRS and SOUT can transition to that logic high level (e.g., 3.3V) in power domain 12. Since control signal PWRS is at that logic high level in response to the power-good signal PWR_OK, switch 1064 is turned on and switch 1066 is turned off when multiple power supply voltages VCC1 and VCC2 are ready. At time tC6, because switch 1064 is turned on to couple power supply voltage VCC1 to inverter input terminal TI, voltage signal PWRB can drop to that logic low level (e.g., 0V) in power domain 11.

[0068] At time tC7, the power control module 16 deserts the power good signal PWR_OK (i.e., the control signal ISO_EN2) to shut down power domain 11. The power good signal PWR_OK can transition from this logic high level in normally open power domain 14 to this logic low level. At time tC8, since the difference between the signal levels of latch input terminals TI1 and TI2 (e.g., |PWRB-PWR_OK|) reaches or exceeds a transition threshold (e.g., 0.9V), both control signals PWRS and SOUT can transition to this logic low level in power domain 12. The voltage signal PWRB can rise to approximately equal to the rated level of the power supply voltage VCC1 (e.g., 1.2V). At time tC9, since switch 1066 is turned on according to the control signal PWRS, the power supply voltage VCC2 is coupled to the inverter power supply terminal TI via resistor unit 1062. The voltage signal PWRB can rise to the rated level V1 of the power supply voltage VCC2.

[0069] Using the power good signal PWR_OK, which indicates the power status of power supply voltage VCC1, when power supply voltage VCC1 is not yet ready or usable, the power management circuit 1000 can isolate one or more circuit blocks (such as physical media connection layer 961) in power domain 11 and power domain 12. Furthermore, when both power supply voltage VCC1 and power supply voltage VCC2 are ready, the power management circuit 1000 can generate control signals SOUTB / SOUT applicable to power domain 12 to allow power domain 11 to be coupled to the one or more circuit blocks in power domain 12.

[0070] In some embodiments, the control signal ISO_EN2 may also carry power state information of the power supply voltage VCC2. When one of the plurality of power supply voltages VCC1 and VCC2 is ready while the other is not (e.g., during power-on timing), the control signal ISO_EN2 may be at a first level (such as one of a logic high level and a logic low level). When both the plurality of power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 may be at a second level different from the first level. FIG12 illustrates a schematic diagram of another embodiment of the signal waveforms involved in the operation of the power management circuit 1000 shown in FIG10. The signal waveforms shown in FIG12 are similar / identical to those shown in FIG11, except that the control signal ISO_EN2 may be at a logic high level before the power supply voltage VCC2 is ready. Furthermore, when power supply voltage VCC2 is ready but power supply voltage VCC1 is not yet ready, the control signal ISO_EN2 can be at a low logic level. When multiple power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 can return to a high logic level. Since those skilled in the art should understand the operational details of the power management circuit 1000 shown in Figure 10 using the signal waveform shown in Figure 12 after reading the relevant paragraphs in Figures 1 to 11, further explanation will not be repeated here.

[0071] In some embodiments, the power management scheme provided by this disclosure can utilize the inverted signal of the power good signal (provided by the normally open power domain) for power isolation. FIG13 is another specific embodiment of the power management circuit 200 shown in FIG2. In this embodiment, the power management circuit 1300 shown in FIG13 can be used to isolate different power domains of the integrated circuit 90 shown in FIG9. The circuit structure of the power management circuit 1300 is similar to / identical to the circuit structure of the power management circuit 1000 shown in FIG10, the main difference being that the power supply voltage VCC1 can be coupled to the inverter power supply terminal TSI before it is ready. In addition, the output buffer 1330 can be implemented using a voltage follower. In this embodiment, the power management circuit 1300 can utilize a power status signal PWR_OKN (which is the inverted signal of the power good signal PWR_OK shown in FIG9) for power isolation. The power status signal PWR_OKN can be an embodiment of the control signal ISO_EN2 shown in FIG9.

[0072] Figure 14 illustrates a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit 1300 shown in Figure 13. Referring to Figure 14 together with Figures 9 and 13, before time point tD1, the power status signal PWR_OKN may be at a logic high level to indicate that the plurality of power supply voltages VCC1 and VCC2 are not yet ready. The voltage signal PWRB input to the latch input terminal TI1 may have a logic low level. Therefore, the signal level of the latch input terminal TI1 will be lower than the signal level of the latch input terminal TI2. The control signal SOUTB may have a logic low level to indicate that the power supply voltage VCC1 is not yet ready. The power management circuit 1300 may generate a control signal SOUT with a logic low level to isolate the power domain 11 from the physical media connection layer 961 operating in the power domain 12.

[0073] At time tD1, the power status signal PWR_OKN may transition to a logic low level to indicate that multiple power supply voltages VCC1 and VCC2 are ready. The signal level of latch input terminal TI1 will be higher than the signal level of latch input terminal TI2. The control signal SOUTB may have a logic high level. The power management circuit 1300 may generate a control signal SOUT with a logic high level, thereby allowing the signal to be transmitted from power domain 11 to the physical media connection layer 961 operating in power domain 12. At time tD2, the power control module 16 may deactivate the power good signal PWR_OK to shut down power domain 11. The power status signal PWR_OKN may transition to this logic high level. Power domain 11 may again be isolated from the physical media connection layer 961 operating in power domain 12.

[0074] In some embodiments, the control signal ISO_EN2 may also carry power state information of the power supply voltage VCC2. When one of the plurality of power supply voltages VCC1 and VCC2 is ready while the other is not (e.g., during power-on timing), the control signal ISO_EN2 may be at a first level (such as one of a logic high level and a logic low level). When both the plurality of power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 may be at a second level different from the first level. FIG15 illustrates a schematic diagram of another embodiment of the signal waveforms involved in the operation of the power management circuit 1300 shown in FIG13. The signal waveforms shown in FIG15 are similar / identical to those shown in FIG14, except that the control signal ISO_EN2 may be at a logic low level before the power supply voltage VCC2 is ready. Furthermore, when power supply voltage VCC2 is ready but power supply voltage VCC1 is not yet ready, the control signal ISO_EN2 can transition to a logic high level. When multiple power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 can return to a logic low level. Since those skilled in the art should understand the operational details of the power management circuit 1300 shown in Figure 13 using the signal waveform shown in Figure 15 after reading the relevant paragraphs in Figures 1 to 14, further explanation will not be repeated here.

[0075] As described above, the power management scheme provided by this disclosure can convert a control signal applicable to one power domain into a control signal applicable to another power domain, thereby performing power control operations. For example (but this disclosure is not limited thereto), the aforementioned power management circuits 200 / 300 / 1000 / 1300 can be implemented as including a level shifter and an output buffer. In the embodiment shown in FIG2, the inverter circuit 210 and the latching circuit 220 can be used to implement at least a portion of the level shifter 202. In the embodiment shown in FIG3, the inverter circuit 310, the latching circuit 320, and the resistor unit 340 can be used to implement at least a portion of the level shifter 302. In the embodiment shown in FIG10, the inverter circuit 1010, the latching circuit 1020, and the switching circuit 1060 can be used to implement at least a portion of the level shifter 1002. In the embodiment shown in FIG13, inverter circuit 1010 and latch circuit 1020 can be used to implement at least a portion of level shifter 1302.

[0076] In some embodiments, the power management scheme provided by this disclosure can utilize a single-ended level shifter and an output buffer for power isolation. FIG16 is another specific embodiment of the power management circuit 200 shown in FIG2. In this embodiment, the power management circuit 1600 can be used to isolate different power domains of the integrated circuit 90 shown in FIG9. Furthermore, the power management circuit 1600 can be implemented to include a single-ended level shifter.

[0077] Referring to Figures 9 and 16 together, the power management circuit 1600 may include a level shifter 1602 and the output buffer 330 shown in Figure 3. The level shifter 1602 is powered by the power supply voltage VCC2 used in power domain 12. The level shifter 1602 can be used to convert the control signal ISO_EN2 into a control signal SOUTB suitable for power domain 12. In this embodiment, the level shifter 1602 includes a transistor MLS and a resistor unit RS (such as a resistor). Furthermore, the control signal ISO_EN2 used to control the switching state of the transistor MLS may be implemented using a power status signal (such as a power good signal PWR_OK).

[0078] During operation, before the power supply voltage VCC1 is ready, the power good signal PWR_OK is at a logic low level. The transistor MLS is turned off. The control signal SOUTB may have a logic high level, such as the rated level of the power supply voltage VCC2. The control signal SOUT may have a logic low level to indicate that the power supply voltage VCC1 is not yet ready. The power management circuit 1600 may isolate the physical media connection layer 961 in power domain 11 and power domain 12 according to the control signal SOUT. When all power supply voltages VCC1 and VCC2 are ready, the power good signal PWR_OK transitions from this logic low level to a logic high level to turn on the transistor MLS. The control signal SOUTB may transition to this logic low level. The control signal SOUT may transition to this logic high level, which may indicate that all power supply voltages VCC1 and VCC2 are ready. The power management circuit 1600 can allow the power domain 11 to be coupled to the physical media connection layer 961 in the power domain 12 according to the control signal SOUT.

[0079] It is worth noting that the power management scheme provided in this disclosure can utilize a single control signal (such as a power status signal provided directly from a normally open power domain) to perform power isolation between different power domains. Referring again to Figures 9 and 13, in some embodiments, since the control signal ISO_EN2 can be level-shifted to a control signal applicable to power domain 13, the power management circuit 900 can isolate one or more circuit blocks in power domain 11 and power domain 13 according to the control signal ISO_EN2. For example, when the power management circuit 900 is used to isolate the graphics processing unit 94 in power domain 11 and power domain 13, the inverter circuit 110 and the latch circuit 1020 can be powered by power supply voltages VCC1 and VCC3, respectively. The level shifter 1302 can still receive the power status signal PWR_OKN, which can be converted into the control signal SOUTB, which can be used in power domain VCC3. Using the power management solution provided in this disclosure, a single control signal can be used to isolate power between multiple power domains, thereby reducing circuit chip area and power consumption.

[0080] Figure 17 is a flowchart of an embodiment of the method for managing an integrated circuit disclosed herein. For ease of explanation, method 1700 will be described below based on the integrated circuit shown in Figure 9 and the level shifter shown in Figure 2. Those skilled in the art will understand that method 1700 can be applied to the integrated circuit 10 shown in Figure 1 or other integrated circuits having a plurality of power domains without departing from the scope of this disclosure. Furthermore, those skilled in the art will understand that method 1700 can utilize other level shifters, such as level shifter 302 shown in Figure 3, level shifter 1002 shown in Figure 10, level shifter 1302 shown in Figure 13, level shifter 1602 shown in Figure 16, or other types of level shifters without departing from the scope of this disclosure. In addition, in some embodiments, other operations may be performed in method 1700. In some embodiments, the operations in method 1700 may be performed in different sequences or implemented by other operations. In some embodiments, one or more operations of method 1700 may be omitted.

[0081] In operation 1702, a bit shifter is used and operated at a first power supply voltage to a first power supply domain of the integrated circuit. The first power supply domain is used to receive an input signal from a second power supply domain of the integrated circuit, which is powered by a second power supply voltage. For example, the bit shifter 202 may be powered by power supply voltage VCC2 in power supply domain 12. The physical media connection layer 961 in power supply domain 12 may receive an input signal, such as a data entry or a control input, from the physical coding sublayer 962 in power supply domain 11, which is powered by power supply voltage VCC1.

[0082] In operation 1704, when the first power supply voltage is ready but the second power supply voltage is not ready, a level shifter is used to convert a first control signal into a second control signal having a first logic level to isolate the second power domain from the first power domain, wherein the first control signal at least indicates the power state of the second power supply voltage. For example, level shifter 202 may be implemented in power management circuit 900. When power supply voltage VCC2 is ready but power supply voltage VCC1 is not ready, level shifter 202 may be used to convert control signal CS into control signal SOUTB having a first logic level (such as a logic high level and a logic low level) to isolate power domain 11 from power domain 12. Therefore, the input signal (which may have an unknown state transmitted from power domain 11) can be isolated from power domain 12. The entity coding sublayer 962 in power domain 11 may not be coupled to the entity media connection layer 961 in power domain 12.

[0083] In some embodiments, the control signal CS shown in FIG2 may be implemented using a power status signal provided by the normally open power domain 14. In some embodiments, the control signal CS shown in FIG2 may be implemented using a power status signal that indicates whether the power supply voltage VCC1 is ready. In some embodiments, the control signal CS shown in FIG2 may be implemented using a power status signal that indicates whether both the power supply voltage VCC1 and the power supply voltage VCC2 are ready. For example, the control signal CS may be implemented by the power good signal PWR_OK transmitted by the power control module 16. As another example, the control signal CS may be implemented by the control signal ISO_EN2 having a signal waveform similar to / the same as that of FIG11, FIG12, FIG14 or FIG15.

[0084] In operation 1706, when both the first power supply voltage and the second power supply voltage are ready, the level shifter converts the first control signal into a second control signal having a second logic level, allowing the first power domain to receive the input signal from the second power domain. For example, when both power supply voltages VCC1 and VCC2 are ready, level shifter 202 can be used to convert the control signal CS into a control signal SOUTB having a second logic level (such as the other of the logic high level and the logic low level), allowing power domain 12 to receive the input signal from power domain 11. Therefore, the input signal provided by power domain 11 can be transmitted to power domain 12. The physical coding sublayer 962 in power domain 11 can be coupled to the physical media connection layer 961 in power domain 12.

[0085] Since those skilled in the art should be able to understand the operational details of the power management circuit 1700 after reading the relevant paragraphs in Figures 1 to 16, further explanation will not be repeated here.

[0086] The foregoing description briefly outlines the features of certain embodiments of this disclosure, enabling those skilled in the art to gain a more comprehensive understanding of the various aspects of this disclosure. Those skilled in the art will understand that they can readily utilize this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0008] The various embodiments disclosed herein can be clearly understood by reading the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the size of certain features may be arbitrarily enlarged or reduced for clear description. FIG1 is a schematic diagram of an embodiment of an integrated circuit including a plurality of power domains disclosed herein. FIG2 is a functional block diagram of an embodiment of at least a portion of a power management circuit disclosed herein. FIG3 is a schematic diagram of a specific embodiment of the power management circuit shown in FIG2. FIG4 is a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit shown in FIG3. FIG5 is a schematic diagram of another specific embodiment of the power management circuit shown in FIG2. FIG6 is a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit shown in FIG5. FIG7 is a schematic diagram of another specific embodiment of the power management circuit shown in FIG2. FIG8 is a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit shown in FIG7. FIG9 is a schematic diagram of an embodiment of the integrated circuit shown in FIG1. Figure 10 is a schematic diagram of another specific embodiment of the power management circuit shown in Figure 2. Figure 11 is a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit shown in Figure 10. Figure 12 is a schematic diagram of another embodiment of the signal waveforms involved in the operation of the power management circuit shown in Figure 10. Figure 13 is a schematic diagram of another specific embodiment of the power management circuit shown in Figure 2. Figure 14 is a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit shown in Figure 13. Figure 15 is a schematic diagram of another embodiment of the signal waveforms involved in the operation of the power management circuit shown in Figure 13. Figure 16 is a schematic diagram of another specific embodiment of the power management circuit shown in Figure 2. Figure 17 is a flowchart of an embodiment of the method for managing an integrated circuit disclosed herein.

Claims

1. A power management circuit for an integrated circuit, comprising: a bit shifter powered at least by a first power supply voltage usable in a first power domain of the integrated circuit, the bit shifter being configured to convert a first control signal into a second control signal usable in the first power domain, the first control signal indicating a power state of a second power supply voltage usable in a second power domain of the integrated circuit, the first power supply voltage being ready before the second power supply voltage, the second power domain being different from the first power domain, wherein the first control signal is provided by a third power domain different from both the first and second power domains; and an output buffer coupled to the bit shifter for buffering the second control signal to generate a third control signal, and thereby performing power control of the integrated circuit.

2. The power management circuit as described in claim 1, wherein the third power domain is a normally open power domain.

3. The power management circuit as claimed in claim 1, wherein the first control signal is a power status signal used to indicate whether the first power supply voltage and the second power supply voltage are both ready.

4. The power management circuit as claimed in claim 1, wherein when the first control signal indicates that the second power supply voltage is not yet ready, the output buffer generates the third control signal to isolate the second power domain from a portion of the integrated circuit operating in the first power domain; and when the first control signal indicates that the second power supply voltage is ready, the output buffer generates the third control signal to allow the second power domain to be coupled to that portion of the integrated circuit.

5. The power management circuit as claimed in claim 1, wherein the level shifter comprises: an inverter circuit having an inverter input terminal and an inverter output terminal, the inverter circuit being configured to receive the first control signal from the inverter input terminal and generate a fourth control signal at the inverter output terminal; and a latching circuit having a latching power supply terminal, a first latching input terminal and a second latching input terminal, the latching power supply terminal being coupled to a power supply voltage supplied to the first power source, the first latching input terminal being coupled to the inverter output terminal to receive the fourth control signal, the second latching input terminal being coupled to the inverter input terminal to receive the first control signal, the latching circuit being configured to generate the second control signal according to the respective signal levels of the first control signal and the fourth control signal.

6. The power management circuit as claimed in claim 5, wherein one inverter power supply terminal of the inverter circuit is used to receive the second power supply voltage; wherein when the second power supply voltage is not yet ready, the first control signal has a first logic level; and when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level.

7. The power management circuit as claimed in claim 5, wherein the latching circuit further includes a first latcher output terminal and a second latcher output terminal, the first latcher output terminal being used to output the second control signal; the level shifter further includes: a resistor unit coupled between a circuit node and an inverter power supply terminal of the inverter circuit; a first switch selectively coupled between the first power supply voltage and the circuit node according to the signal level of the second latcher output terminal; and a second switch selectively coupled between the second power supply voltage and the inverter power supply terminal according to the signal level of the second latcher output terminal; wherein when the second power supply voltage is not yet ready, the first control signal has a first logic level, the first switch is turned on, and the second switch is turned off; when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level, the first switch is turned off, and the second switch is turned on.

8. The power management circuit as claimed in claim 1, wherein the level shifter comprises: a resistor unit coupled between the first power supply voltage and an input terminal of the output buffer; and a transistor having a control terminal, a first connection terminal and a second connection terminal, wherein the control terminal is coupled to the first control signal, the first connection terminal is coupled to the input terminal of the output buffer, and the second connection terminal is coupled to a reference voltage.

9. The power management circuit as claimed in claim 1, wherein the first control signal further indicates the power state of the first power supply voltage; when neither the first power supply voltage nor the second power supply voltage is ready, the first control signal has a first logic level; when the first power supply voltage is ready but the second power supply voltage is not ready, the first control signal has a second logic level different from the first logic level; when both the first power supply voltage and the second power supply voltage are ready, the first control signal has the first logic level.

10. A power management circuit for an integrated circuit, comprising: a level shifter powered at least by a first power supply voltage usable in a first power domain of the integrated circuit, the level shifter being configured to convert a first control signal into a second control signal usable in the first power domain, the first control signal indicating whether both the first power supply voltage usable in the first power domain of the integrated circuit and a second power supply voltage usable in a second power domain of the integrated circuit are ready, the first power supply voltage being ready earlier than the second power supply voltage, the second power domain being different from the first power domain; and an output buffer coupled to the level shifter for buffering the second control signal to generate a third control signal, and thereby performing power control of the integrated circuit.

11. The power management circuit as claimed in claim 10, wherein the first control signal is provided by a third power domain different from the first power domain and the second power domain.

12. The power management circuit of claim 10, wherein when the first control signal indicates that the second power supply voltage is not yet ready, the output buffer generates the third control signal to isolate the second power domain from a portion of the integrated circuit operating in the first power domain; and when the first control signal indicates that the second power supply voltage is ready, the output buffer generates the third control signal to allow the second power domain to be coupled to that portion of the integrated circuit.

13. The power management circuit as claimed in claim 10, wherein the level shifter comprises: an inverter circuit having an inverter input terminal and an inverter output terminal, the inverter circuit being configured to receive the first control signal from the inverter input terminal and generate a fourth control signal at the inverter output terminal; and a latching circuit having a latching power supply terminal, a first latching input terminal and a second latching input terminal, the latching power supply terminal being coupled to a power supply voltage supplied to the first power supply, the first latching input terminal being coupled to the inverter output terminal to receive the fourth control signal, the second latching input terminal being coupled to the inverter input terminal to receive the first control signal, the latching circuit being configured to generate the second control signal according to the respective signal levels of the first control signal and the fourth control signal.

14. The power management circuit as claimed in claim 13, wherein one inverter power supply terminal of the inverter circuit is used to receive the second power supply voltage; wherein when the second power supply voltage is not yet ready, the first control signal has a first logic level; and when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level.

15. The power management circuit as claimed in claim 13, wherein the latching circuit further includes a first latcher output terminal and a second latcher output terminal, the first latcher output terminal being used to output the second control signal; the level shifter further includes: a resistor unit coupled between a circuit node and an inverter power supply terminal of the inverter circuit; a first switch selectively coupled between the first power supply voltage and the circuit node according to the signal level of the second latcher output terminal; and a second switch selectively coupled between the second power supply voltage and the inverter power supply terminal according to the signal level of the second latcher output terminal; wherein when the second power supply voltage is not yet ready, the first control signal has a first logic level, the first switch is turned on, and the second switch is turned off; when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level, the first switch is turned off, and the second switch is turned on.

16. The power management circuit as claimed in claim 10, wherein the level shifter comprises: a resistor unit coupled between the first power supply voltage and an input terminal of the output buffer; and a transistor having a control terminal, a first connection terminal and a second connection terminal, wherein the control terminal is coupled to the first control signal, the first connection terminal is coupled to the input terminal of the output buffer, and the second connection terminal is coupled to a reference voltage.

17. The power management circuit as claimed in claim 10, wherein when neither the first power supply voltage nor the second power supply voltage is ready, the first control signal has a first logic level; when the first power supply voltage is ready but the second power supply voltage is not ready, the first control signal has a second logic level different from the first logic level; and when both the first power supply voltage and the second power supply voltage are ready, the first control signal has the first logic level.

18. A method of managing an integrated circuit, comprising: operating a bit shifter at a first power supply voltage supplying a first power supply domain of the integrated circuit, wherein the first power supply domain is configured to receive an input signal from a second power supply domain of the integrated circuit, the second power supply domain being powered by a second power supply voltage; when the first power supply voltage is ready but the second power supply voltage is not ready, using the bit shifter to convert a first control signal provided by a third power supply domain different from the first and second power supply domains into a second control signal having a first logic level to isolate the second power supply domain from the first power supply domain, wherein the first control signal at least indicates a power state of the second power supply voltage; and when both the first and second power supply voltages are ready, using the bit shifter to convert the first control signal provided by the third power supply domain into the second control signal having a second logic level different from the first logic level to allow the first power supply domain to receive the input signal from the second power supply domain.

19. The method as described in claim 18, wherein the third power domain is a normally-on power domain.

20. The method as described in claim 19, wherein the first control signal is a power status signal indicating whether both the first power supply voltage and the second power supply voltage are ready.

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