Circuit module with improved line load
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2021-08-03
- Publication Date
- 2023-02-16
Smart Images
Figure TWG2TA000894984_001 
Figure TWG2TA000894984_002 
Figure TWG2TA000894984_003
Abstract
Description
[Technical Field]
[0001] The present invention relates to a circuit module with improved interconnect load, and more particularly to a circuit module comprising an intermediate circuit and organizing multiple internal circuit blocks into different groups with different short connections, wherein when a signal is transmitted on one of the short connections, the intermediate circuit can latch the signal and drive it to the other short connections. [Previous Technology]
[0002] Various circuit modules, such as memory modules, are important basic building blocks of integrated circuits (semiconductor chips).
[0003] Figures 1a and 1b respectively illustrate the waveform timing of a known memory module 100 and related signals. As shown in Figure 1a, the known memory module 100 includes memory banks bk1 to bk4, a long connection line L0, and a control and input / output circuit gctrl_io_0. The connection line L0 extends across memory banks bk1 to bk4 to couple to memory banks bk1 to bk4, and is coupled to the control and input / output circuit gctrl_io_0 at node QBI_M0. Through the connection line L0, each memory bank bk1 to bk4 can transfer its stored data to the control and input / output circuit gctrl_io_0. The control and input / output circuit gctrl_io_0 controls the operating timing of the circuit module 100 according to a clock CK0. This timing control includes: providing a signal SAT0 to memory banks bk1 to bk4 to control the timing of data transfer from memory banks bk1 to bk4.
[0004] In Figure 1b, the period T0 represents one cycle of the clock CK0, and the waveform vL0 is the voltage waveform of the connection L0 at node QBI_M0. When one of the memory banks bk1 to bk4 needs to transfer data to the control and input / output circuit gctrl_io_0 via the connection L0, the voltage of the connection L0 will be driven according to the data content when the signal SAT0 is at voltage v_on, and the driving of the connection L0 will stop when the signal SAT0 switches to another voltage v_off. For example, during the cycle from time tp1 to tp2, signal SAT0 switches from voltage v_off to voltage v_on at time t11 and switches back to voltage v_off at time t13. Correspondingly, assuming memory bank bk2 needs to transfer one bit of data (bit 0) to the control and input / output circuit gctrl_io_0 during this cycle, it will start driving connection L0 after time t11, and at time t12, pull the voltage of connection L0 down to the voltage v0 representing bit 0, as shown in waveform vL0. Based on the voltage of connection L0, the control and input / output circuit gctrl_io_0 can determine what data memory bank bk2 is transferring. After time t13, signal SAT0 returns to voltage v_off, and memory bank bk2 (as well as other memory banks bk1, bk3, and bk4) will stop driving connection L0.
[0005] Similarly, in the next cycle from time tp2 to tp3, signal SAT0 will switch from voltage v_off to voltage v_on at time t21, and switch back to voltage v_off at time t23. Assuming that memory bank bk3 needs to transfer one bit of data (digit 1) to the control and input / output circuit gctrl_io_0 in this cycle, it will start driving connection L0 after time t21, and pull the voltage of connection L0 high to the voltage v1 representing digit 1 at time t22. After time t23, memory bank bk3 (and other memory banks bk1, bk2, and bk4) will stop driving connection L0.
[0006] The disadvantages of the above-mentioned prior art can be summarized as follows. First, because the connection L0 needs to extend across all four memory banks kb1 to kb4, its length is relatively long; for example, if each of the memory banks kb1 to kb4 contains a memory array with 512 word lines, then the connection L0 needs to cross a total of 512*4=2048 word lines. Due to the long length of the connection L0, its equivalent load is also relatively high, and the time (such as time points t11 to t12 or t21 to t22) required for one of the memory banks bk1 to bk4 to drive the connection L0 to the desired voltage will also be relatively long; consequently, the data access speed (frequency) is also difficult to improve. Furthermore, the drive circuits in the memory banks bk1 to bk4 used to drive the connection L0 also require a large layout area to provide sufficient driving force.
[0007] Furthermore, when signal SAT0 switches from voltage v_off to voltage v_on (e.g., at times t11 and t21) causing one of the memory banks bk1 to bk4 to start driving connection L0, once signal SAT0 switches back from voltage v_on to voltage v_off (e.g., at times t13 and t23), the voltage of connection L0 is no longer driven and begins to float, neither the voltage v0 of digit 0 nor the voltage v1 of digit 1. As shown in Figure 1b, between times t13 and t21, because signal SAT0 is at voltage v_off, memory banks bk1 to bk4 do not drive connection L0, so the voltage of connection L0 will drift to an uncertain voltage vf0 between voltage v0 and v1, and cannot be maintained at voltage v0 or v1; consequently, the data hold-time of node QBI_M0 will also be insufficient. [Summary of the Invention]
[0008] One object of the present invention is to provide a circuit module (e.g., 200, FIG. 2) with improved interconnect load. The circuit module may include a first interconnect and a second interconnect (e.g., L1 and L2, FIG. 2 and 4), a first switch and a second switch (e.g., s1 and s2), and a second driver (e.g., d2). The first switch is coupled between the first interconnect and a first node (e.g., QBI), and can be turned on and off to conduct or de-conduct between the first interconnect and the first node. The second switch is coupled between the second interconnect and the first node, and can be turned on and off to conduct or de-conduct between the second interconnect and the first node. The second driver may include a second driver input (e.g., i2) and a second driver output (e.g., o2), respectively coupled to a second node (e.g., QBII) and the second interconnect. The second driver can be enabled and disabled to drive and de-drive the second interconnect according to the voltage of the second node. The voltage of the second node is controlled by the voltage of the first node. When the first switch is on, the second switch can be closed; when the second switch is on, the first switch can be closed. When the second switch is closed, the second driver can be enabled; when the second switch is on, the second driver can be disabled.
[0009] In one embodiment, the circuit module may further include a buffer (e.g., b1, Figures 2 and 4). The buffer may include a buffer input (e.g., i3) and a buffer output (e.g., o3), respectively coupled to the first node and the second node. In one embodiment, the buffer may further include a first inverter (e.g., iv1, Figure 4), coupled between the buffer input and the buffer output.
[0010] In one embodiment, the circuit module may further include one or more first circuit blocks (e.g., BK[M0+1] to BK[M], FIG. 2) coupled to the first connection. When one of the one or more first circuit blocks needs to transmit data, the first connection is driven according to the data after the first switch is turned on (e.g., at time tu1, FIG. 5) (e.g., at time ta1), and the driving of the first connection is stopped before the first switch is turned off (e.g., at time tu2) (e.g., at time ta3). In one embodiment, each of the first circuit blocks may be a memory bank. In one embodiment, the circuit module may further include a latch (e.g., h1, FIG. 2 and 4) coupled to the first node. When one of the one or more first circuit blocks stops driving the first connection (e.g., at time ta3, FIG. 5), the latch maintains the voltage of the first node, preventing the voltage of the first node from floating.
[0011] In one embodiment, the latch may include a third inverter and a fourth inverter (e.g., iv3 and iv4, FIG. 4). The third inverter may include a third inverter input and a third inverter output, respectively coupled to the first node and an internal node (e.g., n0). The fourth inverter may include a fourth inverter input and a fourth inverter output, respectively coupled to the internal node and the first node.
[0012] In one embodiment, during a period of time (e.g., from time tu2 to t2, FIG. 5), both the first switch and the second switch are closed.
[0013] In one embodiment, the circuit module may further include one or more second circuit blocks (e.g., BK[1] to BK[M0], FIG. 2) coupled to the second connection. When one of the one or more second circuit blocks needs to transmit data, the second connection is driven according to the data (e.g., at time td1, FIG. 5) after the second switch is turned on (e.g., at time td1), and the driving of the second connection is stopped before the second switch is turned off (e.g., at time td2) (e.g., at time tb3). In one embodiment, each of the second circuit blocks may be a memory bank.
[0014] In one embodiment, the circuit module may further include a first driver (e.g., d1, Figures 2 and 4). The first driver may include a first driver input (e.g., i1) and a first driver output (e.g., o1), respectively coupled to the second node and the first connection. The first driver can be enabled and disabled to drive the first connection and stop driving the first connection according to the voltage of the second node. Specifically, the first driver can be enabled when the first switch is closed and disabled when the first switch is open.
[0015] In one embodiment (e.g., FIG. 4), the first driver may further include a first transistor, a second transistor, a seventh transistor, and an eighth transistor (e.g., N1, N2, P1, and P2, FIG. 4). The first transistor may include a first controlled terminal (e.g., a gate terminal) and a first channel terminal (e.g., n1). The second transistor may include a second controlled terminal and two second channel terminals (e.g., a source terminal and a drain terminal), the two second channel terminals being respectively coupled to the first channel terminal and the output terminal of the first driver. The eighth transistor may include an eighth controlled terminal and an eighth channel terminal (e.g., n2). The seventh transistor may include a seventh controlled terminal and two seventh channel terminals, the two seventh channel terminals being respectively coupled to the eighth channel terminal and the output terminal of the first driver. One of the first controlled terminal and the second controlled terminal is coupled to the input terminal of the first driver, and the other of the first controlled terminal and the second controlled terminal is coupled to a first inverting selection signal (e.g., LC34b). One of the seventh controlled terminal and the eighth controlled terminal is coupled to the first driver input terminal, and the other of the seventh controlled terminal and the eighth controlled terminal is coupled to a first selection signal (e.g., LC34); the first selection signal and the first inverting selection signal are inverted.
[0016] In one embodiment (e.g., FIG. 4), the first switch may include a fifth transistor (e.g., N5, FIG. 4) and / or an eleventh transistor (e.g., P5). The fifth transistor may include a fifth controlled terminal and two fifth channel terminals, respectively coupled to the first selection signal, the first node, and the first connection. The eleventh transistor may include an eleventh controlled terminal and two eleventh channel terminals, respectively coupled to the first inverting selection signal, the first node, and the first connection.
[0017] In one embodiment (e.g., FIG. 4), the second driver may further include a third transistor, a fourth transistor, a ninth transistor, and a tenth transistor (e.g., N3, N4, P3, and P4, FIG. 4). The third transistor may include a third controlled terminal and a third channel terminal (e.g., n3). The fourth transistor may include a fourth controlled terminal and two fourth channel terminals, the two fourth channel terminals being respectively coupled to the third channel terminal and the output terminal of the second driver. The tenth transistor may include a tenth controlled terminal and a tenth channel terminal (e.g., n4). The ninth transistor may include a ninth controlled terminal and two ninth channel terminals, the two ninth channel terminals being respectively coupled to the tenth channel terminal and the output terminal of the second driver. One of the third controlled terminal and the fourth controlled terminal is coupled to the input terminal of the second driver, and the other of the third controlled terminal and the fourth controlled terminal is coupled to a second inverting selection signal (e.g., LC12b). One of the ninth controlled terminal and the tenth controlled terminal is coupled to the second driver input terminal, and the other of the ninth controlled terminal and the tenth controlled terminal is coupled to a second selection signal (e.g., LC12); the second selection signal and the second inverted selection signal are inverted.
[0018] In one embodiment (e.g., FIG. 4), the second switch may include a sixth transistor (e.g., N6, FIG. 4) and / or a twelfth transistor (e.g., P6). The sixth transistor may include a sixth controlled terminal and two sixth channel terminals, respectively coupled to the second selection signal, the first node, and the second connection. The twelfth transistor may include a twelfth controlled terminal and two twelfth channel terminals, respectively coupled to the second inverting selection signal, the first node, and the second connection.
[0019] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:
Implementation Method
[0021] Figure 2 illustrates a circuit module 200 according to an embodiment of the present invention, which may include M circuit blocks BK[1] to BK[M] and a control and input / output circuit gctrl_io; in order to implement the technology of the present invention, the circuit module 200 further includes an intermediate circuit 210 and two connecting lines L1 and L2. For example, the circuit module 200 may be a memory module, and each circuit block in the circuit blocks BK[1] to BK[M] may be a memory bank, including a memory array (not shown), such as a static random access memory array with 512 word lines. Circuit blocks BK[1] to BK[M] can be organized into two groups. Circuit blocks BK[M0+1] to BK[M] ((M0+1)<M) form a first group, which is coupled to node QBI_U of intermediate circuit 210 via line L1. Circuit blocks BK[1] to BK[M0] form a second group, which is coupled to node QBI_D of intermediate circuit 210 via line L2. The numbers M0 and M can be two preset integers. In one implementation, the number M can be twice the number M0 (M=2*M0). For example, the numbers M0 and M can be 2 and 4 respectively. That is, circuit module 200 can contain four circuit blocks BK[1] to BK[4]. Circuit blocks BK[3] and BK[4] form one group, which is coupled to line L1. Circuit blocks BK[1] and BK[2] form another group, which is coupled to line L2.
[0022] The intermediate circuit 210 is coupled to the control and input / output circuit gctrl_io at node QBI_M. Circuit blocks BK[1] to BK[M0] can transmit data to the control and input / output circuit gctrl_io via the connection L2 and the intermediate circuit 210; circuit blocks BK[M0+1] to BK[M] can transmit data to the control and input / output circuit gctrl_io via the connection L1 and the intermediate circuit 210. The control and input / output circuit gctrl_io controls the operation timing of the circuit module 200 according to a clock CK. This timing control may include: providing a signal SAT to circuit blocks BK[1] to BK[M] to control the timing of data transmission of each circuit block BK[1] to BK[M].
[0023] As shown in Figure 2, the intermediate circuit 210 may include two switches s1 and s2, two drivers d1 and d2, a latch h1, and two buffers b1 and b2. Switch s1 is coupled between node QBI_U and node QBI of line L1 and can be turned on and off; when on, switch s1 can conduct between line L1 and node QBI, and when off, switch s1 can stop conducting between line L1 and node QBI. Switch s2 is coupled between node QBI_D and node QBI of line L2 and can be turned on and off; when on, switch s2 can conduct between line L2 and node QBI, and when off, switch s2 can stop conducting between line L2 and node QBI.
[0024] Driver d1 includes an input terminal i1 and an output terminal o1, which are respectively coupled to node QBII and node QBI_U of line L1. Driver d1 can be enabled and disabled; when enabled, driver d1 can drive the voltage of line L1 according to the voltage of node QBII; when disabled, driver d1 can stop driving the voltage of line L1. Driver d2 includes an input terminal i2 and an output terminal o2, which are respectively coupled to node QBII and node QBI_D of line L2. Driver d2 can be enabled and disabled; when enabled, driver d2 can drive the voltage of line L2 according to the voltage of node QBII; when disabled, driver d2 can stop driving the voltage of line L2.
[0025] Buffer b1 includes an input terminal i3 and an output terminal o3, respectively coupled to nodes QBI and QBII. It can drive the voltage of node QBII according to the voltage of node QBI, so that the voltage of node QBII is controlled by the voltage of node QBI. Buffer b2 includes an input terminal i4 and an output terminal o4, respectively coupled to nodes QBII and QBI_M. It can drive the voltage of node QBI_M according to the voltage of node QBII. Latch h1 is coupled to node QBI.
[0026] Continuing from Figure 2, Figures 3a to 3e illustrate the operation embodiments of the circuit module 200. As shown in Figure 3a, when the control and input circuit gctrl_io requests one of the circuit blocks BK[m] to BK[M0+1] to transmit a first data (not shown) to the control and input circuit gctrl_io, switch s1 will be turned on, switch s2 will be turned off, driver d1 will be disabled, and driver d2 will be enabled. After switch s1 is turned on, circuit block BK[m] can drive the voltage of connection L1 (and node QBI_U) according to the content of the first data. The turned-on switch s1 will conduct the voltage of node QBI_U to node QBI, latch h1 will latch the voltage of node QBI, buffer b1 will drive the voltage of node QBII according to the voltage of node QBI, and buffer b2 will drive the voltage of node QBI_M according to the voltage of node QBII, so that the control and input / output circuit gctrl_io can determine and receive the first data transmitted by circuit block BK[m] according to the voltage of node QBI_M. At the same time, the enabled driver d2 will also drive the voltage of connection L2 according to the voltage of node QBII, so that the voltage of connection L2 is controlled by the voltage of connection L1 (for example, make the voltage of connection L2 consistent with the voltage of connection L1).
[0027] As shown in Figure 3b, when circuit block BK[m] stops driving connection L1 and other circuit blocks also do not drive connections L1 and L2, switch s1 can be open, switch s2 can be closed, driver d1 is disabled, and driver d2 is enabled. Through node QBI and the open switch s1, the voltage of node QBI_U and connection L1 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffer b1 and the enabled driver d2, the voltage of node QBI_D and connection L2 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffers b1 and b2, the voltage of node QBI_M is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same).
[0028] As shown in Figure 3c, when all circuit blocks BK[1] to BK[M] are not driving connections L1 and L2, switches s2 and s2 can also be closed, and drivers d1 and d2 can be enabled. Through buffer b1 and the enabled driver d1, the voltage of node QBI_U and connection L1 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffer b1 and the enabled driver d2, the voltage of node QBI_D and connection L2 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffers b1 and b2, the voltage of node QBI_M is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same).
[0029] As shown in Figure 3d, when the control and input circuit gctrl_io requests one of the circuit blocks BK[m'] from BK[1] to BK[M0] to transmit a second data (not shown) to the control and input circuit gctrl_io, switch s2 will be turned on, switch s1 will be turned off, driver d1 will be enabled, and driver d2 will be disabled; after switch s2 is turned on, circuit block BK[m'] can drive the voltage of connection L2 (and node QBI_D) according to the content of the second data; the turned-on switch s2 will conduct the voltage of node QBI_D to node QBI, latch h1 will latch the voltage of node QBI, buffer b1 drives the voltage of node QBII according to the voltage of node QBI, buffer b2 drives the voltage of node QBI_M according to the voltage of node QBII, so that the control and input circuit gctrl_io can judge and receive the second data transmitted by circuit block BK[m'] according to the voltage of node QBI_M. At the same time, the enabled driver d1 will also drive the voltage of connection L1 according to the voltage of node QBII, so that the voltage of connection L1 is controlled by the voltage of connection L2 (for example, make the voltage of connection L1 consistent with the voltage of connection L2).
[0030] As shown in Figure 3e, when circuit block BK[m'] stops driving connection L2 and other circuit blocks also do not drive connections L1 and L2, switch s1 can be closed, switch s2 can be open, driver d1 is enabled, and driver d2 is disabled. Through node QBI and the open switch s2, the voltage of node QBI_D and connection L2 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffer b1 and the enabled driver d1, the voltage of node QBI_U and connection L1 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffers b1 and b2, the voltage of node QBI_M is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same).
[0031] Continuing from Figure 2, Figure 4 illustrates a circuit embodiment of the intermediate circuit 210. Driver d1 may include transistors P1, P2, N1, and N2; driver d2 may include transistors P3, P4, N3, and N4; switch s1 may include transistors P5 and N5; and switch s2 may include transistors P6 and N6. Transistors P1 to P6 may be p-type metal-oxide-semiconductor (MOS) transistors, and transistors N1 to N6 may be n-type MOS transistors. Buffer b1 may include one (or an odd number) inverters iv1; buffer b2 may include one (or an odd number) inverters iv2; and latch h1 may include two inverters iv3 and iv4.
[0032] In driver d1, transistor N1 may include a controlled terminal (e.g., a gate terminal) and two channel terminals (e.g., a source terminal and a drain terminal), respectively coupled to input terminal i1, a voltage VG (e.g., a ground voltage), and node n1. Transistor N2 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to an inverting selection signal LC34b at node n5b, and the two channel terminals are respectively coupled to node n1 and output terminal o1. Transistor P1 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to a selection signal LC34 at node n5, and the two channel terminals are respectively coupled to node n2 and output terminal o1. Transistor P2 may include a controlled terminal and two channel terminals, respectively coupled to input terminal i1, a voltage VCCAPI (e.g., a supply voltage), and node n2. The selection signal LC34 and the inverting selection signal LC34b are inverted.
[0033] In driver d2, transistor N3 may include a controlled terminal and two channel terminals, respectively coupled to input terminal i2, voltage VG, and node n3. Transistor N4 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to an inverting selection signal LC12b at node n6b, and the two channel terminals are respectively coupled to node n3 and output terminal o2. Transistor P3 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to a selection signal LC12 at node n6, and the two channel terminals are respectively coupled to node n4 and output terminal o2. Transistor P4 may include a controlled terminal and two channel terminals, respectively coupled to input terminal i2, voltage VCCAPI, and node n4. The selection signal LC12 and the inverting selection signal LC12b are inverted.
[0034] In switch s1, transistor N5 may include a controlled terminal and two channel terminals, respectively coupled to selection signal LC34, node QBI, and node QBI_U of connection L1. Transistor P5 may include a controlled terminal and two channel terminals, respectively coupled to inverting selection signal LC34b, node QBI, and node QBI_U of connection L1. In switch s2, transistor N6 may include a controlled terminal and two channel terminals, respectively coupled to selection signal LC12, node QBI, and node QBI_D of connection L2. Transistor P6 may include a controlled terminal and two channel terminals, respectively coupled to inverting selection signal LC12b, node QBI, and node QBI_D of connection L2. When the control and input circuit gctrl_io (Figure 2) requests one of the circuit blocks BK[1] to BK[M] to transmit data, the selection signal LC34 can reflect whether the circuit block belongs to the first group (i.e., circuit blocks BK[M0+1] to BK[M]) and the selection signal LC12 can reflect whether the circuit block belongs to the second group (i.e., circuit blocks BK[1] to BK[M0]).
[0035] In buffer b1, inverter iv1 may include an input terminal and an output terminal, respectively coupled to input terminal i3 and output terminal o3. In buffer b2, inverter iv2 may include an input terminal and an output terminal, respectively coupled to input terminal i4 and output terminal o4. In latch h1, inverter iv3 may include an input terminal and an output terminal, respectively coupled to node QBI and node n0; inverter iv4 may include an input terminal and an output terminal, respectively coupled to node n0 and QBI.
[0036] Continuing from Figures 2, 3a to 3e and 4, Figure 5 illustrates the waveform timing of relevant signals in circuit module 200. In Figure 5, period T1 represents one cycle of clock CK (Figure 2), and waveforms vQBI_U, vQBI_D and vQBI are the voltage waveforms of nodes QBI_U, QBI_D and QBI, respectively. In one cycle T1 from time t1 to t2, if the control and input / output circuit gctrl_io requires one of the circuit blocks BK[M0+1] to BK[M], BK[m] (Figure 2), to transmit data, the voltage of signal LC34 (Figure 5) will switch from voltage v_off to voltage v_on at time tu1, indicating that circuit block BK[m] belongs to the first group; the voltage of signal LC12 will be v_off, indicating that circuit block BK[m] does not belong to the second group.
[0037] When the selection signal LC34 is voltage v_off, transistors N5 (Figure 4) and P5 are off (not conducting), while transistors P1 and N2 are on (conducting). Therefore, switch S1 is off and driver D1 is enabled. Similarly, when the selection signal LC12 is voltage v_off, transistors N6 and P6 are off, while transistors P3 and N4 are on. Therefore, switch S2 is off and driver D2 is enabled. On the other hand, when the selection signal LC34 switches to voltage v_on at time tu1, transistors N5 and P5 are on, while transistors P1 and N2 are off. Therefore, switch S1 is on and driver D1 is disabled.
[0038] As shown in Figure 5, after the selection signal LC34 switches to voltage v_on at time tu1, the signal SAT will switch from voltage v_off to v_on at time ta1, causing circuit block BK[m] to start driving the voltage of connection L1 according to the data it wants to transmit. For example, if the data that circuit block BK[m] wants to transmit is the number 0, circuit block BK[m] can start driving the voltage of connection L1 (and node QBI_U) towards the voltage v0 representing the number 0 at time ta1, and make the voltage of node QBI_U reach voltage v0 at time ta2, as shown in the waveform vQBI_U.
[0039] After time point tu1, switch s1 is turned on, switch s2 is turned off, driver d1 is disabled, and driver d2 is enabled, as shown in Figure 3a. Therefore, the voltage of node QBI_U will be conducted to node QBI through the turned-on switch s1, so that the voltage of node QBI reflects the voltage of node QBI_U, as shown in waveform vQBI (Figure 5). Furthermore, buffer b1 and the enabled driver d2 will cause the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI, as shown in waveform vQBI_D; and buffers b1 and b2 will also cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, when connection L1 and node QBI_U are driven to voltage v0 at time point ta2, the voltages of nodes QBI, QBI_D, QBI_M and connection L2 will also become voltage v0. Thus, the 0 data transmitted by circuit block BK[m] on connection L1 will be transmitted to the control and input / output circuit gctrl_io via node QBI_M, and to connection L2 via node QBI_D. At time ta2, as nodes QBI_U and QBI are driven to voltage v0, the voltage v0 of node QBI will also be latched to latch h1.
[0040] At time ta3, after time ta2, the signal SAT switches from voltage v_on back to voltage v_off, so circuit block BK[m] stops driving connection L1. However, as shown in Figure 3b, since latch h1 has latched voltage v0, the voltage of node QBI will remain at voltage v0; the open switch s1 will cause the voltage of node QBI_U and connection L1 to reflect the voltage of node QBI, buffer b1 and the enabled driver d2 will cause the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI, and buffers b1 and b2 will cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, even if circuit block BK[m] no longer drives connection L1 after time ta3, the voltage of connection L1, L2 and node QBI_M will still remain at voltage v0 and will not fluctuate.
[0041] At time tu2, after time ta3, the selection signal LC34 switches from voltage v_on back to voltage v_off. After time tu2, since both selection signals LC12 and LC34 are at voltage v_off, switches s1 and s2 are both closed, and both drivers d1 and d2 are enabled, as shown in Figure 3c. Buffer b1 and the enabled driver d1 cause the voltage of node QBI_U and connection L1 to reflect the voltage latched by latch h1 on node QBI. Buffer b1 and the enabled driver d2 cause the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI. Buffers b1 and b2 cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, after time tu2, the voltage of connection L1, L2 and node QBI_M remains at voltage v0 and does not fluctuate.
[0042] In another cycle T1 from time t2 to t3, if the control and input / output circuit gctrl_io requires one of the circuit blocks BK[1] to BK[M0], BK[m'] (Fig. 2), to transmit data, the voltage of the selection signal LC12 (Fig. 5) will switch from voltage v_off to voltage v_on at time td1, indicating that the circuit block BK[m'] belongs to the second group; the selection signal LC34 will be voltage v_off, indicating that the circuit block BK[m'] does not belong to the first group. When the selection signal LC12 switches to voltage v_on at time td1, transistors N6 and P6 (Fig. 4) are turned on, while transistors P3 and N4 are turned off, so switch s2 is turned on and driver d2 is disabled.
[0043] After time point td1, the signal SAT will switch from voltage v_off to v_on at time point tb1, causing circuit block BK[m'] to start driving the voltage of connection L2 according to the data it wants to transmit. For example, if the data that circuit block BK[m'] wants to transmit is a digit 1, circuit block BK[m'] can start driving the voltage of connection L2 (and node QBI_D) towards the voltage v1 representing the digit 1 after time point tb1, and make the voltage of node QBI_D reach voltage v1 at time point tb2, as shown in the waveform vQBI_D.
[0044] After time point td1, switch s1 is closed, switch s2 is opened, driver d1 is enabled, and driver d2 is disabled, as shown in Figure 3d. Therefore, the voltage of node QBI_D will be conducted to node QBI through the open switch s2, causing the voltage of node QBI to reflect the voltage of node QBI_D, as shown in waveform vQBI (Figure 5). Furthermore, buffer b1 and the enabled driver d1 will cause the voltage of node QBI_U and connection L1 to reflect the voltage of node QBI, as shown in waveform vQBI_U; and buffers b1 and b2 will also cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, when connection L2 and node QBI_D are driven to voltage v1 at time point tb2, the voltages of nodes QBI, QBI_U, QBI_M, and connection L1 will also become voltage v1. Thus, the digital 1 data transmitted by circuit block BK[m'] on connection L2 will be transmitted to the control and input / output circuit gctrl_io via node QBI_M, and to connection L1 via node QBI_U. At time tb2, as nodes QBI_D and QBI are driven to voltage v1, the voltage v1 of node QBI will also be latched to latch h1.
[0045] At time tb3, after time tb2, the signal SAT switches from voltage v_on back to voltage v_off, so circuit block BK[m'] stops driving connection L2. However, as shown in Figure 3e, since latch h1 has latched voltage v1, the voltage of node QBI will remain at voltage v1; the open switch s2 will cause the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI, buffer b1 and the enabled driver d1 will cause the voltage of node QBI_U and connection L1 to reflect the voltage of node QBI, and buffers b1 and b2 will cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, even if circuit block BK[m'] no longer drives connection L2 after time tb3, the voltage of connection L1, L2 and node QBI_M will still remain at voltage v1 and will not fluctuate.
[0046] At time td2, after time tb3, the selection signal LC12 switches from voltage v_on back to voltage v_off. After time td2, since both selection signals LC12 and LC34 are at voltage v_off, switches s1 and s2 are both closed, and both drivers d1 and d2 are enabled, as shown in Figure 3c. Buffer b1 and the enabled driver d1 cause the voltage of node QBI_U and connection L1 to reflect the voltage latched by latch h1 on node QBI. Buffer b1 and the enabled driver d2 cause the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI. Buffers b1 and b2 cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, after time td2, the voltage of connection L1, L2 and node QBI_M remains at voltage v1 and does not fluctuate.
[0047] In summary, the advantages of the present invention compared to the prior art can be described as follows. In the circuit module 200 of the present invention, although all circuit blocks BK[1] to BK[M] are coupled to the control and input circuit gctrl_io, the circuit blocks BK[1] to BK[M] are not coupled to the control and input circuit gctrl_io with a long connecting line that spans all circuit blocks BK[1] to BK[M]. Instead, the circuit blocks BK[1] to BK[M] are divided into a first group (circuit blocks BK[M0+1] to BK[M]) and a second group (circuit blocks BK[1] to BK[M0]), which are respectively coupled to the intermediate circuit 210 via short connecting lines L1 and L2, and then coupled to the control and input circuit gctrl_io from the intermediate circuit 210. Under this architecture, the connections L1 and L2 do not need to span all circuit blocks BK[1] to BK[M], but only some of the circuit blocks. Therefore, the lengths of the connections L1 and L2 are shorter, and their equivalent loads are also lower. The time required for one of the circuit blocks BK[1] to BK[M] to drive the corresponding connection L1 or L2 can also be shortened, thereby improving the data access speed. Furthermore, due to the reduced connection load, the layout area of the drive circuits in the circuit blocks BK[1] to BK[M] used to drive the corresponding connection L1 or L2 can also be reduced.
[0048] When one of the circuit blocks BK[1] to BK[M] (as shown in Figure 3a or 3d, circuit block BK[m] or BK[m']) needs to transmit data to the control and input / output circuit gctrl_io, the circuit block only needs to drive the corresponding short connection (L1 or L2) to the voltage corresponding to the data to enable the control and input / output circuit gctrl_io to receive the data via node QBI_M; even if the other short connection (L2 or L1) is driven to the voltage corresponding to the data later by the intermediate circuit 210, it will not affect the data reception of the control and input / output circuit gctrl_io. That is, the data module 200 of the present invention has a better margin in the timing of data access, which also helps to improve the data access speed.
[0049] Furthermore, when the signal SAT (Fig. 5) is voltage v_on, causing one of the circuit blocks BK[1] to BK[M] to drive line L1 or L2 to the voltage (v0 or v1) corresponding to the data, even if the signal SAT switches back to voltage v_off, causing lines L1 and L2 to no longer be driven by circuit blocks BK[1] to BK[M], the intermediate circuit 210 will still ensure that lines L1, L2 and node QBI_M maintain the voltage (v0 or v1) corresponding to the data without fluctuation, as shown in Figs. 3b, 3c and 3e. In this way, node QBI_M can have sufficient data maintenance time.
[0050] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]
[0020] (Prior Art) Figures 1a and 1b respectively illustrate the waveform timing of a known memory module and related signals. Figure 2 illustrates a circuit module according to an embodiment of the present invention, which may include an intermediate circuit. Figures 3a to 3e illustrate operational embodiments of the circuit module in Figure 2. Figure 4 illustrates a circuit embodiment of the intermediate circuit in Figure 2. Figure 5 illustrates the waveform timing of the related signals in Figures 2 and 4.
Claims
1. A circuit module with an improved interconnect load, comprising: a first interconnect; a first switch coupled between the first interconnect and a first node, operable to turn on and off to conduct and de-conduct between the first interconnect and the first node; a second interconnect; a second switch coupled between the second interconnect and the first node, operable to turn on and off to conduct and de-conduct between the second interconnect and the first node; and a second driver comprising a second driver input and a second driver output, respectively coupled to a second node and the second interconnect; the second driver is operable to enable and disable to drive and de-drive the second interconnect according to the voltage of the second node; wherein: The voltage of the second node is controlled by the voltage of the first node; when the first switch is turned on, the second switch is turned off; and when the second switch is turned off, the second driver is enabled.
2. The circuit module as described in claim 1, wherein: When the second switch is turned on, the first switch is turned off.
3. The circuit module as described in claim 1, wherein: When the second switch is turned on, the second driver is disabled.
4. The circuit module as described in claim 1 further includes: a buffer, comprising a buffer input and a buffer output, respectively coupled to the first node and the second node.
5. The circuit module as claimed in claim 4, wherein the buffer further includes a first inverter coupled between the input and output of the buffer.
6. The circuit module as described in claim 1 further comprises: one or more first circuit blocks coupled to the first connection; wherein, When one of the one or more first circuit blocks needs to transmit data, the first connection is driven according to the data after the first switch is turned on, and the driving of the first connection is stopped before the first switch is switched off.
7. The circuit module as described in claim 6, wherein, Each of these first circuit blocks is a memory bank.
8. The circuit module as claimed in claim 6 further includes: a latch coupled to the first node; the latch maintains the voltage of the first node so that the voltage of the first node does not fluctuate when one of the one or more first circuits stops driving the first connection.
9. The circuit module as described in claim 8, wherein, The latch includes: a third inverter with a third inverter input and a third inverter output, respectively coupled to the first node and an internal node; and a fourth inverter with a fourth inverter input and a fourth inverter output, respectively coupled to the internal node and the first node.
10. The circuit module as described in claim 1, wherein, During a certain period of time, both the first switch and the second switch are closed.
11. The circuit module as described in claim 1 further comprises: one or more second circuit blocks coupled to the second connection; wherein, When one of the one or more second circuit blocks needs to transmit data, the second connection is driven according to the data after the second switch is turned on, and the driving of the second connection is stopped before the second switch is switched off.
12. The circuit module as described in claim 11, wherein, Each of these second circuit blocks is a memory bank.
13. The circuit module as claimed in claim 1 further comprises: a first driver, including a first driver input and a first driver output, respectively coupled to the second node and the first connection; the first driver is enable and disable to drive the first connection and stop driving the first connection according to the voltage of the second node; wherein: When the second switch is turned on, the first switch is turned off; and when the first switch is turned off, the first driver is enabled.
14. The circuit module as described in claim 13, wherein, When the first switch is turned on, the first driver is disabled.
15. The circuit module as claimed in claim 13, wherein the first driver further comprises: a first transistor including a first controlled terminal and a first channel terminal; a second transistor including a second controlled terminal and two second channel terminals, the two second channel terminals being respectively coupled to the first channel terminal and the output terminal of the first driver; an eighth transistor including an eighth controlled terminal and an eighth channel terminal; and a seventh transistor including a seventh controlled terminal and two seventh channel terminals, the two seventh channel terminals being respectively coupled to the eighth channel terminal and the output terminal of the first driver; wherein: One of the first controlled terminal and the second controlled terminal is coupled to the first driver input terminal, and the other of the first controlled terminal and the second controlled terminal is coupled to a first inverting selection signal; one of the seventh controlled terminal and the eighth controlled terminal is coupled to the first driver input terminal, and the other of the seventh controlled terminal and the eighth controlled terminal is coupled to a first selection signal; and the first selection signal and the first inverting selection signal are inverted.
16. The circuit module as claimed in claim 15, wherein the first switch comprises: a fifth transistor including a fifth controlled terminal and two fifth channel terminals, respectively coupled to the first selection signal, the first node and the first connection.
17. The circuit module as claimed in claim 15, wherein the first switch comprises: an eleventh transistor including an eleventh controlled terminal and two eleventh channel terminals, respectively coupled to the first inverting selection signal, the first node and the first connection.
18. The circuit module as claimed in claim 1, wherein the second driver further comprises: a third transistor including a third controlled terminal and a third channel terminal; a fourth transistor including a fourth controlled terminal and two fourth channel terminals, the two fourth channel terminals being respectively coupled to the third channel terminal and the output terminal of the second driver; a tenth transistor including a tenth controlled terminal and a tenth channel terminal; and a ninth transistor including a ninth controlled terminal and two ninth channel terminals, the two ninth channel terminals being respectively coupled to the tenth channel terminal and the output terminal of the second driver; wherein: One of the third controlled terminal and the fourth controlled terminal is coupled to the second driver input terminal, and the other of the third controlled terminal and the fourth controlled terminal is coupled to a second inverting selection signal; one of the ninth controlled terminal and the tenth controlled terminal is coupled to the second driver input terminal, and the other of the ninth controlled terminal and the tenth controlled terminal is coupled to a second selection signal; and the second selection signal and the second inverting selection signal are inverted.
19. The circuit module as claimed in claim 18, wherein the second switch comprises: a sixth transistor including a sixth controlled terminal and two sixth channel terminals, respectively coupled to the second selection signal, the first node and the second connection.
20. The circuit module as claimed in claim 18, wherein the second switch comprises: a twelfth transistor including a twelfth controlled terminal and two twelfth channel terminals, respectively coupled to the second inverting selection signal, the first node and the second connection.