Configurable voltage regulator circuit and transmitter circuit

Abstract

A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

Description

[Technical Field]

[0001] This disclosure relates to data transmission, and more particularly to a configurable voltage regulation circuit located in a transmission circuit. [Previous Technology]

[0002] In mobile and mobile-influenced applications, low-power, high-speed interfaces are used to process and transmit large amounts of data. For example, MIPI D-PHY, a physical layer (PHY) defined by the Mobile Industry Processor Interface (MIPI) standard, is widely used in smartphone cameras and displays. MIPI D-PHY uses differential signaling to transmit data over a bandwidth-limited channel containing one clock lane and multiple scalable data lanes. To provide higher throughput over this bandwidth-limited channel, MIPI C-PHY, another physical layer defined by the Mobile Industry Processor Interface standard, was developed. MIPI C-PHY employs three-phase symbol encoding and an embedded clock link to transmit data symbols over multiple three-wire lanes, each of which (or "trio") contains an embedded clock. MIPI C-PHY allows for a high data rate at a relatively low toggling frequency, thus providing high-speed and low-power data transmission. [Summary of the Invention]

[0003] Embodiments of this disclosure provide a voltage regulation circuit that is configurable to support different interface specifications. Furthermore, embodiments of this disclosure also provide a data serialization circuit and a driving circuit, both of which can support different interface specifications. Embodiments of this disclosure also provide a related transmission circuit including at least one of the above-described voltage regulation circuit, the above-described data serialization circuit, and the above-described driving circuit.

[0004] Certain embodiments of this disclosure include a voltage regulation circuit comprising a first amplifier, a second amplifier, and a first transistor. Both the first amplifier and the second amplifier include a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first amplifier is coupled to a first reference voltage. The first input terminal of the second amplifier is coupled to a second reference voltage. A first connection terminal of the first transistor is coupled to a supply voltage. A control terminal of the first transistor is selectively coupled to one of the output terminals of the first amplifier and the second amplifier. When the control terminal of the first transistor is coupled to the output terminal of the first amplifier, a second connection terminal of the first transistor is coupled to the second input terminal of the first amplifier to output a first regulated voltage in response to the first reference voltage and the supply voltage. When the control terminal of the first transistor is coupled to the output terminal of the second amplifier, the second connection terminal of the first transistor is coupled to the second input terminal of the second amplifier, so as to output the first regulated voltage in response to the second reference voltage and the supply voltage.

[0005] Certain embodiments of this disclosure include a voltage regulation circuit for receiving a supply voltage to generate a first regulated voltage. The voltage regulation circuit includes a first amplifier, a second amplifier, a first transistor, a first switching circuit, and a second switching circuit. Both the first amplifier and the second amplifier include a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first amplifier is coupled to a first reference voltage. The first input terminal of the second amplifier is coupled to a second reference voltage. A first connection terminal of the first transistor is coupled to the supply voltage. A second connection terminal of the first transistor is used to output the first regulated voltage. The first switching circuit is used to selectively couple one of the output terminals of the first amplifier and the second amplifier to a control terminal of the first transistor. The second switching circuit is used to selectively couple one of the second input terminals of the first amplifier and the second amplifier to the second connection terminal of the first transistor.

[0006] Certain embodiments of this disclosure include a transmission circuit comprising a data serialization circuit, a decoder, a voltage regulation circuit, and a drive circuit. The data serialization circuit is used to convert an M-bit data signal into a serial data stream according to a first clock signal. M is a positive integer greater than 1. The decoder is coupled to the data serialization circuit to decode the serial data stream to generate decoded data. The voltage regulation circuit is powered by a first supply voltage and a second supply voltage, and is used to convert the second supply voltage into a third supply voltage. The voltage regulation circuit includes a first amplifier, a second amplifier, and a first transistor. Both the first amplifier and the second amplifier are powered by the first supply voltage and each includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first amplifier is coupled to a first reference voltage. The first input terminal of the second amplifier is coupled to a second reference voltage. A first connection terminal of the first transistor is coupled to the second supply voltage. A second connection terminal of the first transistor is used to output the third supply voltage. One control terminal of the first transistor is selectively coupled to one of the output terminals of the first amplifier and the second amplifier. The drive circuit is coupled to the decoder and, via a node coupled to the second connection terminal of the first transistor, is selectively coupled to one of the second input terminals of the first amplifier and the second input terminal of the second amplifier. The drive circuit is used to generate output data based on the decoded data and the third supply voltage received from the node.

[0007] Using the configurable voltage regulation or data transmission schemes provided in this disclosure, one or more amplifiers can be operated with one or more transistors to realize a configurable voltage regulator capable of supporting different channel configurations. Furthermore, using the multi-mode data serialization or data transmission schemes provided in this disclosure, data signals conforming to different interface standards can be successfully received or processed. Moreover, the drive schemes provided in this disclosure can be configured as different types of drivers, such as differential drivers, three-bit quasi-drivers, four-bit quasi-drivers, de-emphasis / pre-emphasis drivers, and / or high-output swing drivers. The data transmission schemes provided in this disclosure offer flexible and simplified designs conforming to different interface specifications, thus achieving good operational flexibility, reducing production costs, and reducing power consumption.

Implementation Method

[0009] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of parameter values, components, and configurations described below are used to simplify this disclosure. It is understood that these descriptions are merely illustrative and are not intended to limit the scope of this disclosure. For example, component symbols and / or reference numerals may be reused in embodiments. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0010] Furthermore, it is understood that if a component is described as being "connected to" or "coupled to" another component, then the two components may be directly connected or coupled, or there may be other intervening components between them.

[0011] To support diverse applications, the transmitter can have its own independent circuitry dedicated to different interface standards. For example, MIPI D-PHY can be used for high-definition (HD) smartphone displays, while MIPI C-PHY can be used for ultra-high-definition (UHD) smartphone displays to achieve a higher data rate per lane. To simultaneously support MIPI D-PHY and MIPI C-PHY, the corresponding interface circuitry can be implemented in the same transmitter; however, this increases chip area and cost.

[0012] This disclosure provides exemplary transmission circuits, each of which includes a circuit block supporting different interface specifications. This circuit block includes at least one of a data serialization circuit, a voltage regulator circuit, and a drive circuit. The different interface specifications include (but are not limited to) MIPI D-PHY, MIPI C-PHY, sub-LVDS, LVDS, HDMI, and MIPI M-PHY. This disclosure also provides exemplary drive circuits, each of which may be disposed in the transmission circuit and includes a variable impedance circuit to implement de-emphasis and / or pre-emphasis. Further details are provided below.

[0013] FIG1 is a functional block diagram of an exemplary transmission circuit according to certain embodiments of the present disclosure. The transmission circuit 100 can transmit an M-bit data signal DA1 in different operating modes, thereby supporting different interface specifications. M is a positive integer greater than 1. The transmission circuit 100 includes (but is not limited to) a data serialization circuit 110, a decoder 120, a voltage regulation circuit 130, and a driver circuit 140. At least one of the data serialization circuit 110, decoder 120, voltage regulation circuit 130, and driver circuit 140 is configurable to meet different interface specifications.

[0014] The data serialization circuit 110 is used to convert an M-bit data signal DA1 into a serial data stream DA2 according to a clock signal CK1. In this embodiment, the data serialization circuit 110 can serialize N bits of the M-bit data signal DA1 at a time. N is a positive integer less than or equal to M and can change depending on the operating mode of the transmission circuit 100. Alternatively, it can transmit one bit of the serial data stream DA2 at a time. For example, the clock signal CK1 can be a bit rate clock. The data serialization circuit 110 can output the serial data stream DA2 according to the bit rate clock, thereby realizing an N-to-1 data serialization operation.

[0015] Decoder 120 is coupled to data serialization circuit 110 to decode serial data stream DA2 to generate decoded data DA3. In some embodiments, the bit pattern and / or bit width of decoded data DA3 may change depending on the operating mode of transmission circuit 100.

[0016] The voltage regulation circuit 130 is powered by at least two supply voltages V1 and V2, and is used to convert the supply voltage V2 into a supply voltage V3. The supply voltage V3 may be supplied to the drive circuit 140 and one or more other drive circuits (not shown in FIG1) according to the operating mode of the transmission circuit 100. In some embodiments, the supply voltage V2 may be at a different voltage level than the supply voltage V1.

[0017] The drive circuit 140 is coupled to the decoder 120 and the voltage regulation circuit 130 to generate output data DA4 based on the decoded data DA3 and the supply voltage V3. The drive circuit 140 can be configured as a different type of driver, such as a differential driver and a three-level driver, depending on the operating mode of the transmission circuit 100.

[0018] Taking the transmission circuit 100 as an example of a C / D PHY combo transmitter circuit that simultaneously supports MIPI D-PHY and MIPI C-PHY specifications, the transmission circuit 100 can receive (but is not limited to) an 8-bit data signal (M=8) as an M-bit data signal DA1. In the operating mode of the transmission circuit 100 to support the MIPI D-PHY specification, the data serialization circuit 110 can serialize 8 bits of the M-bit data signal DA1 at a time. The decoder 120 can decode the serial data stream DA2 to generate 4 bits of data, which serves as the decoded data DA3. The voltage regulation circuit 130 can provide the supply voltage V3 to two different drivers located on the same signal lane. The drive circuit 140 can be configured to be one of the two different drivers and generate output data DA4 based on the decoded data DA3. In the operating mode of the transmission circuit 100 supporting the MIPI C-PHY specification, the data serialization circuit 110 can serialize 7 bits of the M-bit data signal DA1 at a time. The decoder 120 can decode the serial data stream DA2 to generate 4-bit data, which serves as the decoded data DA3. The voltage regulation circuit 130 can distribute the supply voltage V3 to three three-bit quasi-drivers located on the same signal channel. The drive circuit 140 can be configured to act as one of the three three-bit quasi-drivers and generate output data DA4 based on the decoded data DA3.

[0019] To facilitate understanding of this disclosure, some embodiments of circuit blocks in the transmission circuit 100 that support different interface specifications are provided below. However, this is not intended to limit the scope of this disclosure. Those skilled in the art will understand that the circuit blocks described below can be applied to other circuit architectures to implement multi-mode signal transmission schemes without departing from the scope of this disclosure.

[0020] Please first refer to FIG2, which is a schematic diagram of an embodiment of the data serialization circuit 110 shown in FIG1 according to certain embodiments of the present disclosure. The data serialization circuit 210 includes (but is not limited to) a frequency divider 212 and a serializer 214. The frequency divider 212 can be configured as a dual-mode or multi-mode frequency divider with an adjustable frequency division factor (the size of which is represented by N). In this embodiment, the frequency divider 212 is used to receive a clock signal CK1 and use the adjustable frequency division factor to divide the frequency of the clock signal CK1 to generate a clock signal CK2. The size of the adjustable frequency division factor can be determined according to the application context of the data serialization circuit 210. For example (but the present disclosure is not limited to this), in one application context of the data serialization circuit 210, the adjustable frequency division factor can be equal to M (that is, the bit width of the M-bit data signal DA1). In another application context of the data serialization circuit 210, the adjustable frequency division factor can be less than M.

[0021] Serializer 214 is coupled to frequency divider 212 to receive M-bit data signal DA1 according to clock signal CK2. Furthermore, serializer 214 can be clocked by clock signal CK1 to convert M-bit data signal DA1 into serial data stream DA2. In this embodiment, the adjustable frequency divider factor can be greater than 1 in various operating scenarios, ensuring that the frequency of clock signal CK2 is lower than the frequency of clock signal CK1 in all these operating scenarios. Serializer 214 can receive multiple bits at a time for each clock cycle of clock signal CK2 and can output one bit at a time for each clock cycle of clock signal CK1, thereby performing parallel-to-serial data conversion on M-bit data signal DA1.

[0022] Taking the transmission circuit (transmission circuit 100 shown in Figure 1) used by the data serialization circuit 210 as an example, which is implemented as a C / D PHY combined transmission circuit, in operation, the data serialization circuit 210 can receive (but is not limited to) an 8-bit data signal (M=8) as an M-bit data signal DA1. In D-PHY mode, the frequency divider 212 can divide the frequency of the clock signal CK1 using the adjustable frequency division factor equal to 8 (i.e., N=M) to generate the clock signal CK2. The plurality of clock signals CK1 and CK2 can be referred to as the bit rate clock and the byte rate clock, respectively. Since each clock cycle of the clock signal CK2 is 8 times the clock cycle of the bit rate clock, the serializer 214 can receive 8 bits of the M-bit data signal DA1 at a time according to each clock cycle of the clock signal CK2. Next, the serializer 214 can be driven by the clock signal CK1 to output one bit of the serial data stream DA2 once per clock cycle of the clock signal CK1. Therefore, the data serialization circuit 210 can implement 8-to-1 data serialization in D-PHY mode.

[0023] In C-PHY mode, frequency divider 212 can divide the frequency of clock signal CK1 using an adjustable division factor equal to 7 (i.e., N=7) to generate clock signal CK2. Serializer 214 can receive 7 bits of M-bit data signal DA1 once per clock cycle of clock signal CK2, and output one bit of serial data stream DA2 once per clock cycle of clock signal CK1. Data serialization circuit 210 can implement 7-to-1 data serialization operation in C-PHY mode.

[0024] It is worth noting that the data serialization circuit 210 can be applied to other multi-mode transmission circuits that support multiple interface specifications without departing from the scope of this disclosure. In some embodiments, the transmission circuit 100 shown in FIG1 can be implemented as a sub-LVDS / LVDS combined transmission circuit. For example, the data serialization circuit 210 can receive an 8-bit data signal (M=8) as an M-bit data signal DA1. In sub-LVDS mode, the frequency divider 212 can divide the frequency of the clock signal CK1 using the adjustable frequency divider factor equal to 8 (i.e., N=M) to generate a clock signal CK2. The serializer 214 can receive the M-bit data signal DA1 according to the clock signal CK2 (whose frequency is equal to 1 / 8 of the frequency of the clock signal CK1) and output the serial data stream DA2 according to the clock signal CK1. In LVDS mode, frequency divider 212 can divide the frequency of clock signal CK1 using an adjustable division factor of 7 (i.e., N=7) to generate clock signal CK2. Serializer 214 can receive M-bit data signal DA1 based on clock signal CK2 (whose frequency is equal to 1 / 7 of the frequency of clock signal CK1) and output serial data stream DA2 based on clock signal CK1.

[0025] In some other embodiments, the transmission circuit 100 shown in FIG1 may be implemented as an HDMI transmission circuit or an M-PHY transmission circuit. The data serialization circuit 210 may use the adjustable divide factor equal to 10 to divide the frequency of the clock signal CK1 (or bit rate clock) to generate a clock signal CK2, thereby performing a 10-to-1 data serialization operation. For example, the data serialization circuit 210 may receive a 10-bit data signal (M=10) as an M-bit data signal DA1. In one operating mode, the divider 212 may use the adjustable divide factor equal to 10 (i.e., N=M) to divide the frequency of the clock signal CK1 to generate a clock signal CK2. The serializer 214 may receive the M-bit data signal DA1 according to the clock signal CK2 (whose frequency is equal to 1 / 10 of the frequency of the clock signal CK1) and output the serial data stream DA2 according to the clock signal CK1. For example, the bit width of the M-bit data signal DA1 can be greater than 10 (i.e., M > 10). In one operating mode, the frequency divider 212 can divide the frequency of the clock signal CK1 using an adjustable division factor equal to 10 (i.e., N = 10 < M) to generate the clock signal CK2. The serializer 214 can receive 10 bits from the M-bit data signal DA1 at a time according to the clock signal CK2, and output the serial data stream DA2 according to the clock signal CK1.

[0026] The circuit structure shown in FIG2 can be applied to multi-channel data serialization operations. FIG3 is a schematic diagram of another embodiment of the data serialization circuit 110 shown in FIG1 according to certain embodiments of the present disclosure. For example (but the present disclosure is not limited thereto), except that the data serialization circuit 310 shown in FIG3 uses a synchronizer in each local channel to implement multi-channel data serialization operations, the circuit structure shown in FIG3 can be similar / identical to the circuit structure shown in FIG2. The data serialization circuit 310 includes (but is not limited to) a plurality of synchronizers 313.1 to 313.4, a plurality of serializers 314.1 to 314.4, and a frequency divider 212 shown in FIG2. Each of the plurality of serializers 314.1 to 314.4 can be implemented using the serializer 214 shown in FIG2. In this embodiment, the frequency divider 212 can be provided in the global channel CH0. One of the serializers 314.1 to 314.4 and its corresponding synchronizer can be set in the corresponding area channel (that is, one of the area channels CH1 to CH4).

[0027] Each of the plurality of synchronizers 313.1 to 313.4 is coupled to the frequency divider 212 and a corresponding serializer among the plurality of serializers 314.1 to 314.4. The plurality of synchronizers 313.1 to 313.4 can be used to synchronize clock signal CK2 according to clock signal CK1, and output a clock signal synchronized with clock signal CK1. As shown in FIG3, the plurality of synchronizers 313.1 to 313.4 can be used to output a plurality of clock signals CK31 to CK34 respectively, wherein the plurality of clock signals CK31 to CK34 are all synchronized with clock signal CK1, and are therefore synchronized with each other. In some embodiments, at least one of the plurality of synchronizers 313.1 to 313.4 can be implemented using a D-type flip-flop.

[0028] Each of the plurality of serializers 314.1 to 314.4 can be driven by a clock signal synchronized with the clock signal CK1 to receive an M-bit data signal (such as one of the plurality of M-bit data signals DA11 to DA14). Furthermore, each of the plurality of serializers 314.1 to 314.4 can be driven by the clock signal CK1 to convert the M-bit data signal into a serial data stream (such as one of the plurality of serial data streams DA21 to DA24).

[0029] During operation, the frequency divider 212 located in the global channel CH0 can divide the frequency of the clock signal CK1 (such as a bit rate clock) to generate a clock signal CK2 (such as a byte rate clock). Each of the plurality of synchronizers 313.1 to 313.4 can generate a synchronized version of the clock signal CK2 (i.e., one of the plurality of clock signals CK31 to CK34 that are synchronized with each other). The plurality of serializers 314.1 to 314.4 are driven by the plurality of clock signals CK31 to CK34 respectively to serialize the plurality of M-bit data signals DA11 to DA14. Therefore, the data conversion operations of the plurality of serializers 314.1 to 314.4 can be synchronized with each other.

[0030] The circuit structure shown in Figure 3 is for illustrative purposes only and is not intended to limit the scope of this disclosure. For example, different numbers of area channels can be provided according to design requirements. As long as a synchronizer is used, which can trigger data serialization operations by a synchronized version of the frequency division signal output by the multi-mode frequency divider, related modifications and variations in the design are within the scope of this disclosure.

[0031] The multi-mode data serialization scheme provided in this disclosure can successfully receive and process data signals conforming to different interface specifications. Compared with transmission circuits that use different data serialization circuits for different interface standards, the transmission circuit using the multi-mode data serialization scheme provided in this disclosure can achieve good operational flexibility and has a relatively small circuit area, thereby reducing production costs.

[0032] FIG4 is a schematic diagram of an embodiment of the voltage regulation circuit 130 shown in FIG1 according to certain embodiments of the present disclosure. The voltage regulation circuit 430 is used to output a regulated voltage (i.e., supply voltage V3) according to a plurality of supply voltages V1 and V2. The voltage regulation circuit 430 may include an amplifier 432, a transistor 434, and a plurality of switching circuits 436 and 438. The amplifier 432 includes a plurality of input terminals TI1 and TI2, an output terminal TO, and a power supply terminal TS. The input terminal TI1 is coupled to a reference voltage VR, and the power supply terminal TS is coupled to the supply voltage V1. In this embodiment, the amplifier 432 may be implemented as (but is not limited to) an error amplifier.

[0033] Transistor 434 includes a plurality of connection terminals TC1 and TC2 and a control terminal TCC. Connection terminal TC1 is coupled to the supply voltage V2. For example, transistor 434 may be an n-channel field-effect transistor. The plurality of connection terminals TC1 and TC2 may be the drain and source terminals of the n-channel field-effect transistor, respectively. The control terminal TCC may be the gate terminal of the n-channel field-effect transistor. As another example, transistor 434 may be a p-channel field-effect transistor. The plurality of connection terminals TC1 and TC2 may be the source and drain terminals of the p-channel field-effect transistor, respectively. The control terminal TCC may be the gate terminal of the p-channel field-effect transistor. In this embodiment, amplifier 432 may be implemented as (but is not limited to) a power transistor with high rated voltage and current.

[0034] Switching circuit 436 is used to selectively couple the output terminal TO to the control terminal TCC. Switching circuit 438 is used to selectively couple the input terminal TI2 to the connection terminal TC2. In operation, when the output terminal TO is coupled to the control terminal TCC via switching circuit 436, and the input terminal TI2 is coupled to the connection terminal TC2 via switching circuit 438, the connection terminal TC2 is used to output the supply voltage V3. The voltage level of the supply voltage V3 may be less than or equal to the voltage level of the supply voltage V2. The power consumption of the voltage regulation circuit 430 can be expressed as V1×I1+V2×I2, where I1 and I2 represent the current supplied to the amplifier 432 and the transistor 434, respectively. In this embodiment, the voltage level of the supply voltage V2 supplied to the transistor 434 may be less than or equal to the voltage level of the supply voltage V1 supplied to the amplifier 432. Compared to the implementation where the supply voltage V2 is equal to the supply voltage V1, the above scheme can reduce power consumption, which can be expressed by the following formula.

[0035] V1×I1+V2×I2 < V1×I1+V1×I2=V1×(I1+I2).

[0036] Taking the transmission circuit (e.g., transmission circuit 100 shown in FIG. 1) used in the voltage regulation circuit 430 as an example, which operates in D-PHY mode, the supply voltage V1 can be equal to 2.5 volts, the current I1 can be equal to 0.1 milliamperes, and the current I2 can be equal to 2.1 milliamperes. In an embodiment where the voltage level of the supply voltage V2 is equal to the voltage level of the supply voltage V1, the power consumption can be expressed as 2.5 × (0.1 + 2.1) = 5.5 milliwatts. In an embodiment where the voltage level of the supply voltage V2 is set to 0.8 volts instead of 2.5 volts, the power consumption can be expressed as 2.5 × 0.1 + 0.8 × 2.1 = 1.93 milliwatts, which is 35% of 5.5 milliwatts.

[0037] It is worth noting that the circuit structure shown in FIG4 can be used to implement a configurable voltage regulation circuit. Please refer to FIG5, which is a schematic diagram of another embodiment of at least a portion of the voltage regulation circuit 130 shown in FIG1 according to certain embodiments of the present disclosure. The voltage regulation circuit 530 includes a plurality of amplifiers 532.1 and 532.2, and a plurality of transistors 534.1 to 534.4. The plurality of amplifiers 532.1 and 532.2 can all be implemented using the amplifier 432 shown in FIG4. The plurality of transistors 534.1 to 534.4 can all be implemented using the transistor 434 shown in FIG4. The voltage regulation circuit 530 can serve as a set of voltage regulators, such as a set of low-dropout regulators (LDO regulators). At least one of the plurality of amplifiers 532.1 and 532.2 can be operated in conjunction with one or more of the plurality of transistors 534.1 to 534.4 to realize one or more configurable voltage regulators, thereby providing one or more of the plurality of supply voltages V31 to V34 to one or more of the plurality of drive circuits 540.1 to 540.4. Each of the plurality of drive circuits 540.1 to 540.4 can be an embodiment of the drive circuit 140 shown in FIG. 1. Each of the plurality of drive circuits 540.1 to 540.4 can receive a corresponding supply voltage via a node coupled to a corresponding transistor (i.e., one of the plurality of nodes N1 to N4).

[0038] In this embodiment, the power supply terminal TS1 of amplifier 532.1 and the power supply terminal TS2 of amplifier 532.2 are both coupled to the supply voltage V1. The input terminal TI11 of amplifier 532.1 is coupled to a reference voltage VR1, and the input terminal TI21 of amplifier 532.2 is coupled to a reference voltage VR2. The reference voltages VR1 and VR2 may be at the same voltage level. In some embodiments, the reference voltage VR2 may be at a different voltage level than the reference voltage VR1 without departing from the scope of this disclosure.

[0039] For the plurality of transistors 534.1 to 534.4, the plurality of connection terminals TC11, TC21, TC31 and TC41 are all coupled to the supply voltage V2, wherein the voltage level of the supply voltage V2 may be lower than the voltage level of the supply voltage V1. At least one of the plurality of transistors 534.1 to 534.4 may be coupled to one of the plurality of amplifiers 532.1 and 532.2 in one mode of the voltage regulation circuit 530, and coupled to the other of the plurality of amplifiers 532.1 and 532.2 in another mode of the voltage regulation circuit 530. For example, the control terminal TCC3 of transistor 534.3 is selectively coupled to one of the output terminals TO1 of amplifier 532.1 and TO2 of amplifier 532.2, while the connection terminal TC32 of transistor 534.3 is selectively coupled to one of the input terminals TI12 of amplifier 532.1 and TI22 of amplifier 532.2. The drive circuit 540.3 can receive the supply voltage V33 from node N3 via node N3, which is coupled to the connection terminal TC32. In this embodiment, when the control terminal TCC3 of transistor 534.3 is coupled to the output terminal TO1 of amplifier 532.1, the connection terminal TC32 of transistor 534.3 is coupled to the input terminal TI12 of amplifier 532.1 to output a supply voltage V33 (i.e., the regulated voltage) in response to the reference voltage VR1 and the supply voltage V2. When the control terminal TCC3 of transistor 534.3 is coupled to the output terminal TO2 of amplifier 532.2, the connection terminal TC32 of transistor 534.3 is coupled to the input terminal TI22 of amplifier 532.2 to output a supply voltage V33 in response to the reference voltage VR2 and the supply voltage V2.

[0040] Furthermore, the control terminal TCC1 of transistor 534.1 can be selectively coupled to the output terminal TO1 of amplifier 532.1, and the connection terminal TC12 of transistor 534.1 can be selectively coupled to the input terminal TI12 of amplifier 532.1. The control terminal TCC2 of transistor 534.2 can be selectively coupled to the output terminal TO1 of amplifier 532.1, and the connection terminal TC22 of transistor 534.2 can be selectively coupled to the input terminal TI12 of amplifier 532.1. The control terminal TCC4 of transistor 534.4 can be selectively coupled to the output terminal TO2 of amplifier 532.2, and the connection terminal TC42 of transistor 534.4 can be selectively coupled to the input terminal TI22 of amplifier 532.2.

[0041] The voltage regulation circuit 530 may further include a plurality of switching circuits 536.1 to 536.4 and 538.1 to 538.4. Switching circuit 536.1 is used to selectively couple the output terminal TO1 of amplifier 532.1 to the control terminal TCC1 of transistor 534.1. Switching circuit 538.1 is used to selectively couple the input terminal TI12 of amplifier 532.1 to the connection terminal TC12 of transistor 534.1. For example (but not limited thereto), switching circuit 536.1 may be implemented using two switches SW11 and SW12. When one of switches SW11 and SW12 is turned on, the other of switches SW11 and SW12 may be turned off. Switching circuit 538.1 may be implemented using two switches SW13 and SW14. When one of switches SW13 and SW14 is turned on, the other of switches SW13 and SW14 can be turned off.

[0042] Similarly, a switching circuit 536.2 for selectively coupling the output terminal TO1 of amplifier 532.1 to the control terminal TCC2 of transistor 534.2 can be implemented using two switches SW21 and SW22. When one of switches SW21 and SW22 is on, the other of switches SW21 and SW22 can be off. A switching circuit 538.2 for selectively coupling the input terminal TI12 of amplifier 532.1 to the connection terminal TC22 of transistor 534.2 can be implemented using two switches SW23 and SW24. When one of switches SW23 and SW24 is on, the other of switches SW23 and SW24 can be off. A switching circuit 536.4 for selectively coupling the output terminal TO2 of amplifier 532.2 to the control terminal TCC4 of transistor 534.4 can be implemented using two switches SW41 and SW42. When one of switches SW41 and SW42 is on, the other of switches SW41 and SW42 can be off. A switching circuit 538.4, used to selectively couple the input terminal TI22 of amplifier 532.2 to the connection terminal TC42 of transistor 534.4, can be implemented using two switches SW43 and SW44. When one of switches SW43 and SW44 is on, the other of switches SW43 and SW44 can be off.

[0043] For transistor 534.3, switching circuit 536.3 is used to selectively couple one of the output terminals TO1 of amplifier 532.1 and TO2 of amplifier 532.2 to the control terminal TCC3 of transistor 534.3. Switching circuit 538.3 is used to selectively couple one of the input terminals TI12 of amplifier 532.1 and TI22 of amplifier 532.2 to the connection terminal TC32 of transistor 534.3. For example (but not limited thereto), switching circuit 536.3 can be implemented using two switches SW31 and SW32. Switch SW31 is selectively coupled between output terminal TO2 and control terminal TCC3. Switch SW32 is selectively coupled between output terminal TO1 and control terminal TCC3. When one of switches SW31 and SW32 is turned on, the other of switches SW31 and SW32 can be turned off. The switching circuit 538.3 can be implemented using two switches, SW33 and SW34. Switch SW33 is selectively coupled between input terminal TI22 and connection terminal TC32. Switch SW34 is selectively coupled between input terminal TI12 and connection terminal TC32. When one of switches SW33 and SW34 is turned on, the other of switches SW33 and SW34 can be turned off.

[0044] FIG6A is a schematic diagram of the operation of the voltage regulation circuit 530 shown in FIG5 according to certain embodiments of the present disclosure in a first mode. In this embodiment, the voltage regulation circuit 530 operating in the first mode can support MIPI D-PHY differential signal transmission. During operation, a plurality of switches SW11, SW13, SW21, SW23, SW31, SW33, SW41, and SW43 are all turned on. A plurality of switches SW12, SW14, SW22, SW24, SW32, SW34, SW42, and SW44 are all turned off. Amplifier 532.1 can be operated in conjunction with transistor 534.1 to implement a voltage regulator that can provide a supply voltage V31 to drive circuit 540.1. In addition, amplifier 532.1 can be operated in conjunction with transistor 534.2 to implement a voltage regulator that can provide a supply voltage V32 to drive circuit 540.2. Amplifier 532.1, a plurality of transistors 534.1 and 534.2, a plurality of switching circuits 536.1, 536.2, 538.1 and 538.2, and a plurality of drive circuits 540.1 and 540.2 can be configured as at least a part of D-PHY channel 601. Similarly, amplifier 532.2 can be operated with transistor 534.3 to implement a voltage regulator that can provide supply voltage V33 to drive circuit 540.3. In addition, amplifier 532.2 can be operated with transistor 534.4 to implement a voltage regulator that can provide supply voltage V34 to drive circuit 540.4. Amplifier 532.2, a plurality of transistors 534.3 and 534.4, a plurality of switching circuits 536.3, 536.4, 538.3 and 538.4, and a plurality of drive circuits 540.3 and 540.4 can be configured as at least part of D-PHY channel 602.

[0045] Since the circuit configuration shown in Figure 6A can implement two D-PHY channels 601 and 602, the voltage regulation circuit 530 can support a 1D1C lane configuration conforming to the MIPI D-PHY specification. By using a single amplifier to provide a fixed current to each D-PHY channel, the voltage regulation circuit 530 can have a simplified design to support MIPI D-PHY differential signal transmission.

[0046] FIG6B is a schematic diagram of the operation of the voltage regulation circuit 530 shown in FIG5 according to certain embodiments of the present disclosure in a second mode. In this embodiment, the voltage regulation circuit 530 operating in the second mode can support MIPI C-PHY signal transmission. During operation, a plurality of switches SW11, SW13, SW21, SW23, SW31, SW33, SW41 and SW43 are all open. A plurality of switches SW12, SW14, SW22, SW24, SW32, SW34, SW42 and SW44 are all closed. Therefore, the amplifier 532.1 shared by a plurality of transistors 534.1 to 534.3 can be operated in conjunction with each of the plurality of transistors 534.1 to 534.3 to implement a voltage regulator respectively. Amplifier 532.1, a plurality of transistors 534.1 to 534.3, a plurality of switching circuits 536.1 to 536.3 and 538.1 to 538.3, and a plurality of drive circuits 540.1 to 540.3 can be configured as at least a portion of C-PHY three-wire channel 611. By using a single amplifier to provide a fixed current to each C-PHY three-wire channel, voltage regulation circuit 530 can have a simplified design to support MIPI C-PHY differential signal transmission.

[0047] FIG7 is a schematic diagram of another embodiment of at least a portion of the voltage regulation circuit 130 shown in FIG1 according to certain embodiments of the present disclosure. For example, except that the voltage regulation circuit 730 shown in FIG7 further includes an amplifier 532.3, a transistor 534.5, and a transistor 534.6, the circuit structure shown in FIG7 may be similar / identical to the circuit structure shown in FIG5. In this embodiment, the power supply terminal TS3 of the amplifier 532.3 is coupled to the supply voltage V1. The input terminal TI31 of the amplifier 532.3 is coupled to a reference voltage VR3. A plurality of reference voltages VR1 to VR3 may be at the same voltage level. In some embodiments, the voltage level of one of the plurality of reference voltages VR1 to VR3 may be different from the voltage level of another of the plurality of reference voltages VR1 to VR3 without departing from the scope of the present disclosure.

[0048] For the plurality of transistors 534.5 and 534.6, the plurality of connection terminals TC51 and TC61 are all coupled to the supply voltage V2. The control terminal TCC5 of transistor 534.5 is selectively coupled to the output terminal TO3 of amplifier 532.3, and the connection terminal TC52 of transistor 534.5 is selectively coupled to the input terminal TI32 of amplifier 532.3. The control terminal TCC6 of transistor 534.6 is selectively coupled to the output terminal TO3 of amplifier 532.3, and the connection terminal TC62 of transistor 534.6 is selectively coupled to the input terminal TI32 of amplifier 532.3.

[0049] In this embodiment, the voltage regulation circuit 730 may further include a plurality of switching circuits 536.5, 536.6, 538.5, and 538.6. Switching circuit 536.5 is used to selectively couple the output terminal TO3 of amplifier 532.3 to the control terminal TCC5 of transistor 534.5. Switching circuit 538.5 is used to selectively couple the input terminal TI32 of amplifier 532.3 to the connection terminal TC52 of transistor 534.5. For example (but not limited thereto), switching circuit 536.5 may be implemented using two switches SW51 and SW52. When one of switches SW51 and SW52 is turned on, the other of switches SW51 and SW52 may be turned off. Switching circuit 538.5 may be implemented using two switches SW53 and SW54. When one of switches SW53 and SW54 is turned on, the other of switches SW53 and SW54 can be turned off.

[0050] Similarly, the switching circuit 536.6 for selectively coupling the output terminal TO3 of amplifier 532.3 to the control terminal TCC6 of transistor 534.6 can be implemented using two switches SW61 and SW62. When one of switches SW61 and SW62 is on, the other of switches SW61 and SW62 can be off. The switching circuit 538.6 for selectively coupling the input terminal TI32 of amplifier 532.3 to the connection terminal TC62 of transistor 534.6 can be implemented using two switches SW63 and SW64. When one of switches SW63 and SW64 is on, the other of switches SW63 and SW64 can be off.

[0051] It is worth noting that, in the embodiment shown in FIG. 7, transistor 534.4 can be coupled to one of the plurality of amplifiers 532.2 and 532.3 in one operating mode of voltage regulation circuit 730, and coupled to another of the plurality of amplifiers 532.2 and 532.3 in another operating mode of voltage regulation circuit 730. For example, the control terminal TCC4 of transistor 534.4 can be selectively coupled to one of the output terminal TO2 of amplifier 532.2 and the output terminal TO3 of amplifier 532.3. In addition, the connection terminal TC42 of transistor 534.4 can be selectively coupled to one of the input terminal TI22 of amplifier 532.2 and the input terminal TI32 of amplifier 532.3.

[0052] In this embodiment, when the control terminal TCC3 of transistor 534.3 is coupled to the output terminal TO1 of amplifier 532.1, the control terminal TCC4 of transistor 534.4 is coupled to the output terminal TO3 of amplifier 532.3, and the connection terminal TC42 of transistor 534.4 is coupled to the input terminal TI32 of amplifier 532.3, so as to output the supply voltage V34 (i.e., the regulated voltage) in response to the reference voltage VR3 and the supply voltage V2. When the control terminal TCC3 of transistor 534.3 is coupled to the output terminal TO2 of amplifier 532.2, the control terminal TCC4 of transistor 534.4 is coupled to the output terminal TO2 of amplifier 532.2, and the connection terminal TC42 of transistor 534.4 is coupled to the input terminal TI22 of amplifier 532.2, so as to output the supply voltage V34 in response to the reference voltage VR2 and the supply voltage V2.

[0053] FIG8A is a schematic diagram of the operation of the voltage regulation circuit 730 shown in FIG7 according to certain embodiments of the present disclosure in a first mode. In this embodiment, the voltage regulation circuit 730 operating in the first mode can support MIPI D-PHY differential signal transmission. During operation, a plurality of switches SW11, SW13, SW21, SW23, SW31, SW33, SW41, SW43, SW51, SW53, SW61 and SW63 are all turned on. A plurality of switches SW12, SW14, SW22, SW24, SW32, SW34, SW42, SW44, SW52, SW54, SW62 and SW64 are all turned off. The amplifier 532.1 shared by the plurality of transistors 534.1 and 534.2 can be operated in conjunction with each of the plurality of transistors 534.1 and 534.2 to implement a voltage regulator that can supply voltage V31 / V32 to drive circuits 540.1 / 540.2. The amplifier 532.2 shared by the plurality of transistors 534.3 and 534.4 can be operated in conjunction with each of the plurality of transistors 534.3 and 534.4 to implement a voltage regulator that can supply voltage V33 / V34 to drive circuits 540.3 / 540.4. The amplifier 532.3 shared by the plurality of transistors 534.5 and 534.6 can be operated in conjunction with each of the plurality of transistors 534.5 and 534.6 to implement a voltage regulator that supplies the supply voltage V35 / V36 to the drive circuits 540.5 / 540.6 via nodes N5 / N6. Therefore, the circuit configuration shown in Figure 8A can implement three D-PHY channels 801–803. The voltage regulation circuit 730 can utilize a simplified design (using a single amplifier to provide a fixed current to each D-PHY channel) to support a 2D1C channel configuration conforming to the MIPI D-PHY specification.

[0054] FIG8B is a schematic diagram of the operation of the voltage regulation circuit 730 shown in FIG7 according to certain embodiments of the present disclosure in a second mode. In this embodiment, the voltage regulation circuit 730 operating in the second mode can support MIPI C-PHY signal transmission. During operation, a plurality of switches SW11, SW13, SW21, SW23, SW31, SW33, SW41, SW43, SW51, SW53, SW61 and SW63 are all open. A plurality of switches SW12, SW14, SW22, SW24, SW32, SW34, SW42, SW44, SW52, SW54, SW62 and SW64 are all closed. Therefore, the amplifier 532.1 shared by a plurality of transistors 534.1 to 534.3 can be operated in conjunction with each of the plurality of transistors 534.1 to 534.3 to implement a voltage regulator respectively. The amplifier 532.3, shared by the plurality of transistors 534.4 to 534.6, can be operated in conjunction with each of the plurality of transistors 534.4 to 534.6 to implement a voltage regulator. The circuit configuration shown in Figure 8B can implement two C-PHY three-wire channels 811 and 812. The voltage regulation circuit 730 can support MIPI C-PHY signal transmission using a simplified design (which uses a single amplifier to provide a fixed current to each C-PHY three-wire channel).

[0055] The above-described voltage regulation circuit architecture is for illustrative purposes and is not intended to limit the scope of this disclosure. In some embodiments, at least one of the plurality of switching circuits 536.1, 536.2, 536.4, 538.1, 538.2, and 538.4 shown in FIG. 5 may be omitted. In some embodiments, at least one of the plurality of switching circuits 536.3 and 538.3 shown in FIG. 5 may be implemented using a single-pole double-throw (SPDT) switch. In some embodiments, at least one of the plurality of switching circuits 536.1, 536.2, 536.5, 536.6, 538.1, 538.2, 538.5, and 538.6 shown in FIG. 7 may be omitted. In some embodiments, at least one of the plurality of switching circuits 536.3, 536.4, 538.3, and 538.4 shown in FIG. 7 may be implemented using a single-pole double-throw switch. Any voltage regulation circuit that utilizes a configurable design that allows a single amplifier to be paired with different transistors in different operating modes to implement one or more voltage regulators, or that utilizes a single transistor that can be configured to be paired with different amplifiers in different operating modes to implement a voltage regulator, any related modifications and variations in the design fall within the scope of this disclosure.

[0056] Using the configurable voltage regulation scheme provided in this disclosure, an amplifier can be paired with one or more transistors to implement one or more configurable voltage regulators capable of supporting different channel configurations. Alternatively, using the configurable voltage regulation scheme provided in this disclosure, a transistor can be paired with different amplifiers to implement configurable voltage regulators capable of supporting different channel configurations. The configurable voltage regulation scheme provided in this disclosure offers flexible and simplified designs that meet different interface specifications.

[0057] FIG9 is an embodiment of at least a portion of the drive circuit 140 shown in FIG1 according to certain embodiments of the present disclosure. The drive circuit 940 can also be used to implement the drive circuits shown in FIG5 and FIG7. The drive circuit 940 may include (but is not limited to) a data output terminal TD and a plurality of switches SW91 to SW94. The data output terminal TD is used to output output data DA4 generated according to the decoded data DA3 and the supply voltage V3. Switch SW91 is selectively coupled between the supply voltage V3 and the data output terminal TD according to the decoded data DA3. Switch SW92 is selectively coupled between the data output terminal TD and a reference voltage VS according to the decoded data DA3. The voltage level of the reference voltage VS (such as the ground voltage level) may be less than the voltage level of the supply voltage V3. When one of the switches SW91 and SW92 is turned on, the other of the switches SW91 and SW92 is turned off. In addition, switch SW93 is selectively coupled between the supply voltage V3 and the data output terminal TD according to the decoded data DA3. Switch SW94 is selectively coupled between the data output terminal TD and the reference voltage VS based on the decoded data DA3. When one of switches SW93 and SW94 is turned on, the other of switches SW93 and SW94 is turned off.

[0058] In this embodiment, a plurality of switches SW91 to SW94 can be controlled by four bits A0 to D0 in the decoded data DA3. The supply voltage V3 can be coupled to the data output terminal TD via a circuit path CP1 (where switch SW91 is disposed) based on bit A0. The reference voltage VS can be coupled to the data output terminal TD via a circuit path CP2 (where switch SW92 is disposed) based on bit B0. The supply voltage V3 can be coupled to the data output terminal TD via a circuit path CP3 (where switch SW93 is disposed) based on bit C0. The reference voltage VS can be coupled to the data output terminal TD via a circuit path CP4 (where switch SW94 is disposed) based on bit D0. When one of the plurality of switches SW91 to SW94 is turned on, a voltage drop can be established across the corresponding circuit path. For example, each of the plurality of circuit paths CP1 to CP4 can include at least one resistive element connected in series with the corresponding switch.

[0059] Figures 10A to 10C are embodiments of the drive circuit 940 shown in Figure 9 according to certain embodiments of the present disclosure. Referring first to Figure 10A, the drive circuit 1040A includes a plurality of resistive elements R01 and R02, wherein each resistive element is coupled to the data output terminal TD. The circuit path CP1 shown in Figure 9 can be implemented using switch SW91 and resistive element R01, while the circuit path CP2 shown in Figure 9 can be implemented using switch SW92 and resistive element R01. Furthermore, the circuit path CP3 shown in Figure 9 can be implemented using switch SW93 and resistive element R02, and the circuit path CP4 shown in Figure 9 can be implemented using switch SW94 and resistive element R02.

[0060] Referring to Figure 10B, the drive circuit 1040B includes a plurality of resistive elements R1 to R4, each of which is coupled to the data output terminal TD. Circuit path CP1 shown in Figure 9 can be implemented using switch SW91 and resistive element R1, while circuit path CP2 shown in Figure 9 can be implemented using switch SW92 and resistive element R2. Circuit path CP3 shown in Figure 9 can be implemented using switch SW93 and resistive element R3, while circuit path CP4 shown in Figure 9 can be implemented using switch SW94 and resistive element R4. In this embodiment, the ratio of the resistance value of resistive element R1 to the resistance value of resistive element R3 is equal to (or approximately equal to) the ratio of the resistance value of resistive element R2 to the resistance value of resistive element R4.

[0061] Referring to Figure 10C, except for the arrangement of the plurality of resistive elements R1 to R4, the structure of the drive circuit 1040C is similar to / identical to the structure of the drive circuit 1040B shown in Figure 10B. In this embodiment, resistive element R1 is disposed between the supply voltage V3 and switch SW91, while resistive element R2 is disposed between switch SW92 and reference voltage VS. Furthermore, resistive element R3 is disposed between the supply voltage V3 and switch SW93, while resistive element R4 is disposed between switch SW94 and reference voltage VS.

[0062] The plurality of drive circuits 1040A to 1040C shown in Figures 10A to 10C can be configured as different types of drivers, such as differential drivers and three-bit quasi-drivers, according to the bit patterns of the plurality of bits A0 to D0. Figures 11A to 11C are schematic diagrams of the operation modes of the plurality of drive circuits 1040A to 1040C shown in Figures 10A to 10C according to certain embodiments of this disclosure. Referring first to Figure 11A, bits A0 and D0 can have the same bit value, and bits B0 and C0 can have the same bit value, wherein the bit value of bits B0 / C0 is equal to the inverse of the bit value of bits A0 / D0. Switches SW91 and SW94 can be considered to be controlled by the same control bit CNT, while switches SW92 and SW93 can be considered to be controlled by the same control bit CNTb, where control bit CNTb is the inverted version of control bit CNT.

[0063] During operation, when switch SW91 is on, switch SW94 is on, while switches SW92 and SW93 are both off. The output data DA4 generated at the data output terminal TD can be a data signal at a first voltage level. The output impedance of the drive circuit 1040A as seen from the data output terminal TD is equal to the equivalent impedance of the plurality of resistive elements R01 and R02 connected in parallel. When switch SW91 is off, switch SW94 is off, while switches SW92 and SW93 are both on. The output data DA4 generated at the data output terminal TD can be a data signal at a second voltage level. The output impedance of the drive circuit 1040A as seen from the data output terminal TD can still be equal to the equivalent impedance of the plurality of resistive elements R01 and R02 connected in parallel. In certain cases where multiple resistive elements R01 and R02 have different resistance values, one of the first voltage level and the second voltage level may correspond to a logic high level, while the other of the first voltage level and the second voltage level may correspond to a logic low level. Therefore, the drive circuit 1040A can be configured as a differential driver.

[0064] Please refer to Figure 11B. Bits A0 and C0 may have the same bit value, and bits B0 and D0 may have the same bit value, wherein the bit value of bits B0 / D0 is equal to the inverted bit value of bits A0 / C0. Switches SW91 and SW93 can be considered to be controlled by the same control bit CNT, while switches SW92 and SW94 can be considered to be controlled by the same control bit CNTb (i.e., the inverted version of control bit CNT). In operation, when switch SW91 is on, switch SW93 is on, while switches SW92 and SW94 are both off. The output data DA4 generated at the data output terminal TD can be a data signal at a first voltage level, wherein the first voltage level corresponds to either a logic high level or a logic low level. When switch SW91 is off, switch SW93 is off, while switches SW92 and SW94 are both on. The output data DA4 generated at the data output terminal TD can be a data signal at a second voltage level, where the second voltage level corresponds to either a logic high level or a logic low level. Therefore, the drive circuit 1040B can be configured as a differential driver.

[0065] It is worth noting that when the drive circuit 1040B is used to output the output data DA4, the output impedance of the drive circuit 1040B as seen from the data output terminal TD is equal to the equivalent impedance of the plurality of resistive elements R1 and R3 connected in parallel, or the equivalent impedance of the plurality of resistive elements R2 and R4 connected in parallel. In some cases where the ratio of the resistance values ​​of resistive element R1 to R3 is equal to the ratio of the resistance values ​​of resistive element R2 to R4, when the plurality of resistive elements R1 and R2 (or the plurality of resistive elements R3 and R4) have the same resistance value, the drive circuit 1040B can have the same output impedance regardless of whether the output data DA4 is at a logic high level or a logic low level.

[0066] Please refer to Figure 11C. The control scheme for the drive circuit 1040C is the same as the control scheme for the drive circuit 1040B shown in Figure 11B. Since those skilled in the art should be able to understand the operational details of the drive circuit 1040C after reading the relevant paragraphs in Figure 11B, further explanation will not be repeated here.

[0067] In some embodiments, the plurality of drive circuits 1040A to 1040C shown in Figures 10A to 10C can all be configured as three-bit quasi-drivers. Figures 12A to 12C are schematic diagrams of the operating modes of the plurality of drive circuits 1040A to 1040C shown in Figures 10A to 10C according to certain embodiments of this disclosure. Referring first to Figure 12A, the bit value of bit B0 can be equal to the inverted bit value of bit A0, and the bit value of bit D0 can be equal to the inverted bit value of bit C0. Switches SW91 and SW92 can be considered to be controlled by control bit CNT1 and control bit CNT1b respectively, wherein control bit CNT1b is the inverted version of control bit CNT1. Similarly, switches SW93 and SW94 can be considered as being controlled by control bit CNT2 and control bit CNT2b respectively, where control bit CNT2b is the inverted version of control bit CNT2.

[0068] During operation, when both switches SW91 and SW93 are open (e.g., the bit type of the plurality of control bits CNT1 and CNT2 is "00"), both switches SW92 and SW94 are open. The output data DA4 generated at the data output terminal TD can be a data signal at a first voltage level, wherein the first voltage level is equal to the voltage level of the reference voltage VS. When both switches SW91 and SW93 are open (e.g., the bit type of the plurality of control bits CNT1 and CNT2 is "11"), both switches SW92 and SW94 are open. The output data DA4 generated at the data output terminal TD can be a data signal at a second voltage level, wherein the second voltage level is equal to the voltage level of the supply voltage V3. When switch SW91 is open and switch SW93 is open (e.g., the bit type of the plurality of control bits CNT1 and CNT2 is "01"), switch SW92 is open, and switch SW94 is open. The output data DA4 generated at the data output terminal TD can be a data signal at a third voltage level, wherein the third voltage level is between the voltage level of the reference voltage VS and the voltage level of the supply voltage V3. When switch SW91 is open and switch SW93 is open (e.g., the bit type of the plurality of control bits CNT1 and CNT2 is "10"), switch SW92 is open, and switch SW94 is open. The output data DA4 generated at the data output terminal TD can be a data signal at a fourth voltage level, wherein the fourth voltage level is between the voltage level of the reference voltage VS and the voltage level of the supply voltage V3.

[0069] In this embodiment, the plurality of resistive elements R01 and R02 may have the same resistance value. Therefore, both the third voltage level and the fourth voltage level can be equal to the average of the reference voltage VS and the supply voltage V3. The drive circuit 1040A can be configured as a three-level driver. It is worth noting that in some embodiments where the plurality of resistive elements R01 and R02 have different resistance values, the drive circuit 1040A can be configured as a four-level driver.

[0070] Please refer to Figure 12B. The control scheme for drive circuit 1040B is the same as the control scheme for drive circuit 1040A shown in Figure 12A. For example, switches SW91 and SW92 can be considered as being controlled by control bits CNT1 and CNT1b, respectively. Switches SW93 and SW94 can be considered as being controlled by control bits CNT2 and CNT2b, respectively.

[0071] Similarly, when both switches SW91 and SW93 are open, both switches SW92 and SW94 are closed. The output data DA4 generated at the data output terminal TD can be a data signal at a first voltage level, wherein the first voltage level is equal to the voltage level of the reference voltage VS. When both switches SW91 and SW93 are closed, both switches SW92 and SW94 are open. The output data DA4 generated at the data output terminal TD can be a data signal at a second voltage level, wherein the second voltage level is equal to the voltage level of the supply voltage V3. When switch SW91 is open and switch SW93 is closed, switch SW92 is closed, and switch SW94 is open. The output data DA4 generated at the data output terminal TD can be a data signal at a third voltage level, wherein the third voltage level is between the voltage level of the reference voltage VS and the voltage level of the supply voltage V3. When switch SW91 is on and switch SW93 is off, switch SW92 is off and switch SW94 is on. The output data DA4 generated at the data output terminal TD can be a data signal at a fourth voltage level, wherein the fourth voltage level is between the voltage level of the reference voltage VS and the voltage level of the supply voltage V3.

[0072] In this embodiment, the plurality of resistive elements R1 to R4 may have the same resistance value. Therefore, both the third voltage level and the fourth voltage level can be equal to the average of the reference voltage VS and the supply voltage V3. The drive circuit 1040B can be configured as a three-level driver. It is worth noting that in some embodiments where the plurality of resistive elements R01 and R02 have different resistance values, the drive circuit 1040B can be configured as a four-level driver.

[0073] Please refer to Figure 12C. The control scheme for the drive circuit 1040C is the same as the control scheme for the drive circuit 1040B shown in Figure 12B. Since those skilled in the art should be able to understand the operational details of the drive circuit 1040C after reading the descriptions related to Figures 12A and 12B, further explanation will not be repeated here.

[0074] The structure of the drive circuit described above with reference to Figures 9 to 12C can be used to implement other types of multi-level drivers, which can serve as de-emphasis / pre-emphasis drivers. Figure 13 is an embodiment of at least a portion of the drive circuit 140 shown in Figure 1 according to certain embodiments of this disclosure. The drive circuit 1340 can also be used to implement the drive circuits shown in Figures 5 and 7. The drive circuit 1340 may include (but is not limited to) a pair of differential data output terminals and a plurality of variable impedance circuits 1350 and 1360. The pair of differential data output terminals is used to output output data DA4 and may include a plurality of data output terminals TDP and TDN. A termination element RTERM (or terminating resistor) is disposed between the plurality of data output terminals TDP and TDN.

[0075] The variable impedance circuit 1350 is switchably coupled between the supply voltage V3 and the data output terminal TDP according to the decoded data DA3. For example, the drive circuit 1340 may further include a switch SWP for selectively coupling the supply voltage V3 to the variable impedance circuit 1350 according to the decoded data DA3. Those skilled in the art will understand that the switch SWP can be set between the variable impedance circuit 1350 and the data output terminal TDP without departing from the scope of this disclosure. Furthermore, when the variable impedance circuit 1350 is coupled between the supply voltage V3 and the data output terminal TDP, the impedance RP of the variable impedance circuit 1350 is determined according to the decoded data DA3.

[0076] Similarly, the variable impedance circuit 1360 is switchably coupled between the data output terminal TDN and the reference voltage VS according to the decoded data DA3. For example, the drive circuit 1340 may further include a switch SWN, which is used to selectively couple the reference voltage VS to the variable impedance circuit 1360 according to the decoded data DA3. Those skilled in the art will understand that the switch SWN can be set between the variable impedance circuit 1360 and the data output terminal TDN without departing from the scope of this disclosure. Furthermore, when the variable impedance circuit 1360 is coupled between the data output terminal TDN and the reference voltage VS, the impedance RN of the variable impedance circuit 1360 is determined according to the decoded data DA3.

[0077] In this embodiment, both impedance RP and impedance RN can dynamically switch between two different impedance values ​​RV1 and RV2, enabling the drive circuit 1340 to be implemented as a de-emphasis / pre-emphasis driver capable of generating four voltage levels. During operation, when the drive circuit 1340 acts as a de-emphasis / pre-emphasis driver, both switches SWP and SWN are turned on according to the decoded data DA3. Furthermore, the impedance RP of the variable impedance circuit 1350 and the impedance RN of the variable impedance circuit 1360 both change according to the decoded data DA3. Therefore, the voltage drop VTERM of the terminal element RTERM can be changed according to the respective impedance values ​​of impedance RP and impedance RN. For example, when both impedance RP and impedance RN are switched to impedance value RV1, the voltage drop VTERM is equal to a first voltage. When impedance RP and impedance RN are switched to impedance values ​​RV1 and RV2 respectively, the voltage drop VTERM is equal to a second voltage different from the first voltage. When impedances RP and RN are switched to impedance values ​​RV2 and RV1 respectively, the voltage drop VTERM is equal to a third voltage that is different from the first voltage and the second voltage. When both impedances RP and RN are switched to impedance value RV2, the voltage drop VTERM is equal to a fourth voltage that is different from the first voltage, the second voltage, and the third voltage.

[0078] Since the current supplied by the power supply does not increase when de-emphasis / pre-emphasis is enabled, the drive scheme provided in this disclosure can effectively reduce power consumption compared to a de-emphasis / pre-emphasis driver that uses a parallel resistor set between the supply voltage / ground voltage and the data output terminal to adjust the output voltage level.

[0079] In some embodiments, at least one of the variable impedance circuit 1350 and the variable impedance circuit 1360 may be implemented using the plurality of drive circuits 1040A to 1040C shown in Figures 10 to 10C. First, referring to Figure 13 along with Figure 10A, the variable impedance circuit 1350 may be implemented using drive circuit 1040A. Switch SWP may be used to selectively couple the supply voltage V3 to the plurality of switches SW91 and SW93, and the data output terminal TDP may be an embodiment of the data output terminal TD. The impedance RP of the variable impedance circuit 1350 is equal to the output impedance of drive circuit 1040A.

[0080] During operation, when multiple switches SW91 and SW93 are turned on and multiple switches SW92 and SW94 are turned off, the impedance value of impedance RP is equal to the equivalent resistance value of multiple resistive elements R01 and R02 connected in series. When switch SW91 is turned on and multiple switches SW92 to SW94 are all turned off, the impedance value of impedance RP is equal to the resistance value of resistive element R01, which is different from the equivalent resistance value of multiple resistive elements R01 and R02 connected in series. When switch SW93 is turned on and multiple switches SW91, SW92, and SW94 are all turned off, the impedance value of impedance RP is equal to the resistance value of resistive element R02, which is different from the equivalent resistance value of multiple resistive elements R01 and R02 connected in series. Therefore, the variable impedance circuit 1350 implemented using drive circuit 1040A can provide at least two different impedance values.

[0081] Similarly, in some embodiments where the variable impedance circuit 1360 is implemented using the drive circuit 1040A, the variable impedance circuit 1360 can provide at least two different impedance values. For example, switch SWN can be used to selectively couple the reference voltage VS to a plurality of switches SW92 and SW94, and data output terminal TDN can be used as an embodiment of data output terminal TD. The impedance RN of the variable impedance circuit 1360 is equal to the output impedance of the drive circuit 1040A. In operation, when a plurality of switches SW92 and SW94 are turned on and a plurality of switches SW91 and SW93 are turned off, the impedance value of impedance RN is equal to the equivalent resistance value of a plurality of resistive elements R01 and R02 connected in series. When switch SW92 is turned on and a plurality of switches SW91, SW93 and SW94 are all turned off, the impedance value of impedance RN is equal to the resistance value of resistive element R01. When switch SW94 is turned on and multiple switches SW91 to SW93 are turned off, the impedance value of impedance RN is equal to the resistance value of resistive element R02.

[0082] Referring to Figure 13 along with Figure 10B, the variable impedance circuit 1350 can be implemented using the drive circuit 1040B. The switch SWP can be used to selectively couple the supply voltage V3 to a plurality of switches SW91 and SW93, while the data output terminal TDP can serve as an embodiment of the data output terminal TD. The impedance RP of the variable impedance circuit 1350 is equal to the output impedance of the drive circuit 1040B.

[0083] During operation, when multiple switches SW91 and SW93 are turned on and multiple switches SW92 and SW94 are turned off, the impedance value of impedance RP is equal to the equivalent resistance value of multiple resistive elements R1 and R3 connected in series. When switch SW91 is turned on and multiple switches SW92 to SW94 are all turned off, the impedance value of impedance RP is equal to the resistance value of resistive element R1, which is different from the equivalent resistance value of multiple resistive elements R1 and R3 connected in series. When switch SW93 is turned on and multiple switches SW91, SW92, and SW94 are all turned off, the impedance value of impedance RP is equal to the resistance value of resistive element R3, which is different from the equivalent resistance value of multiple resistive elements R1 and R3 connected in series. Therefore, the variable impedance circuit 1350 implemented using drive circuit 1040B can provide at least two different impedance values.

[0084] Similarly, in some embodiments where the variable impedance circuit 1360 is implemented using the drive circuit 1040B, the variable impedance circuit 1360 can provide at least two different impedance values. For example, switch SWN can be used to selectively couple the reference voltage VS to a plurality of switches SW92 and SW94, and data output terminal TDN can be used as an embodiment of data output terminal TD. The impedance RN of the variable impedance circuit 1360 is equal to the output impedance of the drive circuit 1040B. In operation, when a plurality of switches SW92 and SW94 are turned on and a plurality of switches SW91 and SW93 are turned off, the impedance value of impedance RN is equal to the equivalent resistance value of a plurality of resistive elements R2 and R4 connected in series. When switch SW92 is turned on and a plurality of switches SW91, SW93 and SW94 are all turned off, the impedance value of impedance RN is equal to the resistance value of resistive element R2. When switch SW94 is turned on and multiple switches SW91 to SW93 are turned off, the impedance value of impedance RN is equal to the resistance value of resistive element R4.

[0085] Referring to FIG. 13 along with FIG. 10C, the variable impedance circuit 1350 can be implemented using the drive circuit 1040C. Alternatively, the variable impedance circuit 1360 can be implemented using the drive circuit 1040C. Since those skilled in the art should understand, after reading the description of FIG. 10B and FIG. 10C, the operational details of the variable impedance circuits 1350 / 1360 implemented using the drive circuit 1040C providing at least two different impedance values, similar descriptions will not be repeated here.

[0086] FIG14 is another embodiment of at least a portion of the drive circuit 140 shown in FIG1 according to certain embodiments of the present disclosure. For example, except that the plurality of impedance circuits 1450 and 1460 shown in FIG14 are used to provide fixed impedance values, the circuit structure of drive circuit 1440 is similar / identical to the circuit structure of drive circuit 1340 shown in FIG13. In this embodiment, impedance circuit 1450 may be implemented using impedance RPF, and impedance circuit 1460 may be implemented using impedance RNF. Both impedance RPF and impedance RNF have fixed impedance values, which may be equal to the smaller of impedance values ​​RV1 and RV2 shown in FIG13. Therefore, in certain cases where at least one of the plurality of variable impedance circuits 1350 and 1360 shown in FIG13 is used to provide the larger of the impedance values ​​RV1 and RV2 shown in FIG13, the output data DA4 transmitted by the drive circuit 1440 can have a larger output swing than the output swing of the output data DA4 transmitted by the drive circuit 1340 shown in FIG13. Since those skilled in the art should understand the operational details of the drive circuit 1440 after reading the description of FIG1 and the paragraphs related to FIG4 to FIG13, further explanation will not be repeated here.

[0087] The foregoing description briefly outlines the features of certain embodiments of this disclosure, enabling those skilled in the art to gain a more comprehensive understanding of the various forms of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0008] The various embodiments disclosed herein can be clearly understood by reading the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the size of certain features may be arbitrarily enlarged or reduced for clear description. FIG1 is a functional block diagram of an exemplary transmission circuit according to some embodiments of the present disclosure. FIG2 is a schematic diagram of an embodiment of the data serialization circuit shown in FIG1 according to some embodiments of the present disclosure. FIG3 is a schematic diagram of another embodiment of the data serialization circuit shown in FIG1 according to some embodiments of the present disclosure. FIG4 is a schematic diagram of an embodiment of the voltage regulation circuit shown in FIG1 according to some embodiments of the present disclosure. FIG5 is a schematic diagram of another embodiment of at least a portion of the voltage regulation circuit shown in FIG1 according to some embodiments of the present disclosure. FIG6A and FIG6B are schematic diagrams of the operation of the voltage regulation circuit shown in FIG5 according to some embodiments of the present disclosure in different modes. FIG7 is a schematic diagram of another embodiment of at least a portion of the voltage regulation circuit shown in FIG1 according to some embodiments of the present disclosure. FIG8A and FIG8B are schematic diagrams of the operation of the voltage regulation circuit shown in FIG7 according to some embodiments of the present disclosure in different modes. Figure 9 is an embodiment of at least a portion of the driving circuit shown in Figure 1 according to certain embodiments of the present disclosure. Figures 10A to 10C are embodiments of the driving circuit shown in Figure 9 according to certain embodiments of the present disclosure. Figures 11A to 11C are schematic diagrams of the operation modes of the plurality of driving circuits shown in Figures 10A to 10C according to certain embodiments of the present disclosure. Figures 12A to 12C are schematic diagrams of the operation modes of the plurality of driving circuits shown in Figures 10A to 10C according to certain embodiments of the present disclosure. Figure 13 is an embodiment of at least a portion of the driving circuit shown in Figure 1 according to certain embodiments of the present disclosure. Figure 14 is another embodiment of at least a portion of the driving circuit shown in Figure 1 according to certain embodiments of the present disclosure.

Claims

1. A driving circuit comprising: a data output terminal for outputting an output data; a first switch selectively coupled between a first voltage and the data output terminal; a second switch selectively coupled between the data output terminal and a second voltage; a third switch selectively coupled between the first voltage and the data output terminal; and a fourth switch selectively coupled between the data output terminal and the second voltage; wherein when one of the first switch and the second switch is turned on, the other of the first switch and the second switch is turned off; and when one of the third switch and the fourth switch is turned on, the other of the third switch and the fourth switch is turned off. When both the first switch and the third switch are turned on, the output data has a first voltage level; when both the second switch and the fourth switch are turned on, the output data has a second voltage level; when one of the first switch and the third switch is turned on and the other of the first switch and the third switch is turned off, the output data has a third voltage level; the first voltage level, the second voltage level and the third voltage level are different from each other.

2. The driving circuit as claimed in claim 1, further comprising: a first resistive element coupled between a first terminal and the data output terminal, wherein the first switch is configured to selectively couple the first voltage to the first terminal, and the second switch is configured to selectively couple the first terminal to the second voltage; and a second resistive element coupled between a second terminal and the data output terminal, wherein the third switch is configured to selectively couple the first voltage to the second terminal, and the fourth switch is configured to selectively couple the second terminal to the second voltage.

3. The driving circuit as claimed in claim 2, wherein the resistance value of the first resistive element is equal to the resistance value of the second resistive element.

4. The driving circuit as claimed in claim 1, further comprising: a first resistive element, one end of which is coupled to one of the first voltage and the data output terminal, and the first switch for selectively coupling the other end of the first resistive element to the other of the first voltage and the data output terminal; A second resistive element, one end of which is coupled to one of the data output terminal and the second voltage, and the second switch is used to selectively couple the other end of the second resistive element to the other of the data output terminal and the second voltage; A third resistive element, one end of which is coupled to one of the first voltage and the data output terminal, and a third switch for selectively coupling the other end of the third resistive element to the other of the first voltage and the data output terminal; and a fourth resistive element, one end of which is coupled to one of the data output terminal and the second voltage, and a fourth switch for selectively coupling the other end of the fourth resistive element to the other of the data output terminal and the second voltage.

5. The drive circuit as claimed in claim 4, wherein the ratio of the resistance value of the first resistive element to the resistance value of the third resistive element is equal to the ratio of the resistance value of the second resistive element to the resistance value of the fourth resistive element.

6. The drive circuit as claimed in claim 4, wherein the resistance value of the first resistive element is equal to the resistance value of the third resistive element, and the resistance value of the second resistive element is equal to the resistance value of the fourth resistive element.

7. The drive circuit as claimed in claim 1, wherein when the first switch is turned on and the third switch is turned off, the output data has the third voltage level; and when the first switch is turned off and the third switch is turned on, the output data has a fourth voltage level different from the third voltage level.

8. A driving circuit, comprising: a pair of differential data output terminals for outputting an output data, the pair of differential data output terminals including a first data output terminal and a second data output terminal; and a first switch; a first variable impedance circuit, wherein a first terminal of the first variable impedance circuit is coupled to one of a first voltage and the first data output terminal, and the first switch is used to selectively couple a second terminal of the first variable impedance circuit to the other of the first voltage and the first data output terminal; A second switch; And a second variable impedance circuit, wherein a first terminal of the second variable impedance circuit is coupled to one of a second voltage and the second data output terminal, and the second switch is used to selectively couple a second terminal of the second variable impedance circuit to the other of the second voltage and the second data output terminal.

9. The driving circuit as claimed in claim 8, wherein the first variable impedance circuit is used to provide a first variable impedance between a first terminal and a second terminal of the first variable impedance circuit, and the second variable impedance circuit is used to provide a second variable impedance between a first terminal and a second terminal of the second variable impedance circuit; both the first variable impedance and the second variable impedance have at least a first impedance value and a second impedance value, wherein the first impedance value is different from the second impedance value.

10. The driving circuit as claimed in claim 8, wherein the first variable impedance circuit comprises: a first resistive element coupled to a second terminal of the first variable impedance circuit; a third switch for selectively coupling a first terminal of the first variable impedance circuit to the second terminal of the first variable impedance circuit via the first resistive element; a fourth switch for selectively coupling a first terminal of the first variable impedance circuit to the second terminal of the first variable impedance circuit via the first resistive element; a second resistive element coupled to the second terminal of the first variable impedance circuit; a fifth switch for selectively coupling a first terminal of the first variable impedance circuit to the second terminal of the first variable impedance circuit via the second resistive element; and a sixth switch for selectively coupling a first terminal of the first variable impedance circuit to the second terminal of the first variable impedance circuit via the second resistive element.

11. The drive circuit as claimed in claim 10, wherein when one of the third switch and the fourth switch is turned on, the other of the third switch and the fourth switch is turned off; and when one of the fifth switch and the sixth switch is turned on, the other of the fifth switch and the sixth switch is turned off.

12. The drive circuit as claimed in claim 10, wherein when both the third switch and the fifth switch are on, both the fourth switch and the sixth switch are off; and when the third switch is on and the fifth switch is off, both the fourth switch and the sixth switch are off.

13. The driving circuit as claimed in claim 8, wherein the first variable impedance circuit comprises: a third switch and a first resistive element, wherein one end of the first resistive element is coupled to one of a first terminal and a second terminal of the first variable impedance circuit, and the third switch is configured to selectively couple the other end of the first resistive element to the other of the first terminal and the second terminal of the first variable impedance circuit; a fourth switch and a second resistive element, wherein one end of the second resistive element is coupled to one of the first terminal and the second terminal of the first variable impedance circuit, and the fourth switch is configured to selectively couple the other end of the second resistive element to the other of the first terminal and the second terminal of the first variable impedance circuit; A fifth switch and a third resistive element, wherein one end of the third resistive element is coupled to one of the first and second terminals of the first variable impedance circuit, and the fifth switch is used to selectively couple the other end of the third resistive element to the other of the first and second terminals of the first variable impedance circuit; and a sixth switch and a fourth resistive element, wherein one end of the fourth resistive element is coupled to one of the first and second terminals of the first variable impedance circuit, and the sixth switch is used to selectively couple the other end of the fourth resistive element to the other of the first and second terminals of the first variable impedance circuit.

14. The drive circuit as claimed in claim 13, wherein when one of the third switch and the fourth switch is turned on, the other of the third switch and the fourth switch is turned off; and when one of the fifth switch and the sixth switch is turned on, the other of the fifth switch and the sixth switch is turned off.

15. The drive circuit as claimed in claim 13, wherein when both the third switch and the fifth switch are on, both the fourth switch and the sixth switch are off; and when the third switch is on and the fifth switch is off, both the fourth switch and the sixth switch are off.

16. A driving circuit comprising: a pair of differential data output terminals for outputting an output data, the pair of differential data output terminals including a first data output terminal and a second data output terminal; a first variable impedance circuit switchably coupled between a first node and the first data output terminal to provide a first variable impedance between the first node and the first data output terminal, wherein the first node is coupled to a first voltage; and a second variable impedance circuit switchably coupled between the second data output terminal and a second node to provide a second variable impedance between the second data output terminal and the second node, wherein the second node is coupled to a second voltage different from the first voltage; the first variable impedance and the second variable impedance each have at least a first impedance value and a second impedance value, and the first impedance value is different from the second impedance value.

17. The driving circuit as claimed in claim 16, wherein the first variable impedance circuit comprises: a first resistive element; a first switch, wherein when the first variable impedance circuit is coupled between the first node and the first data output terminal, the first switch is configured to selectively couple the first voltage to the first data output terminal via the first resistive element; a second switch, wherein when the first variable impedance circuit is coupled between the first node and the first data output terminal, the second switch is configured to selectively couple the first voltage to the first data output terminal via the first resistive element; and a second resistive element; A third switch, wherein when the first variable impedance circuit is coupled between the first node and the first data output terminal, the third switch is used to selectively couple the first voltage to the first data output terminal via the second resistive element; And a fourth switch, wherein when the first variable impedance circuit is coupled between the first node and the first data output terminal, the fourth switch is used to selectively couple the first voltage to the first data output terminal via the fourth resistive element.

18. The drive circuit as claimed in claim 17, wherein when the first variable impedance circuit is used to provide the first variable impedance having the first impedance value between the first node and the first data output terminal, the first switch and the third switch are both turned on, and the second switch and the fourth switch are both turned off; when the first variable impedance circuit is used to provide the first variable impedance having the second impedance value between the first node and the first data output terminal, the first switch is turned on, the second switch is turned off, and the third switch and the fourth switch are both turned off.

19. The drive circuit as claimed in claim 16, wherein the first variable impedance circuit comprises: a first switch and a first resistive element, wherein when the first variable impedance circuit is coupled between the first node and the first data output terminal, one end of the first resistive element is coupled to one of the first node and the first data output terminal, and the first switch is used to selectively couple the other end of the first resistive element to the other of the first node and the first data output terminal; A second switch and a second resistive element, wherein when the first variable impedance circuit is coupled between the first node and the first data output terminal, one end of the second resistive element is coupled to one of the first node and the first data output terminal, and the second switch is used to selectively couple the other end of the second resistive element to the other of the first node and the first data output terminal; A third switch and a third resistive element, wherein when the first variable impedance circuit is coupled between the first node and the first data output terminal, one end of the third resistive element is coupled to one of the first node and the first data output terminal, and the third switch is used to selectively couple the other end of the third resistive element to the other of the first node and the first data output terminal; The circuit includes a fourth switch and a fourth resistive element. When the first variable impedance circuit is coupled between the first node and the first data output terminal, one end of the fourth resistive element is coupled to one of the first node and the first data output terminal, and the fourth switch is used to selectively couple the other end of the fourth resistive element to the other of the first node and the first data output terminal.

20. The drive circuit as claimed in claim 19, wherein when the first variable impedance circuit is used to provide the first variable impedance having the first impedance value between the first node and the first data output terminal, the first switch and the third switch are both turned on, and the second switch and the fourth switch are both turned off; when the first variable impedance circuit is used to provide the first variable impedance having the second impedance value between the first node and the first data output terminal, the first switch is turned on, the second switch is turned off, and the third switch and the fourth switch are both turned off.

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