Overlaying on locally dispositioned patterns by ML based dynamic digital corrections (ML-ddc)
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-08-02
- Publication Date
- 2023-04-01
Smart Images
Figure TWG2TA000903172_001 
Figure TWG2TA000903172_002 
Figure TWG2TA000903172_003
Abstract
Description
[Technical Field]
[0001] The embodiments of this disclosure are generally related to the integration of pre-assembled components on a substrate for substrate processing, and more specifically to the detection and correction of connections between displacement design components. [Previous Technology]
[0002] As the demand for additional functionality in semiconductor devices increases, heterogeneous integration modules that enable such additional functionality are becoming an increasingly important factor in semiconductor manufacturing. Integration modules may include, but are not limited to, memory, sensors, logic, antennas, display drivers, controllable drivers, etc. In this context, an integration module may be a separately manufactured semiconductor product placed on a substrate, or a design manufactured onto a substrate using a separate process.
[0003] When a design is patterned on a substrate or an integrated module is placed on a substrate, each substrate may be affected by conditions that could lead to misalignment, dimensional errors, or other displacements, thereby altering the connection path between the integrated module and the patterned design. Traditionally, the altered connection path is provided by one or more correction masks, which are fabricated to adjust the connection based on a fixed set of potential displacements. However, the set of correction masks is typically limited and may not cover all possible corrections. The limitations imposed by the limited set of correction masks are further exacerbated by the increasing number of nodes placed in a single wafer package. As node density increases, more and more localized and precise corrections are required, which may exceed the correction capabilities of a limited number of correction masks.
[0004] What is needed now is a system and method to mitigate the shortcomings of previous methods. [Summary of the Invention]
[0005] The disclosed system and method are generally related to maskless development of connections between chip groups on a substrate and designed connection points. In this context, the chip group can be a separately manufactured semiconductor product placed on the substrate, or a design manufactured onto the substrate via a separate process. When placing chip groups on a substrate, whether physically placed or separately manufactured, according to some embodiments, the chip group may be misaligned, missized, or otherwise displaced relative to its intended position as designed for the substrate layout, resulting in misalignment of connections with designed connection points. According to some embodiments, a machine learning (ML) model is trained based on historical and simulated pixel models of chip group connections and designed connection points. After determining chip group misalignment by metrology, the trained ML model determines pixel models to connect the misaligned chip group, and exposes the pixel models to the substrate using digital lithography tools, thereby connecting the displaced chip group to the designed connection points.
[0006] In one embodiment, a system is disclosed that includes memory containing computer-readable instructions, and a processor is configured to read the computer-readable instructions. The computer-readable instructions cause the processor to: receive a substrate layout design including design connection points; receive a chip group layout design including metadata defining a chip group including chip group connection points; and generate digital exposure groups based on the substrate layout design and the chip group layout design. The computer-readable instructions further cause the processor to: pattern the substrate with the design connection points and place the chip group based on the digital exposure groups; measure the displacement of the chip group causing the chip group connection points to be displaced relative to the design connection points; and determine a transformed pixel model using a trained machine learning (ML) model, the transformed pixel model including connection paths from the design connection points to the chip group connection points.
[0007] In another embodiment, a computer program product is disclosed, comprising a non-transitory computer-readable storage medium having computer-readable code embossed thereon. The computer-readable code is executable by one or more processors to: receive a substrate layout design including design connection points; receive a chip group layout design including metadata defining a chip group including chip group connection points; and generate digital exposure groups based on the substrate layout design and the chip group layout design. The computer-readable code is further executable by the one or more processors to: pattern the substrate with the design connection points and place the chip group based on the digital exposure groups; measure the displacement of the chip group causing the chip group connection points to be displaced relative to the design connection points; and determine a transformed pixel model using a trained machine learning (ML) model, the transformed pixel model including connection paths from the design connection points to the chip group connection points.
[0008] In another embodiment, a method is disclosed, comprising the steps of: receiving a substrate layout design including design connection points; receiving a chip group layout design including metadata defining a chip group including chip group connection points; and generating digital exposure groups based on the substrate layout design and the chip group layout design. The method further comprises the steps of: patterning a substrate with the design connection points and placing the chip group based on the digital exposure groups; measuring the displacement of the chip group that causes the chip group connection points to be displaced relative to the design connection points; and determining a transformed pixel model using a trained machine learning (ML) model, the transformed pixel model including connection paths from the design connection points to the chip group connection points.
Implementation Method
[0029] In the following, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, any combination of the following features and elements may be considered for implementation and practice of this disclosure, whether or not they are associated with different embodiments. Furthermore, while embodiments of this disclosure may achieve advantages relative to other possible solutions and / or relative to prior art, whether a given embodiment achieves a particular advantage is not a limitation of this disclosure. Therefore, the following appearances, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, the designation "this disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims unless expressly stated in the claims.
[0030] The disclosed systems and methods are generally related to masklessly exposing the connections between chip groups and design connection points on a substrate. In this context, the chip group can be a separately manufactured semiconductor product placed on the substrate, or a design manufactured onto the substrate via a separate process. When placing chip groups on a substrate, whether physically placed or separately manufactured, according to some embodiments, the chip group may be misaligned, missized, or otherwise displaced relative to its intended position as designed for the substrate layout, resulting in misalignment of connections with design connection points. According to some embodiments, a machine learning (ML) model is trained based on historical and simulated pixel models of chip group connections and design connection points. After determining chip group misalignment by metrology, the trained ML model determines pixel models to connect the misaligned chip group, resulting in the exposure of pixel-model-corrected connections or connection segments on the substrate using digital lithography tools, thereby connecting the displaced chip group to the design connection points.
[0031] The design requirements of semiconductor devices such as integrated circuits, video displays, and other devices increasingly demand the separate fabrication of components, such as memory, processors, application-specific logic, lens arrays, active quantum dots, color filters, optical focusing sidewall mirrors, and other components for additional functionality. As these demands increase, the space required to place these components on a given substrate becomes increasingly demanding in terms of placement accuracy, as the available substrate space for correction becomes increasingly limited.
[0032] FIG1 is a perspective view of a system 100 that may benefit from certain embodiments. System 100 is a digital lithography tool including a base frame 110, a plate 120, a platform 130, and a processing device 160. The base frame 110 rests on the floor of a manufacturing facility and may support the plate 120. A passive air isolator 112 is positioned between the base frame 110 and the plate 120. The plate 120 may be a single piece of granite, and the platform 130 is disposed on the plate 120. A substrate 140 may be supported by the platform 130. A plurality of holes (not shown) may be formed in the platform 130 to allow a plurality of lifting pins (not shown) to extend therethrough. The lifting pins may rise to an extended position to receive the substrate 140, for example, from a transfer robot (not shown). The transfer robot positions the substrate 140 on the lifting pins, after which the lifting pins gently lower the substrate 140 onto the platform 130.
[0033] For example, substrate 140 may be made of quartz and used as part of a flat panel display, and processes using substrates made of different materials (e.g., silicon, germanium, and other materials, and combinations thereof) for different purposes (e.g., integrated circuits (ICs), application-specific integrated circuits (ASICs), etc.) may benefit from the disclosure herein. In other embodiments, substrate 140 may be made of other materials. In some embodiments, substrate 140 may have a photoresist layer formed thereon. The photoresist is radiation-sensitive and may be a positive or negative photoresist, meaning that the portion of the photoresist exposed to radiation will be soluble or insoluble in the photoresist developer applied to the photoresist after the pattern is written into the photoresist. The chemical composition of the photoresist determines whether the photoresist is a positive or negative photoresist. For example, the photoresist may include at least one of diazonaphthoquinone, phenol-formaldehyde resin, poly(methyl methacrylate), poly(methylpentadienylimide), and SU-8. In this way, patterns can be created on the surface of the substrate 140 to form an electronic circuit system.
[0034] System 100 further includes a pair of supports 122 and a pair of tracks 124. The pair of supports 122 are disposed on a plate 120, and the plate 120 and the pair of supports 122 may be a single block of material. The pair of tracks 124 are supported by the pair of supports 122, and the platform 130 moves along the tracks 124 in an in-scan direction. In one embodiment, the pair of tracks 124 are a pair of parallel magnetic channels. As shown, each of the pairs of tracks 124 is linear. In other embodiments, the tracks 124 may have a non-linear shape. An encoder 126 or other sensor is coupled to the platform 130 to provide position information to the controller 170 and can detect movement of the platform caused by vibration. In some embodiments, the encoder 126 may be an interferometer, or other device or sensor capable of detecting the position of the platform, vibration of the platform, and in-scan and / or cross-scan deviations of the platform caused by vibration.
[0035] The processing apparatus 160 includes a support 162 and a processing unit 164. The support 162 is disposed on the plate 120 and may include an opening 166 for the platform 130 to pass under the processing unit 164. The processing unit 164 may be supported by the support 162. In one embodiment, the processing unit 164 is a pattern generator configured to expose photoresist in a photolithography process. In some embodiments, the pattern generator may be configured to perform a maskless photolithography process. The processing unit 164 may include a plurality of image projection systems 301 (shown in FIG. 3) disposed in a housing 165. The processing apparatus 160 may be used to perform maskless direct patterning. During operation, one of the platforms 130 moves in the scan-in direction from a loading position (as shown in FIG. 1) to a processing position. The processing position may refer to one or more positions of the platform 130 as it passes under the processing unit 164. During operation, platform 130 is lifted by a plurality of air bearings 202 (shown in FIG. 2) and moved along the pair of tracks 124 from a loading position to a processing position. A plurality of vertically guiding air bearings 202 (shown in FIG. 2) are coupled to platform 130 and positioned near the inner wall 128 of each support 122 to stabilize the movement of platform 130. Platform 130 can also be moved in the cross-scanning direction by moving along track 150 to process and / or index the substrate 140.
[0036] FIG2 is a cross-sectional side view 200 of the system 100 of FIG1 according to some embodiments. As shown, platform 130 includes a plurality of air bearings 202 for lifting platform 130. Platform 130 may also include motor coils (not shown) for moving platform 130 along track 124. Platform 130 and processing device 160 may be enclosed by a housing (not shown) to provide temperature and pressure control.
[0037] System 100 also includes a controller 170. The controller is generally designed to facilitate the control and automation of the processing techniques described herein. The controller is coupled to or communicates with one or more of the processing device 160, platform 130, and encoder 126. The processing device 160 and platform 130 provide the controller with information about substrate processing and substrate alignment. For example, the processing device 160 may provide information to the controller to alert it that substrate processing has been completed. The encoder 126 may provide position information to the controller, which is then used to control the platform 130 and processing device 160.
[0038] The controller may include a central processing unit (CPU) (not shown), memory (not shown), and support circuitry (or I / O) (not shown). The CPU may be any type of computer processor used in industrial environments to control various processes and hardware (e.g., pattern generators, motors, and other hardware) and monitor processes (e.g., processing time and substrate position). The memory is connected to the CPU and may be one or more readily available types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. Software instructions and data may be encoded and stored in the memory to instruct the CPU. Support circuitry (not shown) is also connected to the CPU to support the processor in a conventional manner. Support circuitry may include conventional cache memory, power supply, clock circuitry, input / output circuitry systems, subsystems, etc. A controller-readable program (or computer instructions) determines which tasks are executable on the substrate. The program may be controller-readable software and may include code used to monitor and control, for example, processing time and substrate position.
[0039] FIG3 is a perspective schematic diagram 300 of a plurality of image projection systems 301 according to certain embodiments. As shown in FIG3, each image projection system 301 generates a plurality of write beams 302 corresponding to a plurality of processing positions 312 on the surface 304 of the substrate 140 along a plurality of tracks 310, and each track 310 is scanned by one or more write beams 302. The substrate 140 moves in the in-scan direction indicated by arrow 315, while the cross-scan direction is indicated by arrow 320. As the substrate 140 moves in the in-scan direction and the cross-scan direction, the entire surface 304 can be patterned by the write beams 302. The number of image projection systems 301 may vary based on the size of the substrate 140 and / or the speed of the platform 130. In one embodiment, there are 22 image projection systems 301 in the processing device 160.
[0040] FIG4 is a perspective schematic diagram 400 of one of the plurality of image projection systems 301 of FIG3 according to certain embodiments.
[0041] The image projection system 301 includes a spatial light modulator (SLM) 410 and projection optics 416. The components of the image projection system 301 vary depending on the SLM 410 used. The SLM 410 includes, but is not limited to, arrays of micro-LEDs, VCSELs, liquid crystal displays (LCDs), or any solid-state electromagnetic radiation emitters, as well as digital mirror devices (DMDs). The SLM 410 includes a plurality of spatial light modulator pixels. Each of the plurality of SLM pixels is individually controllable and configured to project a write beam corresponding to one of the pixels (e.g., as shown in Figures 5, 6, 7, and other figures). The aggregation of the plurality of pixels forms a pattern written into a photoresist, referred to herein as a mask pattern. The projection optics 416 includes a projection lens, such as a 10x objective lens, for projecting light onto the substrate 140. In operation, based on the mask pattern data provided to the SLM 410 by the controller 170, each of the plurality of SLM pixels is in an "on" or "off" position. Each SLM pixel in the "on" position forms a write beam, which is then projected onto the photoresist layer surface of the substrate 140 by the projection optics 416 to form the pixel of the mask pattern.
[0042] In one embodiment, the spatial light modulator 410 is a DMD. The image projection system 301 includes a light source 402, an aperture 404, a lens 406, a frustrated prism assembly 408, an SLM 410, and projection optics 416. In this embodiment, the SLM 410 includes a plurality of mirrors, such as the plurality of spatial light modulator pixels. Each of the plurality of mirrors corresponds to a pixel, which may correspond to a pixel of a mask pattern. In some embodiments, the DMD includes more than about 4,000,000 mirrors, while in other embodiments it may include 1920x1080 mirrors, which represents the number of pixels in a high-definition television. The light source 402 is any suitable light source, such as a light-emitting diode (LED) or laser, capable of producing light with a predetermined wavelength. In one embodiment, the predetermined wavelength is in the blue or near-ultraviolet (UV) range, for example, less than about 450 nm. The suppressed prism assembly 408 includes a plurality of reflective surfaces. In operation, a beam 403 is generated by a light source 402. The beam 403 is reflected by the suppressed prism assembly 408 onto the DMD. When the beam 403 reaches the mirrors of the DMD, each mirror in the "on" position reflects the beam 403, forming a write beam, also known as a "shot," which is then projected by projection optics 416 to shoot the photoresist layer surface of the substrate 140. The plurality of write beams 302 (also known as a plurality of shots) form a plurality of pixels of a mask pattern.
[0043] FIG5 is an enlarged perspective view 500 of two pixel elements 502, 504 of an SLM 410 according to certain embodiments. In embodiments where the SLM 410 is a DMD, the pixel elements may be mirrors. As shown, each pixel element 502, 504 is disposed on a tilting mechanism 506 disposed on a memory cell 508. The memory cell 508 may be a CMOS SRAM. During operation, each pixel element 502, 504 is controlled by loading mask data into the memory cell 508. The mask data electrostatically controls the tilt of the pixel elements 502, 504 in a binary manner. When the pixel elements 502, 504 are in reset mode, or when no power is applied, the pixel elements 502, 504 are in a flat position that does not correspond to any binary position. A binary zero (0) may correspond to an "off" position, which means that the pixel element is tilted by -10 degrees, -12 degrees, or any other possible negative direction tilt. The binary 1 (1) can correspond to the "on" position, which means that the pixel element is tilted by +10 degrees, +12 degrees or any other possible positive direction. As shown in Figure 5, pixel element 502 is in the "off" position and pixel element 504 is in the "on" position.
[0044] FIG6 depicts a schematic diagram 600 of the beam 403 reflected by two pixel elements 502, 504 of the SLM 410 of FIG5, according to certain embodiments. As shown, the pixel element 502 in the "off" position reflects the beam 403 generated from the light source 402 toward the light storage device 412. The pixel element 504 in the "on" position forms a write beam 302 by reflecting the beam 403 toward the projection optics 416, which in turn projects the beam 403 onto the substrate 140.
[0045] FIG. 7A depicts a substrate layout design 700A according to certain embodiments. In this context, the layout design can be a layout of design elements to be patterned on substrate 140, developed by a designer, developed in a procedural manner, or a combination of both. Although the illustrated example design shows a single layer, those skilled in the art will understand that typical designs may include more than one layer for patterning on substrate 140. The substrate layout design 700A is provided to system 100 for patterning on substrate 140 and includes various features that are limited only by the design to meet one or more customer requirements. Such features may include one or more design elements 704, which may be interconnects, logic, transistors, vias from other layers, having design connection points 708 for patterning on substrate 140. According to certain embodiments, design connection points 708 may be positioned to connect to another design connection point via pixel model 710, or to package 712, and / or to chip group 716 at chip group connection point 728. Although shown as points, both design connection point 708 and chip group connection point 728 can include both points and lines extending from those points, as discussed below in relation to Figures 10C and 10D. Package 712 includes a collection of one or more chip groups, such as chip group 716 according to some embodiments. Chip group 716 can be a pre-assembled / manufactured element that can be placed on substrate 140 during manufacturing, and in some embodiments can be manufactured separately from design element 704 on substrate 140. According to some embodiments, chip group 716 can include functional elements that provide functionality as part of substrate layout design 700A, and can include functional elements such as memory, processor, application-specific logic, lens array, active quantum dots, color filters, light-focusing sidewall mirrors, and other components for additional functionality. In the illustrated example substrate layout design 700A, driver chiplet 720 and memory chip group 724 are other examples of chip groups according to some embodiments.
[0046] FIG7B depicts a package layout design 700B according to certain embodiments. According to certain embodiments, the package layout design 700B includes a layout design of package 712. In this context, the layout design can be a layout of design elements to be patterned on substrate 140, developed by a designer, developed in a programming manner, or a combination of both.
[0047] FIG7C depicts a chip group layout design 700C according to certain embodiments. The chip group layout design 700C includes a layout design for a chip group 716, namely one or more chip group connection points 728 positioned on the chip group. In this context, the layout design can be a layout of design elements to be patterned on a substrate 140, developed by a designer, developed procedurally, or a combination of both. According to certain embodiments, the chip group layout design 700C includes metadata defining the chip group including the relative positions of one or more chip group connection points 728.
[0048] FIG8 depicts a schematic diagram 800 of a controller 170 according to some embodiments. Although the controller 170 has been described as a unit item, it may also be a single integrated circuit designed to operate according to some embodiments, a processor coupled to one or more memories, a standalone computing system, a group of computing systems coupled together, a distributed computing system, or a combination of these items.
[0049] In addition to the functionality of digital lithography tools for controlling and operating system 100, controller 170 also includes machine learning (ML) model 804. When the chip group layout design 700C is patterned on substrate 140, according to certain embodiments, chip groups 716 may be displaced, as described below in relation to FIG10. As a result, the pixel model 710 of the connection between chip group connection points 728 of the patterned chip group 716 is not at a position relative to design connection point 708 or at a position relative to a connection point of another chip group as specified in substrate layout design 700A. If pixel model 710 is patterned onto substrate 140, proper electrical connections may not be formed between chip group connection points 728 and design connection points 708. According to the disclosed embodiments, the measurement data for the displaced chip groups is detected by scanning substrate 140 with a measurement tool (not shown) or by modeling the chip groups.
[0050] According to the disclosed embodiments, ML model 804 employs a substrate layout design 700A, a chip group layout design 700C, measurement data (e.g., the actual placement of chip groups 716 on substrate 140), and a pixel model 710, and generates a transformed pixel model for patterning on the substrate (discussed below in conjunction with FIG. 10) to make appropriate electrical connections. According to some embodiments, the transformed pixel model is provided to system 100 to optically image the transformed pixel model onto substrate 140. According to some embodiments, ML model 804 is a component of a laser system or process for generating the transformed pixel model. In these embodiments, some or all of the transformed pixel models generated by ML model 804 are utilized. In some embodiments, a modified pixel model is selected by table lookup based on known displacement (e.g., known offset) between components on substrate 140. In these embodiments, table lookup determines the modified pixel model for selection from a library of modified pixel models configured to address known offsets between design elements. In some embodiments, the modified pixel model is combined with the transformed pixel model generated by ML model 804. In some embodiments where the required correction is known, this information is provided to ML model 804 to generate the transformed pixel model. Alternatively, the transformed pixel model generated by ML model 804 may be further modified based on known displacement offsets.
[0051] Because the transformed pixel model provides the correct connection path between the displaced wafer group and the design connection point to address a specific wafer group displacement, according to some embodiments, no additional correction is required. For example, it is not necessary to correct the set of masks to pattern the transformed pixel model, because the transformed pixel model is generated for each specific displacement.
[0052] While the embodiments described herein contemplate generating a transformed pixel model to connect displaced chip groups to design connection points, those skilled in the art will understand that other types of displacement can also be addressed according to other embodiments. For example, if two design connection points on a substrate are not patterned as defined by the substrate design layout due to factors such as vibration, humidity, particulate contamination, SLM skew, etc., the techniques described herein can be advantageously employed to develop a transformed pixel model that addresses such displacement. Furthermore, relative displacement between chip groups can be addressed using the techniques described herein.
[0053] According to some embodiments, the ML model 804 can be a supervised or unsupervised machine learning model. According to some embodiments, the ML model 804 is a classifier, such as a neural network, a deep learning neural network, a k-means classifier, a random forest walk, etc., capable of receiving input, such as measurement data of a substrate (e.g., substrate 140) processed by a digital lithography tool (e.g., system 100), and classifying displacements between components on the substrate. By way of example and not limitation, the ML model 804 can receive a substrate layout design 700A as input, measurement data of one or more displaced elements of the substrate layout design 700A, and a pixel model for connecting displaced elements to another element of the substrate layout design 700A, to classify the displacements, and as a result of the classification, determine a transformed pixel model to resolve the displacements (e.g., generate a path to electrically couple the displaced element to another element).
[0054] Controller 170 receives design data 808 including substrate layout design 700A data, package design 700B data, and chip group design 700C data, and generates digital exposure groups 806. Chip group design data 808 may include or be accompanied by chip group metadata 812, which includes information about the placement of chip group design unit instances on the substrate layout design and connections or connection segments that need to be transformed using ML models. Digital exposure groups 806 are provided to tool 832, which, according to some embodiments, may be a digital lithography tool of system 100 for patterning on substrate 140.
[0055] The ML model 804 receives design data 808 and associated chip group element data 812. The ML model 804 further receives measurement data 816, which is generated by a measurement tool (not shown) measuring the patterned substrate 140 of the substrate layout design 700A, or generated by simulating this measurement.
[0056] The controller further includes an ML training unit 820 for training the ML model 804. The ML training unit 820 may receive historical connection data 824, simulated connection data 828, or both to train the ML model 804. In this context, the historical connection data 824 and the simulated connection data 828 may be pixel models of connections between chip group connection points and design connection points, pixel models of connections between two (or more) design connection points, or pixel models of connections between two (or more) chip group connection points, one of which may connect two points to displacement or otherwise displacement. For historical data, the historical connection data 824 may include historical pixel model data (e.g., measurement data) from previously measured patterned substrates indicated as displaced or shifted. The simulated connection data 828 may include simulated pixel model data, such as paths between connection points simulated as displacement or shifted. According to some embodiments, the ML model 804 is trained offline or at some point before processing with the system 100, while in other embodiments, training may occur while the system 100 is processing the substrate.
[0057] The ML training unit 820 uses historical connection data 824 and / or simulated connection data 828 to train the ML model 804. Once trained, the ML model 804 can receive the data as described above to generate a transformed pixel model for the tool 832, such as the digital lithography tool of the system 100.
[0058] FIG9 depicts a flowchart 900 of a pattern for correcting local displacement by means of ML-based dynamic digital correction according to certain embodiments. At block 904, ML model 804 is trained by ML training unit 820. At block 908, design data and chip group meta data are received by controller 170 of digital lithography tool (e.g., system 100).
[0059] At block 912, chip group 716, including chip group connection point 728, and design connection point 708 of substrate layout design 700A, are patterned onto substrate 140. After these are patterned onto substrate 140, metrological data is developed from a metrological source for the patterned substrate by scanning substrate 140 with a metrological tool and / or by analog metrological measurement. The displacement of chip group 716 relative to the patterned design connection point 708 on the substrate is measured by a metrological source at block 916.
[0060] At block 920, design data, chip group element data, and displacement data are provided to the ML model, which categorizes the paths required for electrically coupling the chip group connection point 728 to the design connection point 708. After categorization, the ML model 804 transforms the pixel model 710 of the substrate layout design 700A into a transformed pixel model for electrical coupling. According to some embodiments, the action of block 920 can be performed in real time during substrate processing.
[0061] At block 924, controller 170 provides a transformed pixel model to the digital lithography tool of system 100 to expose the transformed pixel model to substrate 140. According to some embodiments, the action of block 924 can be performed in real time during substrate processing.
[0062] FIG10A depicts a schematic diagram 1000A of a chip group 716 depicted by a layout design according to certain embodiments.
[0063] FIG10B depicts a schematic diagram 1000B of a displaced chip group 716 connected to a design connection point 708 via a transformed pixel model 1012 according to certain embodiments. As shown, the chip group 716 is displaced (e.g., rotated) in a manner different from that depicted in the substrate layout design. After such displacement is detected by a metrology tool (or simulated metrology), the displacement data is provided to an ML model 804 that has been trained by an ML training unit 820, in addition to other data as described above. The ML model 804 generates a transformed pixel model 1012 to connect the chip group connection point 728 to the design connection point 708.
[0064] FIG10C depicts a schematic diagram 1000C of a chip group 716 depicted by a layout design according to certain embodiments. In the disclosed embodiments, chip group interconnects 1004 may extend from chip group connection points 728, and design point interconnects 1008 may extend from design connection points 708, wherein pixel models 710 complete the connection between chip group interconnects 1004 and design point interconnects 1008.
[0065] FIG10D depicts a schematic diagram 1000D of a displaced chip group 716 connected by a transformed pixel model 1012 and a design connection point 708 according to certain embodiments. In these embodiments, a transformed pixel model 1012 is generated when the chip group 716 is displaced to connect the chip group connection line 1004 and the design point connection line 1008.
[0066] Although displacement is shown as rotation in this example, other types of displacement of the wafer group 716 can also be achieved using the techniques described herein to create and then implement electrical connections between the wafer group connection point 728 and the design connection point 708. In this context, in addition to rotation, displacement can also include lateral, longitudinal, or both movement, as well as dimensional errors. Changes in the dimensions of the wafer group may also cause displacement of the connection point.
[0067] FIG11 depicts a schematic diagram 1100 of a machine learning (ML) model 804 according to certain embodiments. After being trained by the ML training unit 820, the ML model 804 receives design connection points 708, wafer group connection points 728, and connection pixel models 710 from a substrate layout design 700A. The connection pixel models may also be generated from corresponding metadata during this process. In this case, the geometric definition of the connection is first transformed into a pixel model. The ML model 804 uses measurement data 816 to determine the offset (e.g., misalignment, rotation, dimensional error, or other displacement) between the design connection points 708 and the patterned wafer group connection points 728 on the substrate 140. The ML model 804 uses the received data to transform the pixel model 710 into a transformed pixel model 1012, which is provided to the controller 170 so that the digital lithography tools of the system 100 pattern the transformed pixel model 1012 onto the substrate 140 to electrically couple the design connection points 708 to the wafer group connection points 728.
[0068] FIG12 depicts a method 1200 for correcting a pattern of local displacement by means of ML-based dynamic digital correction according to certain embodiments. At block 1204, controller 170 receives a substrate layout design 700A including design connection points 708.
[0069] At block 1208, controller 170 receives chip group layout design 700C including metadata, which defines chip groups including chip group connection points 728.
[0070] At block 1212, the controller generates digital exposure group 806 based on substrate layout design 700A and chip group layout design 700C.
[0071] At block 1216, system 100 patterns substrate 140 with design connection point 708 and places chip group connection point 728 based on digital exposure group 806.
[0072] At block 1220, ML model 804 measures the displacement of chip group connection point 728 relative to design connection point 708.
[0073] At block 1224, ML model 804 determines a transformed pixel model 1012, which includes a connection path from design connection point 708 to chip group connection point 728. According to some embodiments, controller 170 causes system 100 to optically expose the transformed pixel model to the substrate, thereby electrically coupling the chip group connection point to the design connection point. According to some embodiments, the ML model is trained with a plurality of training pixel models, each training pixel model defining a path between the training design connection point and the training chip group connection point of the training substrate design layer.
[0074] FIG13 depicts a processing system 1300 according to some embodiments. According to some embodiments, the processing system 1300 is an example of a controller 170 and can be used in place of the controller 170 described above. FIG13 depicts an example processing system 1300 that can operate the embodiment system described herein to perform the embodiments according to the flowcharts and methods described herein (e.g., the method for correcting patterns of local displacement by dynamic digital correction as described in FIG1-12).
[0075] The processing system 1300 includes a central processing unit (CPU) 1302 connected to a data bus 1316. The CPU 1302 is configured to process computer-executable instructions (e.g., computer-executable instructions stored in memory 1308 or storage 1310) and to cause the processing system 1300 to perform embodiments of the methods described herein (e.g., those described with respect to Figures 1-12) on embodiments of the system described herein. The inclusion of CPU 1302 is to represent a single CPU, multiple CPUs, a single CPU having multiple processing cores, and other forms of processing architecture capable of executing computer-executable instructions.
[0076] The processing system 1300 further includes input / output (I / O) devices 1312 and interfaces 1304, which allow the processing system 1300 to interface with the input / output devices 1312, such as keyboards, displays, mouse devices, pen input, and other devices that allow interaction with the processing system 1300. Note that the processing system 1300 can be connected to external I / O devices (e.g., external display devices) via physical and wireless connections.
[0077] The processing system 1300 further includes a network 1314 interface that enables the processing system to access the external network 1314, thereby accessing external computing devices.
[0078] The processing system 1300 further includes a memory 1308, which in this example includes a receiving unit 1318, a generating unit 1320, a patterning unit 1322, a measuring unit 1324, and a determining unit 1326 for performing the operations described herein, such as those described in conjunction with FIG12.
[0079] Please note that although it is shown as a single memory 1308 in Figure 13 for simplicity, the various states stored in memory 1308 can also be stored in different physical memories, including memories far away from the processing system 1300, but can all be accessed by the CPU 1302 via internal data connections such as bus 1316.
[0080] The storage 1310 further includes substrate layout design data 1328, chip group layout design data 1330, digital exposure group data 1332, displacement data 1334, machine learning (ML) model data 1336, ML training data 1338, pixel model data 1340, and transformed pixel model data 1342 for performing the operations described herein. As will be understood by those skilled in the art, other data and patterns may be included in the storage 1310.
[0081] Similar to memory 1308, for simplicity, a single memory 1310 is depicted in FIG13. However, the various states stored in memory 1310 can also be stored in different physical memory units, all of which can be accessed by CPU 1302 via internal data connections (e.g., bus 1316) or external connections (e.g., network interface 1306). Those skilled in the art will understand that one or more components of processing system 1300 can be located remotely and accessed via network 1314.
[0082] The foregoing description is provided to enable any person skilled in the art to practice the various embodiments described herein. The examples discussed herein do not limit the scope, applicability, or embodiments set forth in the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. For example, the function and arrangement of the discussed elements may be changed without departing from the scope of the disclosure. Various procedures or components may be omitted, substituted, or added as appropriate in the various examples. For example, the described methods may be performed in a different order than that described, and various steps may be added, omitted, or combined. In addition, features described with respect to some examples may be combined in some other examples. For example, any number of the variations set forth herein may be used to implement the apparatus or the method. Furthermore, the scope of this disclosure is intended to cover an apparatus or method implemented using various variations of the disclosure set forth herein or other structures, functionalities, or structures and functionalities other than those variations. It should be understood that any variation of the disclosure disclosed herein may be implemented by one or more elements of the claims.
[0083] As used herein, the term "exemplary" means "serving as an example, instance or illustration". Any state described herein as "exemplary" is not necessarily to be construed as being more preferred or advantageous than other states.
[0084] As used herein, the phrase “at least one of” in a list of items refers to any combination of those items, including a single member. For example, “at least one of the following items: a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination of multiple of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).
[0085] As used herein, the term "decision" encompasses a wide variety of actions. For example, "decision" can include calculating, computed, processed, deduced, investigated, searched (e.g., searching in a table, database, or another data structure), and ascertained. Additionally, "decision" can also include receiving (e.g., receiving information) and accessing (e.g., accessing data in memory). Furthermore, "decision" can also include parsing, selecting, choosing, and establishing.
[0086] The methods disclosed herein include one or more operations or actions for implementing such methods. Without departing from the scope of the claims, the operations and / or actions of the methods may be interchanged with each other. In other words, unless a specific order of operations or actions is specified, the order and / or use of specific operations and / or actions may be modified without departing from the scope of the claims. Furthermore, the various operations of the above methods can be performed by any suitable means capable of performing the corresponding functions. Such means may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, if operations are shown in the diagrams, those operations may have corresponding means-plus-function components with similar numbering.
[0087] The following claims are not intended to be limited to the embodiments shown herein, but are intended to be given the full scope consistent with the language of the claims. Within the claims, unless specifically stated otherwise, reference to an element in the singular is not intended to mean "one and only one," but rather "one or more." Unless specifically stated otherwise, the term "some" refers to one or more. An element shall not be construed under 35 USC §112(f) unless it is explicitly described using the phrase "means for..." or, in the case of a method claim, "steps for...". All structural and functional equivalents of the various forms of elements described throughout this disclosure that are known or subsequently known to a person skilled in the art are incorporated herein by reference and are intended to be included in the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly stated in the claims. [Simplified Explanation of the Diagram]
[0009] In order to understand the above features of this disclosure in detail, a more detailed description of this disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate exemplary embodiments and should not be regarded as limiting the scope of such embodiments, and other equally effective embodiments are acceptable.
[0010] Figure 1 is a perspective view of a system that may benefit from certain embodiments.
[0011] FIG2 is a cross-sectional side view of the system of FIG1 according to certain embodiments.
[0012] Figure 3 is a perspective view of a plurality of image projection systems according to certain embodiments.
[0013] Figure 4 is a perspective view of one of the plurality of image projection systems in Figure 3 according to certain embodiments.
[0014] Figure 5 is an enlarged perspective view of two pixel elements of an SLM according to certain embodiments.
[0015] FIG6 depicts a schematic diagram of a beam reflected by two pixel elements of the SLM of FIG5 according to certain embodiments.
[0016] FIG7A depicts a substrate layout design according to certain embodiments.
[0017] Figure 7B depicts a package layout design according to certain embodiments.
[0018] Figure 7C depicts a chip group layout design according to certain embodiments.
[0019] Figure 8 depicts a schematic diagram of a controller according to certain embodiments.
[0020] Figure 9 depicts a flowchart of a pattern for correcting local displacement by means of ML-based dynamic digital correction according to certain embodiments.
[0021] FIG10A depicts a schematic diagram of a chip group depicted by a layout design according to certain embodiments.
[0022] FIG10B depicts a schematic diagram of a group of displacement chips connected by a transformed pixel model and a design connection point according to certain embodiments.
[0023] FIG10C depicts a schematic diagram of a chip group depicted by a layout design according to certain embodiments.
[0024] FIG10D depicts a schematic diagram of a group of displacement chips connected by a transformed pixel model and a design connection point according to certain embodiments.
[0025] Figure 11 illustrates a schematic diagram of a machine learning (ML) model according to certain embodiments.
[0026] Figure 12 depicts a method for correcting patterns of local displacement by means of ML-based dynamic digital correction, according to certain embodiments.
[0027] FIG13 depicts a processing system according to certain embodiments.
[0028] For ease of understanding, the same reference numerals are used where possible to indicate common elements in the figures. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. [Biomaterial Storage]
[0089] Domestic Deposit Information (Please note in order of deposit institution, date, and number) None
[0090] Overseas Deposit Information (Please note in the order of deposit country, institution, date, and number) None
Claims
1. A system comprising: A memory module containing computer-readable instructions; And a processor configured to read computer-readable instructions that cause the processor to: receive a substrate layout design including a design connection point; receive a chip group layout design including metadata defining a chip group including a chip group connection point; generate a digital exposure group based on the substrate layout design and the chip group layout design; pattern a substrate using the design connection point and place the chip group connection point based on the digital exposure group; measure a displacement of the chip group connection point relative to the design connection point; and determine a transformed pixel model using a trained machine learning (ML) model, the transformed pixel model including a connection path from the design connection point to the chip group connection point.
2. The system of claim 1, wherein the computer-readable instructions further cause the processor to optically expose the transformed pixel model to the substrate, thereby electrically coupling the chip group connection point to the design connection point.
3. The system of claim 2, wherein the computer-readable instructions further cause the processor to: operate an ML model; and train the ML model with a plurality of training pixel models, each training pixel model defining a path between a training design connection point of a training substrate design layer and a training chip group connection point.
4. The system as claimed in claim 3, wherein the plurality of trained pixel models are based on one or more of historical pixel model data or simulated pixel model data.
5. The system as claimed in claim 4, wherein the ML model includes one of a supervised or unsupervised ML model configured as a classification ML model.
6. The system of claim 1, wherein the computer-readable instructions further cause the processor, based on the substrate layout design, to determine whether the measured displacement of the chip group connection point relative to the designed connection point differs from a placement of the chip group connection.
7. The system as claimed in claim 6, wherein measuring a displacement of the wafer group includes measuring the placement of the wafer group using a metering tool or a simulation.
8. A computer program product, comprising: A non-transitory computer-readable storage medium having computer-readable code implemented thereon, the computer-readable code being executable by one or more processors to: receive a substrate layout design including a design connection point; receive a chip group layout design including metadata defining a chip group including a chip group connection point; generate a digital exposure group based on the substrate layout design and the chip group layout design; pattern a substrate using the design connection point and place the chip group based on the digital exposure group; measure a displacement of the chip group connection point relative to the design connection point; and determine a transformed pixel model using a trained machine learning (ML) model, the transformed pixel model including a connection path from the design connection point to the chip group connection point.
9. The computer program product as claimed in claim 8, wherein the program code further enables the processor to optically expose the transformed pixel model to the substrate, thereby electrically coupling the chip group connection point to the design connection point.
10. The computer program product as claimed in claim 9, wherein the program code further enables the processor to: operate an ML model; and train the ML model with a plurality of training pixel models, each training pixel model defining a path between a training design connection point of a training substrate design layer and a training chip group connection point.
11. The computer program product as claimed in claim 10, wherein the plurality of pixel models are based on one or more of historical pixel model data or simulated pixel model data.
12. The computer program product as claimed in claim 11, wherein the ML model includes one of a supervised or unsupervised ML model configured as a classification ML model.
13. The computer program product as claimed in claim 8, wherein the program code causes the processor, based on the substrate layout design, to determine that the measured displacement of the chip group connection point relative to the designed connection point is different from a placement of the chip group connection.
14. The computer program product as claimed in claim 13, wherein measuring a displacement of the chip group includes measuring the placement of the chip group using a measuring tool or a simulation.
15. A method comprising the steps of: receiving a substrate layout design including a design connection point; receiving a chip group layout design including metadata defining a chip group including a chip group connection point; generating a digital exposure group based on the substrate layout design and the chip group layout design; patterning a substrate with the design connection point and placing the chip group based on the digital exposure group; measuring a displacement of the chip group connection point relative to the design connection point; and determining a transformed pixel model using a trained machine learning (ML) model, the transformed pixel model including a connection path from the design connection point to the chip group connection point.
16. The method of claim 15 further includes the step of: optically exposing the transformed pixel model to the substrate, thereby electrically coupling the wafer group connection point to the design connection point.
17. The method of claim 16 further includes the steps of: operating an ML model; and training the ML model with a plurality of training pixel models, each training pixel model defining a path between a training design connection point of a substrate design layer and a training chip group connection point.
18. The method of claim 17, wherein the plurality of pixel models are based on one or more of historical pixel model data or simulated pixel model data.
19. The method of claim 18, wherein the ML model includes one of a supervised or unsupervised ML model configured as a classification ML model.
20. The method of claim 15 further includes the step of: determining, based on the substrate layout design, that the measured displacement of the wafer group connection point relative to the designed connection point is different from a placement of the wafer group connection.