Method of forming semiconductor structure, semiconductor processing system, and semiconductor device
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-06-28
- Publication Date
- 2023-04-16
Smart Images
Figure TWG2TA000904745_001 
Figure TWG2TA000904745_002 
Figure TWG2TA000904745_003
Abstract
Description
[Technical Field]
[0001] This disclosure generally relates to the formation of structures. More specifically, this disclosure relates to the formation of structures of cover substrates using trench bottom-up filling techniques, such as during the manufacture of semiconductor devices. [Previous Technology]
[0002] Films are typically deposited on substrates to form various types of structures during the fabrication of various types of semiconductor devices, such as display devices, power electronic components, and very large-scale integrated circuits. The deposition of such films is generally accomplished by positioning the substrate within a reactor, heating the substrate to a temperature suitable for depositing the desired film onto the substrate, and allowing a gas containing the components of the desired film to flow into the reactor. As the gas flows through the reactor and across the substrate, the components form a film on the substrate (typically at a rate) to a thickness corresponding to the environmental conditions within the reactor and the temperature of the substrate. The resulting film is generally conformal to the underlying substrate, and the film is typically deposited on the substrate topology in a manner corresponding to the substrate topology.
[0003] During the manufacture of some semiconductor devices, it may be necessary to deposit films into trenches, which are defined within the surface of a substrate. For example, during the manufacture of transistor devices with a two-dimensional or three-dimensional architecture, a filling structure, such as an isolation feature for electrically separating adjacent transistors, can be formed within the trench by depositing a film with desired electrical properties within the trench. Such filling features can be formed using epitaxial technology, whereby the filling features are produced by progressively thickening the film (from the bottom of the trench upwards and laterally inwards from the opposite sidewalls of the trench). Film deposition typically continues until the trench is closed – either by bridging the film covering the bottom of the trench with the film covering the sidewalls and extending beyond the trench opening, or by the surfaces of the films covering the sidewalls agglomerating against each other within the trench.
[0004] In some filled structures, the interface (or seam) at the polymerization of the opposing surfaces of the sidewall films and / or the bottom surface films can affect the electrical properties of the resulting filled structure. For example, in a substrate where the crystalline structure at the bottom of the trench differs from that at the sidewalls, the film deposited on the bottom surface of the trench can form a crystalline structure different from that deposited on the sidewalls. Therefore, the crystalline structure within the filled structure can be altered at the interface between opposing surfaces within the filled structure, locally increasing (or decreasing) the resistivity at the interface relative to the rest of the filled structure. While generally manageable, localized variations in electrical properties at the interface can affect the reliability of semiconductor devices containing filled structures in some semiconductor devices.
[0005] Such systems and methods are generally considered suitable for their intended use. However, there is still a need in the art for improved methods of forming structures using bottom-up fill technology, semiconductor processing systems configured to use structures formed using bottom-up fill technology, and semiconductor devices including structures formed using bottom-up fill technology. This disclosure provides a solution to this need. [Summary of the Invention]
[0006] A method for forming a structure is provided. The method includes supporting a substrate in a reaction chamber of a semiconductor processing system, the substrate having a recess, the recess having a bottom surface and a sidewall surface extending upward from the bottom surface of the recess. Depositing a film within the recess and onto the bottom surface and sidewall surface of the recess, the film having a bottom segment and a sidewall segment, the bottom segment covering the bottom surface of the recess, and the sidewall segment deposited on the sidewall surface of the recess. Removing the sidewall segment of the film while retaining at least a portion of the bottom segment of the film within the recess, and removing the sidewall segment of the film from the sidewall surface more rapidly than removing the bottom segment of the film from the bottom surface of the recess.
[0007] In addition to one or more of the features described above, or as an alternative, further examples of the method may include depositing the bottom section of the film onto the bottom surface more rapidly than the sidewall section of the deposited film onto the sidewall surface of the groove.
[0008] In addition to one or more of the features described above, or as an alternative, further examples of the method may include removing the sidewall and bottom sections of the membrane at a removal rate ratio between 5:1 and 25:1.
[0009] In addition to one or more of the features described above, or as an alternative, further examples of the method may include depositing a bottom section and a sidewall section of a film at a deposition rate ratio between 1.1:1 and 2:1.
[0010] In addition to one or more of the features described above, or as an alternative, further examples of the method may include removing the sidewall and bottom sections of the membrane under a predetermined removal pressure between about 1 Torr and about 50 Torr.
[0011] In addition to one or more of the features described above, or as an alternative, further examples of the method may include removing the sidewall and bottom sections of the membrane at a predetermined removal temperature between about 675 °C and about 800 °C.
[0012] In addition to one or more of the features described above, or as an alternative, further examples of the method may include depositing a sidewall section and a bottom section of a film at a predetermined deposition pressure between about 1 Torr and about 50 Torr.
[0013] In addition to one or more of the features described above, or as an alternative, further examples of the method may include depositing the sidewall and bottom sections of the film at a predetermined deposition temperature between about 675 °C and about 800 °C.
[0014] In addition to one or more of the features described above, or as an alternative, further examples of the method may include the deposition and removal of the sidewall and bottom sections of the membrane under a common pressure, wherein the sidewall and bottom sections of the membrane are deposited and removed at a common temperature.
[0015] In addition to one or more of the features described above, or as an alternative, further examples of the method may include flowing dichlorosilane (DCS), hydrochloric acid (HCl) and hydrogen (H2) gas through the interior of one of the reaction chambers to deposit the sidewall and bottom sections of the membrane into the groove.
[0016] In addition to one or more of the features described above, or as an alternative, further examples of the method may include flowing hydrochloric acid (HCl) and hydrogen (H2) gas through the interior of one of the reaction chambers to remove a portion of the sidewall section and the bottom section of the membrane from within the recess.
[0017] In addition to one or more of the features described above, or as an alternative, a further example of the method may include a bottom surface of the groove having a silicon 100 crystalline structure and a sidewall surface of the groove having a silicon 110 crystalline structure.
[0018] In addition to one or more of the features described above, or as an alternative, further examples of the method may include a deposition operation and a removal operation forming a first deposition / removal cycle, and the method further includes one or more second deposition / removal cycles.
[0019] In addition to one or more of the features described above, or as an alternative, a further example of the method may include filling the groove from bottom to top from the bottom surface of the groove to one of the openings into the groove.
[0020] In addition to one or more of the features described above, or as an alternative, a further example of the method may include exposing the sidewall surface above a reserved portion of one of the bottom sections of the membrane from the groove.
[0021] The present invention provides a semiconductor processing system. The semiconductor processing system includes a reaction chamber, a gas delivery system connected to the reaction chamber, and a controller. The controller is operatively connected to the gas delivery system and the reaction chamber, and responds to instructions recorded on a non-transitory machine-readable memory to support a substrate in the reaction chamber, wherein the substrate has a recess, the recess has a bottom surface and a sidewall surface, the sidewall surface extending upward from the bottom surface of the recess; depositing a film in the recess and onto the bottom surface and sidewall surface of the recess, the film having a bottom section and a sidewall section, the bottom section covering the bottom surface of the recess, and the sidewall section deposited on the sidewall surface of the recess; and removing the sidewall section of the film while retaining at least a portion of the bottom section of the film in the recess, removing the sidewall section of the film from the sidewall surface of the recess faster than removing the bottom section of the film from the bottom surface of the recess.
[0022] In addition to one or more of the features described above, or as an alternative, further examples of the system may include instructions to cause the controller to perform the following steps: flow hydrochloric acid (HCl) and hydrogen (H2) gas through the interior of one of the reaction chambers to remove a portion of the sidewall section and the bottom section of the membrane from the groove; flow dichlorosilane (DCS), hydrochloric acid (HCl) and hydrogen (H2) gas through the interior of the reaction chamber to deposit the sidewall section and the bottom section of the membrane into the groove; and deposit the bottom section of the membrane onto the bottom surface of the groove more rapidly than the sidewall section of the membrane is deposited on the sidewall surface of the groove.
[0023] In addition to one or more of the features described above, or as an alternative, a further example of the system may include instructions to cause the controller to perform the following steps: depositing the bottom section and sidewall section of the membrane at a deposition rate ratio between about 1.1:1 and about 2:1; and removing the bottom section and sidewall section of the membrane at a removal rate ratio between about 5:1 and about 25:1.
[0024] In addition to one or more of the features described above, or as an alternative, further examples of the system may include instructions to cause the controller to perform the following steps: depositing a sidewall section and a bottom section of the membrane at a predetermined deposition pressure between about 1 Torr and about 50 Torr; depositing a sidewall section and a bottom section of the membrane at a predetermined deposition temperature between about 675 °C and 800 °C; removing a portion of the sidewall section and the bottom section of the membrane at a predetermined deposition pressure between about 1 Torr and about 50 Torr; and removing a portion of the sidewall section and the bottom section of the membrane at a predetermined deposition temperature between about 675 °C and about 850 °C.
[0025] A semiconductor device structure is provided. The semiconductor device structure includes a finned FET or a gate-all-around transistor having a structure formed using the method described above.
[0026] This invention is intended to introduce selected concepts in a simplified form. These concepts will be described in more detail in the embodiments disclosed below. This invention is not intended to identify the essential or necessary features of the claimed substance, nor is it intended to limit the scope of the claimed substance.
Implementation Method
[0028] Referring now to the figures, similar reference numerals denote similar structural features or configurations of the invention. For purposes of explanation and illustration, and not for limitation, FIG1 is a partial view showing an example of a semiconductor processing system according to the present disclosure, and is generally indicated by reference numeral 100. Other examples, or configurations, of the semiconductor processing system, the method of forming the structure, and the structure formed using the bottom-up fill technique according to the present disclosure are provided in FIGS. 2 through 14, as will be described. The systems and methods of the present disclosure can be used to form semiconductor devices, such as three-dimensional transistor devices having a fin FET or a gate-all-around architecture, but the present disclosure is generally not limited to any particular architecture or semiconductor device.
[0029] Referring to FIG1, a semiconductor processing system 100 is shown. The semiconductor processing system 100 includes a reaction chamber 102 having an injection manifold 104 and an exhaust manifold 106. The semiconductor processing system also includes a process assembly 108 having an outer ring 110, a base 112, a base support member 114, and a shaft 116. The semiconductor processing system 100 further includes a gas delivery configuration 118 having a first precursor source 120, a second precursor source 122, a halide source 124, and a purging / carrier gas source 126. The semiconductor processing system 100 further includes a controller 128. Although the specific type of reaction chamber shown in FIG1 and described herein is, for example, a cross-flow reaction chamber, it should be understood and appreciated that semiconductor processing systems having other types of reaction chambers (such as downflow reaction chambers) may also benefit from this disclosure.
[0030] The reaction chamber 102 has a hollow interior 130 extending between the injection end 132 and the exhaust end 134 of the reaction chamber 102, and is formed of a transmissive material 136. The transmissive material 136 may include a glass material, such as quartz. One or more heater elements 138 may be disposed outside the reaction chamber 102. The one or more heater elements 138 may be configured to transfer heat H to the interior 130 of the reaction chamber 102 via the transmissive material 136 forming the reaction chamber 102, in such instances the transmissive material 136 radially couples the interior 130 of the reaction chamber 102 to the one or more heater elements 138. The one or more heater elements 138 are also operatively associated with a controller 128.
[0031] The exhaust manifold 106 is connected to the exhaust end 134 of the reaction chamber 102 and is configured to connect the interior 130 of the reaction to an exhaust source, such as a scrubber. In some embodiments, the exhaust end 134 of the reaction chamber 102 may have an exhaust flange extending around it, in which case the exhaust manifold 106 is connected to the exhaust flange. The injection manifold 104 is connected to the injection end 132 of the reaction chamber 102. It is conceivable that the injection manifold 104 connects the gas delivery configuration 118 to the reaction chamber 102. In this respect, in the illustrated embodiment, the injection manifold 104 connects each of the first precursor source 120, the second precursor source 122, the halide source 124, and the rinsing / carrier gas source 126 to the reaction chamber 102. In some embodiments, the injection end 132 of the reaction chamber 102 may have an injection flange extending around it, and the injection manifold 104 may be connected to the injection flange. The reaction chamber 102 is shown and described as in U.S. Patent Application Publication No. 2018 / 0363139 A1 filed April 25, 2018, by Rajavelu et al., the contents of which are incorporated herein by reference in their entirety.
[0032] A first precursor source 120 is connected to an injection manifold 104 via a precursor conduit 140 and is configured to provide a first precursor 142 to a reaction chamber 102. In some instances, the first precursor 142 may include a silicon-containing precursor, such as a hydrogenated silicon-containing precursor and / or a chlorinated silicon-containing precursor. Examples of suitable chlorinated silicon-containing precursors include monochlorosilane (MCS), dichlorosilane (DCS), trichlorosilane (TCS), hexachlorodisilazane (HCDS), octachlorotrisilane (OCS), and silicon tetrachloride (STC). Examples of suitable hydrogenated silicon-containing precursors include silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H10). It is conceivable that a first precursor mass flow controller (MFC) 144 connects a first precursor source 120 to a precursor conduit 140. The first precursor MFC 144 is operatively associated with a controller 128 to flow the first precursor 142 to an injection manifold 104 and through it into the interior 130 of the reaction chamber 102.
[0033] The second precursor source 122 is also connected to the injection manifold 104 via the precursor conduit 140 and configured to provide the second precursor 146 to the reaction chamber 102. In some embodiments, the second precursor 146 may include a germanium-containing precursor. Examples of suitable germanium-containing precursors include germanane (GeH4), digermanane (Ge2H6), trigermanane (Ge3H8), and germanium-based silane (GeH6Si). According to some embodiments, the second precursor 146 may include an n-type or p-type dopant. Examples of suitable n-type dopant include phosphorus (P) and arsenic (As). Examples of suitable p-type dopant include boron (B), gallium (Ga), and indium (In). It is contemplated that the second precursor MFC 148 connects the second precursor source 122 to the precursor conduit 140. The second precursor MFC 148 is operatively associated with the controller 128 to control the flow of the second precursor 146 to the injection manifold 104 and through it into the interior 130 of the reaction chamber 102.
[0034] In the illustrated example, halide source 124 is connected to injection manifold 104 via precursor conduit 140 and halide conduit 150, and is configured to supply halide 152 to reaction chamber 102. Halide 152 may include fluorine (F) or chlorine (Cl), for example, by supplying hydrochloric acid (HCl) to reaction chamber 102. It is conceivable that a first halide MFC 154 connects halide source 124 to precursor conduit 140 and through it to reaction chamber 102 via injection manifold 104, and a second halide MFC 156 also connects halide source 124 to halide conduit 150 and through it to reaction chamber 102 via injection manifold 104. The first halide MFC 154 and the second halide MFC 156 are sequentially operably associated with the controller 128 to control the flow of halide 152 through one (or both) of the precursor conduit 140 and the halide conduit 150, respectively. As will be understood by those skilled in the art upon viewing this disclosure, this allows the halide source 124 to flow halide 152 into the reaction chamber 102 together with and / or independently of the first precursor 142 and / or the second precursor 146.
[0035] The flushing / carrier gas source 126 is connected to the injection manifold 104 via the precursor conduit 140 and the halide conduit 150, and is configured to provide flushing / carrier gas 158 to the reaction chamber 102. Examples of suitable flushing / carrier gases include hydrogen (H2), nitrogen (N2), helium (He), krypton (Kr), argon (Ar), and mixtures thereof. It is conceivable that a first flushing / carrier gas MFC 160 connects the flushing / carrier gas source 126 to the precursor conduit 140 and through it to the reaction chamber 102 via the injection manifold 104, and a second flushing / carrier gas MFC 162 further connects the flushing / carrier gas source 126 to the halide conduit 150 and through it to the reaction chamber 102 via the injection manifold 104. The first flushing / carrier gas MFC 160 and the second flushing / carrier gas MFC 162 are sequentially operably associated with the controller 128 to control the flow of flushing / carrier gas 158 into the reaction chamber 102. As will be appreciated by those skilled in the art upon viewing this disclosure, this allows flushing / carrier gas 158 to be supplied to the reaction chamber 102 via either (or both) the precursor conduit 140 and the halide conduit 150. In some instances, the gas delivery configuration 118 may be shown and described as in U.S. Patent Application Publication No. 2020 / 00404458 A1, filed August 6, 2018, the contents of which are incorporated herein by reference in their entirety. However, as will be appreciated by those skilled in the art upon viewing this disclosure, gas delivery configurations using one or more manually operated flow control valves may also be used, and are still within the scope of this disclosure.
[0036] The outer ring 110 is fixed within the interior 130 of the reaction chamber 102. The outer ring 110 may be formed of an opaque material 164 to receive heat H from one or more heater elements 138. Examples of suitable opaque materials include silicon carbide-coated graphite. It is conceivable that the outer ring 110 has pores therein, the pores being configured to receive a base 112 therein, the base 112 being circumferentially spaced from the outer ring 110 by gaps.
[0037] The base 112 is disposed within the interior 130 and outer ring 110 of the reaction chamber 102, and is configured to support the substrate 302 thereon during the formation of structure 300 in the groove 308 (shown in FIG. 5) of the covering substrate 302. In this regard, it is conceivable that the outer ring 110 extends circumferentially around the base 112, and the base 112 is also formed of an opaque material 164 to receive heat H transmitted by one or more heater elements 138, for example, directly or indirectly from the outer ring 110. It is conceivable that the base 112 is further disposed along a rotation axis 166 and rotatably fixed to a base support member 114 about the rotation axis 166. The base support member 114 then couples the base 112 to the axis 116 and is rotatably fixed relative to the axis 116 about the rotation axis 166. Shaft 116 is supported by rotation R about rotation axis 166 and is operatively associated with drive module 168 to rotate substrate 302 within interior 130 of reaction chamber 102 about rotation axis 166 during formation of structure 300 within recess 308 of cover substrate 302. Drive module 168 is then operatively associated with controller 128.
[0038] The controller 128 includes a processor 170, a device interface 172, a user interface 174, and memory 176. The device interface 172 operatively associates the controller 128 with the semiconductor processing system 100, for example, via wired or wireless connection to one or more heater elements 138, one or more MFCs of the semiconductor processing system 100 (e.g., first precursor MFC 144, second precursor MFC 148, first halide MFC 154 and second halide MFC 156, and first flushing / carrier gas MFC 160 and second flushing / carrier gas MFC 162), and drive modules 168. The processor 170 is also operatively connected to the user interface 174, which may include a display and / or user input device, and is configured to communicate with the memory 176. The memory 176 has a plurality of program modules 178 recorded thereon, which, when read by the processor 170, cause the processor 170 to perform certain operations. Among these operations is the operation of method 200 (shown in Figures 2 and 3) for forming a structure (e.g., structure 300 (shown in FIG. 10)) covering the substrate supported on the base 112.
[0039] Referring to Figures 2 to 4, method 200 is shown. As shown in block 210, method 200 begins by supporting a substrate (e.g., substrate 302 (shown in Figure 1)) in a reaction chamber of a semiconductor processing system, e.g., reaction chamber 102 (shown in Figure 1) of semiconductor processing system 100 (shown in Figure 1). It is conceivable that the substrate has a recess covering the substrate, e.g., recess 308 (shown in Figure 5). It is also conceivable that the recess has a bottom surface and sidewall surfaces, e.g., bottom surface 316 (shown in Figure 5) and sidewall surface 318 (shown in Figure 5). It is further conceivable that the bottom surface has a silicon 100 crystal structure, e.g., silicon 100 crystal structure 320 (shown in Figure 5), and the sidewall surfaces have a silicon 110 crystal structure, e.g., silicon 110 crystal structure 322 (shown in Figure 5).
[0040] As shown in block 220, a film system, such as film 328 (shown in FIG. 6), is deposited within a groove covering the substrate. In some instances, as shown in block 222, the bottom section of the film can be deposited onto the bottom surface of the groove more quickly than the sidewall sections can be deposited onto the sidewall surfaces of the groove. Those skilled in the art who have viewed this disclosure will understand that depositing the bottom section onto the bottom surface more quickly than the sidewall sections can reduce the cycle time required to fill the groove and increase the yield of the semiconductor processing system used to form the structure.
[0041] Referring to FIG3, the deposition of a film (block 220) within a groove may only include partially filling the groove. In this respect, a film may be deposited such that the groove is partially filled with the bottom segment and the sidewall segment of the film, as shown in blocks 224 and 226. It is conceivable that the bottom segment and the sidewall segment are deposited at a bottom segment deposition rate to the sidewall segment deposition rate ratio (i.e., deposition rate ratio). In some instances, the deposition rate ratio may be between about 1.1:1 and about 2:1. It is also conceivable that the bottom segment of the film has a different crystalline structure than the crystalline structure of the sidewall segment of the film. For example, according to some embodiments, the bottom segment of the film may have a 100 crystalline structure, and the sidewall segment of the film may have a 110 crystalline structure, as shown in block 221.
[0042] As shown in block 223, the deposition (block 220) of the membrane may include allowing dichlorosilane (DCS), hydrochloric acid (HCl), and hydrogen (H2) gases to flow into the interior of the reaction chamber, for example, using gas delivery configuration 118 (shown in FIG. 1). In some instances, as shown in block 225, a predetermined deposition pressure may be maintained within the reaction chamber during membrane deposition within the groove. It is conceivable that the predetermined deposition pressure may be between about 1 Torr and about 50 Torr during the deposition (block 220) operation, also as shown in block 225. For example, during the deposition operation, the pressure inside the reaction chamber may be maintained below about 50 Torr, or below about 40 Torr, or below about 30 Torr, or below about 20 Torr, or even below about 10 Torr, as shown in block 225. The predetermined deposition pressure may be about 1 Torr.
[0043] As shown in block 227, a predetermined deposition temperature can be maintained inside the reaction chamber during the deposition (block 220) operation. During the deposition (block 220) operation, the predetermined deposition temperature can be between approximately 675°C and approximately 850°C, also as shown in block 227. For example, during the deposition (block 220) operation, the predetermined deposition temperature can be less than approximately 850°C, or less than 800°C, or less than approximately 750°C, or even less than approximately 675°C, also as shown in block 227. Advantageously, in examples where the bottom surface of the groove has a silicon 100 crystalline structure and the lower surface of the groove has a silicon 110 crystalline structure, the flow of dichlorosilane (DCS), hydrochloric acid (HCl) and hydrogen (H2) gas within these pressure and temperature ranges allows the bottom section of the film to be deposited onto the bottom surface of the groove more rapidly than the sidewall section of the deposited film on the sidewall surface of the groove, as shown in Figure A of Figure 11 and Figure B of Figure 12.
[0044] Continuing with Figure 2, once the film is deposited within the trench, the sidewall segments of the film are subsequently removed from the sidewall surface of the trench, while at least a portion of the bottom segment of the film remains within the trench, as shown in block 230. In some instances, the sidewall segments of the film can be removed from the sidewall surface of the trench more quickly than the bottom segment of the film can be removed from the bottom surface of the trench. Those skilled in the art who have viewed this disclosure will understand that removing the sidewall segments of the film from the sidewall surface of the trench more quickly than the bottom segment of the trench can also reduce the cycle time required to fill the trench and increase the yield of the semiconductor processing system used to form the structure.
[0045] Referring to Figure 4, removing the sidewall section of the membrane (block 230) while retaining at least a portion of the bottom section of the membrane may include allowing hydrochloric acid (HCl) and hydrogen (H2) gas to flow into the interior of the reaction chamber, as shown in block 234. According to some examples, removing the sidewall section (block 230) while retaining at least a portion of the bottom section of the membrane within the groove may include completely removing the sidewall section of the membrane from the sidewall surface of the groove, as shown in block 236. In examples where the bottom surface of the groove has a silicon 100 crystalline structure and the sidewall surface of the groove has a silicon 110 crystalline structure, substantially all of the membrane having the 110 crystalline structure can be removed from the groove, and a portion of the membrane having the 100 crystalline structure remains within the groove, as shown in blocks 238 and 231.
[0046] In some instances, removing (block 230) the sidewall section of the membrane while retaining at least a portion of the bottom section may include maintaining a predetermined removal pressure within the reaction chamber, as shown in block 233. During the removal operation, the pressure within the reaction chamber may be maintained between about 1 Torr and about 50 Torr, also as shown in block 233. For example, as shown in block 235, the pressure within the reaction chamber may be maintained at less than about 50 Torr, or less than about 40 Torr, or less than about 30 Torr, or less than about 20 Torr, or even less than about 10 Torr. Advantageously, pressures within this range allow the sidewall section of the membrane to be removed more rapidly than the bottom section of the membrane, as shown in graph C of Figure 13. Furthermore, the removal rate ratio increases exponentially with decreasing pressure, for example, at a pressure of about 2 Torr, providing unexpected advantages in terms of cycle time and yield. In this regard, the removal operation may include removing the film at a removal rate ratio greater than about 5:1, or greater than about 10:1, or greater than about 15:1, or even greater than about 20:1, as shown in block 237. The removal rate ratio may be between about 5:1 and about 25:1, also as shown in block 237. As shown in block 235, the deposition and removal operations may be performed under a common deposition pressure and removal pressure, in which respects, the deposition and removal operations are isobaric.
[0047] In some instances, removing the sidewall section of the membrane while retaining at least a portion of the bottom section may include maintaining a predetermined removal temperature within the interior of the reaction chamber, as shown in block 239. For example, the temperature within the interior of the reaction chamber may be maintained below about 850 °C, or below about 800 °C, or below about 750 °C, or even below about 675 °C, also as shown in block 239. During the removal operation, the temperature within the interior of the reaction chamber may be maintained between about 850 °C and about 675 °C, as further shown in block 239. Advantageously, the temperature within this range may further increase the removal rate ratio during the removal operation, as shown in graph D of FIG14. As shown in block 290, the deposition and removal operations may be performed at a common deposition and removal temperature, in which respects, the deposition and removal operations are isothermal. It is noteworthy that, as shown in graph B of FIG12, the deposition rate ratio is less sensitive to temperature, and therefore the deposition temperature can be selected within this temperature range according to the desired removal rate ratio.
[0048] Referring again to FIG2, the deposition and removal operations may be a first deposition / removal cycle for depositing a first retained portion of a film within the groove, for example, the first retained portion 336 (shown in FIG7), and the method may include one or more second deposition / removal cycles, as indicated by arrow 240. It is conceivable that at least one second deposition / removal cycle is used to deposit at least one second retained portion within the groove and cover the first retained portion, for example, the second retained portion 344 (shown in FIG9), the first retained portion and the second retained portion forming part of the structure formed using method 200, also as indicated by arrow 240.
[0049] As shown in block 250, method 200 may include filling a groove. In this respect, the groove may be filled from bottom to top, i.e., without incorporating the film deposited on the sidewalls of the groove into the retained portion forming the structure, as shown in block 252. The filling may be completed in a planarization operation, during which a planarized film is deposited on at least one second retained portion, as shown in block 254. It is conceivable that each of the retained portions has a homogeneous 100 crystal structure, and the structure as a whole has a homogeneous 100 crystal structure, i.e., without any internal polymeric surfaces and / or portions formed with a 110 crystal structure, as shown in block 256. Those skilled in the art who have viewed this disclosure will understand that a homogeneous 100 crystal structure limits variations in the electrical properties of the structure, improving the reliability of semiconductor devices including those with structures formed using the method.
[0050] In some embodiments, the semiconductor device, such as semiconductor device 400 (shown in FIG. 10), may be formed as a substrate covering the structure, as shown in block 260. In some embodiments, the semiconductor device may be a finned FET semiconductor device, as shown in block 262. According to some embodiments, the semiconductor device may be a gate-all-around semiconductor device, as shown in block 264.
[0051] Referring to Figures 5 to 10, an exemplary structure 300 formed according to method 200 is shown (as shown in Figure 10). In the illustrated example, and as shown in Figure 5, substrate 302 has a surface 304 and a material layer 306 having a groove 308. Substrate 302 is formed of a semiconductor material and may include a silicon wafer in some embodiments. Material layer 306 covers surface 304 of substrate 302 and is formed of silicon-containing material 310. Silicon-containing material 310 extends upward from surface 304 of substrate 302, and opening 314 leads into groove 308. Groove 308 is defined by a bottom surface 316 and a sidewall surface 318, each defined by silicon-containing material 310. Bottom surface 316 covers substrate 302, and sidewall surface 318 extends upward from bottom surface 316 to opening 314. It is conceivable that the bottom surface 316 of the groove 308 has a crystalline structure different from the crystalline structure of the sidewall surface 318 of the groove 308. In this respect, the bottom surface 316 has a silicon 1 0 0 crystalline structure 320, and the sidewall surface 318 has a silicon 1 1 0 crystalline structure 322.
[0052] The groove 308 has a width 324 and a depth 326. In some embodiments, the groove 308 may be a groove with a high aspect ratio. For example, the aspect ratio defined by the depth 326 and the width 324 may be greater than about 3:1, or greater than about 10:1, or greater than about 50:1, or even greater than about 100:1. The aspect ratio may be between about 3:1 and about 100:1. According to some embodiments, the groove may be a trench. It is also conceivable that the groove 308 may be a through hole, a contact, or any other groove suitable for forming structure 300 (shown in FIG. 10). The groove 308 (shown in FIG. 5) may be formed using an etching technique, for example, after patterning the surface 312 of the material layer (shown in FIG. 5), to position the opening 314 (shown in FIG. 5) of the groove 308 within the material layer 306.
[0053] As shown in Figure 6, it is conceivable that an epitaxial layer is used to deposit a film 328 in the groove 308 to form structure 300. The film 328 is deposited in the groove 308 by allowing one or more of the first precursor 142, the second precursor 146, the halide 152, and the flushing / carrier gas 158 to flow into the interior 130 (shown in Figure 1) of the reaction chamber 102 to form the film 328. The film 328 is deposited such that the film 328 only partially occupies the groove 308, in which respect the film 308 has a sidewall section 332 and a bottom section 330 located within 308. Those skilled in the art who have viewed this disclosure will understand that the bottom section 330 of the membrane 328 has a crystalline structure conforming to the crystalline structure of the bottom surface 316 of the groove 308, namely, a silicon 1 0 0 crystalline structure 320 conforming to the bottom surface 316, and the sidewall section 332 of the membrane 328 has a crystalline structure conforming to the crystalline structure of the sidewall surface 318 of the groove 308, namely, a silicon 1 1 0 crystalline structure 322 conforming to the sidewall surface 318.
[0054] Membrane 328 can be deposited in groove 308 by allowing dichlorosilane (DCS), hydrochloric acid (HCl), and hydrogen (H2) gases to flow through the interior 130 of reaction chamber 102. Membrane 328 can be deposited in groove 308 by maintaining at least one of a predetermined deposition pressure and a predetermined deposition temperature within the interior 130 of reaction chamber 102 (shown in FIG. 1) during the deposition of membrane 328. The predetermined deposition temperature can be between about 675 °C and about 850 °C. The predetermined deposition pressure can be between about 1 Torr and about 50 Torr. As explained above, and as shown in Figure A of FIG. 12, deposition temperatures and / or deposition pressures within these ranges allow the bottom section 330 of membrane 328 to be deposited onto the bottom surface 316 of groove 308 more rapidly than the sidewall section 332 of membrane 328 on the sidewall surface 318 of groove 308, i.e., at a deposition rate ratio greater than 1:1. Those skilled in the art who have viewed this disclosure will understand that a deposition rate ratio greater than 1:1 can reduce the cycle time required to form structure 300 (shown in FIG. 10) by reducing the number of times the reactor is returned to fill the recess 308, thereby increasing the yield of the semiconductor processing system used to form structure 300, such as semiconductor processing system 100 (shown in FIG. 1). In some instances, and as shown in FIG. 11, the deposition rate ratio may be between about 1.1:1 and about 2:1.
[0055] As shown in Figure 7, it is conceivable that the sidewall section 332 (shown in Figure 6) of the membrane 328 (shown in Figure 6) is removed from the groove 308, while a portion of the bottom section 330 (shown in Figure 6) remains within the groove 308. This removal can be accomplished by flowing at least one of the halide 152 and the rinsing / carrier gas 158 into the interior 130 of the reaction chamber 102 (shown in Figure 1), whereby the halide 152 and the rinsing / carrier gas 158 cooperate to etch the sidewall section 332 and the bottom section 330 of the membrane 328 from within the groove 308. It is conceivable that the halide 152 and the rinsing / carrier gas 158 remove substantially all of the sidewall section 332 of the membrane 328 from within the groove 308. It is also conceivable that the retained portion 336 of the bottom section 330 remains within the groove 308, and the retained portion 336 presents a 1 0 0 crystalline structure relative to the groove 308 at the filling surface 334.
[0056] The sidewall section 332 (shown in Figure 6) can be removed from the sidewall surface 318 by flowing hydrochloric acid (HCl) and hydrogen (H2) gas through the interior 130 (shown in Figure 1) of the reaction chamber 102, with at least a portion of the bottom section 330 (shown in Figure 6) remaining in the groove 308. Removal can be accomplished by maintaining at least one of a predetermined removal temperature and a predetermined removal pressure within the interior 130 of the reaction chamber 102. The predetermined removal temperature can be between 675 °C and approximately 850 °C. The predetermined removal pressure can be between approximately 5 Torr and approximately 50 Torr. As explained above and as shown in Figure 13, the removal temperature and / or removal pressure within these ranges allow the sidewall section 332 of film 328 to be removed more quickly than the bottom section 330 of film 328, i.e., with a removal rate ratio greater than 1. This also reduces the cycle time required to form structure 300 (shown in Figure 10) and improves the semiconductor processing system used to form structure 300, such as semiconductor processing system 100 (shown in Figure 1). In some instances, the removal rate ratio may be between approximately 5:1 and approximately 25:1.
[0057] As shown in Figures 8 and 9, a second membrane 338 having a second membrane bottom section 340 and a second membrane sidewall section 342 is subsequently deposited in the groove 308, and the second membrane sidewall section 342 is removed, while a portion of the second membrane bottom section 340 remains in the groove 308. Referring to Figure 7, it is conceivable that membrane 328 (shown in Figure 6) is a first membrane 328 having a first bottom section 330 (shown in Figure 6) and a first sidewall section 332 (shown in Figure 6), and the second membrane 338 is deposited in the groove 308 and on the sidewall surface 318 and the retained portion 336 of the groove 308. More specifically, the second membrane sidewall section 342 of the second membrane 338 is deposited on the sidewall surface 318 of the groove 308, and the second membrane bottom section 340 is deposited on the filling surface 334 of the retained portion 336 of the first membrane 328. It is conceivable that the second film 338 is deposited epitaxially, for example, in a deposition operation similar to (or the same as) the deposition operation used to deposit the first film 328, the bottom section 340 of the second film thereby forms a 100 crystal structure conforming to the silicon 100 crystal structure 320 of the bottom surface 316 of the groove 308, and the sidewall section 342 of the second film thereby forms a 110 crystal structure conforming to the silicon 110 crystal structure 322 of the sidewall surface 318 of the groove 308.
[0058] As shown in FIG. 9, the second membrane sidewall section 342 (shown in FIG. 8) is then removed and a portion of the second membrane bottom section 340 (shown in FIG. 8) is retained in the groove 308. As described above, it is conceivable that the second membrane sidewall section 342 is completely removed and the second retained portion 344 having the second filling surface 346 is retained in the groove 308. It is also conceivable that the second retained portion 344 forms a 100 crystal structure conforming to the silicon 100 crystal structure 320 of the bottom surface 316, and the second retained portion 344 presents a 100 crystal structure relative to the groove 308 at the second filling surface 346. Those skilled in the art who have viewed this disclosure will understand that, because both the first retention portion 336 and the second retention portion 344 have a 100 crystal structure conforming to the silicon 100 crystal structure 320 of the bottom surface 316 of the groove, the resulting structure is substantially homogeneous in relation to the crystal structure, for example, without a 110 crystal structure, limiting (or eliminating) variations in electrical properties in the structure that might otherwise accompany such crystal discontinuities.
[0059] As shown in FIG10, it is conceivable that the first retention portion 336 is deposited onto the bottom surface 316 of the trench 308 during a first deposition / removal cycle including a first deposition operation (shown in FIG6) and a first removal operation (shown in FIG7), and the second retention portion 344 is deposited onto the first retention portion 336 during a second deposition / removal cycle including a second deposition operation (shown in FIG8) and a second removal operation (shown in FIG9), and then the trench 308 (shown in FIG10) is filled from bottom to top. In this regard, one or more additional retention portions 350 may be deposited onto the second filling surface 346 of the second retention portion 344, and / or flat portions 348 may be deposited within the trench 308 and cover the bottom surface 316 of the trench 308 to form structure 300. A semiconductor device 400 (such as a fin FET device or a gate-all-around device) may then be formed to cover a substrate 302 (substrate 302 including structure 300). Although structure 300 is shown in Figure 10 as comprising ten (10) reserved portions, it should be understood and comprehended that the structure may include fewer or more reserved portions and is still within the scope of this disclosure.
[0060] Although this disclosure has been provided in the context of certain embodiments and examples, those skilled in the art will understand that this disclosure extends beyond the specifically described embodiments to other alternative embodiments and / or uses of embodiments and their obvious modifications and equivalents. Furthermore, while several variations of the embodiments of this disclosure have been shown and described in detail, other modifications based on this disclosure within its scope will be apparent to those skilled in the art. It is also conceivable that various combinations or sub-combinations of specific features and styles of the embodiments can be made and still fall within the scope of this disclosure. It should be understood that various features and styles of the disclosed embodiments can be combined or substituted with each other to form different modes of embodiments of this disclosure. Therefore, it is intended that the scope of this disclosure should not be limited to the specific embodiments described above.
[0061] The titles provided herein (if any) are for convenience only and are not intended to affect the scope or meaning of the apparatus and methods disclosed herein. [Simplified Explanation of the Diagram]
[0027] These and other features, features and advantages of the present invention will be described below with reference to certain embodiments and are intended to be illustrative and not limiting. Figure 1 is a schematic diagram of the semiconductor processing system according to the present disclosure, showing a controller operatively associated with a reaction chamber to form a structure within a groove covering a substrate supported within the reaction chamber; Figures 2 to 4 are block diagrams of a method for forming a structure covering a substrate using the semiconductor processing system of Figure 1, showing the operation of the method according to illustrative and non-limiting examples; Figures 5 to 10 are cross-sectional side views of a substrate, sequentially showing a structure formed by filling a groove covering the substrate, by circulating deposition of a film within the groove, and by removing sidewall sections of the film from the groove; Figures 11 and 12 are graphs of film deposition rate ratios based on temperature and pressure, showing that the deposition rate ratio is constant within the deposition temperature range and increases with decreasing pressure within the deposition pressure range; and Figures 13 and 14 are graphs of film removal rate ratios based on temperature and pressure, showing that the removal rate ratio is constant within the removal temperature range and increases with decreasing pressure within the removal pressure range. It will be understood from the figures that the elements in the figures are shown for simplicity and are not necessarily drawn to scale. For example, the relative size of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the embodiments illustrated in the invention.
Claims
1. A method of forming a structure, comprising: supporting a substrate in a reaction chamber of a semiconductor processing system, wherein the substrate has a recess having a bottom surface and a sidewall surface extending upward from the bottom surface of the recess; depositing a film in the recess and onto the bottom surface and the sidewall surface of the recess, the film having a bottom section and a sidewall section, the bottom section covering the bottom surface of the recess and the sidewall section deposited on the sidewall surface of the recess; removing the sidewall section of the film while retaining at least a portion of the bottom section of the film in the recess; and wherein removing the film includes removing the sidewall section of the film from the sidewall surface more rapidly than removing the bottom section of the film from the bottom surface of the recess.
2. The method of claim 1, wherein depositing the film comprises depositing the bottom section of the film onto the bottom surface more rapidly than depositing the sidewall section of the film onto the sidewall surface of the groove.
3. The method of claim 1, wherein the sidewall section and the bottom section of the membrane are removed at a removal rate ratio between 5:1 and 25:
1.
4. The method of claim 1, wherein the bottom section and the sidewall section of the membrane are deposited at a deposition rate ratio between 1.1:1 and 2:
1.
5. The method of claim 1, wherein the sidewall section and the bottom section of the membrane are removed under a predetermined removal pressure between 1 Torr and 50 Torr.
6. The method of claim 1, wherein the sidewall section and the bottom section of the membrane are removed at a predetermined removal temperature between 675 °C and 850 °C.
7. The method of claim 1, wherein the sidewall section and the bottom section of the membrane are deposited at a predetermined deposition pressure between 1 Torr and 50 Torr.
8. The method of claim 1, wherein the sidewall section and the bottom section of the membrane are deposited at a predetermined deposition temperature between 675 °C and 850 °C.
9. The method of claim 1, wherein the sidewall section and the bottom section of the membrane are deposited and removed under a common pressure, and wherein the sidewall section and the bottom section of the membrane are deposited and removed at a common temperature.
10. The method of claim 1, further comprising flowing dichlorosilane (DCS), hydrochloric acid (HCl) and hydrogen (H2) gas through the interior of one of the reaction chambers to deposit the sidewall section and the bottom section of the membrane into the groove.
11. The method of claim 1, further comprising allowing hydrochloric acid (HCl) and hydrogen (H2) gas to flow through the interior of one of the reaction chambers to remove a portion of the sidewall section and the bottom section of the membrane from the recess.
12. The method of claim 1, wherein the bottom surface of the groove has a silicon 100 crystalline structure, and the sidewall surface of the groove has a silicon 110 crystalline structure.
13. The method of claim 1, wherein the deposition operation and the removal operation comprise a first deposition / removal cycle, and the method further comprises at least a second deposition / removal cycle.
14. The method of claim 1, further comprising filling the groove from bottom to top from the bottom surface of the groove to an opening into the groove.
15. The method of claim 1, wherein removing the sidewall segment from the sidewall surface comprises exposing the sidewall surface above a retained portion of the bottom segment of the membrane from the groove.
16. A semiconductor processing system comprising: a reaction chamber; a gas delivery configuration connected to the reaction chamber; and a controller including a non-transitory machine-readable memory and a processor operatively connected to the gas delivery configuration, wherein the memory has a plurality of program modules recorded thereon, the plurality of program modules containing instructions that, when read by the processor, cause the processor to perform the following steps: supporting a substrate in the reaction chamber, wherein the substrate has a recess having a bottom surface and a sidewall surface extending upward from the bottom surface of the recess; depositing a film in the recess and onto the bottom surface and the sidewall surface of the recess, the film having a bottom section and a sidewall section, the bottom section covering the bottom surface of the recess, and the sidewall section deposited on the sidewall surface of the recess; Remove the sidewall section of the membrane while retaining at least a portion of the bottom section of the membrane within the groove; and remove the sidewall section of the membrane from the sidewall surface of the groove more quickly than removing the bottom section of the membrane from the bottom surface of the groove.
17. The system of claim 16, wherein the instructions further cause the controller to perform the following steps: circulate hydrochloric acid (HCl) and hydrogen (H2) gas through the interior of one of the reaction chambers to remove a portion of the sidewall segment and the bottom segment of the membrane from the recess; circulate dichlorosilane (DCS), hydrochloric acid (HCl), and hydrogen (H2) gas through the interior of the reaction chamber to deposit the sidewall segment and the bottom segment of the membrane into the recess; and wherein the bottom segment of the membrane is deposited onto the bottom surface of the recess more rapidly than the sidewall segment of the membrane is deposited onto the sidewall surface of the recess.
18. The system of claim 16, wherein the instructions further cause the controller to perform the following steps: depositing the bottom section and the sidewall section of the membrane at a deposition rate ratio between 1.1:1 and 2:1; and removing the bottom section and the sidewall section of the membrane at a removal rate ratio between 5:1 and 25:
1.
19. The system of claim 16, wherein the instructions further cause the controller to perform the following steps: depositing the sidewall section and the bottom section of the membrane at a predetermined deposition pressure between 1 Torr and 50 Torr; depositing the sidewall section and the bottom section of the membrane at a predetermined deposition temperature between 675 °C and 850 °C; removing a portion of the sidewall section and the bottom section of the membrane at a predetermined deposition pressure between 1 Torr and 50 Torr; and removing that portion of the sidewall section and the bottom section of the membrane at a predetermined deposition temperature between 675 °C and 850 °C.
20. A finned FET or a gate-all-around semiconductor device comprising a structure formed using the method of claim 1.