Triple-path clock and data recovery circuit, oscillator circuit and method for clock and data recovery

Abstract

A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Description

[Technical Field]

[0001] This disclosure relates to clock data recovery, and more particularly to a clock data recovery circuit having a three-path structure for bandwidth tracking, and its associated oscillation circuit and method for clock data recovery. [Previous Technology]

[0002] Using clock and data recovery (CDR) technology, a receiver can retrieve data from a data stream without additional timing information. First, the receiver performs clock recovery to extract a clock signal embedded in the level transition of the data stream. Next, the receiver phase-aligns the clock signal with the level transition of the data stream and samples the data stream based on the phase-aligned clock signal to recover the data. For example, clock and data recovery circuits are widely used in high-speed serial interfaces to regenerate a data stream based on a high-speed clock signal, where the high-speed clock signal and the level transition of the data stream are phase-aligned. Clock and data recovery circuits may face several challenges. For example, the oscillation circuit of a clock and data recovery circuit may suffer from significant jitter. This jitter is caused by process variation, temperature variation, and / or timing uncertainty in high-speed data transmission. [Summary of the Invention]

[0003] The embodiments disclosed herein provide a clock data recovery circuit having a three-path structure for bandwidth tracking, and an associated oscillation circuit and a method for clock data recovery.

[0004] Certain embodiments of this disclosure include a clock data recovery circuit, comprising a sampling circuit, a phase detector, a first processing circuit, a second processing circuit, and an oscillation circuit. The sampling circuit samples input data based on an output clock and generates a sampling result accordingly. The phase detector is coupled to the sampling circuit and generates a detection result based on the sampling result. The first processing circuit is coupled to the sampling circuit and processes the sampling result to generate a first digital code. The second processing circuit is coupled to the first processing circuit and accumulates a portion of the first digital code to generate a second digital code. The rate of change of the value of the second digital code is less than the rate of change of the value of the first digital code. The oscillation circuit is coupled to the sampling circuit, the phase detector, the first processing circuit, and the second processing circuit and generates the output clock based on the detection result, the first digital code, and the second digital code. The phase of the output clock is adjusted at least according to the detection result, and the frequency of the output clock is adjusted according to the first digit and the second digit.

[0005] Certain embodiments of this disclosure include an oscillation circuit comprising a current-controlled oscillator, a first conversion circuit, a second conversion circuit, and a third conversion circuit. The current-controlled oscillator is used to generate an output clock based on a first control current, a second control current, and a third control current. The frequency of the output clock is controlled by the first control current and the second control current, and the phase of the output clock is controlled by the third control current. The first conversion circuit is coupled to the current-controlled oscillator and is used to convert a first digital code into the first control current based on a first reference current. The second conversion circuit is coupled to the current-controlled oscillator and the first conversion circuit and is used to convert a second digital code into the second control current, the first reference current, and a second reference current. The second digital code is the accumulation result of at least one most significant bit of the first digital code. The third conversion circuit is coupled to the current-controlled oscillator and the second conversion circuit and is used to convert a third digital code and the second reference current into the third control current.

[0006] Certain embodiments of this disclosure include a method for clock data recovery, comprising: sampling input data based on an output clock output by an oscillator to generate a data signal and an edge signal, the data signal and the edge signal carrying phase error information of a phase error between the input data and the output clock; generating a detection result based on the data signal and the edge signal, the detection result indicating a phase relationship between the input data and the output clock; accumulating the phase error information carried by the data signal and the edge signal to generate a first digital code; accumulating at least one most significant bit of the first digital code to generate a second digital code; adjusting the phase of the output clock based on the detection result and the second digital code; and adjusting the frequency of the output clock based on the first digital code and the second digital code.

[0007] With the clock data recovery scheme provided in this disclosure, the oscillation circuit in the clock data recovery circuit can still have a wide frequency adjustment range and high resolution even under the influence of temperature variations. In addition, the clock data recovery scheme provided in this disclosure can achieve bandwidth tracking at various frequency angles, thereby ensuring good loop stability.

Implementation Method

[0009] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of parameter values, components, and configurations described below are used to simplify this disclosure. It is understood that these descriptions are merely illustrative and are not intended to limit the scope of this disclosure. For example, component symbols and / or reference numerals may be reused in embodiments. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0010] Furthermore, it is understood that if a component is described as being "connected to" or "coupled to" another component, then the two components may be directly connected or coupled, or there may be other intervening components between them.

[0011] To ensure good loop stability under the influence of temperature variations, the clock data recovery circuit can employ an oscillator circuit with a wide frequency tuning range. For example, the oscillator circuit can be designed with a large frequency step to widen its frequency tuning range. However, a large frequency step can cause significant jitter in the output of the oscillator circuit.

[0012] This disclosure provides exemplary clock data recovery circuits, wherein each clock data recovery circuit may employ a triple-path structure to control the operation of an oscillating circuit. The oscillating circuit is located within the clock data recovery circuit and is used to generate an output clock to recover data from a data stream. Two circuit paths in the aforementioned triple-path structure can respectively perform coarse tuning and fine tuning of the frequency of the output clock. In some embodiments, one of the two circuit paths is used to receive a digital code for fine tuning, while the other of the two circuit paths is used to receive an accumulated result of a portion of the digital code for coarse tuning. This disclosure also provides exemplary oscillating circuits, wherein each oscillating circuit not only has a wide frequency adjustment range but also high resolution. This disclosure also provides related methods for clock data recovery. Further explanation follows.

[0013] FIG1 is a functional block diagram of an exemplary clock data recovery circuit according to certain embodiments of the present disclosure. The clock data recovery circuit 100 can be used to recover timing information carried by an input data DIN (e.g., a data stream) and regenerate the input data DIN based on the recovered timing information. The clock data recovery circuit 100 includes (but is not limited to) a sampling circuit 110, a phase detector (PD) 120, a plurality of processing circuits 130 and 140, and an oscillation circuit 150. In this embodiment, the clock data recovery circuit 100 may employ a triple-loop structure. For example, the sampling circuit 110 may be used together with the phase detector 120 and the oscillation circuit 150 to implement a phase tracking loop. The sampling circuit 110 may be used together with the processing circuit 130 and the oscillation circuit 150 to implement a frequency tracking loop. In addition, the sampling circuit 110, together with the processing circuit 130, the processing circuit 140 and the oscillation circuit 150, can implement another frequency tracking loop.

[0014] The sampling circuit 110 is used to sample the input data DIN according to an output clock CKOUT, and generate a sampling result SR accordingly. In this embodiment, the sampling circuit 110 can sample multiple data bits of the input data DIN and the data edge between two consecutive data bits according to the output clock CKOUT, and generate a data signal DS and an edge signal ES accordingly. Therefore, the data signal DS and the edge signal ES can carry phase error information of the phase error between the input data DIN and the output clock CKOUT. For example (but this disclosure is not limited to this), the sampling circuit 110 can perform a two-times oversampling (2x oversampling) operation on the input data DIN to generate the sampling result SR.

[0015] A phase detector 120 is coupled to a sampling circuit 110 to generate a detection result DR based on a sampling result SR. The detection result DR indicates whether the output clock CKOUT lags behind or leads the input data DIN. In this embodiment, the phase detector 120 may receive a data signal DS and an edge signal ES to detect the phase difference between the input data DIN and the output clock CKOUT. The detection result DR may include a rising signal UP and a falling signal DN to indicate whether the output clock CKOUT lags behind or leads the input data DIN. For example, the phase detector 120 may generate a rising signal UP with a predetermined logic level when the output clock CKOUT lags behind the input data DIN, and a falling signal DN with a predetermined logic level when the output clock CKOUT leads the input data DIN. In some embodiments, the detection result DR may be implemented using a digital code DCP that includes the rising signal UP and the falling signal DN.

[0016] The processing circuit 130 is coupled to the sampling circuit 110 to process the sampling result SR to generate a digital code DCI, which indicates information about the frequency error between the input data DIN and the output clock CKOUT. In this embodiment, the digital code DCI can be implemented as an M-bit digital signal, where M is an integer greater than 1.

[0017] Processing circuit 140 is coupled to processing circuit 130 and is used to accumulate a portion of the digital code DCI to generate a digital code DCF. The rate of change of the code value of the digital code DCF may be less than the rate of change of the code value of the digital code DCI. For example, this portion of the digital code DCI may be K bits of the digital code DCI, where K is a positive integer less than M. Alternatively, this portion of the digital code DCI may be the most significant bit (MSB) of the digital code DCI. Alternatively, this portion of the digital code DCI may be the first two most significant bits of the digital code DCI. Alternatively, this portion of the digital code DCI may be at least one most significant bit of the digital code DCI. In this embodiment, since the digital code DCF is the accumulated result of this portion of the digital code DCI, the digital code DCF can indicate information about the frequency error between the input data DIN and the output clock CKOUT. A digital code (DCF) can be implemented as an N-bit digital signal, where N is a positive integer.

[0018] Oscillator 150 is coupled to sampling circuit 110, phase detector 120, processing circuit 130, and processing circuit 140 to generate an output clock CKOUT based on the detection result DR, digital code DCI, and digital code DCF. The phase of the output clock CKOUT is adjusted at least according to the detection result DR, and the frequency of the output clock CKOUT is adjusted according to the digital code DCI and digital code DCF. In some embodiments where the detection result DR is implemented using digital code DCP, oscillator 150 may be implemented as a digitally-controlled oscillator (DCO) circuit. Alternatively, since the rate of change of the code value of digital code DCF may be less than the rate of change of the code value of digital code DCI, digital code DCF can be regarded as a control input for coarse adjustment of the frequency of output clock CKOUT, and digital code DCI can be regarded as a control input for fine adjustment of the frequency of output clock CKOUT.

[0019] In this embodiment, the oscillator 150 includes (but is not limited to) a control circuit 160 and an oscillator 170. The control circuit 160 is coupled to the phase detector 120, the processing circuit 130, and the processing circuit 140, and may employ a three-path structure to control the operation of the oscillator 170. For example, the control circuit 160 is used to generate a control signal CSP based at least on the detection result DR, a control signal CSI based at least on the digital code DCI, and a control signal CSF based on the digital code DCF. The control signal CSP generated by one path of the control circuit 160 may be transmitted to the oscillator 170 to adjust the phase of the output clock CKOUT. The control signals CSI and CSF generated by the other two paths of the control circuit 160 may be transmitted to the oscillator 170 to adjust the frequency of the output clock CKOUT. The increment of the control signal CSF (signal level) relative to the digital code DCF (code value) by a predetermined amount (e.g., the binary value 1) is greater than the increment of the control signal CSI (signal level) relative to the digital code DCI (code value) by that predetermined amount. Therefore, the control signal CSF can be used for coarse adjustment of the output clock CKOUT frequency, while the control signal CSI can be used for fine adjustment of the output clock CKOUT frequency.

[0020] Oscillator 170 is coupled to sampling circuit 110 and control circuit 160 to generate output clock CKOUT based on control signals CSP, CSI, and CSF. Oscillator 170 can be implemented using a current-controlled oscillator (CCO), a voltage-controlled oscillator (VCO), or a hybrid current / voltage-controlled oscillator.

[0021] During operation, the sampling circuit 110 oversamples the input data DIN according to the output clock CKOUT, and generates a data signal DS and an edge signal ES accordingly. The phase detector 120 outputs a rising signal UP and a falling signal DN according to whether the output clock CKOUT lags behind or leads the input data DIN. The control circuit 160 uses the rising signal UP and the falling signal DN to generate a control signal CSP, thereby adjusting the phase of the output clock CKOUT. The circuit path involved in generating the control signal CSP can be called the proportional path and is labeled "P path". The processing circuit 130 processes the sampling result SR to accumulate the phase error information carried by the data signal DS and the edge signal ES, and generates a digital code DCI, which indicates the frequency error information between the input data DIN and the output clock CKOUT. The control circuit 160 uses the digital code DCI to generate a control signal CSI, thereby adjusting the frequency of the output clock CKOUT. The circuit path involved in generating the control signal CSI can be called the integral path and is labeled "I path". Furthermore, the processing circuit 140 can accumulate at least one most significant bit of the digital code DCI to generate the digital code DCF. The control circuit 160 can use the digital code DCF to generate the control signal CSF, thereby adjusting the frequency of the output clock CKOUT. The circuit path involved in generating the control signal CSF can be labeled "F path".

[0022] Compared to the value of the digital code DCI, the value of the digital code DCF changes more slowly. Therefore, the control circuit 160 can use the digital code DCF to coarsely adjust the frequency of the output clock CKOUT, and use the digital code DCI to finely adjust the frequency of the output clock CKOUT. For example, when the value of the digital code DCF remains unchanged, but the value of the digital code DCI increases, the signal level of the control signal CSI can increase. The frequency of the output clock CKOUT can be adjusted based on the fine step size. When the value of the digital code DCF increases, the signal level of the control signal CSF can increase. The frequency of the output clock CKOUT can be adjusted based on the coarse step size.

[0023] It is worth noting that, by means of the clock data recovery scheme provided in this disclosure, the gain involved in the integration path of the control circuit 160 can be maintained at a small gain value to provide high frequency resolution. Furthermore, the coarse adjustment operation implemented by the processing circuit 140 can provide a larger frequency adjustment interval, thereby allowing the oscillator circuit 150 to have a wider frequency adjustment range. Moreover, the control circuit 160 can generate a control signal CSP based on the detection result DR and the digital code DCF. By adjusting the signal levels of the plurality of control signals CSP, CSI, and CSF according to the digital code DCF, the control circuit 160 can allow the control signal CSP generated by the P path and the control signal CSI generated by the I path to follow / track the control signal CSF generated by the F path, thereby achieving bandwidth tracking at various frequency corners.

[0024] In some embodiments, before the clock data recovery circuit 100 begins tracking the input data DIN, the processing circuit 140 can compare the frequency of the reference signal CKR with the frequency of the output clock CKOUT, and set the code value of the digital code DCF to a predetermined value accordingly. When the clock data recovery circuit 100 begins tracking the input data DIN, the processing circuit 140 can accumulate this portion of the digital code DCI to update the code value of the digital code DCF. Using this predetermined value, the clock data recovery circuit 100 can shorten the time required to lock the output clock CKOUT.

[0025] To facilitate understanding of the contents of this disclosure, certain embodiments are provided below to further illustrate the clock data recovery scheme provided by this disclosure. Those skilled in the art should understand that other embodiments using the architecture shown in Figure 1 are within the scope of this disclosure.

[0026] FIG2 is a schematic diagram of an embodiment of the clock data recovery circuit 100 shown in FIG1 according to certain embodiments of the present disclosure. The clock data recovery circuit 200 includes (but is not limited to) a plurality of processing circuits 230 and 240, an oscillation circuit 250, and a sampling circuit 110 and a phase detector 120 shown in FIG1. ​​The plurality of processing circuits 230 and 240 may be embodiments of the plurality of processing circuits 130 and 140 shown in FIG1, respectively. The oscillation circuit 250 may be embodiments of the oscillation circuit 150 shown in FIG1, respectively.

[0027] The processing circuit 230 includes (but is not limited to) a deserializer 232 and an accumulator 236. The deserializer 232 is coupled to the sampling circuit 110 and processes the data signal DS and the edge signal ES to generate a deserialization result DES. The deserialization result DES indicates the phase difference information between the input data DIN and the output clock CKOUT. The accumulator 236 is coupled to the deserializer 232 and accumulates the phase difference information indicated by the deserialization result DES to generate a digital code DCI.

[0028] The processing circuit 240 includes (but is not limited to) a correction circuit 242 and an accumulator 246. The correction circuit 242 is coupled to the oscillation circuit 250 and is used to compare the frequency of the reference clock CKR with the frequency of the output clock CKOUT to generate a correction result CR. The accumulator 246 is coupled to the correction circuit 242 and is used to set the code value of the digital code DCF according to the correction result CR, and after the code value of the digital code DCF is set according to the correction result CR, it accumulates a portion of the digital code DCI to update the code value of the digital code DCF.

[0029] The oscillation circuit 250 includes (but is not limited to) a control circuit 260 and a current-controlled oscillator (labeled "CCO") 270. The control circuit 260 is used to generate a control current II based on the digital code DCI, a control current IF based on the digital code DCF, and a control current IP based on the digital code DCP (i.e., the detection result DR output by the phase detector 120). The plurality of control currents IP, II, and IF can be respectively implemented as the plurality of control signals CSP, CSI, and CSF shown in FIG1. ​​The current increment of the control current IF when the code value of the digital code DCF increases by a predetermined amount (e.g., the binary value 1) is greater than the current increment of the control current II when the code value of the digital code DCI increases by that predetermined amount. Therefore, the control current IF can be used for coarse adjustment of the frequency of the output clock CKOUT, while the control current II can be used for fine adjustment of the frequency of the output clock CKOUT.

[0030] In this embodiment, the control circuit 260 can generate a control current II based on the digital code DCI and the digital code DCF, and a control current IP based on the digital code DCP and the digital code DCF. Therefore, the control circuit 260 allows the control current IP and the control current II to track the control current IF, thus achieving bandwidth tracking and ensuring good loop stability. For example, the control circuit 260 may include a plurality of conversion circuits 262, 264, and 266, which can be used to implement the P path, I path, and F path shown in FIG. 1, respectively. The control circuit 260 allows at least one of the control current II generated by the conversion circuit 262 and the control current IP generated by the conversion circuit 266 to track the control current IF generated by the conversion circuit 264.

[0031] Conversion circuit 262 is coupled to processing circuit 230 and is used to generate control current II based on digital code DCI and a reference current IREFI. For example, conversion circuit 262 is used to convert digital code DCI into control current II based on reference current IREFI. When the code value of digital code DCI remains unchanged, the current level of control current II can be changed according to the current level of reference current IREFI.

[0032] Conversion circuit 264 is coupled to processing circuit 230 and conversion circuit 262 to generate control current IF and reference current IREFI based on digital code DCF. For example, conversion circuit 264 converts digital code DCF (i.e., the accumulated result of a portion of digital code DCI) into control current IF and reference current IREFI. When the code value of digital code DCF increases, both control current IF and reference current IREFI can increase. In this embodiment, conversion circuit 264 can also convert digital code DCF into a reference current IREFP. When the code value of digital code DCF remains unchanged, the current levels of reference current IREFI and reference current IREFP can change according to the current level of control current IF. That is, both reference current IREFI and reference current IREFP from conversion circuit 264 can follow control current IF. For example, when the code value of digital code DCF increases, both reference current IREFI and reference current IREFP can increase.

[0033] Conversion circuit 266 is coupled to phase detector 120 and conversion circuit 264 to convert digital code DCP and reference current IREFP into control current IP. For example, conversion circuit 266 can selectively drive (steer) reference current IREFP from conversion circuit 264 to current-controlled oscillator 270 according to digital code DCP to generate control current IP. When the code value of digital code DCP remains unchanged, the current level of control current IP can be changed according to the current level of reference current IREFP.

[0034] A current-controlled oscillator 270 is coupled to a plurality of switching circuits 262, 264 and 266 to generate an output clock CKOUT based on a plurality of control currents IP, II and IF. In this embodiment, the frequency of the output clock CKOUT is controlled by control currents II and IF, while the phase of the output clock CKOUT is controlled by control current IP.

[0035] During operation, before the clock data recovery circuit 200 begins tracking the input data DIN, the correction circuit 242 can be enabled to compare the frequency of the reference clock CKR with the frequency of the output clock CKOUT, thereby generating a correction result CR. The accumulator 246 can set the code value of the digital code DCF to a predetermined value based on the correction result CR. After the clock data recovery circuit 200 begins tracking the input data DIN, the correction circuit 242 can be disabled. The sampling circuit 110 can oversample the input data DIN according to the output clock CKOUT, and generate the data signal DS and the edge signal ES accordingly.

[0036] For the frequency tracking loop, deserializer 232 can convert the serial form data signal DS and edge signal ES into a parallel form deserialization result DES. Accumulator 236 can accumulate the phase error information indicated by the deserialization result DES to generate digital code DCI, which indicates the frequency error information between the input data DIN and the output clock CKOUT. Accumulator 246 can accumulate digital code DCI starting from this predetermined value to update the code value of digital code DCF.

[0037] Furthermore, the conversion circuit 264 can generate a control current IF and a reference current IREFI based on the digital code DCF. The conversion circuit 262 can convert the digital code DCI into a control current I based on the reference current IREFI provided by the conversion circuit 264. When the code value of the digital code DCF increases, the control current IF increases. When the code value of another part of the digital code DCI increases, the control current I increases. For example, the accumulator 246 can accumulate at least one most significant bit of the digital code DCI starting from a predetermined value to update the digital code DCF. The other part of the digital code DCI can be at least one least significant bit (LSB) of the digital code DCI that has not been accumulated by the accumulator 246. When the code value of the digital code DCF does not change, and the code value of another part of the digital code DCI increases, this indicates that the control circuit 260 performs a fine adjustment operation on the frequency of the output clock CKOUT. When the value of the digital code DCF changes or increases, it indicates that the control circuit 260 performs a coarse adjustment operation on the frequency of the output clock CKOUT. The control current IF can be increased accordingly. The frequency of the output clock CKOUT can be adjusted by the coarse frequency adjustment interval.

[0038] For the phase tracking loop, the phase detector 120 can generate a rising signal UP and a falling signal DN based on the data signal DS and the edge signal ES. The conversion circuit 266 can convert the digital code DCP and the reference current IREFP (provided by the conversion circuit 264) into a control current IP. For example, when the digital code DCP has a predetermined code value, the conversion circuit 266 increases the control current IP by driving the reference current IREFP from the conversion circuit 264 to the current-controlled oscillator 270. When the digital code DCP has another predetermined code value, the conversion circuit 266 decreases the control current IP by stopping the driving of the reference current IREFP to the current-controlled oscillator 270. The phase of the output clock CKOUT can be adjusted according to the control current IP.

[0039] The circuit structure described above is for illustrative purposes only and is not intended to limit the scope of this disclosure. In some embodiments, the correction circuit 242 may be omitted. In some embodiments, the oscillation circuit 250 may be implemented using a voltage-controlled oscillator circuit or a hybrid current / voltage oscillator circuit. These design modifications and variations are within the scope of this disclosure.

[0040] FIG3 is a schematic diagram of an embodiment of the control circuit 260 shown in FIG2 according to certain embodiments of the present disclosure. The control circuit 360 may include a plurality of conversion circuits 362, 364 and 366, which may be embodiments of the plurality of conversion circuits 262, 264 and 266 shown in FIG2, respectively. In this embodiment, the conversion circuit 362 includes (but is not limited to) a current mirror circuit 372, a digital-to-analog converter (DAC) 382 and a voltage-to-current converter 392. The current mirror circuit 372 can mirror a reference current IREFI to generate an auxiliary current IAUXI. For example (but not limited to this disclosure), the current mirror circuit 372 may include a plurality of transistors M31 and M32. The digital-to-analog converter 382 is coupled to the current mirror circuit 372 to convert the digital code DCI into an auxiliary voltage VAUXI according to the auxiliary current IAUXI. A voltage-to-current converter 392 is coupled to a digital-to-analog converter 382 to convert an auxiliary voltage VAUXI into a control current II. For example (but not limited thereto), the voltage-to-current converter 392 may include an amplifier A1, a resistor R1, and a plurality of transistors M33 and M34.

[0041] The conversion circuit 364 includes (but is not limited to) a digital-to-analog converter 374 and a voltage-to-current converter 384. The digital-to-analog converter 374 converts the digital code DCF into an auxiliary voltage VAUXF. The voltage-to-current converter 384 is coupled to the digital-to-analog converter 374 to convert the auxiliary voltage VAUXF into a reference current IREFI, a reference current IREFP, and a control current IF. For example (but not limited thereto), the voltage-to-current converter 384 may include an amplifier A2, a resistor R2, and a plurality of transistors M35 to M39.

[0042] The switching circuit 366 includes (but is not limited to) a plurality of switches SWU and SWD. The plurality of switches SWU and SWD can be controlled by the rising signal UP and the falling signal DN provided by the phase detector 120 shown in FIG2, respectively. Since those skilled in the art should understand the details of generating the plurality of control currents IP, II and IF after reading the above description of FIG1 and FIG2, further explanation will not be repeated here.

[0043] FIG4 is a schematic diagram of an embodiment of the digital-to-analog converter 382 shown in FIG3 according to certain embodiments of the present disclosure. The digital-to-analog converter 382 is used to convert a digital code DCI (implemented as an M-bit digital signal) into an auxiliary voltage VAUXI according to an auxiliary current IAUXI. In this embodiment, the digital-to-analog converter 382 includes a plurality of transistors M40 to M4M+1, a plurality of switches SW0 to SWM, and a resistor R4. SW0 to SWM are controlled by M bits B0 to BM of the digital code DCI, respectively. Therefore, the voltage level of the auxiliary voltage VAUXI can be determined according to the number of switches that are turned on. In some embodiments, the digital-to-analog converter 374 shown in FIG3 may adopt a similar circuit structure to the digital-to-analog converter 382 shown in FIG4.

[0044] It is worth noting that the circuit implementations shown in Figures 3 and 4 described above are for illustrative purposes only and are not intended to limit the scope of this disclosure. Any design variations of a control circuit that employs a three-path structure to control the operation of the oscillator, allowing the accumulation of a digital code for fine frequency adjustment and a portion of that digital code for coarse frequency adjustment, are within the scope of this disclosure. Furthermore, any design variations of a control circuit that allow the control signals provided by the proportional and integral paths to follow the control signal provided by the other path used for coarse frequency adjustment, are within the scope of this disclosure.

[0045] FIG5 is a flowchart of a method for clock data recovery according to certain embodiments of the present disclosure. For ease of explanation, the method 500 will be described below in conjunction with the clock data recovery circuit 200 shown in FIG2. Those skilled in the art will understand that the method 500 can be applied to the clock data recovery circuit 100 shown in FIG1 or other clock data recovery circuits with a three-path structure without departing from the scope of the present disclosure. Furthermore, in some embodiments, the method 500 may include other operations. In some embodiments, the operations of the method 500 may be performed based on different sequences, and / or may be implemented using other methods. In some embodiments, one or more operations of the method 500 may be omitted.

[0046] In operation 502, input data is sampled based on an output clock output by an oscillator to generate a data signal and an edge signal. The data signal and the edge signal carry phase error information regarding the phase error between the input data and the output clock. For example, sampling circuit 110 may sample input data DIN based on the output clock CKOUT output by current-controlled oscillator 270 to generate a data signal DS and an edge signal ES. The data signal DS and the edge signal ES may carry phase error information regarding the phase error between the input data DIN and the output clock CKOUT.

[0047] In operation 504, a detection result is generated based on the data signal and the edge signal. The detection result indicates the phase relationship between the input data and the output clock. For example, the phase detector 120 can generate a detection result DR based on the data signal DS and the edge signal ES, wherein the detection result DR (including the rising signal UP and the falling signal DN) can indicate the phase relationship between the input data DIN and the output clock CKOUT.

[0048] In operation 506, the phase error information carried by the data signal and the edge signal is accumulated to generate a first digital code. For example, deserializer 232 can process the serial data signal DS and the edge signal ES to generate a parallel deserialization result DES, wherein the deserialization result DES can indicate phase error information of the phase error between the input data DIN and the output clock CKOUT. Accumulator 236 can accumulate the phase error information indicated by the deserialization result DES to generate a digital code DCI.

[0049] In operation 508, at least one most significant bit of the first digital code is accumulated to generate a second digital code. For example, accumulator 246 may accumulate one or more most significant bits of digital code DCI to generate digital code DCF.

[0050] In operation 510, the phase of the output clock is adjusted according to the detection result and the second digital code. For example, the control circuit 260 can adjust the phase of the output clock CKOUT according to the detection result DR and the digital code DCF.

[0051] In operation 512, the frequency of the output clock is adjusted according to the first digital code and the second digital code. For example, the control circuit 260 can adjust the frequency of the output clock CKOUT according to the digital code DCI and the digital code DCF. It is worth noting that since both the phase and frequency of the output clock CKOUT can be adjusted according to the digital code DCF, the clock data recovery circuit 200 can achieve bandwidth tracking and provide good loop stability.

[0052] In some embodiments, during operation 508, the initial value of the second digit code can be determined based on a reference clock and the output clock, which can shorten the time required to lock the output clock. For example, before the clock data recovery circuit 200 begins tracking the input data DIN, the correction circuit 242 can compare the frequency of the reference clock CKR with the frequency of the output clock CKOUT to generate a correction result CR. Next, the accumulator 246 can set the code value of the digit code DCF according to the correction result CR. After the code value of the digit code DCF is set according to the correction result CR, the accumulator 246 can accumulate the one or more most significant bits of the digit code DCI to update the code value of the digit code DCF.

[0053] Since those skilled in the art should be able to understand the operational details of the method 500 shown in Figure 5 after reading the above description of Figures 1 to 4, further explanation will not be repeated here.

[0054] With the clock data recovery scheme provided in this disclosure, the oscillation circuit in the clock data recovery circuit can still have a wide frequency adjustment range and high resolution even under the influence of temperature variations. In addition, the clock data recovery scheme provided in this disclosure can achieve bandwidth tracking at various frequency angles, thereby ensuring good loop stability.

[0055] The foregoing description briefly outlines the features of certain embodiments of this disclosure, enabling those skilled in the art to gain a more comprehensive understanding of the various forms of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0008] The various embodiments disclosed herein can be clearly understood by reading the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the size of certain features may be arbitrarily enlarged or reduced for clear description. FIG1 is a functional block diagram of an exemplary clock data recovery circuit according to certain embodiments of the present disclosure. FIG2 is a schematic diagram of an embodiment of the clock data recovery circuit shown in FIG1 according to certain embodiments of the present disclosure. FIG3 is a schematic diagram of an embodiment of the control circuit shown in FIG2 according to certain embodiments of the present disclosure. FIG4 is a schematic diagram of an embodiment of the digital-to-analog converter shown in FIG3 according to certain embodiments of the present disclosure. FIG5 is a flowchart of a method for clock data recovery according to certain embodiments of the present disclosure.

Claims

1. A clock generation circuit, comprising: an oscillator for generating an output clock based on a first control signal, a second control signal, and a third control signal, wherein the frequency of the output clock is controlled by the first control signal and the second control signal, and the phase of the output clock is controlled by the third control signal; a processing circuit for accumulating a portion of a first digital code to generate a second digital code, wherein the rate of change of the code value of the second digital code is less than the rate of change of the code value of the first digital code; and a control circuit coupled to the oscillator and the processing circuit for generating the first control signal based at least on the first digital code, generating the second control signal based on the second digital code, generating the third control signal based at least on a third digital code, and outputting the first control signal, the second control signal, and the third control signal to the oscillator to lock the output clock.

2. The clock generation circuit as described in claim 1, wherein the portion of the first digital code is at least one most significant bit of the first digital code.

3. The clock generation circuit as described in claim 1, wherein the increment of the second control signal when the code value of the second digital code increases by a predetermined amount is greater than the increment of the first control signal when the code value of the first digital code increases by the predetermined amount.

4. The clock generation circuit as described in claim 1, wherein the control circuit comprises: a first circuit path for receiving the first digital code to generate the first control signal; a second circuit path for receiving the second digital code to generate the second control signal; and a third circuit path for receiving the third digital code to generate the third control signal, wherein the signal level of each of the first control signal, the second control signal, and the third control signal is adjusted according to the second digital code.

5. The clock generation circuit as described in claim 4, wherein the first circuit path is used to generate a first control current based on the first digital code and a first reference current as the first control signal; and the second circuit path is used to generate a second control current based on the second digital code and the first reference current, wherein the second control current is used as the second control signal.

6. The clock generation circuit as described in claim 5, wherein the second circuit path is used to generate a second reference current according to the second digital code; and the third circuit path is used to selectively drive the second reference current from the second circuit path to the oscillator according to the third digital code to generate a third control current as the third control signal.

7. The clock generation circuit as described in claim 6, wherein when the code value of the second digit code increases, both the first reference current and the second reference current increase.

8. The clock generation circuit as claimed in claim 5, wherein the first circuit path comprises: a current mirror circuit for mirroring the first reference current to generate an auxiliary current; a digital-to-analog converter coupled to the current mirror circuit for converting the first digital code into an auxiliary voltage according to the auxiliary current; and a voltage-to-current converter coupled to the digital-to-analog converter for converting the auxiliary voltage into the first control current.

9. The clock generation circuit as claimed in claim 5, wherein the second circuit path includes: a digital-to-analog converter for converting the second digital code into an auxiliary voltage; and a voltage-to-current converter coupled to the digital-to-analog converter for converting the auxiliary voltage into the first reference current and the second control current.

10. The clock generation circuit as claimed in claim 1, wherein the processing circuit is configured to compare the frequency of a reference clock with the frequency of the output clock to set the code value of the second digit to a predetermined value, and after the code value of the second digit is set to the predetermined value, accumulate the portion of the first digit to update the second digit.

11. An oscillation circuit comprising: an oscillator for generating an output clock; A control circuit is provided for outputting a first control signal and a second control signal to the oscillator, coupled to the oscillator, to adjust the frequency of the output clock of the oscillator, wherein the control circuit includes: A first circuit path for receiving a first digital code to generate the first control signal; And a second circuit path for receiving a second digital code to generate the second control signal, wherein the second digital code is an accumulation of a portion of the first digital code, and the rate of change of the value of the second digital code is less than the rate of change of the value of the first digital code.

12. The oscillating circuit as claimed in claim 11, wherein the portion of the first digital code is at least one most significant bit of the first digital code.

13. The oscillation circuit as described in claim 11, wherein the increment of the second control signal when the code value of the second digital code increases by a predetermined amount is greater than the increment of the first control signal when the code value of the first digital code increases by the predetermined amount.

14. The oscillating circuit as claimed in claim 11, wherein the control circuit is further configured to output a third control signal to the oscillator to adjust the phase of the output clock of the oscillator; the control circuit further includes: a third circuit path for receiving a third digital code to generate the third control signal, wherein the signal levels of the first control signal, the second control signal and the third control signal are each adjusted according to the second digital code.

15. The oscillating circuit as claimed in claim 11, wherein the first circuit path is used to generate a first control current based on the first digital code and a first reference current as the first control signal; and the second circuit path is used to generate a second control current based on the second digital code and the first reference current, wherein the second control current serves as the second control signal.

16. The oscillating circuit as claimed in claim 15, wherein the second circuit path is used to generate a second reference current according to the second digital code; the control circuit further includes: a third circuit path for selectively driving the second reference current from the second circuit path to the oscillator according to a third digital code to generate a third control current, wherein the phase of the output clock is controlled by the third control current.

17. The oscillating circuit as claimed in claim 16, wherein when the code value of the second digital code increases, both the first reference current and the second reference current increase.

18. The oscillation circuit as claimed in claim 15, wherein the first circuit path comprises: a current mirror circuit for mirroring the first reference current to generate an auxiliary current; a digital-to-analog converter coupled to the current mirror circuit for converting the first digital code into an auxiliary voltage according to the auxiliary current; and a voltage-to-current converter coupled to the digital-to-analog converter for converting the auxiliary voltage into the first control current.

19. The oscillating circuit as claimed in claim 15, wherein the second circuit path includes: a digital-to-analog converter for converting the second digital code into an auxiliary voltage; and a voltage-to-current converter coupled to the digital-to-analog converter for converting the auxiliary voltage into the first reference current and the second control current.

20. A method for locking the output clock of an oscillator, comprising: accumulating a portion of a first digital code to generate a second digital code, wherein the rate of change of the code value of the second digital code is less than the rate of change of the code value of the first digital code; generating a first control current based on the first digital code and the second digital code; generating a second control current based on the second digital code; generating a third control current based on the second digital code and a third digital code, wherein the first control current and the third control current both follow the second control current; adjusting the frequency of the output clock based on the first control current and the second control current; and adjusting the phase of the output clock based on the third control current.

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