Page group read voltage threshold calibration

Abstract

A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Description

[Technical Field]

[0001] This disclosure generally relates to data storage, and more particularly to non-volatile memory systems. More particularly, this disclosure relates to read voltage threshold calibration in non-volatile memory systems. [Previous Technology]

[0002] NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more data bits of each memory cell as charges on a floating gate of a transistor or a similar charge trapping structure. In a typical implementation, a NAND flash memory array is organized in physical blocks of memory, each of which includes multiple physical pages stored in multiple memory cells. By means of the configuration of word lines and bit lines used to access memory cells, flash memory arrays can typically be programmed on a page-by-page basis but erased on a block-by-block basis.

[0003] As known in the art, blocks of NAND flash memory must be erased before being programmed with new data. After erasure, NAND flash memory cells can be programmed by applying a positive high programming voltage to the word line of the memory cell to be programmed and applying an intermediate on voltage to memory cells in the same string to be suppressed from programming. Applying the programming voltage causes electrons to tunnel to the floating gate of the memory cell to change its state from an initial erased state to a programmed state with a net negative charge. The voltage of the gate associated with one or more read voltage thresholds indicates the bit value stored in the memory cell.

[0004] Due to programming / erase cycles, data retention, read interference, programming interference, and / or other reasons, the programmed voltage distribution of memory cells can change during the operation of a NAND flash memory device. In response to changes in the programmed voltage distribution, the controller can perform calibration to adjust the read voltage threshold, thereby reducing the bit error rate (BER). For example, some prior art controllers take into account permanent and temporary changes in the voltage distribution by calculating an optimal offset from the initial read voltage threshold based on two permanent effects (e.g., due to cycle wear) and temporary effects (e.g., due to data retention and read interference). Such optimal offsets can be determined using iterative algorithms that issue multiple page reads with different offsets. To reduce the additional load of calibration and the data following the read voltage threshold, physical pages can be grouped into page groups. These groups can consist of, for example, all physical pages coupled to a common word line, all physical pages in one or more vertically stacked physical layers of 3D NAND flash memory, a collection of physical pages in a physical layer with the same page type (i.e., top page, bottom page, extra page, or top page), or physical pages that generally have similar characteristics. Typically, each time a read voltage threshold calibration is triggered, the controller performs a read voltage threshold calibration on the entire physical block. [Summary of the Invention]

[0005] This disclosure understands that conventional read voltage threshold calibration cannot provide the expected performance and error reduction. For example, calibrating an entire physical block due to read failures imposes significant latency on the host's performance-critical read path. Furthermore, in some prior art systems, page groups within a physical block undergoing read voltage threshold calibration are calibrated separately based on randomly selected physical pages within a page group. As a result of this random selection, the physical page that triggers the read voltage threshold calibration may not be used as the basis for calibrating its own page group. Therefore, due to the different manifestations of error effects (e.g., read interference, hammering, holding, programming interference, flash memory media problems, etc.) in different physical pages, the optimal read voltage threshold determined for a specific page group may not be applicable to all physical pages in that page group, and may even fail to correct errors in the physical page that triggered the read voltage threshold calibration.

[0006] In at least one embodiment, the controller of the non-volatile memory detects errors in data read from a specific physical page of the non-volatile memory. Based on the detected error, the controller performs a read voltage threshold calibration on a page group including the specific physical page and a plurality of other physical pages. Performing the read voltage threshold calibration includes calibrating the read voltage threshold only based on the specific physical page of the page group. After the controller performs the read voltage threshold calibration, the controller verifies the calibration as appropriate. Verifying the calibration includes determining whether the bit error rate within the page group is diverging, and if so, mitigating the divergence. Mitigating the divergence includes relocating the data from the page group to another block of the non-volatile memory.

Implementation Method

[0015] Referring to the figures, and specifically to Figure 1, a high-level block diagram of an exemplary data processing environment 100 is shown, which includes a data storage system 120, as further described herein. As shown, the data processing environment 100 includes one or more hosts, such as a processor system 102 having one or more processors 104 that process instructions and data. The processor system 102 may additionally include local storage 106 (e.g., DRAM or a disk) that can store program code, operands, and / or execution results of the processing executed by the processor 104. In various embodiments, the processor system 102 may be, for example, a mobile computing device (such as a smartphone or tablet), a laptop or desktop personal computer system, a server computer system (such as one of the POWER® series available from IBM), or a mainframe computer system. The processor system 102 may also be an embedded processor system using various processors such as ARM®, POWER, Intel x86, or any other processor combined with memory cache, memory controller, local storage, I / O bus, etc.

[0016] Each processor system 102 further includes an input / output (I / O) adapter 108 that is directly coupled (i.e., without any intermediary device) or indirectly coupled (i.e., via at least one intermediate device) to the data storage system 120 via I / O channel 110. In various embodiments, I / O channel 110 may use any or a combination of known or future-developed communication protocols, including, for example, Fibre Channel (FC), Ethernet FC (FCoE), Internet Small Computer System Interface (iSCSI), InfiniBand, Transmission Control Protocol / Internet Protocol (TCP / IP), Peripheral Component Rapid Interconnect (PCIe), High-Speed ​​Non-Volatile Memory (NVMe), Mesh NVMe (NVMe over Fabrics; NVMe-oF), etc. The I / O commands transmitted via I / O channel 110 include host read commands by which processor system 102 requests data from data storage system 120, and host write commands by which processor system 102 requests data to be stored in data storage system 120.

[0017] In the illustrated embodiment, the data storage system 120 includes a plurality of interface nodes 122 through which the data storage system 120 receives and responds to I / O commands via I / O channels 110. Each interface node 122 is coupled to one of a plurality of low-cost redundant array of disks (RAID) controllers 124 to facilitate fault tolerance and load balancing. Each of the RAID controllers 124 is further coupled (e.g., via a PCIe bus) to one of a plurality of flash memory cards 126, in this example including NAND flash memory storage media. In other embodiments, other lossy storage media may be used.

[0018] FIG2 depicts a more detailed block diagram of a flash memory card 126 of a data storage system 120 of FIG1 according to one embodiment. In this embodiment, the flash memory card 126 includes a gateway 130 that acts as an interface between the flash memory card 126 and a RAID controller 124. The gateway 130 is coupled to a general-purpose processor (GPP) 132, which can be configured (e.g., via code) to perform various management functions, such as preprocessing I / O commands received by the gateway 130, scheduling the servicing of I / O commands by the flash memory card 126, and / or performing other management functions. The GPP 132 is coupled to a GPP memory 134 (e.g., dynamic random access memory (DRAM)) that can conveniently buffer data created, referenced, and / or modified by the GPP 132 during its processing.

[0019] The gate 130 is further coupled to at least one flash memory controller 140, which controls a high-capacity non-volatile memory system, such as a NAND flash memory system 150. The flash memory controller 140 serves I / O commands, such as reading requested data from or writing requested data to the NAND flash memory system 150 by accessing the NAND flash memory system 150, as further discussed below. In various embodiments, the flash memory controller 140 may be implemented, for example, by an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). In an embodiment where the flash memory controller 140 is implemented by an FPGA, the GPP 132 may program and configure the flash memory controller 140 during startup of the data storage system 120 based on code in the GPP memory 134.

[0020] The flash memory controller 140 is coupled to a flash memory controller memory, which in this embodiment includes both a flash memory controller non-volatile memory 142 and a flash memory controller volatile memory 144. The flash memory controller non-volatile memory 142 may be implemented, for example, by MRAM, FRAM, PCM, battery-backed DRAM, or other non-volatile memory technologies, and the flash memory controller volatile memory 144 may be implemented by a relatively inexpensive volatile memory technology such as DRAM. As further indicated in FIG2, the flash memory controller non-volatile memory 142 may include a host write cache 146 for buffering host write data associated with host write commands received from a host, such as processor system 102.

[0021] The flash memory controller 140 implements a flash memory translation layer (FTL) that provides logic-to-physical address translation to enable access to specific memory locations within the NAND flash memory system 150. Generally, I / O commands received by the flash memory controller 140 from a host device (such as processor system 102) contain the logical block address (LBA) of the data to be accessed (read or write), and if it is a host write command, the host write data is written to the data storage system 120. The I / O command may also specify the amount (or size) of the data to be accessed. Depending on the protocols and features supported by the data storage system 120, other information may also be conveyed. As is known to those skilled in the art, in some implementations of NAND flash memory, the smallest data block that can be accessed by a host read or host write command is a single codeword, which may be, for example, 8 or 16 kilobits (kB). The LBA provided by the host device corresponds to a logical page within the logical address space, which may have a size of, for example, 4 kB or 16 kB. This logical page can be further compressed by the flash memory controller 140 so that each physical page can store one or more logical pages. The FTL translates the LBA into a physical address assigned to the corresponding physical location in the NAND flash memory system 150. The flash memory controller 140 can store the mapping between logical addresses and physical addresses in a logic-to-physical translation data structure, such as a logic-to-physical translation (LPT) table 152, which can be conveniently stored in the flash memory controller volatile memory 144.

[0022] As further shown in FIG2, in the depicted embodiment, the flash memory controller volatile memory 144 further includes a relocation write buffer 148 for buffering data collected by the discarded item collection procedure and to be relocated to the NAND flash memory system 150. Additionally, the flash memory controller volatile memory 144 may include a read cache 156 for buffering data from the NAND flash memory system 150 that has recently and / or frequently been requested by host read commands. The flash memory controller 140 may also store voltage threshold (Vth) shift data 154 in the flash memory controller volatile memory 144. This shift data is used to calibrate the read voltage thresholds of various subsets (e.g., page groups) of the NAND flash memory system 150, as well as other management data structures 158 that store management data such as bit error rate (BER), programming / erase (P / E) cycle count, read count, and other block, page group, and page statistics.

[0023] In various embodiments, the NAND flash memory system 150 may take many forms. Referring now to Figures 3 to 6, an exemplary configuration of physical memory within a NAND flash memory system 150 according to one embodiment is depicted.

[0024] As shown in Figure 3, the NAND flash memory system 150 can be formed from forty (40) individually addressable NAND flash memory storage devices. In the illustrated example, each of the flash memory storage devices M0a to M19b takes the form of a board-mounted flash memory module capable of storing two or more bits per cell. In a particular embodiment, the memory module is implemented by a quad-level cell (QLC) NAND flash memory configured to operate in a hybrid hierarchical configuration, which includes a first set of physical blocks operating in QLC mode and a second set of physical blocks operating in single-level cell (SLC) mode. The forty NAND flash memory modules are configured into twenty groups of two modules: (M0a, M0b) to (M19a, M19b). For the purpose of physical addressing scheme, the groups of the two modules form "simplex channels" (sometimes also called "channels"), so that the NAND flash memory system 150 includes twenty channels or simplex channels (simplex channel 0 to simplex channel 19).

[0025] In a preferred embodiment, each of the individual simplex channels has a separate associated bus that couples it to the associated flash memory controller 140. Therefore, by directing its communication to one of the specific communication buses, the flash memory controller 140 can direct its communication to one of the simplex channels of the memory module. Because each communication bus for a given simplex channel is independent of the communication buses for other simplex channels, the flash memory controller 140 can simultaneously issue commands and send or receive data across various communication buses, thereby enabling the flash memory controller 140 to access the flash memory module corresponding to the individual simplex channel simultaneously or nearly simultaneously.

[0026] Referring now to FIG4, an exemplary embodiment of a flash memory module 400 that can be used to implement any of the flash memory modules M0a to M19b of FIG3 is shown. As shown in FIG4, the physical storage location provided by the flash memory module 400 is further subdivided into physical locations that can be addressed and / or identified via chip enable (CE). In the example of FIG4, the physical memory of each flash memory chip 400 is divided into four chip enable (CE0, CE1, CE2 and CE3), each chip enable having a separate CE line verified by the flash memory controller 140 to enable access to or from the physical memory location within the corresponding CE. Each CE is further divided into multiple dies (e.g., die 0 and die 1) each having two or four planes (e.g., plane 0 and plane 1). Each plane represents a collection of physical blocks. Due to the physical layout of the flash memory chip, these physical blocks are physically associated with each other and utilize a common circuit system (e.g., I / O buffers) to perform various operations, such as read and write operations.

[0027] As further illustrated in Figures 5 and 6, an exemplary plane 500, which can be used to implement any of the planes within the flash memory module 400 of Figure 4, includes, for example, 512, 2048, or 4096 blocks of physical memory. Some manufacturers include additional blocks in this nominal block count because some blocks may fail prematurely due to manufacturing defects. Generally, a block is a collection of physical pages that are typically associated with each other in a physical manner. This association makes a block defined as the smallest granularity of physical storage location that can be erased within the NAND flash memory system 150. In the embodiment of Figure 6, each block 600 includes hundreds or thousands of pages, such as 512, 1024, or 4096 physical pages, where a physical page is defined as the smallest individually addressable unit of data for read and write access. In the exemplary system, each physical page of data has a common capacity for data storage (e.g., 16 kB) plus additional storage space for data after the page. Therefore, data is typically written to or read from the NAND flash memory system 150 on a page-by-page basis, but erased on a block-by-block basis.

[0028] In at least some embodiments, each entity page in block 600 is assigned to a page group containing two or more entity pages. Since the entity pages belong to the same page type (e.g., bottom page, top page, extra page, top page, etc.), are manufactured in the same physical layer of the chip, etc., the controller (e.g., GPP 132 or flash memory controller 140) may assign the entity pages of block 600 to the page group based on the expected similarity of the entity page characteristics (e.g., error characteristics).

[0029] Because the FTL implemented by the data storage system 120 isolates the logical address space available to the host device from the physical memory within the NAND flash memory system 150, the size of the NAND flash memory system 150 does not need to be equal to the size of the logical address space presented to the host device. In most embodiments, it is beneficial to present a logical address space smaller than the total available physical memory (i.e., it is beneficial to over-deploy the NAND flash memory system 150). Over-deployment in this manner ensures that physical memory resources are available when the logical address space is fully utilized, even if there is a certain amount of invalid data as described above. In addition to accommodating invalid data that has not yet been reclaimed, the over-deployed space can be used to ensure that there is sufficient logical space, even in the event of memory failures and additional memory load caused by the use of data protection schemes (such as error correction codes (ECC), cyclic redundancy checks (CRC), and parity checks).

[0030] In some embodiments, data is written to the NAND flash memory system 150 one physical page at a time. In other embodiments requiring more robust error recovery, data is written to a group of associated physical pages of the NAND flash memory system 150, referred to herein as a "page stripe". In one embodiment, all pages of a page stripe are associated with different simplex channels to achieve high write bandwidth. Because in many implementations the smallest unit of erasure is a block, multiple page stripes can be grouped into block stripes, where each block in a block stripe is associated with a different simplex channel. When constructing a block stripe, any free block of a simplex channel can be selected, but preferably, all blocks within the same block stripe have the same or similar health level. It should be noted that block selection may be further limited to those from the same plane, die, and / or wafer enablement. The length of the block equalization area can vary, but in one embodiment of the NAND flash memory system 150 that includes 20 simplex channels, each block equalization area includes two to twenty blocks, wherein each block comes from a different simplex channel.

[0031] Once blocks have been selected from each simplex channel and block equivalences have been formed, page equivalences are preferably formed from physical pages with the same page number from all blocks within the block equivalences. While the lengths of the various page equivalences stored in the NAND flash memory system 150 can vary, in one embodiment, each page equivalence includes one to twenty data pages (typically provided by the host device) for writing data. In another embodiment, a page equivalence includes one to nineteen data pages for writing data and an additional page ("data protection page") for storing data protection information for the written data. The data protection page can be placed on any simplex channel containing a page equivalence containing non-obsolete pages, but is typically placed on the same simplex channel for all page equivalences of the same block equivalence to minimize post-processing data. As shown, adding a data protection page requires simultaneous obsolescence collection for all page equivalences of the same block equivalence. After the collection of discarded items in the block equal-size area is completed, the block equal-size area can be decomposed, and each block can be placed in the relevant ready-to-use (RTU) queue, as explained below.

[0032] Having described the general physical structure and operation of an exemplary embodiment of the data storage system 120, some operational states of the data storage system 120 are now described with reference to FIG7, which is a high-level data flow diagram illustrating the flash memory management functions and data structure used by the controller of the NAND flash memory system 150 (e.g., GPP 132 and / or flash memory controller 140) according to an embodiment.

[0033] As mentioned above, the data storage system 120 typically does not allow external devices (e.g., a host) to directly address and / or access the physical memory locations within the NAND flash memory system 150. In fact, the data storage system 120 is typically configured to present one or more logical disk areas to the host device. Each of these logical disk areas has a contiguous logical address space, thus allowing the host device to read data from logical block addresses (LBAs) within the logical address space and write data to those logical block addresses. Simultaneously, one or more controllers at various levels (e.g., RAID controller 124, flash memory controller 140, and GPP 132) are allowed to control where the data associated with the various LBAs actually resides within the physical memory locations of the NAND flash memory system 150. In this way, the performance and lifespan of the NAND flash memory system 150 can be intelligently managed and optimized. In the illustrated embodiment, each flash memory controller 140 uses a logic-to-entity address translation (LPT) data structure, such as a LPT table 152, to perform LBT translation on the associated set of LBAs. This translated data structure can be stored in the associated flash memory controller volatile memory 144. It should be noted that the logical addresses supplied to the flash memory controller 140 may differ from the logical addresses initially supplied to the data storage system 120, because various components within the data storage system 120 can perform address translation operations between external devices and the flash memory controller 140.

[0034] Flash memory management code running on GPP 132 tracks erased blocks in NAND flash memory system 150 that are ready for use (RTU) queues 700, such queues may be stored, for example, in GPP memory 134. In the depicted embodiment, the flash memory management code running on GPP 132 preferably maintains one or more RTU queues 700 per plane or channel, and the identifiers of each erased block to be reused are queued in the RTU queue 700 corresponding to one of its channels. For example, in one embodiment, for each channel, the RTU queue 700 includes a separate RTU queue 700 for each of a plurality of block health levels. In various implementations, it has been found that 2 to 8 RTU queues 700 per plane (and the corresponding number of block health levels) are sufficient.

[0035] The block equivalence construction function 702 (e.g., executed by flash memory management code running on GPP 132) constructs new block equivalences from erased blocks queued in the RTU queue 700. As mentioned above, the block equivalences are preferably formed from blocks residing in different channels with the same or similar health status (i.e., expected remaining lifespan). This means that the block equivalences can be easily constructed by extracting the blocks of the new block equivalence from the corresponding RTU queues 700 in different planes or channels using the block equivalence construction function 702. The new block equivalences are then queued in the flash memory controller 140 for data placement by the data placement function 704.

[0036] The data placement function 704 includes an open block queue 706 that tracks identifiers of unprogrammed blocks in the block equivalence constructed by the block equivalence construction function 702. As further shown in FIG7, the data placement function 704 also includes a cache engine 714 for writing host write data to the host write cache (HWC) 146 and for writing reposition write data to the reposition write buffer 148. The data placement function 704 also includes a dump engine 716 for writing data from the host write cache 146 and the reposition write buffer 148 to open blocks of the NAND flash memory system 150 identified in the open block queue 706.

[0037] In response to a host write command received from a host such as processor system 102, the data placement function 704 of flash memory controller 140 determines, by referring to LPT table 152, whether the target LBA indicated in the host write command is currently mapped to a physical page in NAND flash memory system 150, and if so, changes the state of each data page currently associated with the target LBA to indicate that it is no longer valid. Cache engine 714 also writes the host write data of the host write command to host write cache memory 146. Once the update of host write cache memory 146 is complete, cache engine 714 can immediately provide an acknowledgment message ("Ack") to the publishing host via I / O channel 110. Cache engine 714 also updates the entries in LPT 704 for the LBA indicated by the host write command to point to the location of the host write data in host write cache memory 146.

[0038] To serve host write commands, the data placement function 702 additionally allocates page equalities as necessary to store the write data of the host write command and any unupdated data from the existing page equalities (if any) of the target of the host write command (i.e., if the write request is smaller than a logical page, there is still valid data that needs to be processed in a read-modify-write manner), and / or stores the write data of the host write command and any unupdated (i.e., still valid) data from the existing page equalities (if any) of the target of the host write command to the allocated page equalities with remaining free space. Page equalities can be allocated from a block equality to store data or from a new block equality. In a preferred embodiment, page equality allocation can be based on the health of the blocks available for allocation and the "hotness" (i.e., the estimated or measured write access frequency) of the LBA of the write data. The dump engine 716 of the data placement function 704 then writes the host-written data and associated post-processor data (e.g., CRC and ECC values) to the pages of the allocated page region identified in the open block queue 706 for each codeword from the host write cache 146, and additionally writes parity information to the data protection pages of the allocated page region as needed. The dump engine 716 also updates the LPT table 152 to associate the LBA of the host-written data with the address of the physical page in the NAND flash memory 150 used to store the written data. Thereafter, the flash memory controller 140 can access the data from the NAND flash memory 150 by referring to the LPT table 152 to serve host read commands.

[0039] Once all pages in a block equivalence have been written to or the block equivalence has been otherwise closed, the flash memory controller 140 places an identifier for the block equivalence on one of the occupied block queues 708. The flash memory management code running on GPP 132 uses this identifier to track the block for obsolescence collection and other management functions. As mentioned above, the pages are invalidated by the write procedure, and therefore a portion of the NAND flash memory system 150 becomes unused. The associated flash memory controller 140 (and / or GPP 132) ultimately needs to reclaim this space through obsolescence collection performed by obsolescence collector 720. Obsolescence collector 720 selects a specific block equivalence for obsolescence collection based on several factors, including, for example, the health of the physical blocks within the block equivalence and how much data within the physical blocks is invalid. In at least one embodiment, discarded item collection is performed on an entire block equivalence region, and the discarded item collector 720 issues a relocation write command to the cache engine 714 of the data placement function 704 to relocate the still valid data in the discarded item collection block equivalence region to another block equivalence region. In a NAND flash memory system 150 implementing a hybrid tiered configuration, which includes a first set of physical blocks operating in a higher storage density mode (e.g., QLC mode) and a second set of physical blocks operating in a lower storage density mode (e.g., SLC mode), it is necessary to allow discarded item collection data to be written from an old block operating in either mode to a new block operating in either mode. Therefore, the relocation write command issued by the discarded item collector 720 can specify the desired operating mode of the target block equivalence region to support, for example, QLC to QLC, SLC to QLC, SLC to SLC, or QLC to SLC discarded item collection.

[0040] As further indicated in Figure 7, the flash memory management functions performed by GPP 132 and / or flash memory controller 140 further include: a wear equalizer 722, which requests the relocation of data stored in block equal areas in occupied block queue 708 to balance wear across blocks; and a cluster equalizer 724, which requests the relocation of data stored in certain block equal areas to allow reconfiguration to constitute some or all of the data in the block, thereby operating in different operating modes (e.g., QLC or SLC).

[0041] Based on the relocation write command received by the self-abandoned item collector 720, wear equalizer 722, and cluster balancer 724, the cache engine 714 stores the relocation write data from the old block equivalent area into the relocation write buffer 148 in the flash memory controller volatile memory 144. Furthermore, the cache engine 714 can update the LPT table 152 to point to a different location in the relocation write buffer 148. Once all still valid data has been moved from the old block equivalent area and written to a new page in the allocated page equivalent area identified in the open block queue 706, the dump engine 716 updates the LPT table 152 to remove the current association between the logical address and physical address of the data, and associates the LBA of the relocated data with the address of the physical page in the NAND flash memory 150 used to store the relocated data. Next, the old block equal-size area is decomposed, thus deassociating the blocks and reordering the block identifiers into the erase queue 710, which may include one erase queue 710 per channel. The block erase function 712 of the flash memory controller 140 then erases each block that was previously formed into the decomposed block equal-size area and increments the associated programmed / erase (P / E) cycle count of the block in the management data structure 158. Based on the health metrics of each erased block, each erased block is either discarded (i.e., no longer used to store user data) or alternatively prepared for reuse by placing the block identifier in the appropriate ready-to-use (RTU) queue 700 in the associated GPP memory 134.

[0042] Figure 7 further illustrates the flash memory management functions of GPP 132 and / or flash memory controller 140, which also include receiving and servicing various read commands. These read commands include host read commands that specify LBAs translated into physical addresses by reference to LPT 152. Additionally, read commands include relocation read commands issued to facilitate the operation of the discarded item collector 720, wear equalizer 722, and cluster balancer 724, as previously described. Read commands may also include read commands initiated by a read scrubber 730, which periodically traverses all pages in all occupied blocks to ensure that data remains readable after persistence.

[0043] In response to various read commands, the flash memory controller 140 initiates the reading of one or more codewords from the relevant physical pages of the NAND flash memory system 150. Each codeword read from the NAND flash memory system 150 is processed by the error correction code (ECC) engine 732 to detect and correct (if possible) bit errors in the codeword (if present). After correction, the ECC engine 732 forwards the data read by the host read command to the requesting host (e.g., one of the processor systems 102). The ECC engine 732 also reports codewords with high bit error rate (BER) to the background health checker 734. Based on the report of codewords with high BER, the background health checker 734 selectively commands the calibration engine 736 to perform read voltage threshold calibration and / or data verification on one or more page groups containing the codeword, as further described below with reference to Figures 10 and 11.

[0044] As mentioned above, the programmed voltage distribution of memory cells can change during the operation of a NAND flash memory device, for example, due to programming / erase cycles, data retention, read interference, programming interference, hammer effect, and / or other reasons. Figure 8 shows an example of the initial and subsequent programmed voltage distribution of memory cells in a block of illustrative three-level cell (TLC) NAND flash memory. Specifically, Figure 8 depicts eight voltage distributions 800a, 802a, 804a, 806a, 808a, 810a, 812a, and 814a, each representing a different individual three-bit value programmed into a memory cell of a block of TLC NAND flash memory. During initial programming, the bit values ​​stored in individual memory cells are distinguished by referring to seven initial read voltage thresholds: 820a, 822a, 824a, 826a, 828a, 830a, and 832a.

[0045] Figure 8 illustrates the following operational scenario: over time, charge decapture causes the voltage distribution to shift towards a lower voltage, as shown by subsequent voltage distributions 800b, 802b, 804b, 806b, 808b, 810b, 812b, and 814b. Without calibrating the read voltage threshold to accommodate the voltage distribution shift, errors in reading data from memory cells can increase to the point where the ECC engine 732 can no longer correct errors and the data stored in the memory cells becomes unreadable. Therefore, to reduce data errors and avoid data loss, the controller of TLC NAND flash memory preferably performs read voltage threshold calibration to determine the voltage offset required to achieve the improved read voltage thresholds 820b, 822b, 824b, 826b, 828b, 830b, and 832b for subsequent voltage distributions 800b, 802b, 804b, 806b, 808b, 810b, 812b, and 814b.

[0046] In at least one embodiment, the controller (e.g., GPP 132 and / or flash memory controller 140) implements a calibration engine 736 that performs calibrations of varying ranges in a variety of calibration operations. For example, in the embodiment of FIG9, the calibration engine 736 may perform a “full block calibration” covering all page groups in a given block or a “single page group calibration” on only a single page group of the block. In the embodiment depicted herein, if the calibration engine 736 chooses to perform a single page group calibration, the calibration engine 736 preferably establishes a read voltage threshold for reading all physical pages in the page group based on the optimal voltage threshold of the affected page in the page group, which triggers calibration upon read. An example of this single page group calibration is described in more detail below with reference to block 1020 of FIG10. After calibrating a single affected page that is considered to represent all physical pages in the page group, the calibration engine 736 may apply the voltage threshold determined for the affected page to all physical pages in the page group. The calibration engine 736 can also verify the calibration as appropriate, as discussed below regarding blocks 1022 to 1024 of Figures 10 and 11.

[0047] Figure 9 further illustrates that, in some situations, the calibration engine 736 may optionally perform full-block calibration by repeatedly performing page group calibration for each page group in the block. Examples of this full-block calibration are described in more detail below with reference to blocks 1012 to 1018 of Figure 10. In at least some embodiments, the calibration engine 736 may support a variety of different calibration techniques that can be selectively applied to each page group to achieve the desired balance between the number of reads performed during read voltage threshold calibration and the degree of optimization of the voltage threshold. For example, so-called "fast" calibration may be used to perform calibration for any given page group, where one or more voltage threshold offsets are determined only for a single sample physical page of the page group and then these offsets are applied to all physical pages in the page group. The selection of the sample page may be randomized based on characteristic data, operational data (e.g., health status), or cyclic selection. Fast calibration involves a substantially fewer number of calibration reads than "normal" calibration, in which the voltage offset of each of the read voltage thresholds for all physical pages in a page group is determined individually using a limited range of voltage offsets (e.g., three voltage offsets above and below each current read voltage threshold). This normal calibration technique also uses fewer calibration reads than the "extended" calibration technique, in which the voltage offset of each of the read voltage thresholds for all physical pages in a page group is determined individually using a larger range of voltage offsets (e.g., all possible voltage offsets above and below each current read voltage threshold). After calibrating each page group, calibration engine 736 may verify the calibration of that page group as appropriate, as discussed below with respect to blocks 1022 to 1024 of Figures 10 and 11. Calibration techniques used for full-block calibration, such as fast, normal, or extended calibration, are efficient calibration techniques in most cases, but in certain situations (e.g., when the variability within a page group is greater than expected), they may not be able to determine the read voltage thresholds that enable successful reading of all pages in the page group. Furthermore, the page that triggers calibration may be among the uncalibrable pages. Although single-page group calibration can also cause other pages in the page group to become uncalibrable, single-page group calibration has the advantage of a significantly higher probability that the affected pages will become readable. On the other hand, if calibration engine 736 only uses single-page group calibration, the total calibration overhead can increase significantly with higher variability within the page group, because the page group will need to be recalibrated more frequently. Therefore, the full-block and single-page group calibration techniques implemented by calibration engine 736 are complementary.

[0048] Referring now to FIG. 10, a high-order logic flowchart is depicted according to an exemplary method of one embodiment, by which a controller calibrates the read voltage thresholds of one or more page groups of a physical block of non-volatile memory. For ease of understanding, the illustrated program described with further reference to the embodiment shown in FIG. 7 can be executed, for example, by the GPP 132 and / or flash memory controller 140 of FIG. 2.

[0049] The procedure in Figure 10 begins at block 1000 and continues to block 1002, where the background health checker 734 receives an error report from the ECC engine 732 regarding a codeword read from the NAND flash memory system 150 in response to a read command. In response to receiving the error report, the background health checker 734 determines at block 1004 whether the BER reported by the ECC engine 732 for the codeword meets (e.g., is greater than or equal to) the calibration threshold. For example, the background health checker 734 may set the calibration threshold to be equal to or lower than the BER of the codeword that cannot be corrected by the ECC engine 732. In response to determining at block 1004 that the BER reported by the ECC engine 732 does not meet the calibration threshold, the procedure in Figure 10 ends at block 1030 until the background health checker 734 receives a subsequent error report. However, if the background health checker 734 determines that the BER meets the calibration threshold at block 1004, the background health checker 734 selects the range of calibration to be performed (block 1006).

[0050] In the illustrated example, at block 1006, the background health checker 734 selects between performing sub-block page group calibration of one or more page groups (hereinafter assumed to be single-page group calibration of a page group containing the codeword that triggered the calibration, as shown in Figure 9) and performing full block calibration of all page groups in the block. The background health checker 734 may make the selection shown at block 1006 based on one or more criteria such as: the error count reported by the ECC engine 732, the data retention duration, and / or the type of read command that leads to the reading of the codeword in question (e.g., host read, relocation read, read purger read, etc.). For example, in some embodiments, if the read command that leads to the reading of the codeword is a host read or a relocation read, the background health checker 734 preferably selects single-page group calibration, and if the read command is issued by the read purger 730, the full block calibration is preferred. As shown in decision block 1010, if the background health inspector 734 selects full block calibration at block 1006, the calibration process continues to block 1012 and subsequent blocks. Alternatively, if the background health inspector 734 selects single-page group calibration at block 1006, the calibration process continues to block 1020 and subsequent blocks.

[0051] Referring now to block 1012, to perform a full block calibration, the background health checker 734 selects the first page group to be calibrated in the block (or, in a subsequent iteration, selects the next page group). The background health checker 734 may select the page group to be calibrated at block 1012, for example, based on a page group sorting to reduce read interference and / or other undesirable inter-page interference effects. Furthermore, at block 1014, the background health checker 734 selects the calibration technique to be performed on the selected page group by the calibration engine 736. The selected calibration technique may depend on various status information being tracked by the GPP 132 or the flash memory controller 140. For example, at block 1014, the background health checker 734 may select from the fast, normal, and extended calibration techniques described above with reference to Figure 9. For example, the background health checker 734 may make the selection depicted at block 1014 based on the BER of the codeword that triggered the calibration, wherein one of the more resource-intensive types of calibration is performed on the codeword with a higher BER and one of the less resource-intensive types of calibration is performed on the codeword with a lower BER.

[0052] At block 1016, the background health checker 734 initiates the calibration of a selected page group using the calibration engine 736. In some embodiments, each physical page stores multiple codewords, and calibration is performed only on a single codeword in each physical page of the page group accessed during the calibration process. The calibration engine 736 uses an iterative process to search for the optimal read voltage threshold. In this iterative process, the calibration engine 736 issues multiple read commands using different read voltage threshold offsets and selects those commands that minimize the number of errors detected by the ECC engine 732. After calibrating the page group, the calibration engine 736 updates the Vth shift data 154 of the page group with a new offset relative to the preset voltage threshold. After calibrating the selected page group at block 1016, the procedure of FIG10 branches and continues parallel to block 1018, and, if implemented, continues to the optional block 1022 described below. Block 1018 displays the background health checker 734 determining whether all page groups in the block have been calibrated. If not, the procedure returns to the already described block 1012. However, if the background health checker 734 determines at block 1018 that all page groups in the block have been calibrated by the calibration engine 736, the procedure continues from block 1018 to block 1026, which is described below.

[0053] Referring now to block 1020, based on the background health checker 734 selecting to perform single-page group calibration, the background health checker 734 initiates calibration of the page group containing the codeword that triggers calibration via the calibration engine 736. In a preferred embodiment, the background health checker 734 causes the calibration engine 736 to select the physical page storing the affected codeword that triggers calibration as a sample page representing all pages in the page group. In some embodiments where multiple codewords are stored per physical page, the background health checker 734 may further limit calibration reads to the affected codeword that triggers calibration. The calibration engine 736 may then use the same iterative calibration reads described above in reference block 1016 to determine the optimal read threshold voltage. In some embodiments or operating scenarios, after calibrating the affected codeword or the read voltage threshold of the physical page storing the affected codeword, the calibration engine 736 may update the Vth shift data 154 with an updated value indicating the offset of the read voltage threshold from a preset voltage threshold, so that future read commands for the page group are served using the updated read voltage threshold. In other embodiments or operating scenarios, the read voltage threshold value determined by the calibration engine 736 can alternatively be used to satisfy the read command triggering calibration, but not to update the Vth shift data 154. For example, if data in a page group and / or block may be relocated, the discard item collector 720, wear equalizer 722, cluster equalizer 724, read clearer 730, or background health checker 734 can determine that the new offset of the read voltage threshold should not be used to update the Vth shift data 154, for example, as discussed below with reference to block 1122 of FIG11. After calibrating a single page group at block 1020, the procedure of FIG10 forks and continues parallel to block 1026, and if implemented, continues to optional block 1022.

[0054] Block 1022 depicts a background health checker 734 determining whether to perform verification on a page group that has already undergone calibration at block 1016 or block 1020. For example, at block 1022, the background health checker 734 may selectively bypass verification to reduce additional load based on factors such as: page type (e.g., bottom page, top page, extra page, top page, etc.), changes in voltage thresholds due to page group calibration, block health status, P / E cycle count, BER before and after calibration, layer (word line) position of the page group in the block, and / or the number of times the block, page group, or page has been read since programming. For example, in one embodiment, the background health checker 734 may determine to bypass or abandon verification based on the fact that the codeword triggering calibration can be corrected by the ECC engine 732. In other embodiments, even if the codeword triggering calibration can be corrected by the ECC engine 732 based on one or more factors, the background health checker 734 may still determine to perform verification, whereby the one or more factors indicate that the optimal read voltage threshold values ​​for different codewords of a given entity page or different entity pages within the same page group may diverge. In response to a negative determination at block 1022, the branch of the program continues to connection point 1028. However, if the background health checker 734 determines to perform verification on the page group at block 1022, the program continues to block 1024, which shows the background health checker 734 performing verification on the page group. An exemplary procedure for performing verification at block 1024 is described below with reference to Figure 11. After block 1024, the program continues to connection point 1028.

[0055] Referring now to block 1026, if the read command that triggers the calibration of the read voltage threshold is a host read command, the controller will send the requested read data (read using the newly calibrated read voltage threshold and, if necessary, calibrated by ECC engine 732) back to the host. Thereafter, the procedure in Figure 10 continues to connection point 1028, and ends at block 1030 once the verification of all page groups from the calibration initiation (if present) has been completed at block 1024.

[0056] Referring now to Figure 11, a high-order logic flowchart of an exemplary method according to one embodiment is shown, by which the controller verifies the result of the read voltage threshold calibration as appropriate. The illustrated program can be executed, for example, by the GPP 132 and / or flash memory controller 140 of Figure 2, and assumes an embodiment in which each physical page stores multiple codewords.

[0057] The procedure in Figure 11 begins at block 1100 and continues to block 1102, which depicts the background health checker 734 issuing a read command from a sample entity page of the relevant page group to read codewords not used for calibration. For example, if a single-page group calibration is performed, the codeword read at block 1102 is a different codeword from the affected codeword that triggered the calibration, located on the same entity page. If a page group is calibrated during a full-block calibration, the codeword may be a codeword representing a sample page of the page group that was not used to calibrate the page group. At block 1104, the background health checker 734 determines whether the divergence between the calibrated BER of the codeword used for calibration and the BER of another codeword read at block 1102 satisfies (e.g., greater than or equal to) a first divergence threshold. If so, the background health checker 734 recognizes that the calibration was unsuccessful in reducing the BER on the affected entity page or sample entity page, and therefore performs mitigation at block 1120, as described below. However, if the background health checker 734 determines at block 1104 that the divergence between the BERs of the codewords does not meet the first divergence threshold, the procedure continues to block 1106.

[0058] Block 1106 depicts the background health checker 734 issuing a read command from an entity page in a relevant page group other than the affected entity page or sample entity page to read codewords not used for calibration. The background health checker 734 then determines at block 1108 whether the divergence between the calibrated BER of the codeword used for calibration and the BER of another codeword read at block 1106 satisfies (e.g., greater than or equal to) a second divergence threshold. In various embodiments, the second divergence threshold may be the same as or different from the first divergence threshold. In response to determining at block 1108 that the BER divergence satisfies the second divergence threshold, the background health checker 734 recognizes that the calibration was unsuccessful in reducing the BER on the page group and therefore performs mitigation at block 1120, as described below. However, if the background health checker 734 determines at block 1106 that the divergence between the BERs of the codewords does not meet the second divergence threshold, then the calibration of the page group is verified as successful, and the verification process ends at block 1130.

[0059] Referring now to block 1120, to mitigate BER divergence detected at block 1104 or block 1108, background health checker 734 may perform any of a variety of mitigation activities. In the depicted example, background health checker 734 triggers the relocation of all valid data in the block containing calibrated page groups (e.g., via discarded item collector 720) (block 1122). It should be noted that if the affected pages require reading valid data, the relocation procedure may better utilize single-page group calibration. Background health checker 734 may also determine whether to discard a block at block 1124, for example, based on whether a threshold number of BER divergences have been detected in the block and / or whether the calibrated BER of a sample page of the page group is substantially less than the correction limit of ECC engine 732. In response to block health checker 734 determining at block 1122 that the block should not be evicted, the controller recycles the block (block 1126) via erase queue 710, block erase function 712, and RTU queue 700 as described above. Otherwise, the controller removes the block from use (block 1128). After block 1126 or block 1128, the procedure in Figure 11 ends at block 1130.

[0060] As described, in at least one embodiment, the controller of the non-volatile memory detects errors in data read from a specific physical page of the non-volatile memory. Based on the detected error, the controller performs a read voltage threshold calibration on a page group including the specific physical page and a plurality of other physical pages. Performing the read voltage threshold calibration includes calibrating the read voltage threshold only based on the specific physical page of the page group. After the controller performs the read voltage threshold calibration, the controller verifies the calibration as appropriate. Verifying the calibration includes determining whether the bit error rate within the page group is diverging, and if so, mitigating the divergence. Mitigating the divergence includes relocating the data from the page group to another block of the non-volatile memory.

[0061] Advantageously, the described calibration technique allows the controller to provide online calibration in the data read path, and thus respond more quickly to errors in the data read path. Furthermore, the described calibration technique ensures that the entity page that causes the calibration to be performed will be used as a sample entity page for its page group.

[0062] In at least some embodiments, page group calibration may be incorporated into an existing calibration architecture that also includes full block calibration. The controller may determine the appropriate range of calibration based on one or more factors. For example, the controller may select full block calibration for calibration triggered by a read-clearer read command, and may select single-page group calibration for calibration triggered by a relocation read command or a host read command.

[0063] The present invention may be a system, a method, and / or a computer program product. The computer program product may include one (or more) computer-readable storage media having computer-readable program instructions thereon to cause a processor to perform the present invention.

[0064] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory flash drive, floppy disk, mechanically encoded device (such as a punch card or a raised structure in a groove on which instructions are recorded), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as temporary signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating via waveguides or other transmission media (e.g., light pulses transmitted via fiber optic cables), or electrical signals transmitted via wires.

[0065] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to individual computing / processing devices or via a network (e.g., the Internet, local area network, wide area network, and / or wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Network adapter cards or network interfaces in each computing / processing device receive computer-readable program instructions from the network and forward them to computer-readable storage media within the individual computing / processing device.

[0066] The computer-readable program instructions used to perform the operations of this invention may be compiler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages. These one or more programming languages ​​include object-oriented programming languages ​​such as Smalltalk, C++, or similar languages, and conventional procedural programming languages ​​such as the "C" programming language or similar languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuit systems, including, for example, programmable logic circuit systems, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute computer-readable program instructions by personalizing the electronic circuit system with state information of computer-readable program instructions in order to perform the present invention.

[0067] The present invention is described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that the blocks of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0068] Such computer-readable program instructions may be provided to the processor of a general-purpose computer, special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions, which are executed by the processor of the computer or other programmable data processing device, create components for implementing the functions / actions specified in one or more flowchart and / or block diagram blocks. Such computer-readable program instructions may also be stored in a computer-readable storage medium that instructs a computer, programmable data processing device, and / or other apparatus to function in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of writing that includes instructions for implementing the functions / actions specified in the one or more flowchart and / or block diagram blocks.

[0069] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing equipment or other device to cause a series of operational steps to be executed on the computer, other programmable equipment or other device to produce a computer-implemented program, such that the instructions executed on the computer, other programmable equipment or other device perform the functions / actions specified in one or more flowchart and / or block diagram blocks.

[0070] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, fragment, or portion of instructions, containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions mentioned in a block may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or such blocks may sometimes be executed in reverse order. It will also be noted that the blocks illustrated in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0071] Although the invention has been specifically illustrated as described with reference to one or more preferred embodiments, those skilled in the art will understand that various changes in form and detail may be made in the invention without departing from the spirit and scope of the appended claims. For example, although a data storage system including a flash memory controller that directs certain functions has been described, it should be understood that the invention may alternatively be implemented as a program product including a storage device storing program code that can be processed by a processor to perform or cause to perform such functions. As used herein, "storage device" is specifically defined to include only legal articles and excludes the transmission medium itself, the transient propagation signal itself, and the form of energy itself.

[0072] Furthermore, although embodiments including the use of NAND flash memory have been described, it should be understood that embodiments of the present invention can also be used with other types of non-volatile random access memory (NVRAM), including, for example, magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), phase-change memory (PCM), battery backup DRAM or other non-volatile memory technologies, and combinations thereof.

[0073] The figures and written descriptions of specific structures and functions described above are not intended to limit the scope of the applicant's invention or the scope of the claims attached. Rather, the figures and written descriptions are provided to teach any person skilled in the art to make and use the invention for which patent protection is sought. Those skilled in the art will understand that, for clarity and understanding, not all features of commercial embodiments of the invention have been described or shown. Those skilled in the art will also understand that the development of actual commercial embodiments of the invention will require numerous implementation-specific decisions to achieve the developer's ultimate goals for the commercial embodiments. These implementation-specific decisions may include, and may not be limited to, compliance with system-related, enterprise-related, governmental-related constraints and other constraints, which may vary depending on the specific implementation, location, and periodicity. While the developer's efforts may be complex and time-consuming in an absolute sense, such efforts will be routine for those skilled in the art who benefit from this disclosure. It must be understood that the invention disclosed and taught herein is readily available in numerous and varied modifications and alternative forms. Finally, the use of singular terms such as, but not limited to, "one" is not intended to limit the number of items. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a high-order block diagram of a data processing environment according to one embodiment;

[0008] Figure 2 is a more detailed block diagram of an exemplary flash memory card of the data storage system of Figure 1 according to an embodiment;

[0009] Figures 3 to 6 illustrate exemplary configurations of physical memory within a NAND flash memory system according to one embodiment;

[0010] Figure 7 is a high-level data flow diagram of the flash memory management functions and data structure used by the controller of a NAND flash memory system according to an embodiment;

[0011] Figure 8 depicts the initial and subsequent programmed voltage distribution of an exemplary three-dimensional cell (TLC) NAND flash memory;

[0012] Figure 9 illustrates different read voltage threshold calibration techniques implemented by a calibration engine according to one embodiment;

[0013] Figure 10 is a high-order logic flowchart of an exemplary method according to one embodiment, by which a controller calibrates the read voltage threshold of one or more page groups of a physical block of non-volatile memory; and

[0014] Figure 11 is a high-order logic flowchart of an exemplary method according to one embodiment, by which the controller verifies the result of reading the voltage threshold calibration as appropriate.

Claims

1. A method for read voltage threshold calibration in a non-volatile memory, the method comprising: a controller of the non-volatile memory detecting errors in data read from a specific physical page of the non-volatile memory; and based on the detection of the errors, the controller performing a read voltage threshold calibration on a page group including the specific physical page and a plurality of other physical pages, wherein performing the read voltage threshold calibration includes calibrating the read voltage threshold only based on the specific physical page of the page group.

2. As in request item 1, where: The specific entity page stores multiple codewords of data, including a first codeword and a second codeword that detect the error; performing the read voltage threshold calibration includes calibrating the read voltage threshold based on the first codeword rather than the second codeword.

3. The method of claim 1, further comprising: the controller selecting a calibration range from single-page group calibration of only a single page group and full-block calibration of all multiple page groups in a block of non-volatile memory.

4. The method of request item 3, wherein the selection includes reading the data from the non-volatile memory in response to a read clearer read command initiated by the controller, and the controller selects the full block calibration.

5. The method of request item 3, wherein the selection includes reading the data from the non-volatile memory in response to a host read command initiated by a host, and the controller selects the single-page group calibration.

6. The method of claim 1, further comprising: after the controller performs the read voltage threshold calibration, the controller verifies the calibration, wherein verifying the calibration includes: Determine whether the bit error rate within the page group is diverging; and based on the controller's determination of whether the bit error rate within the page group is diverging, the controller mitigates the divergence, wherein the mitigation includes the controller relocating data from the page group to another block of the non-volatile memory.

7. As in request item 1, where: The page group is a first page group; and the method further includes: after read voltage threshold calibration of a second page group in the non-volatile memory, the controller determines a possibility that the bit error rate in the second page group is diverging; and based on determining a low possibility that the bit error rate in the second page group is diverging, the controller avoids verifying the read voltage threshold calibration of the second page group.

8. A program product comprising: a storage device; and program code stored in the storage device and executable by a controller of a non-volatile memory to cause the controller to perform the following operations: detecting errors in data read from a specific physical page of the non-volatile memory; and, based on the detection of such errors, performing a read voltage threshold calibration on a page group including the specific physical page and a plurality of other physical pages, wherein performing the read voltage threshold calibration includes calibrating the read voltage threshold only based on the specific physical page of the page group.

9. As in request item 8, the program product, wherein: The specific entity page stores multiple codewords of data, including a first codeword and a second codeword that detect the error; performing the read voltage threshold calibration includes calibrating the read voltage threshold based on the first codeword rather than the second codeword.

10. The program product as requested in item 8, wherein the program code further causes the controller to perform the following operations: select a calibration range from single-page group calibration of only a single page group and full-block calibration of all multiple page groups in a block of non-volatile memory.

11. The program product as requested in item 10, wherein the selection includes reading the data from the non-volatile memory in response to a read clearer read command initiated by the controller, and the controller selects the full block calibration.

12. As in request item 10, wherein the selection includes reading the data from the non-volatile memory in response to a host read command initiated by a host, the controller selects the single-page group calibration.

13. The program product as requested in item 8, wherein the program code further causes the controller to perform the following operation: After the controller performs the read voltage threshold calibration, verifying the calibration, wherein verifying the calibration includes: Determine whether the bit error rate within the page group is diverging; and based on the controller's determination of whether the bit error rate within the page group is diverging, mitigate the divergence, wherein the mitigation includes the controller relocating data from the page group to another block of the non-volatile memory.

14. As in request item 8, the program product, wherein: The page group is a first page group; and the code further causes the controller to perform the following operations: after read voltage threshold calibration of a second page group in the non-volatile memory, determine a possibility that the bit error rate in the second page group is diverging; and based on the determination of a low possibility that the bit error rate in the second page group is diverging, avoid verifying the read voltage threshold calibration of the second page group.

15. A method of controlling a non-volatile memory, the method comprising: a controller performing a read voltage threshold calibration on a group of pages comprising a plurality of physical pages of the non-volatile memory; and, after the controller performs the read voltage threshold calibration, the controller verifying the calibration, wherein verifying the calibration includes: Determine whether the bit error rate within the page group is diverging; and based on the controller's determination of whether the bit error rate within the page group is diverging, the controller mitigates the divergence, wherein the mitigation includes the controller relocating data from the page group to another block of the non-volatile memory.

16. As in request item 15, wherein: The page group is a first page group; and the method further includes: after read voltage threshold calibration of a second page group in the non-volatile memory, the controller determines a possibility that the bit error rate in the second page group is diverging; and based on determining a low possibility that the bit error rate in the second page group is diverging, the controller avoids verifying the read voltage threshold calibration of the second page group.

17. The method of claim 16, wherein determining the probability of the equibit error rate divergence in the second page group includes determining the probability of the equibit error rate divergence based on at least one of the following: a page type of a sample page of the second page group in the read voltage calibration of the second page group; a physical layer of a memory chip containing the sample page; and the health status of a block of the non-volatile memory including the second page group.

18. The method of request 15, wherein determining whether the bit error rate within the page group is divergent includes determining whether the bit error rate is divergent between codewords in a particular page of the page group.

19. The method of request 15, wherein determining whether the bit error rate within the page group is divergent includes determining whether the bit error rate is divergent between different entity pages in the page group.

20. The method of claim 15, wherein performing the read voltage threshold calibration includes calibrating the read voltage threshold of the page group solely based on data read from a specific entity page of the page group that self-detected an error in response to a read command.

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