Wafer bonding method using selective deposition and surface treatment

Abstract

A semiconductor package is disclosed. The semiconductor package includes a first substrate including a first interconnect structure and a first bonding layer adjacent the first interconnect structure. The semiconductor package includes a second substrate including a second interconnect structure and a second bonding layer adjacent the second interconnect structure. The first bonding layer and second bonding layer each include a metal oxide.

Description

[Technical Field]

[0001] This application claims the rights and priority of U.S. Provisional Patent Application No. 63 / 242,182, filed September 9, 2021, entitled “Wafer Bonding Method Using Selective Deposition and Surface Treatment,” the entire contents of which are incorporated herein by reference for all purposes.

[0002] This disclosure relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, and includes microfabrication methods. [Previous Technology]

[0003] The semiconductor industry has developed rapidly due to the continuous improvement in the integrated density of many electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integrated density has come from the repeated reduction in the size of the smallest feature, which allows more components to be integrated into a given area. Due to the recent increase in demand for miniaturization, higher speed, greater bandwidth, and lower power consumption and latency, the demand for smaller and more innovative semiconductor die packaging technologies is also growing. [Summary of the Invention]

[0004] Wafer-to-wafer and chip-to-chip bonding is implemented to continuously scale power-performance-area-cost (PPAC) for complex circuits such as systems on a chip (SOC). Many bonding technologies utilize oxide-to-oxide bonding and form integrated interconnect structures through hybrid bonding techniques, which can form interconnects at the bonding interface between two wafers or dies. However, prior to bonding the wafers, current technologies typically use at least one etching technique (e.g., wet or dry etching) to recess the interconnect structures (e.g., interconnect structures formed by conductive materials, wires, vias, conductors, pads, etc.) on the corresponding wafers to, for example, allow proper alignment and expansion of the interconnect structures used for interconnects (e.g., during heating or annealing processes). In other words, the etching or recessing process of the interconnect structure may result in rounded corners, voids, or roughness of the interconnect structure.

[0005] This disclosure provides numerous embodiments for the selective deposition of a material (e.g., oxide material, sometimes referred to as an adhesion material) at interconnect portions between two wafers (or dies). For example, each wafer may include separate substrates (e.g., a first substrate for a first wafer and a second substrate for a second wafer). The first and second substrates may include separate interconnect structures (e.g., interconnect structures made of conductive material) and dielectric layers surrounding the sidewalls and bottom of the interconnect structures. Selective deposition techniques can be performed to deposit oxide material above the top surface of the dielectric layer. After depositing the oxide material, at least one adhesion / coupling technique can be used to align and adhere / connect / couple the two wafers (e.g., one wafer is flipped) via the oxide material. By coupling the wafers, channels can be formed extending from the top surface of the corresponding interconnect structure. Thus, the first and second substrates can be heated / annealed to expand and solidly connect the interconnect structures of the two wafers. In this way, this disclosure avoids or minimizes rounded corners, voids, and / or roughness of the interconnect structure when forming recesses to couple the wafers.

[0006] One embodiment includes a semiconductor package. The semiconductor package includes a first substrate. The first substrate includes a first interconnect structure. The first substrate includes a first adhesion layer portion adjacent to the first interconnect structure. The semiconductor package includes a second substrate coupled to the first substrate. The second substrate includes a second interconnect structure. The second substrate includes a second adhesion layer portion adjacent to the second interconnect structure. At least one of the first adhesion layer portion and the second adhesion layer portion includes a metal oxide.

[0007] The top surface of the first interconnect structure is in contact with the top surface of the second interconnect structure, and the top surface of the first bonding layer portion is in contact with the top surface of the second bonding layer portion. The first substrate further includes a first dielectric material embedded in the lower portion of the first interconnect structure, and the second substrate further includes a second dielectric material embedded in the lower portion of the second interconnect structure.

[0008] The first adhesive layer portion and the second adhesive layer portion are in contact with each other along the adhesive interface. The first substrate further includes a plurality of first device features disposed on the opposite side of the first interconnect structure relative to the second interconnect structure. The second substrate further includes a plurality of second device features disposed on the opposite side of the second interconnect structure relative to the first interconnect structure.

[0009] A first adhesive layer portion is disposed around the upper portion of the first interconnect structure, and a second adhesive layer portion is disposed around the upper portion of the second interconnect structure. The metal oxide is selected from the group consisting of aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), and combinations thereof.

[0010] Another embodiment includes a method of manufacturing a semiconductor package. The method includes providing a first substrate, the first substrate including a first dielectric layer and a first interconnect structure. The method includes selectively forming a first adhesion layer only on the first dielectric layer. The method includes providing a second substrate, the second substrate including a second dielectric layer and a second interconnect structure. The method includes coupling the first substrate to the second substrate based on making the first interconnect structure and the first adhesion layer physically contact the second interconnect structure and the second dielectric layer, respectively.

[0011] The step of coupling the first substrate to the second substrate further includes selectively forming a second adhesive layer only on the second dielectric layer. The method includes coupling the first substrate to the second substrate based on making the first interconnect structure and the first adhesive layer physically contact the second interconnect structure and the second adhesive layer, respectively. The first and second adhesive layers each comprise a material selected from the group consisting of silicon oxide (SiO₂), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), and combinations thereof. The method includes rinsing the first substrate with deionized water to hydrophilize the first adhesive layer.

[0012] The step of coupling the first substrate to the second substrate further includes aligning the first interconnect structure with the second interconnect structure. The method includes bringing a first bonding layer into contact with the second dielectric layer. The method includes annealing the first and second substrates to bring the first interconnect structure into contact with the second interconnect structure.

[0013] The step of selectively forming the first adhesive layer includes performing at least one atomic layer deposition process. Prior to selectively forming the first adhesive layer, the method includes performing a first polishing process on the first substrate to form a first coplanar surface shared by the first dielectric layer and the first interconnect structure.

[0014] After selectively forming the first bonding layer, the top surface of the first interconnect structure is recessed from the top surface of the first bonding layer.

[0015] Yet another embodiment includes a method of manufacturing a semiconductor package. The method includes providing a first substrate including a first dielectric layer and a first interconnect structure exposed on a surface of the first dielectric layer. The method includes forming a first adhesion layer on the first dielectric layer using an atomic deposition process. The method includes providing a second substrate including a second dielectric layer and a second interconnect structure. The method includes attaching the first adhesion layer to the second substrate. The method includes making the first interconnect structure physically contact the second interconnect structure.

[0016] The first adhesive layer comprises a material selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), aluminum oxide (Al2O3), hafnium oxide (HfO2), and combinations thereof. Before bonding the first adhesive layer to the second substrate, the method includes rinsing the first substrate with deionized water to hydrophilize the first adhesive layer.

[0017] The first adhesive layer is formed to a thickness of 1-10 nm, thereby forming a recess between the surface of the first adhesive layer and the surface of the first interconnect structure. After the first adhesive layer is bonded to the second substrate, annealing is performed to allow the first interconnect structure to physically contact the second interconnect structure through the recess. After the first adhesive layer is formed, the top surface of the first interconnect structure is recessed from the top surface of the first adhesive layer.

[0018] These and other embodiments and examples are discussed in detail below. The foregoing information and the following details include illustrative examples of numerous embodiments and examples, and provide an overview or framework for understanding the nature and features of the claims and examples. The accompanying drawings provide illustration and further understanding of the numerous embodiments and examples, and are incorporated into and constitute a part of this specification. Embodiments can be combined, and it will be readily understood that features described in one embodiment of the invention can be combined with other embodiments. Embodiments can be implemented in any convenient form. Unless the context clearly indicates otherwise, as used in the specification and claims, the singular forms "a," "an," and "the" include the plural objects.

Implementation Method

[0022] Reference will now be made to the exemplary embodiments shown in the drawings, and specific terminology will be used to describe the exemplary embodiments. However, it will be understood that this is not intended to limit the scope of the claims or the scope of this disclosure. Those skilled in the art and possessing this disclosure may make changes and further modifications to the inventive features shown herein and the principles of the subject matter shown herein, which are considered to be within the scope of the subject matter disclosed herein. Other embodiments and / or other changes may be used without departing from the spirit or scope of this disclosure. The illustrative embodiments described in the detailed description are not intended to limit the subject matter presented.

[0023] According to one embodiment, a process for manufacturing a semiconductor package is provided, which utilizes selective deposition and (multiple) wafer bonding techniques. By utilizing selective deposition techniques, a recessed region can be formed above the top surface of the interconnect structure of the wafers before coupling or physically connecting the two wafers (or dies). For example, each wafer may include a separate substrate (e.g., a first substrate of a first wafer and a second substrate of a second wafer). The first and second substrates may include separate interconnect structures (e.g., interconnect structures composed of conductive material) and dielectric layers surrounding the sidewalls and bottom of the interconnect structures. Selective deposition techniques can be performed to deposit an oxide material on the top surface of the dielectric layer. After depositing the oxide material, using at least one bonding / coupling technique, the two wafers can be aligned and bonded / connected / coupled via the oxide material (e.g., one wafer is flipped). By coupling the wafers, channels can be formed extending from the top surface of the corresponding interconnect structure. Therefore, the first and second substrates can be heated / annealed to extend and physically connect the interconnect structure of the two wafers. Therefore, this disclosure avoids or minimizes the rounding of corners, voids and / or roughness of interconnect structures when forming recesses to couple wafers, and further enhances the efficiency of wafer bonding (e.g., reduces time).

[0024] Figure 1 shows a flowchart of an illustrative method 100, which uses selective deposition and surface treatment on the surface of a wafer, die, or other substrate to attach (e.g., couple) a surface (e.g., the surface of one wafer) to the surface of another wafer, die, or other substrate. It should be noted that method 100 is merely exemplary and is not intended to limit the scope of this disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 100 of Figure 1, and some of these other operations are only briefly described herein.

[0025] In many embodiments, the operation of method 100 may be associated with perspective and cross-sectional views of an exemplary semiconductor package 200 during various manufacturing stages, as shown in Figures 2A to 6B, which will be discussed in more detail below. It should be understood that the semiconductor package 200 shown in Figures 2A to 6B may include many other devices, such as inductors, fuses, capacitors, coils, etc., which are still within the scope of this disclosure. In general, method 100 may include providing a first substrate 102. The method may include forming a first bonding layer 104 (e.g., sometimes referred to as a first bonding layer portion). The method may include providing a second substrate 106. The method may include forming a second bonding layer 108 (e.g., sometimes referred to as a second bonding layer portion). The method may include coupling the first substrate to a second substrate 110.

[0026] Corresponding to operations 102-108 of FIG1, FIG2A illustrates a perspective view of semiconductor package 200, and FIG2B illustrates a cross-sectional view 300 of semiconductor package 200. At least FIG3A-B may also correspond to operations 102-108 of FIG1. ​​Semiconductor package 200 may include a first wafer (e.g., a top / bottom wafer or die, sometimes referred to as a first substrate) and a second wafer (e.g., a bottom / top wafer or die, sometimes referred to as a second substrate). For simplicity and example, in this document, the first wafer may correspond to the top wafer, and the second wafer may correspond to the bottom wafer. Cross-sectional view 300 may correspond to a cross-sectional view of the first wafer 202 and / or the second wafer 204. In some cases, one or more materials forming the first wafer 202 may be different from those forming the second wafer 204. In some other cases, one or more materials forming the first wafer 202 may be the same as those forming the second wafer 204. For example, wafers 202, 204 may include or correspond to respective substrates (not shown). The substrate of wafers 202 and 204 may be a support structure formed under or around one or more other materials of wafers 202 and 204.

[0027] The substrate can be a semiconductor substrate, such as a host semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate may be, or correspond to, a specific wafer (e.g., 202 or 204), such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; compound semiconductors containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors containing SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The materials of each of the two wafers may be different.

[0028] In some embodiments, the substrate includes a plurality of device features (e.g., transistors, diodes, resistors, etc., not shown for clarity) formed along a surface (e.g., front side) of the substrate and a plurality of interconnect structures (e.g., metal wires, metal vias, etc., not shown for clarity) formed on the device features. The interconnect structures are configured to electrically connect the device features to each other to form an integrated circuit, which can be used as a logic device, memory device, input / output device, etc. These interconnect structures (e.g., interconnect structures formed of conductive materials such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof) may be embedded in one or more dielectric layers, such as 206 (e.g., dielectric layers formed of low-k dielectric materials, such as SiO2), which are sometimes referred to as metallization layers. In other words, each dielectric layer 206 may include a plurality of metal wires and a plurality of metal vias embedded therein. One or more such dielectric layers 206 may be formed above the surface of the substrate (e.g., front side). In some cases, dielectric layer 206 may be formed on the back side of the substrate. Dielectric layer 206 and other materials discussed herein may be formed or deposited using at least one suitable deposition technique.

[0029] As shown, dielectric layer 206 may surround or encircle the sidewalls and bottom of interconnect structures 208. Dielectric layer 206 may expose the top surface of interconnect structures 208. Dielectric layer 206 may extend at least from the bottom of interconnect structures 208 and along the sidewalls of interconnect structures 208. The top surface of interconnect structures 208 may be smooth / flat / slightly recessed with respect to the plane of the top surface of dielectric layer 206.

[0030] After forming the dielectric layer 206 and interconnect structure 208 of wafers 202 and 204, an adhesion layer 210 may be (e.g., selectively deposited) using at least one suitable deposition technique (e.g., selective deposition technique). The adhesion layer 210 may sometimes be referred to as an adhesion film, material, or structure. The adhesion layer 210 may be formed from one or more materials selected from, for example, the group consisting of: silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), aluminum oxide (Al 2O 3), hafnium oxide (HfO 2), or combinations thereof, and other types of metal oxide materials. For example, the adhesion layer 210 may be (e.g., selectively) formed or deposited by performing at least one suitable deposition process, such as atomic layer deposition (e.g., ALD, to deposit material at precise locations), and other types of deposition techniques. Such selective ALD can be termed atomic selective deposition (ASD). Then, layer 210 may be preferentially (or selectively) formed or deposited on dielectric layer 206 (e.g., on the top surface of dielectric layer 206). Due to the preferential nature of the ASD process, layer 210 may not be significantly formed on interconnect structure 208. Such an ASD process can be implemented on either or both of these wafers.

[0031] After (e.g., selectively) forming the bonding layer 210, the top surface of the interconnect structure 208 may be recessed from the top surface of the bonding layer 210, at least as shown in FIG2B. The bonding layer 210 may protrude from the top surface of the dielectric layer 206 by a predetermined height, which is configured for the fabrication / forming / manufacturing process of the semiconductor package 200, such as 1~10nm. In this case, the size (e.g., steepness) of the recess for the top surface of the interconnect structure 208 (e.g., from the top surface of the bonding layer 210) may correspond to the height of the bonding layer 210. At this stage, the interconnect structure 208 may share a common planar surface with the dielectric layer 206 below the bonding layer 210. In some embodiments, the bonding layer 210 may form a channel (e.g., a channel corresponding to the recessed portion) above the interconnect structure 208.

[0032] In some embodiments, prior to selectively forming the bonding layers for wafers 202, 204, at least a suitable polishing process or technique may be used to polish a portion of at least one of the dielectric layer 206 or interconnect structure 208. For example, the multiple surfaces of dielectric layer 206 may include excess portions or material to be removed, such as the top surface of dielectric layer 206. Therefore, a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof may be performed on the surface of dielectric layer 206 (e.g., the top surface) to remove excess material. In another example, the surface of interconnect structure 208 (e.g., the top) may include excess material or protrude beyond the top surface of dielectric layer 206. Therefore, at least one suitable CMP process, an etching process, or a combination thereof may be used to polish or etch interconnect structure 208.

[0033] In many embodiments, the top surface of the polished dielectric layer 206 and the top surface of the interconnect structure 208 may form a common coplanar surface, wherein the top surface of the dielectric layer 206 is flush with the top surface of the interconnect structure 208. For example, before forming the bonding layer, polishing the top surface of the first wafer 202 (e.g., the first substrate) may form a first coplanar surface shared by the dielectric layer 206 and the interconnect structure 208 of the first wafer 202. Similarly, polishing the top surface of the second wafer 204 (e.g., the second substrate) may form a second coplanar surface shared by the dielectric layer 206 and the interconnect structure 208 of the second wafer 204.

[0034] In some embodiments, the surfaces of one or more materials (e.g., dielectric layer 206, interconnect structure 208, or adhesive layer 210) may be treated using at least one suitable surface treatment process or technique, such as a plasma initiation process. For example, the surface of dielectric layer 206 (e.g., the top or exposed surface) may be treated to prepare it for attachment or coupling with adhesive layer 210 (e.g., treating the material forming adhesive layer 210). In another example, the surface of adhesive layer 210 (e.g., the top surface) may be treated to prepare it for attachment with a different adhesive layer (e.g., attaching an adhesive layer of first wafer 202 to an adhesive layer of second wafer 204). In some cases, at least one surface treatment process may not be performed on one or more materials (e.g., dielectric layer 206, interconnect structure 208, or adhesive layer 210). In some other cases, the interconnect structure 208 may be protected (e.g., using a mask, and other materials / covers) during the surface treatment process of at least one of the dielectric layer 206 or the bonding layer 210.

[0035] FIG3A shows a perspective view of a semiconductor package 200 including a first wafer 202 and a second wafer 204. FIG3B shows a cross-sectional view 300 of the bonding layer 210 of wafers 202, 204. After (e.g., selectively) depositing the bonding layer 210, a surface hydrophilization process or technique (e.g., and other suitable rinsing techniques) may be performed on one or more bonding layers 210. For example, the bonding layer 210 may be rinsed by applying deionized water to the (e.g., top) surface of the bonding layer 210. At least as shown in FIG3B, hydroxide (OH) may be introduced to the top surface of the bonding layer 210 via a deionized water rinsing process. Therefore, the substrate (e.g., the first or second substrate of wafers 202, 204) may be rinsed with deionized water to hydrophilize the bonding layer 210 of the respective wafers 202, 204. By introducing hydroxide onto the surface of the bonding layer 210, the bonding or coupling capability between the bonding layers 210 of the two wafers 202 and 204 can be enhanced (e.g., making the bonding layer 210 ready for interconnection).

[0036] Corresponding to operation 110 in FIG1, FIG4A shows a perspective view of a semiconductor package 200 including a first wafer 202 and a second wafer 204, and FIG4B shows a cross-sectional view 300 of wafers 202 and 204. As shown, the first wafer 202 may be flipped or inverted (e.g., rotated 180 degrees), wherein the top surface of the first substrate (e.g., the first wafer 202) faces down or towards the top of the second substrate (e.g., the second wafer 204), and the second substrate (e.g., the second wafer 204) faces up. In some cases, the second wafer 204 may be flipped instead of the first wafer 202. For simplicity and by way of example, the first wafer 202 may include a first substrate that includes at least one of a dielectric layer 306 and an interconnect structure 308, and the second wafer 204 may include a second substrate that includes at least one of a dielectric layer 206 and an interconnect structure 208. Wafers 202 and 204, or both of them, may include a respective bonding layer 210 (e.g., which is bonded herein to form a connected bonding layer or a single bonding layer, referred to herein simply as bonding layer 210).

[0037] After hydrophilizing the bonding layer 210, wafers 202 and 204 (e.g., one of which is flipped) can be aligned and bonded / coupled (e.g., using a hybrid bonding process). For example, the first interconnect structure 308 can be aligned with the second interconnect structure 208. In this case, the bonding layers 210 of wafers 202 and 204 can also be aligned. Aligning interconnect structures 208 and 308 may include or refer to positioning the wafers such that interconnect structures 208 and 308 directly face each other. In some cases, the sidewalls of interconnect structures 208 and 308 may be coplanar (e.g., vertical planes).

[0038] When wafers 202 and 204 are aligned, the first bonding layer (e.g., bonding layer 210 of the first wafer 202) may be in physical contact, coupled, or interconnected with the second bonding layer (e.g., bonding layer 210 of the second wafer 204). For example, the surface of bonding layer 210 may be prepared for bonding by at least one of surface hydrophilization or other surface treatment processes. (e.g., during physical contact between the first and second bonding layers of the respective wafers 202 and 204) the first and second bonding layers may be coupled / bonded / interconnected by applying heat and / or pressure. The applied pressure may include pressure less than about 30 MPa, and the applied heat may include an annealing process at a temperature of about 100 to 500 degrees Celsius. For example, other amounts of pressure and heat may be used in a mixed bonding process, but this is optional. The hybrid bonding process can be performed in the following environments: N₂ environment, Ar environment, He environment, (about 4 to 10% H₂) / (about 90 to 96% inert gas or N₂) environment, inert gas mixture environment, combinations thereof, or other types of environments. Therefore, the first and second wafers 202, 204 (e.g., first and second substrates) can be coupled based on at least making the bonding layers physically contact each other. In some cases, the coupled first and second bonding layers can form bonding layer 210.

[0039] In some embodiments, the bonding between wafers 202 (e.g., bonding via bonding layer 210 at this stage) may include non-metal-to-non-metal bonding or metal-to-metal bonding. A portion of the hybrid bonding process may include a fusion process that forms a non-metal-to-non-metal bonding, and a portion of the hybrid bonding process may include, for example, a copper-to-copper bonding process that forms a metal-to-metal bonding. The term "hybrid" means using at least one bonding process to form two different types of bonding (e.g., bonding between bonding layer 210 and interconnect structures 208, 308), rather than forming only one type of bonding, as is done in other types of wafer-to-wafer or die-to-die bonding processes.

[0040] In many embodiments, in response to coupling the bonding layer 210, channels associated with the respective recessed regions of interconnect structures 208 and 308 may form a common channel. This channel may extend from the top surface of the first interconnect structure 308 to the top surface of the second interconnect structure 208. The channel may provide openings for coupling / bonding of the interconnect structures 208 and 308.

[0041] In some embodiments, the adhesive layer 210 may (e.g., selectively) be deposited on the top surface of one of the dielectric layers 206, 306. In this case, wafers 202, 204 (e.g., one of which is flipped) may be aligned and bonded / coupled using at least one suitable bonding process or technique. For example, the first interconnect structure 308 may be aligned with the second interconnect structure 208. In this case, the adhesive layer 210 (e.g., its top surface) of one of wafers 202, 204 may also be aligned with the top surface of the dielectric layer 206, 306 of the other of wafers 202, 204. For example, the surface of the adhesive layer 210 (or the surface of the dielectric layer 206, 306 of the other of wafers 202, 204) may be prepared for bonding by at least one suitable surface treatment process. Therefore, (for example, during physical contact between bonding layer 210 and dielectric layer 206, 306 of the other of wafers 202, 204) two wafers 202, 204 can be coupled / bonded / interconnected by applying heat and / or pressure.

[0042] Figure 5A shows a perspective view of a semiconductor package 200 having first and second wafers 202, 204 coupled together. Figure 5B shows a cross-sectional view 300 of the coupled wafers 202, 204. For example, after the coupling bonding layer 210, at least one suitable thermal processing process, such as rapid thermal processing (RTP), can be used to heat the first and second substrates (e.g., annealing or other heating processes). Heating the substrates allows the interconnect structures 208, 308 to extend along the channels surrounded by the bonding layer 210. Therefore, annealing the substrates can increase the dimensions (e.g., height) of the interconnect structures 208, 308 along the channels, thereby enabling them to make physical contact with each other (e.g., establishing physical contact between the interconnect structures 208, 308 by / via recessed portions).

[0043] In some embodiments, interconnect structures 208, 308 can be extended to the same size. In other cases, interconnect structures 208, 308 can be extended to include the same size or at the same rate, such that the first or second interconnect structure 208, 308 extends further than the other to form a physical contact. In some embodiments, the coupling of the first and second substrates (e.g., first and second wafers 202, 204) may refer to or correspond to the coupling of the bonding layer 210 and the interconnect structures 208, 308.

[0044] Figure 6A shows a perspective view of a semiconductor package 200 including first and second wafers 202, 204, which has undergone at least one thinning or etching process. Figure 6B shows a perspective view of the semiconductor package 200 including first and second wafers 202, 204 after the thinning process. The thinning process can be performed before, during, or after the interconnect structures 208, 308. The thinning process can be performed on the first substrate and / or the second substrate using at least one suitable etching technique, such as a chemical etching process.

[0045] For example, at least one suitable etching technique can be used to etch or thin the bottom surface of the first wafer 202. In some cases, the semiconductor package 200 may be inverted such that the second wafer 204 (e.g., the second substrate) is the top wafer above the first wafer 202 (e.g., the first substrate). In this case, the bottom of the second wafer 204 may be etched. In some cases, the semiconductor package 200 may not be inverted, and at least one of the first or second wafers 202, 204 may be etched. Etching the bottom surface of at least one wafer 202, 204 may reduce the size (e.g., thickness) of the semiconductor package 200.

[0046] In some embodiments, after thinning wafers 202 and 204, at least one suitable lithography technique, such as photolithography, may be performed on at least one of wafers 202 and 204. For example, after thinning wafers 202 and 204 and other manufacturing processes following a plurality of interconnect structures (e.g., 208, 308), one or more patterns may be formed in at least one of the first or second substrates to achieve connections (e.g., electrical connections) with interconnect structures 208, 308 and other materials.

[0047] In the foregoing description, specific details, such as the processing system and its specific geometry, as well as the numerous components and processes used therein, have been set forth. However, it should be understood that the techniques described herein may be implemented in other embodiments departing from these specific details, which are for illustrative purposes and not for limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments may be implemented without these specific details. Elements having substantially the same functional construction are denoted by similar reference numerals, and therefore any redundant description may be omitted.

[0048] Numerous techniques have been described as complex, separate operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations are necessarily sequentially dependent. In fact, these operations do not need to be performed in the presented order. The described operations may be performed in a different order than in the described embodiments. In additional embodiments, numerous additional operations may be performed, and / or the described operations may be omitted.

[0049] As used herein, "substrate" or "target substrate" generally refers to an object processed according to the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may, for example, be a base substrate structure (e.g., a semiconductor wafer), a reticle, or a cladding (e.g., a thin film) on or over a base substrate structure. Therefore, a substrate is not limited to any particular base structure, lower or upper layer, patterned or unpatterned, but is interpreted to include any such cladding or base structure, and any combination of cladding and / or base structures. Reference may be made to specific types of substrates, but this is for illustrative purposes only.

[0050] Those skilled in the art will also understand that many changes can be made to the operation of the above-described techniques while still achieving the same objectives of the present invention. Such changes are intended to be included within the scope of this disclosure. Therefore, the foregoing description of embodiments of the present invention is not intended to be limiting. Rather, any limitations on embodiments of the present invention are presented in the appended claims. [Simplified Explanation of the Diagram]

[0019] Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying drawings, which are schematic and not intended to be drawn to scale. Unless otherwise specified as representing prior art, the drawings represent embodiments of the present disclosure. For clarity, not every element in every figure is labeled. In the drawings:

[0020] Figure 1 shows a flowchart of an exemplary method for manufacturing a semiconductor package according to some embodiments.

[0021] Figures 2A to 6B show separate cross-sectional views of a semiconductor package manufactured by the method of Figure 1 during various manufacturing stages according to some embodiments.

Claims

1. A semiconductor package, comprising: A first substrate includes: a first interconnect structure; and a first bonding layer portion adjacent to the first interconnect structure; and a second substrate coupled to the first substrate, the second substrate including: a second interconnect structure; and a second bonding layer portion adjacent to the second interconnect structure, wherein at least one of the first bonding layer portion and the second bonding layer portion includes a metal oxide.

2. The semiconductor package as described in claim 1, wherein, A top surface of the first interconnect structure contacts a top surface of the second interconnect structure, and a top surface of the first adhesive layer portion contacts a top surface of the second adhesive layer portion.

3. The semiconductor package as described in claim 1, wherein, The first substrate further includes a first dielectric material embedded in the lower part of one of the first interconnect structures, and the second substrate further includes a second dielectric material embedded in the lower part of one of the second interconnect structures.

4. The semiconductor package as described in claim 3, wherein, The first adhesive layer portion and the second adhesive layer portion are in contact with each other along an adhesive interface.

5. The semiconductor package as described in claim 1, wherein, The first substrate further includes a plurality of first device features disposed on the opposite side of the first interconnect structure to the second interconnect structure.

6. The semiconductor package as described in claim 1, wherein, The second substrate further includes a plurality of second device features disposed on the opposite side of the second interconnect structure to the first interconnect structure.

7. The semiconductor package as described in claim 1, wherein, The first bonding layer portion is disposed around an upper portion of the first interconnect structure, and the second bonding layer portion is disposed around an upper portion of the second interconnect structure.

8. The semiconductor package as described in claim 1, wherein, The metal oxide is selected from the group consisting of aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), and combinations thereof.

9. A method for manufacturing a semiconductor package, comprising: A first substrate is provided, the first substrate including a first dielectric layer and a first interconnect structure; a first adhesion layer is selectively formed only on the first dielectric layer; A second substrate is provided, the second substrate including a second dielectric layer and a second interconnect structure; and a first substrate is coupled to the second substrate by means of making the first interconnect structure and the first bonding layer physically contact the second interconnect structure and the second dielectric layer, respectively.

10. A method for manufacturing a semiconductor package as described in claim 9, wherein, The step of coupling the first substrate to the second substrate further includes: selectively forming a second bonding layer only on the second dielectric layer; and coupling the first substrate to the second substrate based on making the first interconnect structure and the first bonding layer physically contact the second interconnect structure and the second bonding layer, respectively, wherein the first bonding layer and the second bonding layer each comprise a material selected from the group consisting of: silicon oxide (SiO 2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), aluminum oxide (Al 2O 3), hafnium oxide (HfO 2), and combinations thereof.

11. The method of manufacturing a semiconductor package as described in claim 9 further includes: The first substrate is rinsed with deionized water to hydrophilize the first adhesive layer.

12. The method for manufacturing a semiconductor package as described in claim 9, wherein, The step of coupling the first substrate to the second substrate further includes: aligning the first interconnect structure with the second interconnect structure; making the first bonding layer material contact the second dielectric layer; and annealing the first substrate and the second substrate so that the first interconnect structure material contacts the second interconnect structure.

13. The method of manufacturing a semiconductor package as claimed in claim 9, wherein the step of selectively forming the first bonding layer includes performing at least one atomic layer deposition process.

14. The method of manufacturing a semiconductor package as described in claim 9 further includes: Before selectively forming the first adhesive layer, a first polishing process is performed on the first substrate to form a first coplanar surface shared by the first dielectric layer and the first interconnect structure.

15. The method for manufacturing a semiconductor package as described in claim 14, wherein, After the first bonding layer is selectively formed, a top surface of the first interconnect structure is recessed from a top surface of the first bonding layer.

16. A method for manufacturing a semiconductor package, comprising: A first substrate is provided, the first substrate including a first dielectric layer and a first interconnect structure, the first interconnect structure being exposed on a surface of the first dielectric layer; a first bonding layer is formed on the first dielectric layer using an atomic deposition process; a second substrate is provided, the second substrate including a second dielectric layer and a second interconnect structure; the first bonding layer is bonded to the second substrate; and the first interconnect structure is physically contacted with the second interconnect structure.

17. A method for manufacturing a semiconductor package as described in claim 16, wherein, The first bonding layer comprises a material selected from the group consisting of silicon oxide (SiO 2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), aluminum oxide (Al 2O 3), hafnium oxide (HfO 2), and combinations thereof.

18. The method of manufacturing a semiconductor package as claimed in claim 16, further comprising, before bonding the first bonding layer to the second substrate: The first substrate is rinsed with deionized water to hydrophilize the first adhesive layer.

19. A method for manufacturing a semiconductor package as described in claim 16, wherein, The first bonding layer is formed to a thickness of 1~10nm, thereby forming a recess between a surface of the first bonding layer and a surface of the first interconnect structure, and wherein, after bonding the first bonding layer to the second substrate, annealing is performed so that the first interconnect structure makes physical contact with the second interconnect structure through the recess.

20. A method for manufacturing a semiconductor package as claimed in claim 16, wherein, After the first bonding layer is formed, a top surface of the first interconnect structure is recessed from a top surface of the first bonding layer.

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