Optical waveguide edge coupling within a substrate
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-08-15
- Publication Date
- 2023-07-16
Smart Images
Figure TWG2TA000916657_001 
Figure TWG2TA000916657_002 
Figure TWG2TA000916657_003
Abstract
Description
[Technical Field]
[0001] Embodiments of the present invention generally relate to the field of semiconductor packaging, and particularly to photonic integrated circuits (PIC). [Previous Technology]
[0002] Continued growth in computing and mobile devices will further increase the demand for bandwidth and speed increases between chips within semiconductor packaging components. [Summary of the Invention]
[0003] and
Implementation Method
[0015] The embodiments described herein relate to apparatus, processes, and techniques for enabling dense integration of a PIC adjacent to a central processing unit (CPU), logic die, processing die, or other die (collectively referred to herein as XPU) in a substrate via the use of an optical fanout. In embodiments, the optical fanout may include a waveguide formed within the substrate for optical coupling with the PIC. The PIC may then be electrically coupled to the XPU. In embodiments, the substrate may be referred to as an optical interposer with integrated optical waveguides. In embodiments, the substrate may be, but is not limited to, made of glass or silicon.
[0016] In embodiments, depending on the design of the substrate, optical waveguide, and PIC, this optical fan-out architecture can enable bandwidths exceeding 1 petabyte per second (Pb / s) on the package. Embodiments of this architecture can enable dense integration of the PIC within the package and promote low latency by reducing the distance between the PIC and the XPU within the package. In embodiments, due to the design of the coupling mechanism within the substrate, passive alignment of components within the package can be enabled to widen the waveguide for optical coupling to the PIC.
[0017] In the following detailed description, reference is made to the accompanying drawings that form part of the detailed description, wherein similar numerals denote similar parts throughout, and illustrated embodiments in which the subject matter of the invention may be implemented are shown. It will be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description is not to be taken in a limiting sense, but rather the scope of the embodiments is defined by the appended claims and their equivalents.
[0018] For the purposes of this invention, the term "A and / or B" means (A), (B), or (A and B). For the purposes of this invention, the term "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0019] This description may use perspective-based descriptions, such as top / bottom, inside / outside, above / below, etc. Such descriptions are only used to aid discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.
[0020] The terms "in one embodiment" or "in an embodiment" may be used in this description, which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising," "including," "having," etc., as used in relation to embodiments of the present invention, are synonymous.
[0021] The terms "coupled" and "together with its derivatives" may be used herein. "Coupled" may mean one or more of the following: "Coupled" may mean two or more elements that are in direct physical or electrical contact. However, "coupled" may also mean two or more elements that are not in direct contact with each other but still cooperate or interact with each other, and may mean one or more other elements that are coupled or connected to elements that are said to be coupled. The term "directly coupled" may mean two or more elements that are in direct contact.
[0022] Various operations can be described as a series of separate operations in a sequential manner, in a way that best facilitates understanding the subject matter of the present invention. However, the order of description should not be construed as meaning that these operations must be performed in sequence.
[0023] As used herein, the term "module" may refer to, be part of, or comprise an ASIC, electronic circuitry, a processor (shared, dedicated, or grouped) and / or memory (shared, dedicated, or grouped) that executes one or more software or firmware programs, combined logic circuitry, and / or other suitable components that provide the aforementioned functionality.
[0024] The various figures herein may depict one or more layers of one or more package components. The layers described herein are examples of the relative positions of layers in different package components. These layers are described for illustrative purposes and are not drawn to scale. Therefore, the relative sizes of the layers should not be assumed from the figures, and their sizes, thicknesses, or dimensions may be assumed only for some embodiments specifically indicated or discussed herein.
[0025] Figure 1 illustrates a top-down view and a cross-sectional side view of a package according to various embodiments, the package including a substrate with a cavity, together with an optical waveguide within the substrate and within the cavity at the edge of the substrate for die optical coupling. Figure 100 shows a top-down view of a substrate 102 having a cavity 104 formed within the substrate 102. The substrate 102 may also be referred to as an interposer. In embodiments, the substrate 102 may be a glass substrate, a silicon substrate, or some other substrate in which the optical waveguide may be formed, as further discussed below. The thickness of the substrate 102 may vary depending on the desired characteristics of the package, which may include the rigidity of the package, the number of optical waveguide layers to be formed within the substrate 102, and / or the size of the PIC and the XPU to be coupled to the PIC.
[0026] Package 140 shows a top-down view of various waveguides 120, 122, and 124, which can be formed within substrate 102 using the techniques and processes described below. These processes can vary depending on the composition of substrate 102. Optical connector 130 can be coupled to the edge of substrate 102 and can be optically coupled to optical waveguides 120 and 122. In an embodiment, optical connector 130 can be used to bridge optical signals between package 140 and other devices (not shown) outside package 140.
[0027] The first PIC 132 can be optically coupled to the optical waveguide 120, and the second PIC 134 can be optically coupled to the optical waveguide 122. In an embodiment, PIC 132 and PIC 134 are located within a recess 104 of the substrate 102. PICs 132 and 134 can have various sizes and can include multiple optical couplers (not shown) to accommodate additional optical waveguides. In an embodiment, the first PIC 132 can also be optically coupled to the second PIC 134 using the optical waveguide 124. The optical waveguide 124 can provide a high-speed communication route between the first PIC 132 and the second PIC 134.
[0028] In an embodiment, the XPU, which is also placed within the recess 104, can be electrically coupled to the first PIC 132 and the second PIC 134. Therefore, in the embodiment shown, the XPU 138 can receive high-speed signals via two different optical paths, optical waveguide 120 and optical waveguide 122. As further discussed below, different architectural embodiments can significantly increase the bandwidth of the XPU 138.
[0029] In an embodiment, the dimensions of recess 104, the dimensions and positioning of PICs 132 and 134, the dimensions and positioning of XPU 138, and the positioning and design of waveguides 120 and 122 can enable passive alignment during the manufacture of package 140.
[0030] Package 170 is a cross-sectional side view of package 140 and includes a substrate 102 and a recess 104 within the substrate 102, a first PIC 132 and a second PIC 134, and an XPU 138 within the recess 104. In an embodiment, an interconnect layer 139 may be used to electrically couple the first PIC 132 to the XPU 138, and to electrically couple the second PIC 134 to the XPU 138. In an embodiment, the interconnect layer 139 may not be present, and electrical interconnection may occur via the substrate 103.
[0031] Waveguide 120 can be optically coupled to the first PIC 132, as shown. In an embodiment, optical underfill 137 can be applied between the end 120a of waveguide 120 and the optical components (not shown) of PIC 132. In an embodiment, optical underfill 137 can be selected based on the refractive index of matching optical waveguide 120 and can be used to fill the gap between end 120a and PIC 132. In an embodiment, optical connector 130 can be placed on the surface of substrate 102 and can be optically coupled to waveguides 120, 122 using evanescent coupling. In other embodiments, end-fire or butt coupling schemes can be used to optically couple waveguides 120, 122 to optical connector 130. Note that these optical couplings can include wavelength insensitive coupling techniques to enable wave division multiplexing (WDM).
[0032] FIG2 illustrates a side view of optical coupling between an optical waveguide and a photonic integrated circuit (PIC) within a substrate, according to various embodiments. The package 200, which may be similar to the package 170 of FIG1, includes a glass substrate 202 and an interconnect layer 239, both of which can be coupled to an IC substrate 203, which may be similar to the glass substrate 102, interconnect layer 139, and IC substrate 103 of FIG1.
[0033] Optical waveguide 220 can be optically coupled to PIC 232, and can be similar to optical waveguide 120 and PIC 132 in FIG1. In an embodiment, optical underfill 237, which can be similar to optical underfill 137 in FIG1, can be located between waveguide 220 and PIC 232. In an embodiment, a portion of optical underfill 237 can also extend to the side of substrate 202 and under a portion of PIC 232.
[0034] The end 220a of the optical waveguide 220 can be optically coupled to the edge of the PIC 232. The end 220a may include a mode expander 221, which in an embodiment may taper outwards and be used in conjunction with the edge coupling to the PIC 232 to reduce the sensitivity of the PIC 232 to misalignment relative to the waveguide 220.
[0035] Figure 3 illustrates a top-down view and a cross-sectional side view of a package according to various embodiments. The package includes a substrate with recesses, along with multiple layers of optical waveguides optically coupled within the substrate and to the edges of the substrate within the recesses. Package 300 shows a top-down view including a substrate 302, a recess 304, an optical connector 330, and an XPU 338 located within the recess 304, which may be similar to the substrate 102, recess 104, optical connector 130, and XPU 138 of Figure 1. A plurality of PICs 332, which may be similar to PIC 132 or PIC 134 of Figure 1, are optically coupled to the optical connector 330 via waveguide 320.
[0036] In an embodiment, interconnect layer 339, which may be similar to interconnect layer 139 of FIG1, may electrically couple one or more of the PICs 332 to the XPU 338, or to other PICs 332. Note that in an embodiment, XPU 338 may contain multiple XPU components or other circuitry.
[0037] Package 370 shows a cross-sectional side view of package 300, wherein interconnect layer 339 is located below a first layer containing PIC 332a, optically coupled to optical waveguide 320a located at a first depth d1 within substrate 302, and electrically coupled to XPU 338a along with PIC 332a, and PIC 332a may be similar to PIC 332 of package 300. Similarly, below interconnect layer 339 is a second layer containing PIC 332b, which is optically coupled to optical waveguide 320b located at a second depth d2 within substrate 302, and electrically coupled to XPU 338b along with PIC 332a, and PIC 332b may be similar to PIC 332 of package 300. Therefore, in this configuration, XPUs 338a, 338b may be electrically coupled to 16 PICs 320a, 320b. In other embodiments, other numbers of PICs 320a, 320b may be used. In an embodiment, interconnect layer 339 may include circuitry and bridges, such as an embedded multi-die interconnect bridge (EMIB) (not shown).
[0038] FIG4 illustrates a top-down view of a package according to various embodiments, the package comprising a substrate having two recesses, together with optical waveguides optically coupled to a die within the substrate at the edge of the first recess and the die at the edge of the second recess. Package 400 shows a substrate 402 having a plurality of optical waveguides 420 optically coupled to an optical coupler 430, which may be similar to substrate 102, optical waveguides 120, 122 and optical coupler 130 of FIG1.
[0039] Package 400 includes two recesses 404a and 404b, which may be similar to recess 104 in Figure 1. PIC 432 is placed within the two recesses 404a and 404b and optically coupled to optical waveguide 420. XPU 438, which may be similar to XPU 338 in Figure 3, may be electrically coupled to the respective PIC 432 within each recess 404a and 404b. In addition, one or more optical waveguides 421 may be used to optically couple PIC 432 located in different recesses 404a and 404b.
[0040] Figure 5 illustrates a top-down view of a package according to various embodiments, the package including a substrate, together with an optical waveguide optically coupled to a die within the substrate and at the edge of the substrate. Package 500 includes a substrate 502, an optical waveguide 520, an optical connector 530, a PIC 532, an XPU 538, and an interconnect layer 539, which may be similar to the substrate 102, optical waveguides 120, 122, optical connector 130, PIC 132, XPU 138, and interconnect layer 139 of Figure 1. In an embodiment, the interconnect layer 539 may electrically couple the PIC 532 and the XPU 538. The PIC 532 may be optically coupled to the optical connector 530 using the optical waveguide 520. In this embodiment, a recess 504 may be formed from a corner of the substrate 502, and the PIC 532 and XPU 538 may be inserted into the recess 504.
[0041] It should be noted that the embodiment shown with respect to package 500 is an example of one of many embodiments, which may include different configurations of substrate 502 having various PICs (such as PIC 532) located at one or more edges of substrate 502, along with various optical waveguides, such as optical waveguide 520 embedded within substrate 502. The PIC may be electrically coupled to XPU (such as XPU 538) or other circuitry using interconnect layer 539. In embodiments, interconnect layer 539 may be implemented as a high-density routing layer, a standard routing layer, or as an embedded die, such as EMIB.
[0042] Figures 6A to 6D illustrate various manufacturing process stages for forming an optical waveguide within a substrate, according to various embodiments. Figure 6A shows a cross-sectional side view in which the manufacturing process stages of a first substrate layer 601 can be identified. The first substrate layer 601 may be similar to the substrate 102 of Figure 1. In embodiments, the first substrate layer 601 may be a glass substrate, a silicon substrate, or a substrate made of some other material.
[0043] Figure 6B shows a cross-sectional side view of a fabrication process stage in which waveguide layer 672 is deposited on the surface of first substrate layer 601. In an embodiment, the deposited waveguide layer 672 may comprise SiNx, doped SiOx, etc. In an embodiment, waveguide layer 672 may be formed of an optically patternable dielectric.
[0044] FIG6C shows a cross-sectional side view of the manufacturing process stage in which waveguide layer 672 is patterned to produce individual waveguides 620 on top of the first substrate layer 601. These individual waveguides 620 may be similar to waveguides 120 and 122 in FIG1.
[0045] FIG. 6D shows a cross-sectional side view of a manufacturing process stage in which a second substrate layer 603 is deposited on top of the first substrate layer 601 and the waveguide 620. In an embodiment, this deposition may be referred to as applying a cladding layer 603. The result is the formation of a substrate 602 in which the optical waveguide 620 is embedded, the substrate 602 being similar to the substrate 102 of FIG. 1.
[0046] Figures 7A to 7E illustrate manufacturing process stages for forming an optical waveguide within a glass substrate according to various embodiments. Figure 7A shows a cross-sectional side view in which the manufacturing process stages of a first glass substrate layer 701 can be identified. The first glass substrate layer 701 may be similar to the substrate 102 of Figure 1.
[0047] Figure 7B shows a cross-sectional side view of a manufacturing process stage in which a masking layer 764 is deposited on the surface of a first glass substrate layer 701. In an embodiment, the deposited masking layer 764 may comprise a metal such as copper, nickel, titanium, chromium, or aluminum.
[0048] Figure 7C shows a cross-sectional side view of a manufacturing process stage in which the mask layer 764 is patterned to create an exposure area 766 above the surface of the first glass substrate layer 701.
[0049] FIG7D shows a cross-sectional side view of the manufacturing process stage in which an ion implantation or ion exchange process is applied to the first glass substrate layer 701. In the ion implantation or ion exchange process, a waveguide 720 is generated by changing the refractive index of the glass in the first glass substrate layer 701 by using ions passing through the exposure area 766. The waveguide 720 may be similar to the waveguide 120 in FIG1.
[0050] Figure 7E shows a cross-sectional side view of a manufacturing process stage in which the masking layer 764 is removed and a second substrate layer 703 is deposited on top of the first substrate layer 701 and the waveguide 720. In an embodiment, this deposition may be referred to as applying the cladding layer 703. The result is the formation of a substrate 702 in which the optical waveguide 720 is embedded, and the substrate 702 may be similar to the substrate 102 of Figure 1.
[0051] Figures 8A to 8C illustrate another manufacturing process stage for forming an optical waveguide within a glass substrate, according to various embodiments. Figure 8A shows a cross-sectional side view in which a manufacturing process stage of a first glass substrate layer 801 can be identified, the first glass substrate layer 801 may be similar to the substrate 102 of Figure 1.
[0052] Figure 8B shows a cross-sectional side view of the manufacturing process stage in which the laser direct writing process is applied to the surface of the first glass substrate layer 801 to form the waveguide 820.
[0053] FIG8C shows a cross-sectional side view of a manufacturing process stage in which a second substrate layer 803 is deposited on top of a first substrate layer 801 and a waveguide 820. The result is the formation of a substrate 802 in which the optical waveguide 820 is embedded, and the substrate 802 may be similar to the substrate 102 of FIG1.
[0054] In the embodiments, it should be appreciated that other processes can also be used to create an optical waveguide on top of the surface of the substrate. For example, trenches can be formed within the surface of a glass substrate layer, such as a first glass substrate layer 801, using the techniques described below with respect to FIG. 9. Once the trenches are formed, optical waveguide material, such as the optical waveguide material of waveguide layer 672 of FIG. 6B, can be deposited within the trenches. After the manufacturing stages, which can be similar to the manufacturing stages described in FIG. 6D, FIG. 7E, and / or FIG. 8 above, can be applied to embed the deposited optical waveguide material within the substrate.
[0055] Figure 9 illustrates various examples of laser-assisted etching of glass interconnect processes (which may be referred to herein as "LEGIT"). One application of LEGIT technology is to provide alternative substrate core material to the core of conventional copper clad laminates (CCLs) used in semiconductor packaging, which are used to implement products such as servers, graphics, clients, 5G, etc. By using laser-assisted etching, crack-free, high-density via drills and hollow shapes can be formed within the glass substrate. In the embodiments, different process parameters can be adjusted to achieve drills of various shapes and depths, thus opening a door to innovative glass devices, architectures, processes, and designs. Embodiments such as the bridges discussed herein can also utilize these technologies.
[0056] Figure 900 illustrates an advanced process flow for creating vias and blind vias (or trenches) in a microelectronic packaging substrate (e.g., glass) using LEGIT. The final volume / shape of the glass with laser-induced morphology changes can then be selectively etched to create trenches, vias, or voids that can be filled with a conductive material. Vias 912 are created by laser pulses from two laser sources 902, 904 on opposite sides of a glass wafer 906. As used herein, through-holes and vias refer to holes or holes that begin on one side of the glass / substrate and end on the other. Blind holes and blind vias refer to holes or holes that begin on the surface of the substrate and stop halfway within the substrate. In an embodiment, laser pulses from the two laser sources 902, 904 are applied vertically to the glass wafer 906, inducing a morphology change 908 in the glass encountering the laser pulses, which may also be referred to as a structural change. This morphological change 908 involves altering the molecular structure of the glass to make it easier to etch away (remove a portion of the glass). In an embodiment, a wet etching process can be used.
[0057] Figure 920 illustrates a high-order process flow for a double-blind shape. Double-blind shapes 932, 933 can be created by laser pulses from two laser sources 922, 924 (which can be similar to laser sources 902, 904) on opposite sides of a glass wafer 926 (which can be similar to glass wafer 906). In this example, the laser pulse energy and / or laser pulse exposure time from the two laser sources 922, 924 can be adjusted. As a result, morphological changes 928, 929 of the glass 926 may lead to these changes making it easier to etch away portions of the glass. In this embodiment, a wet etching process can be used.
[0058] Figure 940 illustrates a high-order process flow for a single-blind shape, which may also be referred to as a trench. In this example, a single laser source 942 delivers laser pulses to a glass wafer 946 to create a morphological change 948 in the glass 946. As described above, these morphological changes make it easier to etch away a portion 952 of the glass. In this embodiment, a wet etching process may be used.
[0059] Figure 960 illustrates a high-order process flow for a through-via shape. In this example, a single laser source 962 applies a laser pulse to glass 966 to create a morphological change 968 in the glass 966, along with this change, making it easier to etch away a portion 972 of the glass. As shown here, the laser pulse energy and / or laser pulse exposure time from the laser source 962 have been adjusted to create the etched portion 972, which extends completely through the glass 966.
[0060] Regarding Figure 9, although the embodiments show laser sources 902, 904, 922, 924, 942, and 962 as perpendicular to glass 906, 926, 946, and 966, in the embodiments, the laser sources may be positioned at an angle relative to the glass surface, along with variations in pulse energy and / or pulse exposure time, to create diagonal vias or trenches, or to create holes such as 912 and 972, for example, forming cylindrical, conical, or other shapes incorporating certain features. Furthermore, when the etching system of the glass is strongly dependent on the chemical composition of the glass, changing the glass type can also create different features within the vias or trenches.
[0061] In embodiments using the process described in relation to FIG9, vias 912, 972 with diameters less than 10 μm and aspect ratios of 40:1 to 50:1 can be created. As a result, a much higher density of vias can be placed within the glass and positioned closer together with a finer pitch. In embodiments, this pitch can be 50 μm or less. After creating the vias or trenches, a metallization process can be applied to create conductive pathways through the vias or trenches, such as plated through holes (PTHs). Using these techniques, finer-pitch vias can result in better signaling, allowing more I / O signals to be routed through the glass wafer and to other coupled components, such as the substrate.
[0062] FIG10 illustrates an example of a process for forming an optical waveguide within a substrate, according to various embodiments. Process 1000 can be implemented using the techniques, methods, systems, and / or apparatus described herein, and particularly with respect to FIG1 through FIG9.
[0063] In block 1002, the process may include identifying the first layer of the substrate. In embodiments, the substrate may be similar to substrate 102 of FIG. 1, substrate 202 of FIG. 2, substrate 302 of FIG. 3, substrate 402 of FIG. 4, substrate 502 of FIG. 5, first substrate layer 601 of FIG. 6A, first glass substrate layer 701 of FIG. 7A, or first glass substrate layer 801 of FIG. 8A.
[0064] In block 1004, the process may further include forming one or more optical waveguides on the surface of the first layer of the substrate. In an embodiment, forming one or more optical waveguides may be similar to the process stages shown and described in Figures 6A to 8C.
[0065] In block 1006, the process may further include applying a second layer of the substrate onto the surface of the first layer of the substrate to cover the one or more formed optical waveguides. In embodiments, forming one or more optical waveguides may be similar to the process stages shown and described in the relevant Figures 6A to 8C.
[0066] FIG11 is a schematic diagram of a computer system 1100 according to an embodiment of the present invention. The computer system 1100 (also referred to as electronic system 1100) shown in the figure enables the embodiment of an optical waveguide edge-coupled within a substrate according to any of the disclosed embodiments and equivalents as presented in this invention. The computer system 1100 can be a portable device such as a netbook computer. The computer system 1100 can be a portable device such as a wireless smartphone. The computer system 1100 can be a desktop computer. The computer system 1100 can be a hand-held reader. The computer system 1100 can be a server system. The computer system 1100 can be a supercomputer or a high-performance computing system.
[0067] In an embodiment, the electronic system 1100 is a computer system that includes a system bus 1120 for electrically coupling various components of the electronic system 1100. The system bus 1120 is a single bus or any combination of buses according to various embodiments. The electronic system 1100 includes a voltage source 1130 for supplying power to the integrated circuit 1110. In some embodiments, the voltage source 1130 supplies current to the integrated circuit 1110 via the system bus 1120.
[0068] Integrated circuit 1110 is electrically coupled to system bus 1120 and includes any circuitry, or a combination of circuitry according to one embodiment. In one embodiment, integrated circuit 1110 includes processor 1112, which can be any type of processor. As used herein, processor 1112 can mean any type of circuitry, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor, or another processor. In one embodiment, processor 1112 includes, or is coupled to, an optical waveguide edge-coupled within a substrate, as disclosed herein. In one embodiment, an SRAM embodiment is found in the processor's memory cache. Other types of circuitry that can be included in integrated circuit 1110 are custom circuitry or application-specific integrated circuits (ASICs), such as communication circuitry 1114 used in wireless devices or communication circuitry used in servers, such as cellular phones, smartphones, pagers, laptops, two-way radios, and similar electronic systems. In one embodiment, the integrated circuit 1110 includes on-die memory 1116, such as static random access memory (SRAM). In another embodiment, the integrated circuit 1110 includes embedded on-die memory 1116, such as embedded dynamic random access memory (eDRAM).
[0069] In one embodiment, the integrated circuit 1110 is supplemented by subsequent integrated circuit 1111. Useful embodiments include dual processors 1113, dual communication circuits 1115, and dual on-die memory 1117 such as SRAM. In one embodiment, the dual integrated circuit 1110 includes embedded on-die memory 1117 such as eDRAM.
[0070] In one embodiment, the electronic system 1100 also includes external memory 1140, which may sequentially include one or more memory elements suitable for a particular application, such as main memory 1142 in the form of RAM, one or more hard disk drives 1144, and / or one or more drives for operating removable media 1146, such as floppy disks, optical discs (CDs), digital versatile discs (DVDs), flash memory drives, and other removable media known in the art. According to one embodiment, external memory 1140 may also be embedded memory 1148, such as the first die in a die stack.
[0071] In one embodiment, the electronic system 1100 also includes a display device 1150 and an audio output 1160. In one embodiment, the electronic system 1100 includes an input device 1170, such as a controller, which may be a keyboard, mouse, trackball, game controller, microphone, voice recognition device, or any other input device that inputs information into the electronic system 1100. In one embodiment, the input device 1170 is a camera. In one embodiment, the input device 1170 is a digital recorder. In one embodiment, the input device 1170 is both a camera and a digital recorder.
[0072] As shown herein, the integrated circuit 1110 can be implemented in many different embodiments, including a package substrate having an optical waveguide edge-coupled within a substrate according to any of the disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of manufacturing integrated circuits, and one or more methods of manufacturing electronic components. In various embodiments and their technically identified equivalents, the electronic components include a package substrate having an optical waveguide edge-coupled within a substrate according to any of the disclosed embodiments as presented herein. Components, materials, shapes, sizes, and operating sequences can be changed to adapt to specific I / O coupling requirements, including array contact counting and array contact configuration for microelectronic chips embedded in a processor mounting substrate, according to any of the disclosed package substrates having an optical waveguide edge-coupled within a substrate and their equivalents. A base substrate can be included, as indicated by the dashed lines in FIG11. Passive devices can also be included, as shown in FIG11.
[0073] Various embodiments may include any suitable combination of the above embodiments, including alternative (or) embodiments of the embodiments presented in the above conjunction (and) (e.g., "and" may include "and / or"). Furthermore, some embodiments may include one or more manufactured articles (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, cause the operation of any of the above embodiments. Moreover, some embodiments may include apparatus or systems having any suitable means for implementing the various operations of the above embodiments.
[0074] The above description illustrating the embodiments, contained in the summary of the invention, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific embodiments have been described herein for illustrative purposes, various equivalent variations are possible within the scope of such embodiments, as will be recognized by those skilled in the art.
[0075] These variations can be made with reference to the embodiments described in the detailed description above. The terminology used in the following claims should not be construed as limiting the embodiments to the specific embodiments disclosed in the specification and claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be interpreted in accordance with the established principles of the interpretation of the claims.
[0076] The following paragraphs illustrate examples of various embodiments.
[0077] Example
[0078] Example 1 may be a device comprising: a substrate having a first side and a second side opposite to the first side; and an optical waveguide within the substrate, the optical waveguide being positioned between the first side and the second side of the substrate, wherein the end of the optical waveguide is positioned at the edge of the substrate, between the first side and the second side.
[0079] Example 2 includes the device of Example 1, wherein the substrate is selected from either a glass substrate or a silicon substrate.
[0080] Example 3 includes the device of Example 1, wherein the optical waveguide is a first optical waveguide, and further includes a second optical waveguide within the substrate, the second optical waveguide being located between the first side and the second side of the substrate, wherein the end of the second optical waveguide is attached to the edge of the substrate; and wherein the first optical waveguide is located at a first distance from the first side of the substrate, and wherein the second optical waveguide is located at a second distance from the first side of the substrate.
[0081] Example 4 includes the device of Example 3, wherein the first distance and the second distance are the same distance.
[0082] Example 5 includes the device of Example 3, wherein the first distance and the second distance are different distances.
[0083] Example 6 includes the apparatus of Example 1, wherein the substrate has a recess extending from the first side of the substrate to the second side of the substrate within the substrate, and wherein the edge of the substrate is adjacent to the recess.
[0084] Example 7 includes the device of Example 6, wherein the end of the optical waveguide is a first end, and further includes a second end of the optical waveguide opposite to the first end, and wherein the second end of the optical waveguide is located at an edge of the substrate that is not adjacent to the recess.
[0085] Example 8 includes the device of Example 1, wherein the waveguide has a first thickness at the edge of the substrate and a second thickness below the edge of the substrate, wherein the first thickness is greater than the second thickness.
[0086] Example 9 includes the device of Example 1, wherein the substrate includes a first layer and a second layer, the first layer extending from the first side glass substrate and the second layer extending from the second side of the substrate, and wherein the optical waveguide system is at least partially disposed within the first layer and within the second layer.
[0087] Example 10 includes the device of Example 1, wherein the optical waveguide is substantially parallel to the first surface of the substrate or parallel to the second surface of the substrate.
[0088] Example 11 includes a device comprising any one of Examples 1 to 10, wherein the cross-section of the optical waveguide perpendicular to the direction of the optical waveguide has a shape selected from: rectangle or circle.
[0089] Example 12 includes a device of any one of Examples 1 to 11, wherein the optical waveguide comprises one or more of silicon, nitrogen, oxygen, or erbium.
[0090] Example 13 is a method comprising: identifying a first layer of a substrate; forming one or more optical waveguides on the surface of the first layer of the substrate; and applying a second layer of the substrate to the surface of the first layer of the substrate.
[0091] Example 14 includes the method of Example 13, wherein applying the second layer of the substrate to the surface of the first layer of the substrate further includes encapsulating one or more formed optical waveguide adhesives within the substrate.
[0092] Example 15 includes the method of Example 13, wherein forming one or more optical waveguides on the surface of the first layer of the substrate further includes depositing optical waveguide material on the surface of the first layer of the substrate.
[0093] Example 16 includes the method of Example 13, wherein the first layer of the substrate is a glass layer, and wherein forming the one or more optical waveguides on the surface of the first layer of the substrate further includes forming the one or more optical waveguides in one or more volumes of substrate material in the first layer adjacent to the surface of the substrate using either implanted ions or direct laser writing.
[0094] Example 17 includes the method of Example 13, wherein the one or more optical waveguides comprise glass.
[0095] Example 18 includes the method of Example 13, wherein applying the second layer of the substrate to the surface of the first layer of the substrate further includes depositing the second layer.
[0096] Example 19 includes the method of any one of Examples 13 to 18, wherein at least two of the one or more optical waveguides are substantially parallel.
[0097] Example 20 is a package comprising: a substrate including: a first side and a second side opposite to the first side; a recess extending from the first side of the substrate to the second side of the substrate within the substrate; and an optical waveguide within the substrate, the optical waveguide being between the first side and the second side of the substrate, wherein an end of the optical waveguide is located at an edge of the substrate, between the first side and the second side, adjacent to the recess; and a photonic integrated circuit (PIC) optically coupled to the end of the optical waveguide.
[0098] Example 21 includes the package of Example 20, wherein at least a portion of the PIC is disposed within the recess of the substrate.
[0099] Example 22 includes the package of Example 21, and further includes a die electrically coupled to the PIC, wherein at least a portion of the die is disposed within the recess of the substrate.
[0100] Example 23 includes the package of Example 20, wherein the optical waveguide is a first optical waveguide, and wherein the PIC is a first PIC, and further includes: a second optical waveguide within the substrate, the second optical waveguide being between the first side and the second side of the substrate, wherein the end of the optical waveguide is located at the edge of the substrate, between the first side and the second side, and adjacent to the recess; a second PIC optically coupled to the end of the second optical waveguide; a die electrically coupled to the first PIC and the second PIC, and wherein at least a portion of the first PIC, the second PIC, and the die is disposed within the recess of the substrate.
[0101] Example 24 includes the package of Example 20, wherein the end of the optical waveguide is a first end, and further includes a second end of the optical waveguide opposite to the first end, the second end being located at the edge of the substrate not adjacent to the recess.
[0102] Example 25 includes a package of any one of Examples 20 to 24, wherein an optical underfill is disposed between the surface of the end of the optical waveguide and the PIC. [Simplified Explanation of the Diagram]
[0004] [Figure 1] According to various embodiments, a top-down view and a cross-sectional side view of a package are shown, the package including a substrate having a cavity, together with an optical waveguide optically coupled to a die within the substrate and within the cavity at the edge of the substrate.
[0005] [Figure 2] A side view illustrating the optical coupling between an optical waveguide and a photonic integrated circuit (PIC) within a substrate, according to various embodiments.
[0006] [Figure 3] According to various embodiments, a top-down view and a cross-sectional side view of a package are shown, the package including a substrate with recesses, together with a multilayer optical waveguide optically coupled to the die within the substrate and the recesses at the edge of the substrate.
[0007] [Figure 4] According to various embodiments, a top-down view of a package is shown, the package including a substrate having two recesses, together with an optical waveguide optically coupled to a die in the first recess at the edge of the substrate and a die in the second recess at the edge of the substrate.
[0008] [Figure 5] According to various embodiments, a top-down view of a package is shown, the package including a substrate, together with an optical waveguide optically coupled to a die within the substrate and at the edge of the substrate.
[0009] [Figures 6A to 6D] According to various embodiments, the manufacturing process stages for forming an optical waveguide within a substrate are illustrated.
[0010] [Figures 7A to 7E] According to various embodiments, the manufacturing process stages for forming an optical waveguide within a glass substrate are illustrated.
[0011] [Figures 8A to 8C] According to various embodiments, another manufacturing process stage for forming an optical waveguide within a glass substrate is illustrated.
[0012] [Figure 9] Various examples of laser-assisted etching glass interconnect processes are illustrated according to various embodiments.
[0013] [Figure 10] An example of a process for forming an optical waveguide within a substrate is illustrated according to various embodiments.
[0014] [Figure 11] A computing device is schematically illustrated according to various embodiments.
Claims
1. An apparatus comprising: A substrate having a first side and a second side opposite to the first side; And an optical waveguide within the substrate, the optical waveguide being located between the first side and the second side of the substrate, wherein the end of the optical waveguide is located at the edge of the substrate, between the first side and the second side.
2. The equipment as requested in item 1, wherein, The substrate is selected from either a glass substrate or a silicon substrate.
3. The equipment as requested in item 1, wherein, The optical waveguide is a first optical waveguide, and a second optical waveguide is also included within the substrate. The second optical waveguide is located between the first side and the second side of the substrate, wherein the end of the second optical waveguide is attached to the edge of the substrate; and wherein the first optical waveguide is located at a first distance from the first side of the substrate, and wherein the second optical waveguide is located at a second distance from the first side of the substrate.
4. The equipment as requested in item 3, wherein, The first distance and the second distance are the same distance.
5. The equipment as requested in item 3, wherein, The first distance and the second distance are different distances.
6. The equipment as requested in item 1, wherein, The substrate has a recess extending from the first side of the substrate to the second side of the substrate within the substrate, and wherein the edge of the substrate is adjacent to the recess.
7. The equipment as requested in item 6, wherein, The optical waveguide has a first end and further includes a second end opposite to the first end, wherein the second end of the optical waveguide is located at the edge of the substrate that is not adjacent to the recess.
8. The device as requested in item 1, wherein, The waveguide has a first thickness at the edge of the substrate and a second thickness below the edge of the substrate, wherein the first thickness is greater than the second thickness.
9. The equipment as requested in item 1, wherein, The substrate includes a first layer and a second layer, the first layer extending from the first side of the glass substrate and the second layer extending from the second side of the substrate, wherein the optical waveguide system is at least partially disposed within the first layer and within the second layer.
10. The device as requested in item 1, wherein, The optical waveguide is substantially parallel to the first surface of the substrate or parallel to the second surface of the substrate.
11. The equipment requested under items 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10, wherein, The cross-section of the optical waveguide perpendicular to its direction has a shape selected from either a rectangle or a circle.
12. The equipment as requested in items 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10, wherein, The optical waveguide contains one or more of silicon, nitrogen, oxygen, or erbium.
13. A method comprising: Identify the first layer of the substrate; One or more optical waveguides are formed on the surface of the first layer of the substrate; And the second layer of the substrate is applied to the surface of the first layer of the substrate.
14. As in request item 13, wherein, Applying the second layer of the substrate to the surface of the first layer of the substrate further includes encapsulating one or more formed optical waveguides within the substrate.
15. As in request item 13, wherein, The formation of one or more optical waveguides on the surface of the first layer of the substrate further includes depositing optical waveguide material on the surface of the first layer of the substrate.
16. As in request item 13, wherein, The first layer of the substrate is a glass layer, and the formation of the one or more optical waveguides on the surface of the first layer of the substrate further includes forming the one or more optical waveguides in the substrate material of the first layer and the surface of the substrate using one of the selected methods of implanted ions or laser direct writing.
17. As in request item 13, wherein, The one or more optical waveguides contain glass.
18. As in request item 13, wherein, The second layer of the substrate is applied to the surface of the first layer of the substrate, and the second layer is further deposited.
19. The method as described in requests 13, 14, 15, 16, 17, or 18, wherein, At least two of the one or more optical waveguides are substantially parallel.
20. A package comprising: A substrate comprising: a first side and a second side opposite to the first side; a recess extending from the first side to the second side within the substrate; an optical waveguide within the substrate, the optical waveguide being situated between the first side and the second side of the substrate, wherein an end of the optical waveguide is situated at an edge of the substrate, between the first side and the second side, adjacent to the recess; and a photonic integrated circuit (PIC) optically coupled to the end of the optical waveguide.
21. As encapsulated in request item 20, wherein, At least a portion of the PIC is disposed within the recess in the substrate.
22. The package as claimed in claim 21 further includes a die electrically coupled to the PIC, wherein, At least a portion of the grain is disposed within the recess in the substrate.
23. As encapsulated in request item 20, wherein, The optical waveguide is a first optical waveguide, and the PIC is a first PIC, and further includes: a second optical waveguide within the substrate, the second optical waveguide being between the first side and the second side of the substrate, wherein the end of the optical waveguide is located at the edge of the substrate, between the first side and the second side, and adjacent to the recess; a second PIC optically coupled to the end of the second optical waveguide; and a die electrically coupled to the first PIC and the second PIC, wherein at least a portion of the first PIC, the second PIC, and the die is disposed within the recess of the substrate.
24. As encapsulated in request item 20, wherein, The optical waveguide has a first end and also includes a second end opposite to the first end, which is located at the edge of the substrate that is not adjacent to the recess.
25. Encapsulation as requested in items 20, 21, 22, 23, or 24, wherein, The optical underfill is disposed between the surface of the end of the optical waveguide and the PIC.