RF amplifiers having shielded transmission line structures

Abstract

RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

Description

[Technical Field]

[0001] This invention relates to microelectronic devices, and more particularly, to high-power, high-frequency transistor amplifiers. [Previous Technology]

[0002] Circuits requiring high power handling capabilities and high-frequency operation in bands such as R (0.5 GHz to 1 GHz), S (3 GHz), X (10 GHz), Ku (12 GHz to 18 GHz), K (18 GHz to 27 GHz), Ka (27 GHz to 40 GHz), and V (40 GHz to 75 GHz) are becoming increasingly common. Specifically, there is a high demand for radio frequency ("RF") transistor amplifiers for amplifying RF signals at frequencies of, for example, 500 MHz and higher (including microwave frequencies). These RF transistor amplifiers need to exhibit high reliability, good linearity, and the ability to handle high output power levels.

[0003] Most RF transistor amplifiers are implemented using silicon or wide-bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. As used herein, the term “group III nitride” refers to a semiconducting compound formed between nitrogen and a group III element of the periodic table (typically aluminum (Al), gallium (Ga), and / or indium (In)). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have an empirical formula for the combination of 1 mole of nitrogen with a total of 1 mole of group III elements.

[0004] Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal-oxide-semiconductor ("LDMOS") transistors. Silicon LDMOS RF transistor amplifiers exhibit high linearity and are relatively inexpensive to manufacture. Group III nitride-based RF transistor amplifiers are typically implemented as high electron mobility transistors ("HEMTs") and are primarily used in applications requiring high power and / or high-frequency operation, where LDMOS RF transistor amplifiers may have inherent performance limitations.

[0005] An RF transistor amplifier may include one or more amplification stages, wherein each stage is typically implemented as a transistor amplifier. To improve output power and current handling capability, an RF transistor amplifier is typically implemented as a "unit cell" configuration in which a large number of individual "unit cell" transistors are connected in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include a plurality of dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0006] RF transistor amplifiers typically include matching circuitry, such as: (1) an impedance matching circuit designed to improve impedance matching between the RF transistor amplifier chip and the transmission lines to which it is connected (for RF signals at the amplifier's fundamental operating frequency); and (2) a harmonic termination circuit designed to at least partially terminate harmonics, such as second and third harmonics, that may be generated during device operation. (Several) The RF transistor amplifier chip and the impedance matching and harmonic termination circuitry may be enclosed in a package. Electrical leads for electrically connecting the RF transistor amplifier to external circuitry elements (such as input and output RF transmission lines and bias voltage sources) may extend from the package.

[0007] As mentioned above, group III nitride-based RF transistor amplifiers are commonly used in high-power and / or high-frequency applications. Typically, a significant amount of heat is generated within the die of a group III nitride-based RF transistor amplifier during operation. If the RF transistor amplifier die becomes too hot, its performance (e.g., output power, efficiency, linearity, gain, etc.) will deteriorate and / or the RF transistor amplifier die may be damaged. Therefore, group III nitride-based RF transistor amplifiers are typically mounted in packages optimized for heat dissipation.

[0008] Figures 1A to 1D schematically illustrate various views of a conventional group III nitride-based RF transistor amplifier die 10. Specifically, Figure 1A is a schematic plan view of a group III nitride-based RF transistor amplifier die 10, and Figure 1B is a side view of the RF transistor amplifier die 10 taken along line 1B-1B of Figure 1A. Figure 1C is a schematic cross-sectional view showing the metal plating on the top surface of the semiconductor layer structure of the RF transistor amplifier die 10 taken along line 1C-1C of Figure 1B, and Figure 1D is a cross-sectional view of the RF transistor amplifier die 10 taken along line 1D-1D of Figure 1C. Figures 1E and 1F are schematic cross-sectional views illustrating two exemplary embodiments of how the RF transistor amplifier die 10 of Figures 1A to 1D can be packaged to provide packaged RF transistor amplifiers 1A and 1B, respectively. It should be understood that Figures 1A to 1F (and many other figures in this application) are highly simplified diagrams, and actual RF transistor amplifiers may include more unit cells and various circuit systems and components not shown in the simplified diagrams herein.

[0009] As shown in Figure 1A, the RF transistor amplifier chip 10 includes a gate terminal 22 and a drain terminal 24 exposed on the top side of the RF transistor amplifier chip 10. A first circuit element (not shown) can be connected to the gate terminal 22 by, for example, wiring (not shown), and a second circuit element (not shown) can be connected to the drain terminal 24 by, for example, wiring (not shown). The first circuit element can, for example, transmit an input RF signal to be amplified to the RF transistor amplifier chip 10, and the second circuit element can receive an amplified RF signal output from the RF transistor amplifier chip 10. A protective insulating layer or pattern 28 can cover the remaining portion of the top surface of the RF transistor amplifier chip 10.

[0010] As shown in Figures 1B to 1D, the RF transistor amplifier die 10 further includes a semiconductor layer structure 30, a top-side metallization structure 20, and a rear-side metallization structure that serves as one of the source terminals 26 of the RF transistor amplifier die 10.

[0011] The semiconductor layer structure 30 includes a plurality of semiconductor layers. The RF transistor amplifier die 10 may be a HEMT-based RF transistor amplifier die; therefore, the semiconductor layer structure 30 may include at least one channel layer and one barrier layer. Referring to FIG1D, in the illustrated example, a total of three layers are shown: a semiconductor channel layer 34 and a semiconductor barrier layer 36 sequentially formed on a growth substrate 32 (which may be a semiconductor or insulating substrate (such as a SiC or sapphire substrate)). Even if the growth substrate 32 is formed of a non-semiconductor material, it is considered part of the semiconductor layer structure 30.

[0012] Referring again to FIG. 1B, the semiconductor layer structure 30 has a top side 12 and a bottom side 14. A top-side metallization structure 20 is formed on the top side 12 of the semiconductor layer structure 30, and a source terminal 26 is formed on the bottom side 14 of the semiconductor layer structure 30. The top-side metallization structure 20 particularly includes a conductive (typically metallic) gate manifold 42 and a conductive (typically metallic) drain manifold 44, a conductive gate path 43 and a drain path 45, a conductive gate terminal 22 and a drain terminal 24, and gate fingers 52, drain fingers 54, and source fingers 56 (described below). The gate manifold 42 is electrically connected to the gate terminal 22 through the gate path 43, and the drain manifold 44 is electrically connected to the drain terminal 24 through the conductive drain path 45. The gate path 43 and the drain path 45 may include, for example, metal-plated paths or metal pillars formed through a dielectric material (such as silicon oxide or silicon nitride).

[0013] As shown in FIG1C, the RF transistor amplifier die 10 includes a plurality of unit cell transistors 16, one of which is indicated by a dashed box in FIG1C. Each unit cell transistor 16 includes a gate finger 52, a drain finger 54, and a source finger 56. The gate finger 52, drain finger 54, and source finger 56 are formed on the upper surface of the semiconductor layer structure 30 and include a portion of the top-side metallization structure 20. The top-side metallization structure 20 further includes a gate manifold 42 and a drain manifold 44. The gate finger 52 is electrically connected to the gate manifold 42, and the drain finger 54 is electrically connected to the drain manifold 44. The source finger 56 is electrically connected to the source terminal 26 (FIG1B) via a plurality of conductive electrode paths 66 extending through the semiconductor layer structure 30. The conductive electrode paths 66 may include metallized paths extending completely through the semiconductor layer structure 30.

[0014] Figure 1E is a schematic side view of one of the packaged group III nitride-based RF transistor amplifiers 1A, which includes the RF transistor amplifier chip 10 of Figures 1A to 1D. As shown in Figure 1E, the packaged RF transistor amplifier 1A includes the RF transistor amplifier chip 10 and an open cavity package 70. The package 70 includes a metal gate lead 72, a metal drain lead 74, a metal base 76, a ceramic sidewall 78, and a ceramic cap 80.

[0015] The RF transistor amplifier die 10 is mounted on the upper surface of the metal base 76 (which may be a metal flange) within a cavity defined by the metal base 76, ceramic sidewalls 78, and ceramic cap 80. The source terminal 26 of the RF transistor amplifier die 10 can directly contact the metal base 76. The metal base 76 provides electrical connection to the source terminal 26 and also serves as a heat dissipation structure for dissipating heat generated in the RF transistor amplifier die 10. Heat is mainly generated in the upper portion of the RF transistor amplifier die 10, where, for example, a relatively high current density is generated in the channel region of the unit cell transistor 16. This heat can be transferred to the source terminal 26 through the source path 66 and the semiconductor layer structure 30 and then to the metal base 76.

[0016] Input matching circuit 90 and / or output matching circuit 92 may also be mounted within package 70. Matching circuits 90 and 92 may be impedance matching circuits that match the impedance of the fundamental component of the RF signal input to or output from RF transistor amplifier 1A to the impedance at the input or output of RF transistor amplifier chip 10, respectively, and / or harmonic termination circuits configured to ground harmonics of the fundamental RF signal that may exist at the input or output of RF transistor amplifier chip 10. More than one input matching circuit 90 and / or output matching circuit 92 may be provided. As schematically shown in FIG1E, input matching circuit 90 and output matching circuit 92 may be mounted on metal base 76. Gate lead 72 may be connected to input matching circuit 90 via one or more first wires 82, and input matching circuit 90 may be connected to gate terminal 22 of RF transistor amplifier chip 10 via one or more second wires 84. Similarly, drain lead 74 can be connected to output matching circuit 92 via one or more fourth wires 88, and output matching circuit 92 can be connected to drain terminal 24 of RF transistor amplifier chip 10 via one or more third wires 86. Wirings 82, 84, 86, and 88 can form part of input and / or output matching circuitry. Gate lead 72 and drain lead 74 can extend through ceramic sidewall 78. The interior of package 70 may include an air-filled cavity.

[0017] Figure 1F is a schematic side view of another known packaged group III nitride-based RF transistor amplifier 1B. The RF transistor amplifier 1B differs from the RF transistor amplifier 1A in that it includes a different package 70'. Package 70' includes a metal substrate 76 (which acts as a metal heat sink and can be implemented as a metal block) and gate leads 72' and drain leads 74'. The RF transistor amplifier 1B also includes a plastic overmolded material 78' that at least partially surrounds the RF transistor amplifier die 10, leads 72', 74', and the metal substrate 76. Other components of the RF transistor amplifier 1B may be identical to those of the same component symbols in the RF transistor amplifier 1A, and therefore further description thereof will be omitted. [Summary of the Invention]

[0018] According to an embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a semiconductor layer structure; a coupling element located on an upper surface of the semiconductor layer structure; and an interconnect structure located on an upper surface of the coupling element, such that the RF transistor amplifier die and the interconnect structure are stacked. The coupling element includes a first shielded transmission line structure.

[0019] In some embodiments, the first shielded transmission line structure may include a first conductive post electrically connected to a first input / output terminal of one of the RF transistor amplifier chips, and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post. The first conductive ground post and the second conductive ground post are electrically connected to a ground terminal of the RF transistor amplifier chip. The first shielded transmission line structure may further include a third conductive ground post and a fourth conductive ground post on the opposite side of the first conductive post, and the third conductive ground post and the fourth conductive ground post are electrically connected to the ground terminal of the RF transistor amplifier. In some embodiments, the first conductive ground post to the fourth conductive ground post may surround the first conductive post.

[0020] In some embodiments, the first conductive post may vertically overlap with an active region of the RF transistor amplifier die. In some embodiments, the first conductive ground post may additionally or alternatively vertically overlap with a manifold of the RF transistor amplifier die, wherein the manifold is connected to a plurality of conductive fingers extending across an active region of the RF transistor amplifier die. In some embodiments, the second conductive ground post may vertically overlap with a portion of the RF transistor amplifier die outside the active region of the RF transistor amplifier die. In some embodiments, both the first conductive post and the first conductive ground post may vertically overlap with the first input / output terminal.

[0021] In some embodiments, the first input / output terminal may be a gate terminal and the ground terminal may be a source terminal, and the coupling element may further include a second shielded transmission line structure, the second shielded transmission line structure including a second conductive post electrically connected to a drain terminal of the RF transistor amplifier chip and a fifth conductive ground post and a sixth conductive ground post on the opposite side of the second conductive post, the fifth conductive ground post and the sixth conductive ground post being electrically connected to the source terminal.

[0022] In some embodiments, the first input / output terminal may include a gate terminal and the ground terminal may include a source terminal, and the RF transistor amplifier die may further include a drain terminal. In these embodiments, the source terminal may be located on the opposite side of the gate terminal and on the opposite side of the drain terminal.

[0023] In some embodiments, the first conductive post and the third conductive post may be electrically connected to a gate manifold of the RF transistor amplifier chip, and the first conductive ground post may be located between the first conductive post and the third conductive post.

[0024] In some embodiments, the second conductive grounding post may include a metal block having a cross-sectional area in a first plane parallel to one of the main surfaces of one of the RF transistor amplifier chips, the cross-sectional area being at least five times the cross-sectional area of ​​one of the first conductive posts in the first plane.

[0025] In some embodiments, the first conductive grounding post may have a first end and a second end, and the second end may not be connected to a conductive element.

[0026] In some embodiments, the coupling element may further include an injectable underfill material surrounding the first conductive post and one of the first conductive ground post and the second conductive ground post.

[0027] In some embodiments, the interconnect structure may include a second shielded transmission line structure. The second shielded transmission line structure may include, for example, a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment.

[0028] In some embodiments, the semiconductor layer structure may be a group III nitride-based semiconductor layer structure. In some embodiments, the interconnect structure may include a redistributed multilayer structure or a printed circuit board. In some embodiments, a plurality of circuit elements (such as, for example, surface mount capacitors or a surface mount inductor) may be mounted on the interconnect structure.

[0029] In some embodiments, the side of the RF transistor amplifier die that is not connected to the interconnect structure may be encapsulated.

[0030] In some embodiments, the RF transistor amplifier die may further include a gate terminal, a drain terminal, and a source terminal on the upper surface of the semiconductor layer structure. In these embodiments, the first shielded transmission line structure may include a first ground terminal and a second ground terminal electrically connected to a gate post of the gate terminal and an opposite ground terminal, the first ground terminal and the second ground terminal being electrically connected to the source terminal.

[0031] In some embodiments, the first shielded transmission line structure may include a plurality of conductive posts, which are configured such that a first of the conductive posts is a signal carrier post surrounded on at least two sides by additional conductive posts coupled to a ground voltage source. In some embodiments, the first of the conductive posts may be surrounded on at least three sides by a plurality of conductive posts coupled to the ground voltage source.

[0032] In some embodiments, the coupling element may have a fan-in configuration.

[0033] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate fingers and drain fingers extending on one upper surface of the semiconductor layer structure; and a first shielded transmission line structure extending perpendicularly to the upper surface of the semiconductor layer structure.

[0034] In some embodiments, the first shielded transmission line structure may be electrically connected to one of the gate fingers and the drain fingers.

[0035] In some embodiments, the RF transistor amplifier may further include an interconnect structure, wherein the first shielded transmission line structure electrically connects the RF transistor amplifier die to the interconnect structure.

[0036] In some embodiments, the first shielded transmission line structure may include a first conductive post electrically connected to one of the gate fingers or one of the drain fingers, and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post, the first conductive ground post and the second conductive ground post being electrically connected to the source finger of the RF transistor amplifier die. In these embodiments, the first shielded transmission line structure may further include a third conductive ground post and a fourth conductive ground post on the opposite side of the first conductive post, the third conductive ground post and the fourth conductive ground post being electrically connected to the source fingers.

[0037] In some embodiments, the first conductive post may vertically overlap with an active region of the RF transistor amplifier die. In some embodiments, the first conductive ground post may vertically overlap with a manifold of the RF transistor amplifier die electrically connected to the gate fingers or the drain fingers. In some embodiments, the second conductive ground post may vertically overlap with a portion of the RF transistor amplifier die outside the active region of the RF transistor amplifier die. In some embodiments, both the first conductive post and the first conductive ground post may vertically overlap with a gate terminal of the RF transistor amplifier die.

[0038] In some embodiments, the first conductive post and the third conductive post may be electrically connected to a gate manifold of the RF transistor amplifier chip, and the first conductive ground post may be located between the first conductive post and the third conductive post.

[0039] In some embodiments, the interconnect structure may include a second shielded transmission line structure.

[0040] In some embodiments, the RF transistor amplifier die may further include a gate terminal electrically connected to one of the gate fingers, a drain terminal electrically connected to one of the drain fingers, and a source finger electrically connected to a source terminal, wherein the gate terminal, the drain terminal, and the source terminal are all located above the gate fingers, the drain fingers, and the source fingers.

[0041] In some embodiments, the first shielded transmission line structure may include a first grounding post and a second grounding post electrically connected to one of the gate terminals and the opposite side of the gate terminal, the first grounding post and the second grounding post being electrically connected to the source terminal.

[0042] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate fingers, drain fingers and source fingers extending on an upper surface of one of the semiconductor layer structures; and a plurality of conductive pillars extending perpendicularly to the upper surface of the semiconductor layer structure, the conductive pillars including a first conductive pillar electrically connected to one of the gate fingers or the drain fingers and a first conductive ground pillar and a second conductive ground pillar on the opposite side of the first conductive pillar, the first conductive ground pillar and the second conductive ground pillar being electrically connected to the source fingers.

[0043] In some embodiments, the RF transistor amplifier may further include an interconnect structure, and the conductive pillars may extend between the interconnect structure and the RF transistor amplifier die and electrically connect the interconnect structure to the RF transistor amplifier die.

[0044] In some embodiments, the first conductive grounding post, the second conductive grounding post, and at least one additional conductive grounding post may surround the first conductive post.

[0045] In some embodiments, the first conductive post may vertically overlap with an active region of the RF transistor amplifier die, and / or the second conductive ground post may vertically overlap with a portion of the RF transistor amplifier die outside the active region. In some embodiments, the first conductive ground post may vertically overlap with a manifold of the RF transistor amplifier die.

[0046] In some embodiments, the drain fingers may extend from a drain manifold across one of the active regions of the RF transistor amplifier die, and the first conductive post and a third conductive post may be electrically connected to the drain manifold, and the first conductive ground post may be located between the first conductive post and the third conductive post.

[0047] In some embodiments, the semiconductor layer structure may include a group III nitride-based semiconductor layer structure.

[0048] In some embodiments, the conductive pillars may have a fan-in configuration.

[0049] According to an additional embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die including a gate terminal, a drain terminal and a source terminal on a first surface of the RF transistor amplifier die; and an interconnection structure stacked with the RF transistor amplifier die and electrically connected to the RF transistor amplifier die via a shielded transmission line structure.

[0050] In some embodiments, the shielded transmission line structure may include a first conductive post electrically connected to one of the gate terminals and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post, the first conductive ground post and the second conductive ground post being electrically connected to the source terminal.

[0051] In some embodiments, the shielded transmission line structure may include a first conductive post electrically connected to one of the drain terminals and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post, the first conductive ground post and the second conductive ground post being electrically connected to the source terminal.

[0052] In some embodiments, the shielded transmission line structure may further include a third conductive grounding post that surrounds one of the first conductive posts on at least three sides together with the first conductive grounding post and the second conductive grounding post.

[0053] In some embodiments, the first conductive post may be perpendicularly overlapped with one of the active regions of the RF transistor amplifier die. In some embodiments, the first conductive ground post may be perpendicularly overlapped with a gate manifold electrically connected to one of the gate terminals. In some embodiments, both the first conductive post and the first conductive ground post may be perpendicularly overlapped with the gate terminal.

[0054] In some embodiments, the first conductive post and the third conductive post may be electrically connected to a gate manifold of the RF transistor amplifier chip, and the first conductive ground post may be located between the first conductive post and the third conductive post.

[0055] In some embodiments, the interconnect structure may include a second shielded transmission line structure electrically connected to one of the shielded transmission line structures.

[0056] According to an embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die, including a gate terminal, a drain terminal and a source terminal on a first surface of the RF transistor amplifier die; and an interconnect structure stacked with the RF transistor amplifier die, the interconnect structure including a shielded transmission line structure, wherein a ground conductor of the shielded transmission line structure is electrically connected to the source terminal and a signal conductor of the shielded transmission line structure is electrically connected to one of the gate terminal and the drain terminal.

[0057] In some embodiments, the shielded transmission line structure may include a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment.

[0058] In some embodiments, the interconnect structure may include a multilayer structure or a printed circuit board. In some embodiments, a plurality of circuit elements may be mounted on the interconnect structure.

Implementation Method

[0094] Cross-reference to related applications This application claims priority to U.S. Patent Application No. 16 / 888,957, filed June 1, 2020, the entire contents of which are incorporated herein by reference.

[0095] As described above, conventional group III nitride-based packaged RF transistor amplifiers (such as packaged RF transistor amplifiers 1A and 1B of Figures 1E and 1F) typically have the gate and drain terminals on the upper side of the semiconductor layer structure and the source terminal on the lower side of the semiconductor layer structure. A conductive power path extends through the semiconductor layer structure to electrically connect the source finger in the upper portion of the semiconductor layer structure to the source terminal. These conventional RF transistor amplifiers also typically use wiring to connect the RF transistor amplifier chip to other components of a device, such as matching circuitry and / or input / output leads. This wiring has an inherent inductance that can supply some of the inductance for impedance matching and / or harmonic termination circuitry. The amount of inductance provided by the wiring can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the wiring to provide the desired inductance. Unfortunately, as applications move to higher frequencies, the inductance of the wiring may exceed the required inductance for impedance matching and / or harmonic termination circuitry. When this occurs, very short and / or large cross-sectional area wiring can be used to reduce inductance. However, very short wiring may be difficult to solder properly, increasing manufacturing costs and / or leading to higher device failure rates. Large cross-sectional area wiring requires larger gate and drain terminals on the RF transistor amplifier die, resulting in an undesirable increase in the overall size of the RF transistor amplifier die. Furthermore, in some higher frequency applications, very short wiring with large cross-sectional area can even have too much inductance, making it impossible for the matching network to (e.g.) properly terminate second or third harmonics. Although RF transistor amplifiers can be implemented as single-crystal microwave integrated circuit ("MMIC") devices to avoid the problem of excessive wiring inductance, MMIC RF amplifiers are expensive to manufacture and can only be used within the frequency range of the matching circuit, reducing flexibility.

[0096] Furthermore, wire bonding equipment commonly used in mass production may have a tolerance of + / - 1 mil, meaning that the length of any particular wire can become up to 4 mils (i.e., + / - 1 mil at each end of the wire). For high-frequency applications, the inductance variation associated with 4 mils of a wire can be significant; therefore, if the wire is 1 to 2 mils shorter or longer than the nominal length, the performance of the matching circuit will be degraded.

[0097] According to an embodiment of the present invention, a group III nitride-based RF transistor amplifier is provided, comprising an RF transistor amplifier die, wherein the gate, drain, and source terminals of the RF transistor amplifier die are all located on the upper side of the RF transistor amplifier die. The RF transistor amplifier may not include wiring for gate and / or drain connections, which can reduce the inductance present in the circuit. Since all three terminals—gate, drain, and source—are located on the upper side of the RF transistor amplifier die, the RF transistor amplifier according to an embodiment of the present invention can be mounted in a flip-chip configuration, wherein the RF transistor amplifier die can be mounted in a stacked configuration on another substrate (such as an interconnect structure). The interconnect structure may include, for example, other circuit elements of the RF transistor amplifier, such as, for example, impedance matching and / or harmonic termination circuitry.

[0098] In some embodiments, a coupling element may be directly connected to the gate, drain, and / or source terminals of the RF transistor amplifier chip. In some embodiments, the coupling element may electrically connect the gate, drain, and / or source terminals of the RF transistor amplifier chip to an interconnect structure. In other embodiments, the interconnect structure may be omitted, and the coupling element may electrically connect the gate, drain, and / or source terminals of the RF transistor amplifier chip to separately mounted components and / or leads of the RF transistor amplifier.

[0099] Furthermore, since the source terminal can be provided on the upper side of the RF transistor amplifier die, according to embodiments of the invention, one or more ground connections can exist on the upper side of the RF transistor amplifier. These ground connections can be used to implement RF transmission line connections to the gate terminal and / or drain terminal using a shielded (i.e., ground-signal-ground) transmission line structure. Hereinafter, "transmission line structure" refers to any physical structure comprising at least two conductive elements configured as a transmission path for an RF signal. Examples of transmission line structures include microstrip transmission lines, stripline transmission lines, conductive pillars, vias, bumps, pads, sheets, and the like (e.g., a pair of conductive pillars can form a transmission line structure). Hereinafter, "shielded transmission line structure" refers to an RF transmission line structure comprising a signal-carrying conductor and one or more ground conductors adjacent to at least two opposing sides, and a transmission line structure in which three or more ground conductors substantially surround a signal-carrying conductor. For example, a shielded transmission line structure can be formed by positioning a first ground conductor and a second ground conductor on the first and second opposing sides of a signal carrying conductor, or by forming a single conductor surrounding the signal carrying conductor such that it is located on the opposing side of the signal carrying conductor. As another example, a shielded transmission line structure can be formed by positioning the first to third ground conductors in a triangle around a signal carrying conductor. Any number of individual ground conductors can be included in the shielded transmission line structure according to embodiments of the invention, comprising one, two, three, four, five, six, or even more ground conductors. As yet another example, a ring-shaped ground conductor can be formed in a dielectric layer that surrounds (or partially surrounds) a signal carrying conductor formed in the dielectric layer. It should be noted that if there are two different portions extending through a ground conductor and an axis of a signal carrying conductor, the ground conductor is considered to be located on the two opposing sides of the signal carrying conductor. Similarly, if there exists an axis extending through a pair of ground conductors and a signal-carrying conductor, the two ground conductors are located on opposite sides of the signal-carrying conductor. In some embodiments, additional shielded transmission line structures (such as, for example, striplines or coplanar waveguide structures) may be provided in the interconnect structure. Using shielded transmission line structures for connections between and / or within the RF transistor amplifier die and interconnect structure can provide increased signal isolation, reduced insertion loss, and / or improved impedance matching. This can significantly improve the overall performance of the RF transistor amplifier.

[0100] According to some embodiments of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a semiconductor layer structure; a coupling element located on an upper surface of the semiconductor layer structure; and an interconnect structure located on an upper surface of the coupling element, such that the RF transistor amplifier die and the interconnect structure are stacked. The coupling element on the RF transistor amplifier includes a first shielded transmission line structure. The RF transistor amplifier die may include a gate terminal, a drain terminal, and a source terminal on the upper surface of the semiconductor layer structure. The semiconductor layer structure may be a group III nitride-based semiconductor layer structure.

[0101] In some embodiments, the first shielded transmission line structure may include a first conductive post electrically connected to one of the first input / output terminals of one of the RF transistor amplifier chips, and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post, the first conductive ground post and the second conductive ground post being electrically connected to a ground terminal of one of the RF transistor amplifier chips. The first shielded transmission line structure may, as appropriate, include a third conductive ground post and a fourth conductive ground post on the opposite side of the first conductive post, the third conductive ground post and the fourth conductive ground post being electrically connected to the ground terminal of the RF transistor amplifier. The first to fourth conductive ground posts may surround the first conductive post. Furthermore, in some embodiments, the first conductive post may vertically overlap with an active region of one of the RF transistor amplifier chips, and the first conductive ground post may vertically overlap with a manifold of one of the RF transistor amplifier chips or some other portion of the RF transistor amplifier chip outside the active region of one of the RF transistor amplifier chips.

[0102] In some embodiments, the RF transistor amplifier may further include an interconnect structure that can be connected to one of the RF transistor amplifier chips via coupling elements. The interconnect structure may include a second shielded transmission line structure, such as a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment. The interconnect structure may include, for example, a redistributed multilayer structure or a printed circuit board. One or more circuit elements (such as surface mount capacitors or inductors) may be mounted on the interconnect structure.

[0103] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a group III nitride-based semiconductor layer structure, gate fingers and drain fingers extending on one of the upper surfaces of the semiconductor layer structure; and a first shielded transmission line structure extending perpendicularly to the upper surface of the semiconductor layer structure.

[0104] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate fingers, drain fingers, and source fingers extending on an upper surface of one of the semiconductor layer structures; and a plurality of conductive pillars extending perpendicularly to the upper surface of the semiconductor layer structure, each conductive pillar including a first conductive pillar electrically connected to one of the gate fingers or drain fingers and a first conductive ground pillar and a second conductive ground pillar on the opposite side of the first conductive pillar, the first conductive ground pillar and the second conductive ground pillar being electrically connected to the source fingers. Such RF transistor amplifiers may further include an interconnect structure, wherein the conductive pillars extend between the interconnect structure and the RF transistor amplifier die and electrically connect the interconnect structure to the RF transistor amplifier die. The first conductive ground pillar, the second conductive ground pillar, and at least one additional conductive ground pillar surround the first conductive pillar.

[0105] According to an additional embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die including a gate terminal, a drain terminal and a source terminal on a first surface of the RF transistor amplifier die; and an interconnection structure stacked with the RF transistor amplifier die and electrically connected to the RF transistor amplifier die via a shielded transmission line structure.

[0106] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die, including a gate terminal, a drain terminal and a source terminal on a first surface of the RF transistor amplifier die; and an interconnect structure stacked with the RF transistor amplifier die, the interconnect structure including a shielded transmission line structure, wherein a ground conductor of the shielded transmission line structure is electrically connected to the source terminal and a signal conductor of the shielded transmission line structure is electrically connected to one of the gate terminal and the drain terminal.

[0107] The embodiments of the present invention will now be discussed in further detail with reference to Figures 2 to 12.

[0108] FIG2 is a schematic cross-sectional view of an RF transistor amplifier 100 according to an embodiment of the present invention. As shown in FIG2, the RF transistor amplifier 100 includes an RF transistor amplifier die 110, a coupling element 120, and an interconnect structure 130. The RF transistor amplifier die 110 may include a group III nitride-based RF transistor amplifier die, which includes a plurality of unit cell transistors (not shown in the figure). Each unit cell transistor may include a field-effect transistor having a gate, a drain, and a source. The unit cell transistors may be connected in parallel. The RF transistor amplifier die 110 may include a gate terminal 122, a drain terminal 124, and a source terminal 126 connected to the gate, drain, and source terminals of the unit cell transistors. The gate terminal 122, drain terminal 124, and source terminal 126 may all be located on the top side of the RF transistor amplifier die 110.

[0109] As further shown in FIG2, a coupling element 120 is provided on the upper surface of the RF transistor amplifier die 110, and an interconnect structure 130 is provided on the upper surface of the coupling element 120. Therefore, the coupling element 120 may be centrally located between the RF transistor amplifier die 110 and the interconnect structure 130. In some embodiments, the coupling element may include conductive structures (e.g., metal pillars and pads) formed using known semiconductor processing techniques and / or other methods during wafer-level processing (i.e., before dicing a semiconductor wafer containing a plurality of RF transistor amplifier dies 110 into individual RF transistor amplifier dies 110). In these embodiments, an underfill material, such as a capillary underfill material, may be injected to fill the spaces between the conductive structures of the coupling element 120. It should be noted that even though the coupling element is formed as part of the wafer-level processing, for ease of description, it will be described herein as an element separate from the RF transistor amplifier die 110. In other embodiments, the coupling element 120 may be a separate structure, such as, for example, a redistribution layer ("RDL") stacked structure and / or an interposer layer, which may be formed separately from the RF transistor amplifier die and may be attached to or applied to the RF transistor amplifier die 110 during a wafer-level processing step (i.e., before the wafer is diced into individual RF transistor amplifier dies 110). It should also be noted that the interconnect structure 130 may be omitted in some embodiments of the invention, as will be described in more detail below.

[0110] Figures 3A to 3I depict a Group III nitride-based RF transistor amplifier 200 according to certain embodiments of the present invention. Specifically, Figure 3A is a schematic plan view of the Group III nitride-based RF transistor amplifier 200. Figure 3B is a schematic cross-sectional view of the RF transistor amplifier 200 of Figure 3A taken along line 3B-3B of Figure 3A. Figure 3C is a schematic plan view taken along line 3C-3C of Figure 3B, showing a portion of the semiconductor layer structure of the RF transistor amplifier die 210 contained in the RF transistor amplifier 200 that directly contacts the top-side metallized portion. Figures 3D to 3G are schematic cross-sectional views of the RF transistor amplifier 200 taken along lines 3D-3D to 3G-3G of Figure 3C, respectively. Figure 3H is a schematic cross-sectional view taken along line 3H-3H of Figure 3B. Figure 3I is a cross-sectional view of one of the RF transistor amplifiers 200 of Figures 3A to 3H mounted on an interconnect structure 300 such as a printed circuit board. The RF transistor amplifier 200 may or may not include the interconnect structure 300, depending on the specific application.

[0111] Referring to Figures 3A and 3B, a group III nitride-based RF transistor amplifier 200 may include an RF transistor amplifier die 210 and a coupling element 270 mounted on the upper surface of the RF transistor amplifier die 210. Further discussing with reference to Figure 3I, the RF transistor amplifier 200 may further include an interconnect structure 300. The coupling element 270 may be located between the RF transistor amplifier die 210 and the interconnect structure 300 and can electrically connect the RF transistor amplifier die 210 to the interconnect structure 300. The RF transistor amplifier die 210, the coupling element 270, and the interconnect structure 300 may be stacked or configured.

[0112] The RF transistor amplifier die 210 includes a semiconductor layer structure 230 having a top side 212 and a back side 214. A top-side metallization structure 220 is formed on the top side 212 of the semiconductor layer structure 230, and a bottom-side thermal layer 240 is formed on the bottom side 214 of the semiconductor layer structure 230. The top-side metallization structure 220 includes a gate terminal 222, a drain terminal 224, and a source terminal 226, as well as other plated metals discussed in further detail below. It should be noted that although the gate terminal 222, drain terminal 224, and source terminal 226 are described herein as each being a single terminal, any of these terminals may alternatively include multiple individual terminals electrically connected to each other. The RF transistor amplifier die 210 may be a HEMT-based RF transistor amplifier die, in which case the semiconductor layer structure 230 may include at least a channel layer and a barrier layer, as discussed in more detail below.

[0113] Gate terminal 222 can receive RF signals input to RF transistor amplifier chip 210 from a first external circuit, and drain terminal 224 can output RF signals amplified by RF transistor amplifier chip 210 to a second external circuit. Gate terminal 222 and drain terminal 224 are generally referred to as input / output terminals herein.

[0114] Coupling element 270 is formed on top of RF transistor amplifier die 210 on top-side metallization structure 220. Coupling element 270 can be used to connect RF transistor amplifier die 210 to another structure, such as an interconnect structure (see FIG. 3I). As described above, in some embodiments, coupling element 270 may be formed using semiconductor and / or non-semiconductor processing techniques during wafer-level processing. In other embodiments, coupling element 270 may include a separate structure, such as (for example) an RDL stacked structure or an interposer. An RDL stacked structure refers to a substrate having a conductive layer pattern and / or conductive pathways. As will be discussed in detail below, according to embodiments of the present invention, coupling element 270 may include a shielded ground-signal-ground transmission line structure that can exhibit increased signal isolation, reduced insertion loss, and / or improved impedance matching.

[0115] The coupling element 270 can be used to connect the RF transistor amplifier chip 210 to another structure, such as an interconnect structure. Figure 3I illustrates how the coupling element 270 can be used to connect the RF transistor amplifier chip 210 to an interconnect structure 300 in the form of a printed circuit board.

[0116] As shown in Figures 3A and 3B, the coupling element 270 includes a gate connection pad 272, a drain connection pad 274, and a source connection pad 276. Each of these connection pads 272, 274, and 276 may include, for example, an exposed copper pad, but the invention is not limited thereto. The gate connection pad 272 may be electrically coupled to the gate terminal 222 via one or more conductive gate posts 273. Similarly, the drain connection pad 274 may be electrically coupled to the drain terminal 224 via one or more conductive drain posts 275, and the source connection pad 276 may be electrically coupled to (a number of) source terminals 226 via one or more conductive power posts 277. Additional conductive power posts 279, which will be discussed in further detail below, may also be provided.

[0117] In some embodiments, the combination of the RF transistor amplifier die 210 and the coupling element 270 may have a fan-in configuration. The fan-in configuration can be used to position the gate connection pad 272 inward relative to the gate terminal 222 (i.e., closer to the center of the coupling element when viewed in a plan view) and / or to position the drain connection pad 274 inward from the drain terminal 224. However, the invention is not limited to devices having such fan-in configurations. For example, as will be discussed below with reference to Figures 5A through 5F, in other embodiments, the connection may be neither fan-in nor fan-out, and it should be understood that fan-out connections are also feasible.

[0118] In some embodiments, the coupling element 270 may be formed as part of a wafer-level processing operation. For example, the coupling element 270 may be formed by forming a conductive gate post 273 on the gate terminal 222, a conductive drain post 275 on the drain terminal 224, and a conductive power post 277 on the source terminal 226. In some embodiments, the conductive posts 273, 275, and 277 may include copper posts. For example, the conductive posts may be formed by electroplating a copper seed layer on the gate terminal 222, drain terminal 224, and source terminal 226 and forming the conductive posts 273, 275, and 277 on the copper seed layer using one or more masks. Then, a gate connection pad 272, a drain connection pad 274, and a source connection pad 276 may be formed on their respective gate posts 273, drain posts 275, and source posts 277. Conductive posts 273, 275, 277 and connecting pads 272, 274, 276 may be at least partially housed within an encapsulation structure 278, which may include a dielectric material. Various dielectric materials may be used, including, for example, silicon oxide, silicon nitride, a polymer, a molding compound, and / or combinations thereof. The dielectric material may be processed (e.g., planarized) to expose the gate connecting pad 272, the drain connecting pad 274, and / or the source connecting pad 276. When the coupling element 270 is formed using a wafer-level process, a plurality of coupling elements 270 may be formed (one on top of each RF transistor amplifier die 210 in the wafer), and the RF transistor amplifier die 210 may then be monolithically formed together with the individual coupling elements 270 formed thereon.

[0119] In some embodiments, the coupling element 270 can be formed in a chip-first or chip-last process. In a chip-first process, the coupling element 270 can be formed directly on the RF transistor amplifier die 210 (or on a wafer containing the RF transistor amplifier die 210). For example, a seed layer can be deposited (e.g., on one or more of the gate terminal 222, drain terminal 224, and one or more source terminals 226). The seed layer can then be patterned and electroplated to form a conductive material layer. This process can be repeated multiple times to form conductive pillars 273, 275, 277 and connection pads 272, 274, 276. The conductive pillars 273, 275, 277 and connection pads 272, 274, 276 can then be encapsulated in an encapsulation structure 278 to form the coupling element 270.

[0120] In a post-wafer assembly process, a coupling element 270 may be formed on a temporary carrier layer (not shown). Conductive pillars 273, 275, 277 and connection pads 272, 274, 276 may be formed on the temporary carrier layer in a manner similar to a pre-wafer assembly process. Upon completion, the coupling element 270 may be decoupled from the temporary carrier layer and then coupled to the RF transistor amplifier die 210 (as part of a wafer-level or wafer-level process). For example, the coupling element 270 may be coupled to one or more of the gate terminal 222, drain terminal 224, and source terminal 226 (e.g., via soldering).

[0121] Other coupling elements 270 may be used alternatively, such as (for example) a printed circuit board (e.g., a multilayer printed circuit board), an RDL multilayer structure, a ceramic substrate containing conductive paths and / or pads, or any coupling suitable for electrical connection to the RF transistor amplifier die 210. In some configurations, as will be further discussed herein, coupling element 270 may be omitted.

[0122] The configuration of conductive pillars 273, 275, 277 and connecting pads 272, 274, 276 shown in Figures 3A to 3B is only one example, and other configurations are also possible without departing from the present invention.

[0123] In an embodiment where the semiconductor layer structure 230 of the RF transistor amplifier die 210 has high thermal conductivity, the rear side of the RF transistor amplifier die 210 may be mounted on a thermally conductive carrier substrate or abutment (such as a metal block, lead frame, or flange) to provide improved heat dissipation from the heat generated by the RF transistor amplifier die from the amplifier package. A thermal layer 240 may be formed on the rear side 214 of the semiconductor layer structure 230. The thermal layer 240 may be configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate or abutment. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die attachment layer, such as a eutectic layer. The thermal layer 240 may be a metal layer for forming a eutectic or other metallic bond. In some embodiments, the thermal layer 240 may be a thermal adhesive.

[0124] Figure 3C is a schematic plan view of an RF transistor amplifier die 210 taken along line 3C-3C of Figure 3B, representing a portion of the top metallization structure 220 of the contact semiconductor layer structure 230. The RF transistor amplifier die 210 may include a group III nitride-based HEMT RF transistor amplifier, which includes a plurality of unit transistors 216 electrically connected in parallel with each other.

[0125] As shown in FIG3C, the RF transistor amplifier die 210 includes a gate manifold 242 and a drain manifold 244, a plurality of gate fingers 252, a plurality of drain fingers 254, and a plurality of source fingers 246, all of which can be formed on one of the upper surfaces of the semiconductor layer structure 230. The gate manifold 242 and the gate fingers 252 are portions of the gate electrode of the RF transistor amplifier die 210. The gate manifold 242 and the gate fingers 252 may be implemented as a first integral metal pattern, but the present invention is not limited thereto. The drain manifold 244 and the drain fingers 254 are portions of the drain electrode of the RF transistor amplifier die 210, and may be implemented as a second integral metal pattern, but the present invention is not limited thereto. The region between the gate manifold 242 and the drain manifold 244, which includes the unit transistor 216, is referred to as the active region 218 of the RF transistor amplifier die 210.

[0126] Gate finger 252 may be formed of a material capable of forming a Schottky contact with a group III nitride-based semiconductor material (such as Ni, Pt, Cu, Pd, Cr, W and / or WSiN). Drain finger 254 and source finger 246 may comprise a metal, such as TiAlN, capable of forming an ohmic contact with a group III nitride-based material. A dielectric layer (or a series of dielectric layers) that helps to isolate the gate manifold 242 / gate finger 252, drain manifold 244 / drain finger 254 and source finger 246 from each other is not shown in Figure 3C to better illustrate the components of the RF transistor amplifier die 210.

[0127] Figure 3C shows one of the unit cell transistors 216. The unit cell transistor 216 includes a gate finger 252, a drain finger 254, and a source finger 246, and a portion beneath the semiconductor layer structure 230. Since all the gate fingers 252 are electrically connected to a common gate manifold 242, all the drain fingers 254 are electrically connected to a common drain manifold 244, and all the source fingers 246 are electrically connected together via source terminals 226 (discussed below), it can be seen that all the unit cell transistors 216 are electrically connected together in parallel.

[0128] The unit transistor 216 may be a HEMT device. For example, suitable structures for a Group III nitride-based HEMT device utilizing embodiments of the present invention are described in the following: Commonly assigned U.S. Patent Publication No. 2002 / 0066908A1, published June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same"; U.S. Patent Publication No. 2002 / 0167023A1, published November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; and U.S. Patent Publication No. 2004 / 0061129, published April 1, 2004, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact". The full text of U.S. Patent No. 7,906,799, "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess", issued March 15, 2011, and U.S. Patent No. 6,316,793, issued November 13, 2001, entitled "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates", is incorporated herein by reference.

[0129] Referring to Figures 3D to 3G, the semiconductor layer structure 230 includes a growth substrate 232 and a plurality of semiconductor layers formed thereon. In the depicted embodiment, the growth substrate 232 exhibits a total of two semiconductor layers, namely, a channel layer 234 and a barrier layer 236 on one top side of the channel layer 234. The semiconductor layer structure 230 may include additional semiconductor and / or non-semiconductor layers, such as selected buffer, nucleation, and / or transition layers (not shown) that can be provided on the growth substrate 232 below the channel layer 234. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the SiC growth substrate 232 and the remainder of the semiconductor layer structure 230. Alternatively, several strain-balanced transition layers may be provided, such as those described in U.S. Patent Publication No. 2003 / 0102482A1, jointly assigned to U.S. Patent No. 2003 / 0102482A1, published June 5, 2003, entitled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," the entire contents of which are incorporated herein by reference as if fully described herein. The growth substrate 232 may include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the growth substrate may be or include a different semiconductor material (e.g., a group III nitride-based material, Si, GaAs, ZnO, InP) or a non-semiconductor material (e.g., sapphire).

[0130] Compared to sapphire (Al₂O₃) or silicon (which are very common substrate materials for group III nitride devices), SiC has a significantly tighter lattice match with group III nitrides. This tighter lattice match of SiC results in higher quality group III nitride films than those typically used on sapphire or silicon. SiC also has very high thermal conductivity, meaning that the total output power of group III nitride devices on silicon carbide is generally not as limited by substrate heat dissipation as the same devices formed on sapphire. Furthermore, the availability of semi-insulating SiC substrates provides device isolation and reduces parasitic capacitance.

[0131] In some embodiments, the channel layer 234 is a group III nitride material (such as Al xGa 1-xN, where 0 ≤ x < 1), provided that the energy at the conduction band edge of the channel layer 234 is less than the energy at the conduction band edge of the barrier layer 236 at the interface between the channel layer 234 and the barrier layer 236. In some embodiments of the invention, x = 0, which indicates that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 may also be other group III nitrides, such as InGaN, AlInGaN, or the like. The channel layer 234 may be undoped or unintentionally doped and may be grown to a thickness greater than, for example, about 2 nm. The channel layer 234 may also be a multilayer structure, such as a superlattice or a combination of GaN, AlGaN, or the like.

[0132] The channel layer 234 may have a band gap smaller than at least a portion of the band gap of the barrier layer 236, and the channel layer 234 may also have an electron affinity greater than that of the barrier layer 236. In some embodiments, the barrier layer 236 is a combination of AlN, AlInN, AlGaN, or AlInGaN layers or the like with a thickness between about 0.1 nm and about 30 nm or greater. In a particular embodiment, the barrier layer 236 is sufficiently thick and has a sufficiently high Al composition and doping to induce a significant carrier concentration at the interface between the channel layer 234 and the barrier layer 236.

[0133] The barrier layer 236 may be a group III nitride and may have a band gap greater than that of the channel layer 234 and an electron affinity less than that of the channel layer 234. In some embodiments, the barrier layer 236 is undoped or doped with an n-type dopant at a concentration of less than about 10¹⁹ cm⁻³. In some embodiments of the invention, the barrier layer 236 is Al xGa 1-xN, where 0 < x < 1. In a particular embodiment, the aluminum concentration is about 25%. However, in other embodiments of the invention, the barrier layer 236 comprises AlGaN having an aluminum concentration between about 5% and about 100%. In a particular embodiment of the invention, the aluminum concentration is greater than about 10%. In some embodiments, the barrier layer 236 may be implemented as a hierarchical layer and / or multiple layers.

[0134] Due to the bandgap difference between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced in the channel layer 234 at a junction between the channel layer 234 and the barrier layer 236. The 2DEG acts as a highly conductive layer that allows connection between the source region and its associated drain region of each unit cell transistor 216, wherein the source region is a portion of the semiconductor layer structure 230 directly below the source finger 246 and the drain region is a portion of the semiconductor layer structure 230 directly below the corresponding drain finger 254.

[0135] An interlayer insulating layer (not shown in the figure) may be formed above the gate finger 252, drain finger 254 and source finger 246. The interlayer insulating layer may contain a dielectric material, such as SiN, SiO2, etc.

[0136] As shown in the figures, for example in Figure 3D, gate terminal 222 may be physically and electrically connected to gate manifold 242 via conductive path 243, drain terminal 224 may be physically and electrically connected to drain manifold 244 via conductive path 245, and source terminal 226 may be physically and electrically connected to source finger 246 via conductive path 247. Although the various terminals 222, 224, 226 are shown as being directly connected to gate manifold 242 / drain manifold 244 and / or source finger 246, it should be understood that in some embodiments, intermediate elements may be present. For example, in some embodiments, capacitors, inductors, resistors, etc., may be coupled between the terminals and their respective manifolds and / or fingers. As an example, a capacitor may be formed on the surface of RF transistor amplifier die 210 coupled to drain manifold 244, and drain terminal 224 may be coupled to the capacitor.

[0137] Since all terminals 222, 224, and 226 are located on the top side of the RF transistor amplifier die 210, there is no need for a conductive path extending through the semiconductor layer structure 230 to the rear side of the RF transistor amplifier die 210. Because there is no path connecting the source to a grounded conductive base on the rear side of the RF transistor amplifier die 210, the base can be completely omitted or a non-conductive base can be used. Furthermore, the rear side of the RF transistor amplifier die 210 can be coupled to a thermally conductive base or layer 240 (such as a heat sink) to provide improved heat dissipation. In some embodiments, the thermal layer 240 can facilitate this thermal coupling. When SiC is used as a substrate material (for substrate 232), the thermal properties of the package can be further improved due to the improved thermal conductivity of SiC.

[0138] Furthermore, placing all terminals 222, 224, and 226 on the top side of the RF transistor amplifier chip 210 allows the use of coupling element 270, which brings all transistor connections to their respective connection pads. This allows the RF transistor amplifier chip 210 to be further coupled to other components of the circuit (e.g., other routing components, grounding components, harmonic and / or input / output impedance matching components) by using connection methods that avoid wiring (such as soldering). As will be discussed in detail below, positioning all terminals on the top side of the RF transistor amplifier chip 210 also allows the use of shielded transmission line structures within coupling element 270, which provides various advantages including increased signal isolation, reduced insertion loss, and / or improved impedance matching.

[0139] Figure 3E is a cross-section obtained through the gate post 273. As shown, each gate post 273 extends between the gate terminal 222 and the gate connection pad 272. A plurality of source posts 281 are also shown in Figure 3E. Each source post 281 extends upward from the source terminal 226. However, the source posts 281 are shorter than the aforementioned source posts 277, so that the gate connection pad 272 can extend above the source posts 281 and be electrically isolated from the source posts 281. In the depicted embodiment, the gate posts 273 are positioned above the gate finger 252 and the drain finger 254, but embodiments of the present invention are not limited thereto. A cross-sectional line 3E'-3E' is also shown in Figure 3C. A cross-section taken along this line looks the same as in Figure 3E, except that gate terminal 222 will be drain terminal 224, gate post 273 will be drain post 275, and gate connection pad 272 will be drain connection pad 274.

[0140] Figure 3F illustrates one example of the plated metal formed above the gate manifold 242. As shown, individual gate terminals 222 are provided above the gate manifold 242 and electrically connected to the gate manifold 242 via the gate passage 243. Although multiple individual gate terminals 222 are shown, it should be understood that a single, larger gate terminal 222 may be used alternatively. As shown in Figures 3B and 3H, the gate terminal 222 extends in the x-direction, allowing the gate post 273 to be laterally offset (in the x-direction) from the gate passage 243. This allows source posts 279 to be formed above the gate manifold 242 (and gate terminals 222). The source posts 279 formed above the gate terminal 222 may be shorter in length than the source posts 277 formed above the source terminal 226, such that a gap 283 is provided between each source post 279 and its respective gate terminal 222 to prevent electrical short circuits between them. As shown in Figure 3F, the source terminal 279 is connected to the source connection pad 276.

[0141] Figure 3G illustrates one example of the plated metal formed above the drain manifold 244. As shown, individual drain terminals 224 are provided above the drain manifold 244 and electrically connected to the drain manifold 244 via drain passage 245. Although multiple individual drain terminals 224 are shown, it should be understood that a single, larger drain terminal 224 can be used alternatively. As shown in Figures 3B and 3H, the drain terminal 224 extends in the x-direction, allowing the drain post 275 to be laterally offset from the drain passage 245. This allows the source post 279 to be formed above the drain manifold 244 (and the drain terminal 224). The source post 279 formed above the drain terminal 224 may be shorter in length than the source post 277 formed above the source terminal 226, such that a gap 283 is provided between each source post 279 and its respective drain terminal 224 to prevent electrical short circuits between them. The source terminal 279 is connected to the source connection pad 276, as shown in Figure 3G.

[0142] As mentioned above, Figure 3H is a cross-sectional view taken along line 3H-3H of Figure 3B showing the arrangement of pillars 273, 275, 277, 279, and 281 included in the coupling element 270. As can be seen on the left side of Figure 3H, the three conductive gate pillars 273 extend upward from the gate terminal 222 to connect to the gate connection pad 272 (see Figures 3A to 3B and Figure 3E). The RF signal input to the RF transistor amplifier chip 210 is transmitted from an external structure to the gate connection pad 272, and then through the gate pillars 273 to the gate terminal 222. The gate terminal 222 feeds the gate signal to the gate finger 252 through the gate path 243 and the gate manifold 242. Therefore, the gate pillars 273 are part of a transmission line used to input the RF signal to the RF transistor amplifier chip 210. As can be seen from Figure 3H, a source path 277, a source path 279, and two source paths 281 surround each gate terminal 273. The four source paths 277, 279, and 281 in each group define a circle surrounding each gate terminal 273, with the source paths 277, 279, and 281 spaced approximately 90 degrees apart. Since the source of the RF transistor amplifier die 210 is maintained at a ground voltage during operation, each gate terminal 273 and its surrounding source paths 277, 279, and 281 form a shielded transmission line segment 285. The shielded transmission line structure can extend perpendicularly to the upper surface of the semiconductor layer structure 230. The source paths 277, 279, and 281 serve to reduce the emission of RF energy transmitted along the transmission line segment 285 and also shield the gate terminal 273 from RF energy from other sources. The drain post 275 has the same design as the drain posts 275 surrounded by four source paths 277, 279, and 281 to form another set of shielded transmission segments 285 for carrying the RF signal output from the RF transistor amplifier chip 210 to an external circuit element. The two shielded transmission segments 285 are shown as dashed circles in Figure 3H. By making the transmission segments 285 shielded transmission segments, the transmission segments can be better isolated from external RF interference and / or noise, resulting in reduced insertion loss and / or improved impedance matching (thereby reducing return loss).

[0143] In the embodiments of Figures 3A to 3H, four source terminals 277, 279, and 281 surround each gate terminal 273 and each drain terminal 275. Source terminals 277, 279, and 281 may also be referred to herein as ground terminals, since source terminal 226 (which is electrically connected to source terminals 277, 279, and 281) is typically coupled to electrical ground during device operation. As best illustrated in Figures 3B and 3H, to provide a source terminal 279 on the exterior of each gate terminal 273 and each drain terminal 275, gate terminal 222 and drain terminal 224 are each designed to have a fan-in configuration to leave space for the source terminal 277 on the exterior of each gate terminal 273 and drain terminal 275.

[0144] As can be seen from Figure 3H, each gate post 273 and each drain post 275 is perpendicularly overlapped with the active region 218 of the RF transistor amplifier die 210. In this document, one element of an RF transistor amplifier is "perpendicularly overlapped" with another element if an axis perpendicular to one of the main surfaces of the semiconductor layer structure 230 passes through the two elements. As can also be seen from Figure 3H, the source post 279 on the left side of the coupling element 270 is perpendicularly overlapped with the gate manifold 242, and the source post 279 on the right side of the coupling element 270 is perpendicularly overlapped with the drain manifold 244. All source posts 279 can be perpendicularly overlapped with their respective portions of the RF transistor amplifier die 210 outside the active region 218. As can also be seen from Figure 3H, one of the gate posts 273 and one of the source posts 279 are perpendicularly overlapped with each gate terminal 222, and one of the drain posts 275 and one of the source posts 279 are perpendicularly overlapped with each drain terminal 224.

[0145] As also shown in Figure 3H, in some embodiments, the source terminal 226 may be implemented as a single, integral structure. This source terminal 226 may be connected to the source finger 246 via a source passage 247, which is not visible in the view of Figure 3H because it is covered by the source terminal 226, but its location below the source terminal 226 is shown by a dashed circle. It should also be understood that in other embodiments, a plurality of smaller source terminals 226 may be provided (e.g., a single source terminal 226 may be provided above each source finger 246), and a source connection pad 276 may electrically connect the source terminal 226 and the source finger 246 together. Note that in Figure 3H, the source posts 277, 281 connecting the source terminal 226 to the source connection pad 276 are visible, but the source connection pad 276 itself is not visible because its cross-section is obtained through the posts. Figure 3A shows the shape of the source connection pad in the embodiments of Figures 3A to 3I in a plan view.

[0146] Figure 3I is a schematic cross-sectional view of one of the RF transistor amplifiers 200, wherein the RF transistor amplifier 200 further includes an interconnect structure 300 mounted to a coupling element 270. The coupling element 270 can be used to connect the RF transistor amplifier chip 210 to the interconnect structure 300. Since the RF transistor amplifier chip 210 and the coupling element 270 have been discussed in detail above with reference to Figures 3A to 3H, the following discussion will focus on the interconnect structure 300.

[0147] The interconnect structure 300 can be used to connect the RF transistor amplifier chip 210 to other circuit elements. For example, the interconnect structure 300 may include an RF input 301 that receives an RF signal coupled to the input of the RF transistor amplifier chip 210, an RF output 308 that receives an RF signal output from the RF transistor amplifier chip 210, and one or more ground inputs 309 that each receive a ground reference voltage. The interconnect structure 300 may further include a first interconnect pad 372 that can be configured to couple to a gate connection pad 272, a second interconnect pad 374 that can be configured to couple to a drain connection pad 274, and a third interconnect pad 376 that can be configured to couple to a source connection pad 276 of the coupling element 270.

[0148] In some embodiments, a bonding element 360 (e.g., solder balls and / or bumps, conductive die attachment material, etc.) may be used to couple the first interconnect pad 372, the second interconnect pad 374, and the third interconnect pad 376 to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276, respectively. Although illustrated as a single pad, in some embodiments, one or more of the first interconnect pad 372, the second interconnect pad 374, and the third interconnect pad 376 may comprise a plurality of pads.

[0149] Each of the first interconnect pad 372, the second interconnect pad 374, and the third interconnect pad 376 may be coupled to one or more conductive patterns 329 within the interconnect structure 300. The conductive patterns 329 may provide various routing and / or circuitry within the interconnect structure 300. For example, the conductive patterns 329 may connect the first interconnect pad 372 to one or more first surface mount pads 312-1, 312-2 and the RF input 301. The conductive patterns 329 may also connect the second interconnect pad 374 to one or more second surface mount pads 322-1, 322-2 and the RF output 308. The conductive patterns 329 may also connect the third interconnect pad 376 to one or more third surface mount pads 332 and one or more ground pads 309. Therefore, the interconnect structure 300 may have a surface (e.g., a top surface) having a plurality of first surface connection pads 312 (each of which is coupled to the gate connection pad 272 of the coupling element 270), a plurality of second surface connection pads 322 (each of which is coupled to the drain connection pad 274 of the coupling element 270), and a plurality of third surface connection pads 332 (each of which is coupled to the source connection pad 276 of the coupling element 270).

[0150] The conductive pattern 329 may be enclosed in an insulating material 315. In some embodiments, the insulating material 315 may comprise, for example, silicon oxide, silicon nitride, a polymer, a molding compound, a dielectric substrate, or a combination thereof. In some embodiments, the interconnect structure 300 may be formed as a printed circuit board (PCB). In a PCB embodiment, the insulating material 315 may be the substrate of the PCB, and the conductive pattern 329 may be traces formed within the substrate and plated or metal-filled pathways.

[0151] Circuit element 350 may also be formed on and / or within interconnect structure 300. For example, circuit element 350 may be coupled (e.g., via soldering or other bonding) to two or more of the first surface mount pad 312, the second surface mount pad 322, and the third surface mount pad 332. Circuit element 350 may provide various electronic capabilities to RF transistor amplifier 200. For example, circuit element 350 may include impedances (including, for example, resistors, inductors, and capacitors) that can be used for impedance matching and / or harmonic termination. Conductive pattern 329 allows circuit element 350 to be coupled along input or output paths in various configurations.

[0152] Although illustrated on the surface of interconnect structure 300, it should be understood that additional circuit elements 350 may be provided within interconnect structure 300. For example, parallel plate capacitors, interdigitated capacitors, and / or capacitors formed between conductive paths may be implemented within interconnect structure 300. Similarly, spiral inductors or other inductive elements may be implemented within interconnect structure 300. Resistive elements may be formed on or within interconnect structure 300 by, for example, forming trace segments or conductive paths using a higher resistivity conductive material. In some embodiments, circuit elements 350 and / or conductive patterns 329 may be configured to provide at least a portion of harmonic termination circuit systems, matching circuit systems, shunt circuit systems, combination circuit systems, and / or bias circuit systems. Other configurations of conductive patterns 329 and / or other types of circuit elements 350 may be used without departing from the scope of the invention.

[0153] One or more ground planes and / or traces 342 may be formed within the interconnect structure 300. These ground planes may be used to form a stripline transmission line structure 344 within the interconnect structure 300. Such a stripline transmission line structure is shown in FIG. 3I within a dashed ellipse. Signal carrying paths 310 and / or 320 may also have ground paths 318 on their opposite sides to form a vertically shielded RF transmission line structure 344 within the interconnect structure 300. It should also be understood that the configuration of the conductive patterns 329 and circuit elements 350 shown in FIG. 3I is merely an example and is not intended to limit the embodiments of the present invention.

[0154] As will be discussed below with reference to Figures 10A to 10G, in some embodiments, the interconnect structure 300 and circuit element 350 may be encapsulated within an encapsulation material (not shown). The encapsulation material may comprise, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof.

[0155] As shown in Figure 3I, the interconnect structure 300 combined with the top-side contacts of the RF transistor amplifier die 210 allows for the convenient addition of additional functions such as impedance matching and / or harmonic termination to the RF transistor amplifier 200 without the use of epitaxial wire bonding. Therefore, different functions and / or capabilities can be coupled to an RF transistor amplifier 200 using only a different interconnect structure 300. Reducing or eliminating the need for wire bonding also allows for a smaller die size in some applications (where the size of the wire bonding pads affects the die size), thus the RF transistor amplifier die according to embodiments of the present invention can also exhibit increased integration density. Therefore, the RF transistor amplifier die according to embodiments of the present invention can exhibit improved product assembly consistency, higher throughput, improved product integration, reduced costs, and improved RF performance, especially for products operating at high frequencies such as millimeter wave frequencies.

[0156] Figure 3J is a schematic cross-sectional view of an RF transistor amplifier 200A, similar to the RF transistor amplifier 200 in Figure 3I. The difference between RF transistor amplifiers 200 and 200A is that RF transistor amplifier 200A includes an interconnect structure 300A, wherein circuit elements 350 are mounted on the same side of interconnect structure 300A as RF transistor amplifier die 210. It should be understood that in other embodiments, circuit elements 350 may be provided on both main surfaces of interconnect structures 300 and 300A. It should also be understood that RF input 301, RF output 308 receiving RF signals from RF transistor amplifier die 210, and one or more ground inputs 309 each receiving a ground reference voltage may be provided on any main surface of the interconnect structure (and inputs 301, 308, and 309 need not all be on the same main surface). These different configurations can facilitate different packaging schemes.

[0157] The techniques disclosed herein are particularly advantageous in higher frequency applications because the required inductance in the matching circuit can be much lower, thus avoiding the injection of excessive inductance using conventional wiring. Additionally, the tolerance for wiring length can have a greater impact at higher frequencies, and in high-frequency applications (especially at lower power), the size of the bonding pads affects the die size. In some embodiments, any of the RF transistor amplifier dies disclosed herein can be configured to operate at frequencies greater than 1 GHz. In other embodiments, such RF transistor amplifier dies can be configured to operate at frequencies greater than 2.5 GHz. In other embodiments, such RF transistor amplifier dies can be configured to operate at frequencies greater than 3.1 GHz. In additional embodiments, such RF transistor amplifier dies can be configured to operate at frequencies greater than 5 GHz. In some embodiments, these RF transistor amplifier chips can be configured to operate in at least one of the following frequency bands or sub-bands: 2.5 GHz to 2.7 GHz, 3.4 GHz to 4.2 GHz, 5.1 GHz to 5.8 GHz, 12 GHz to 18 GHz, 18 GHz to 27 GHz, 27 GHz to 40 GHz, or 40 GHz to 75 GHz.

[0158] In the above embodiments, the gate manifold 242 and the gate terminal 222 are separate elements, and the drain manifold 244 and the drain terminal 224 are separate elements (e.g., connected by passages 243 and 245 respectively). The invention is not limited thereto. For example, the gate manifold 242 and the gate terminal 222 may be formed as a single integral structure and / or the drain manifold 244 and the drain terminal 224 may similarly be formed as a single integral structure.

[0159] Although Figures 3A to 3I illustrate a semiconductor layer structure 230 including a HEMT, it should be understood that other types of semiconductor devices may be formed in the semiconductor layer structure 230 without departing from the present invention. For example, the semiconductor layer structure 230 may include a MOSFET, a DMOS transistor, a MESFET, and / or an LDMOS transistor. Those skilled in the art will recognize that the configuration of all source / drain / gate contacts on one side of the semiconductor layer structure 230 (including the use of coupling element 270) allows for improved connectivity and thermal performance.

[0160] By placing the gate, drain, and source contacts on the same side of one of the RF transistor amplifier chips 210, previously infeasible connection options can be used. These connection options also allow for embodiments that can more effectively utilize the improved thermal conductivity of SiC materials.

[0161] Figure 3K is a schematic cross-sectional view of an RF transistor amplifier 200A', which is a modified version of the RF transistor amplifier 200 of Figures 3A to 3I. As shown in Figure 3K, the RF transistor amplifier 200A' is very similar to the RF transistor amplifier 200. However, the source terminal 226 is raised above the gate terminal 222 and drain terminal 224 and extends further outward in the X direction. This modified configuration allows the lower surface of each source terminal 279 to connect to the source terminal 226, because the source terminal 226 can extend above the top of the gate terminal 222 and drain terminal 224 while maintaining electrical isolation from the gate terminal 222 and drain terminal 224. The gate terminal 273 and drain terminal 275E can extend through the opening in the source terminal 226. The opening in the source terminal 226 can be similar to the opening in the source terminal 226G shown in Figure 5I (see discussion below).

[0162] Figure 3L is a schematic cross-sectional view of an RF transistor amplifier 200B, which is another modified version of the group III nitride-based RF transistor amplifier 200 shown in Figures 3A to 3H. The main difference between RF transistor amplifier 200B and 200 is that RF transistor amplifier 200 has a fan-in configuration for gate connection pad 272 and drain connection pad 274, while RF transistor amplifier 200B has a fan-out configuration for gate connection pad 272 and drain connection pad 274. Due to the fan-out configuration, the coupling element 270B of RF transistor amplifier 200B can extend further in the X direction than RF transistor amplifier die 210. By making the coupling element 270B wider than RF transistor amplifier die 210, the gate connection pad 272 and drain connection pad 274 can be fanned out and include the ground post 277 outside each gate post 273 and drain post 275. In one exemplary embodiment, gate connection pad 272 and drain connection pad 274 may each include a plurality of discrete pads formed in an opening within a large source connection pad (and will be similar to pads 272, 274, 276 shown in FIG5I, as will be discussed below).

[0163] It should also be understood that the RF transistor amplifier die can have various different configurations. For example, although the RF transistor amplifier die has a top-side gate terminal 222, a drain terminal 224, and a source terminal 226, in some embodiments, it may also have one or more of a rear-side gate terminal 222', a drain terminal 224', and a source terminal 226'. This configuration is schematically shown in FIG3M, which is a schematic cross-sectional view of an RF transistor amplifier 200C corresponding to the cross-section of FIG3B. As shown in FIG3M, the gate path 211, the drain path 213, and / or the source path 215 may be connected to their respective gate terminals 222', drain terminals 224', and source terminals 226' by forming through the semiconductor layer structure 230. As explained, for example, in U.S. Provisional Patent Application No. 63 / 004,985 (“985 Application”), filed April 3, 2020, including gate and drain terminals on the rear side of an RF transistor amplifier die can have various advantages, such as allowing for more flexible impedance matching circuit implementations. The entire contents of '985 Application are incorporated herein by reference. It should be understood that rear gate terminal 222', drain terminal 224', and source terminal 226' and / or corresponding gate path 211, drain path 213, and source path 215 may be included in any of the RF transistor amplifier die disclosed herein.

[0164] Figures 4A and 4B are schematic cross-sectional views of a Group III nitride-based RF transistor amplifier 200D, which is a modified version of the Group III nitride-based RF transistor amplifier 200 of Figures 3A to 3H. As shown in Figures 4A and 4B, the difference between the RF transistor amplifier 200D and the RF transistor amplifier 200 of Figures 3A to 3H is that the source terminal 226 and the source posts 277 and 281 are replaced by a thick source plug 226D and a much shorter source post 277 in the RF transistor amplifier 200D. The source connection pad 276 can be the same as the source connection pad 276 of the RF transistor amplifier 200 of Figures 3A to 3I. The thick metal source plug 226D eliminates the need for the source post 281 and provides an efficient heat dissipation path for the active region heat removal of the transistor amplifier die 210D. The source terminal 279 is still included in the RF transistor amplifier 200D and is connected to the source plug 226D through the source connection pad 276. The RF transistor amplifier 200D can exhibit improved heat dissipation performance. As shown in Figure 4B, each gate terminal 273 and drain terminal 275 is surrounded by a source terminal 277, a source terminal 279 and a source plug 226D to form a shielded transmission line segment 285D.

[0165] Figures 5A to 5F illustrate a group III nitride-based RF transistor amplifier 200E according to a further embodiment of the present invention. Specifically, Figure 5A is a schematic plan view of the RF transistor amplifier 200E, and Figure 5B is a schematic cross-sectional view of the RF transistor amplifier 200E taken along line 5B-5B of Figure 5A. Figure 5C is a schematic plan view taken along one of the source fingers of the RF transistor amplifier 200E (corresponding to line 3D-3D of Figure 3C). Figure 5D is a schematic cross-sectional view of the RF transistor amplifier 200E taken along the longitudinal axis of the gate manifold (corresponding to line 3F-3F of Figure 3C). Figure 5E is a cross-sectional view taken along line 5E-5E of Figure 5B. Finally, Figure 5F is a schematic cross-sectional view of the RF transistor amplifier 200E, wherein the RF transistor amplifier further includes an interconnect structure 300E. The RF transistor amplifier 200E in Figures 5A to 5F is similar to the RF transistor amplifier 200 in Figures 3A to 3I. Therefore, the following discussion will focus on the differences between these two RF transistor amplifiers.

[0166] One of the complexities of the RF transistor amplifier 200 in Figures 3A to 3I lies in the fact that the source terminal 279 is provided "outside" the gate terminal 273 and "outside" the drain terminal 275 (in other words, referring to Figures 3C and 3H, when viewed in plan view, each gate terminal 273 is between one of the source terminals 279 and the active region 218 of the RF transistor amplifier die 210, and each drain terminal 275 is between one of the source terminals 279 and the active region 218). Typically, the gate manifold 242 and drain manifold 244 are positioned very close to the edge of the RF transistor amplifier die 210 to maximize the area of ​​the active region 218. Therefore, there may not be enough space to place the source terminal 279 outside the gate terminal 273 or drain terminal 275. The RF transistor amplifier die 210 in Figures 3A to 3I uses a fan-in configuration of one of the gate connection pads 272 and drain connection pads 274 to solve this problem. Specifically, in the RF transistor amplifier 200, the gate terminal 273 is laterally offset from the gate manifold 242 and the drain terminal 275 is laterally offset from the drain manifold 244 to make room for the source terminal 279 located outside the gate terminal 273 and drain terminal 275. However, this repositioning complicates the design of the coupling element 270.

[0167] The RF transistor amplifier chip 210E of Figures 5A to 5E avoids the complexity of positioning the source terminal 279 outside the gate terminal 273 and drain terminal 275 by omitting only the source terminal 279. This simplification is included in (or mounted in) the design of the coupling element 270E in the RF transistor amplifier chip 210E. Because the source terminal 279 is omitted, the RF transmission line structure in the coupling element 270E is not completely shielded as in the corresponding RF transmission line structure in the RF transistor amplifier chip 210 of Figures 3A to 3I, but it is still shielded on three sides, which will provide significantly improved performance than the more conventional transmission line connection to the RF transistor amplifier chip.

[0168] In the RF transistor amplifier chip 210E and the RF transistor amplifier chip 210 of Figures 3A to 3I, the semiconductor layer structure 230 and the metal plating (e.g., gate manifold 242, drain manifold 244, gate finger 252, drain finger 254, and source finger 246) directly contacting the semiconductor layer structure 230 can be the same. Therefore, Figure 3C schematically illustrates the metal plating of the direct contact semiconductor layer structure of both the RF transistor amplifier chips 210 and 210E.

[0169] Referring to Figures 5A to 5D, the RF transistor amplifier die 210E provides an extended gate post 273E for directly connecting the gate manifold 242 to the gate connection pad 272E, and an extended drain post 275E for directly connecting the drain manifold 244 to the drain connection pad 274E. The gate terminal 222 and drain terminal 224 provided in the RF transistor amplifier 200E can be omitted from the RF transistor amplifier 200E to result in a simpler design. Furthermore, in the RF transistor amplifier 200E, the gate post 273E is positioned directly above the gate manifold 242 and the drain post 275E is positioned directly above the drain manifold 244. Additionally, the positions of gate interconnect 272E and drain interconnect 274E can be changed, and the size and shape of source interconnect 276E are modified so that source interconnect 276E comprises a strip that is simpler than the generally E-shaped source interconnect 276 included in RF transistor amplifier 200 (compare Figures 3A and 5A). Source post 279 is omitted in RF transistor amplifier 200E, while an additional source post 277 is provided. It should be noted that the gate interconnect 272E and drain interconnect 274E of RF transistor amplifier 200E do not have a fan-in configuration.

[0170] Figure 5E is a cross-section taken through gate post 273E, drain post 275E, and source post 277, illustrating how these posts are implemented as a shielded transmission line structure. As can be seen, the three source posts 277 partially surround each gate post 273E. Specifically, in the view of Figure 5E, one source post 277 is provided above, below, and to the right of each gate post 273E. Similarly, the three source posts 277 partially surround each drain post 275E; one source post 277 is provided above, below, and to the left of each drain post 275E. No additional shielding is provided to the left of each gate post 273E or to the right of each drain post 275E. It should be noted that the source terminal 281 of the RF transistor amplifier 200 can be replaced by the source terminal 277 in the RF transistor amplifier 200E, because the gate terminal 222 and drain terminal 224 are omitted in the RF transistor amplifier 200E.

[0171] Figure 5F is a schematic cross-sectional view of an RF transistor amplifier 200E when the amplifier further includes an interconnect structure 300E. A coupling element 270E is used to connect the RF transistor amplifier die 210B to the interconnect structure 300E. As shown in Figure 5F, bonding elements (e.g., solder balls and / or bumps) 360 can be used to couple the interconnect structure 300E to the coupling element 270E respectively. The interconnect structure 300E may be substantially the same as the interconnect structure 300 described above, therefore further description thereof will be omitted.

[0172] Figure 5G is a schematic cross-sectional view of an RF transistor amplifier 200F, which is identical to the RF transistor amplifier 200E in Figure 5F, except that the RF transistor amplifier 200F includes an interconnect structure 300F, wherein circuit elements 350 are mounted on the side of the interconnect structure 300F, which is identical to the RF transistor amplifier die 210. It should be understood that in other embodiments, circuit elements 350 may be provided on both main surfaces of interconnect structures 300E and 300F. It should also be understood that RF input 301, RF output 308, and / or ground input 309 may be provided on any main surface of interconnect structures 300E and 300F.

[0173] Figures 5H and 5I are respectively a schematic cross-sectional view and a schematic plan view of an RF transistor amplifier 200G according to a further embodiment of the present invention. The RF transistor amplifier 200G is very similar to the RF transistor amplifier 200E of Figures 5A to 5E, except that the RF transistor amplifier 200G includes an additional source post 277 outside each gate post 273E and drain post 275E, such that a total of four source posts 277 surround each gate post 272E and drain post 274E. Similar to the embodiment of Figure 3L discussed above, this can be achieved by forming a coupling element 270G that is wider than the RF transistor amplifier die 210.

[0174] Figure 3A illustrates two exemplary embodiments of the gate connection pads 272, 272E, drain connection pads 274, 274E, and source connection pads 276, 276E included in the RF transistor amplifiers 200 and 200E of Figures 3A to 3I and Figures 5A to 5F. Figures 6A and 6B are schematic plan views illustrating two alternative embodiments of the gate, drain, and source connection pads that can be used, for example, in the RF transistor amplifiers 200 of Figures 3A to 3I. The cross-sections in Figures 6A and 6B are horizontal cross-sections obtained through the gate connection pad 272, drain connection pad 274, and source connection pad 276 (i.e., obtained along the equivalent line 6-6 of Figure 3A). The dashed circles in Figures 6A and 6B indicate the positions of the gate post 273, drain post 275, and source posts 277, 279, and 281. The dielectric underfill material provided between the gate terminal 273, drain terminal 275 and source terminals 277, 279, 281 is shown in Figures 6A and 6B and thus obstructs the view of the underlying structures such as the gate terminal 222, drain terminal 224 and source terminal 226.

[0175] Referring first to Figure 6A, it can be seen that a plurality of source connection pads 276H are provided, rather than a monolithic source connection pad 276 included in the RF transistor amplifier 200. In Figure 6A, each source connection pad 276H is implemented as a strip of conductive material. It should be noted that the source connection pads 276H are not electrically connected to each other within the RF transistor amplifier die 210 or coupling element 270. Therefore, each source connection pad 276H may have its own individual ground connection. The source connection pads 276H may be electrically connected to each other through, for example, a common source connection attached to one of the interconnect structures 300 of the coupling element 270.

[0176] As shown in FIG6B, in another alternative embodiment, gate connection pad 272, drain connection pad 274, and source connection pad 276 can be completely omitted. In this embodiment, gate post 273, drain post 275, and source posts 277, 279 can be directly connected to corresponding pads on an interconnect structure using bonding materials such as conductive bumps configured as a ball grid array or conductive die-attachment material. Furthermore, since gate connection pad 272 and drain connection pad 274 are omitted, the source post 281 included in the embodiments of FIG3A to FIG3I can be replaced by a source post 277 extending all the way to the upper surface of the coupling element.

[0177] Although Figures 6A and 6B are described above as two alternative embodiments illustrating the gate connection pad 272, drain connection pad 274 and source connection pad 276 of the embodiments of Figures 3A to 3I, it should be understood that the same modifications may be made to any other embodiments disclosed herein, such as (for example) the embodiments of Figures 3J to 3M, Figures 5A to 5I, Figures 7A to 7C and Figures 10A to 10G.

[0178] Figures 7A to 7C illustrate exemplary embodiments of matching circuits, such as impedance matching circuits or harmonic termination circuits, that can be implemented in an RF transistor amplifier according to an embodiment of the present invention. Specifically, Figure 7A is a circuit diagram of an RF transistor amplifier 200I including both impedance matching and harmonic termination circuits. Figure 7B is a schematic plan view of an interconnect structure 300I according to an embodiment of the present invention, which is a portion of the RF transistor amplifier 200I. Figure 7C is a schematic cross-sectional view (taken along line 7C-7C of Figure 7B) illustrating the RF transistor amplifier 200I and the coupling element 270I included in the RF transistor amplifier 200I.

[0179] Referring to Figure 7A, it can be seen that the RF transistor amplifier 200I includes an input impedance matching circuit 202, an input harmonic termination circuit 204, an RF transistor amplifier chip 210, and an output impedance matching circuit 206. The input impedance matching circuit 202 is coupled in series between one of the RF inputs 201 of the RF transistor amplifier 200I and the gate terminal 222 of the RF transistor amplifier chip 210, and includes an inductor L1. The input harmonic termination circuit 204 is coupled between the gate terminal 222 of the RF transistor amplifier chip 210 and ground, and includes a series LC circuit, which includes an inductor L2 and a capacitor C1. The output impedance matching circuit 206 is coupled in series between the drain terminal 224 of the RF transistor amplifier chip 210 and one of the RF outputs 208 of the RF transistor amplifier 200I, and includes a series LC circuit, which includes an inductor L3 and a capacitor C2.

[0180] Referring next to Figures 7B and 7C, it can be seen that the inductors L1 to L3 and capacitors C1 and C2 can be implemented using surface-mount circuit elements mounted on the surface of the interconnect structure 300I. The RF input 201 and RF output 208 can be implemented as pads on the bottom surface of the interconnect structure 300I.

[0181] The first conductive gate path 310-1 and the second conductive gate path 310-2 extend through the interconnect structure 300I. A horizontal gate segment 314 is also provided to allow the RF input 201 to have a fan-out configuration, making it easier for the RF input 201 to be electrically connected to an external circuit. Similarly, the first conductive drain path 320-1 and the second conductive drain path 320-2 also extend through the interconnect structure 300I. A horizontal drain segment 324 is provided to allow the RF output 208 to have a fan-out configuration, making it easier for the RF output 208 to be electrically connected to an external circuit. A conductive pad 312-1 is formed on top of the first conductive gate path 310-1 and a conductive pad 312-2 is formed on top of the second conductive gate path 310-2. Surface mount circuit element L1 is mounted above conductive pads 312-1 and 312-2 and electrically connected to conductive pads 312-1 and 312-2 to implement an inductor L1 connected in series between RF input 201 and the gate terminal 222 of RF transistor amplifier chip 210. A conductive pad 322 is formed on top of both the first conductive drain path 320-1 and the second conductive drain path 320-2.

[0182] As shown in Figure 7B, conductive traces 330, 332, 334, and 336 are provided on the surface of the interconnect structure 300I. Conductive trace 330 electrically connects conductive pad 312-1 to one of the input pads of surface mount circuit element L2, conductive trace 332 electrically connects one of the output pads of surface mount circuit element L2 to one of the input pads of surface mount circuit element C1, and one of the output pads of surface mount circuit element C1 is mounted on and electrically connected to a grounded pad 340. Conductive traces 330, 332, and surface mount circuit elements L2 and C1 implement an input harmonic termination circuit 204. Conductive trace 334 electrically connects conductive pad 322 to one of the input pads of surface mount circuit element L3, conductive trace 336 electrically connects one of the output pads of surface mount circuit element L3 to one of the input pads of surface mount circuit element C2, and one of the output pads of surface mount circuit element C2 is mounted on and electrically connected to a grounded pad 340. Conductive traces 334 and 336 and surface mount circuit elements L3 and C2 implement the output impedance matching circuit 206.

[0183] As shown in FIG7C, the shielded transmission line structure can be implemented within the interconnect structure 300I. For example, conductive grounding paths 318 are formed on the opposite sides of each conductive gate path 310-1, 310-2 and each conductive drain path 320-1, 320-2. Although two conductive grounding paths 318 are shown on the opposite sides of each conductive gate path 310 and drain path 320 in the cross-section of FIG7C, it should be understood that additional conductive grounding paths 318 may (as appropriate) further surround each conductive gate path 310 and drain path 320 outside the cross-section of FIG7C. In addition, conductive grounding traces 342 are formed above and below the horizontal gate section 314 and above and below the horizontal drain section 324. The conductive grounding trace 342 converts the horizontal gate segment 314 and the horizontal drain segment 324 into shielded transmission segments in the form of their respective wired transmission segments 344.

[0184] Positioning the source terminal 226 on the top side of the RF transistor amplifier die 210 (i.e., the same side as the gate terminal 222 and drain terminal 224) facilitates the use of the shielded transmission line segment 344 discussed above, as it allows for easy grounding voltage connection at close proximity to the transmission line structure connected to the gate and drain terminals of the RF transistor amplifier die 210. Additionally, the signal carrying paths 310 and / or 320 may also have a grounding path 318 on their opposite sides to form a vertically shielded RF transmission line structure 344 within the interconnect structure 300I.

[0185] Although the embodiments of Figures 7B to 7C implement circuit elements L1 to L3 and C1 to C2 on the main surface of the interconnect structure 300I opposite to the RF transistor amplifier die 210, it should be understood that the embodiments of the present invention are not limited thereto. For example, in other embodiments, some or all of the circuit elements L1 to L3 and C1 to C2 may be mounted on the main surface of the interconnect structure 300I on the same main surface on which the RF transistor amplifier die 210 is mounted, or may be implemented in the interconnect structure 300I or within a conductive pattern on the interconnect structure 300I.

[0186] Although the example of FIG7C includes a stripline transmission segment implemented within the interconnect structure 300I, it should be understood that embodiments of the present invention are not limited thereto. For example, coplanar waveguide transmission segments and / or grounded coplanar waveguide transmission segments can be used to form part or all of the shielded transmission line structures in the interconnect structure according to embodiments of the present invention. FIG8A to FIG8D are schematic diagrams of two exemplary coplanar waveguide transmission segments that can be used to form some shielded transmission line structures, while FIG9A to FIG9C are schematic diagrams of one exemplary grounded coplanar waveguide transmission segment that can be used to form some shielded transmission line structures.

[0187] Specifically, Figure 8A is a plan view of one of the coplanar waveguide transmission segments 400. Figure 8B is a side view of one of the coplanar waveguide transmission segments 400 in Figure 8A (obtained along line 8B-8B in Figure 8A), and Figure 8C is a front view of one of the coplanar waveguide transmission segments 400 in Figure 8A (obtained along line 8C-8C in Figure 8A).

[0188] As shown in Figures 8A to 8C, the coplanar waveguide transmission segment 400 includes a conductive trace 402 and first and second ground conductive traces 404. The conductive trace 402 and the first and second ground conductive traces 404 extend parallel to each other, wherein the first and second ground conductive traces 404 are located on opposite sides of the conductive trace 402. The conductive trace 402 and the first and second ground conductive traces 404 may include, for example, metal traces of a printed circuit board formed on a dielectric layer of a printed circuit board. A ground metal layer 406 is disposed below the conductive trace 402 and the first and second ground conductive traces 404. This ground metal layer 406 extends parallel to the conductive trace 402 and the first and second ground conductive traces 404 (and alternatively, is disposed above the conductive trace 402). As shown in Figure 8B, a conductive path 412 may be connected to the conductive trace 402. Conductive path 412 can be used to transmit RF signals between conductive trace 402 and another component (e.g., another RF transmission line segment). Similarly, first and second conductive ground paths 414 can be connected to their respective first and second conductive ground traces 404 to maintain conductive ground traces 404 at ground potential. Conductive ground traces 414 help to contain RF energy in the dielectric between ground metal layer 406 and conductive ground traces 414.

[0189] It should also be understood that other coplanar waveguide transmission segments can be used. For example, FIG8D is a side view of another coplanar waveguide structure 400A (corresponding to the view in FIG8B), wherein a ground metal layer 406 is disposed above conductive traces 402 and ground conductive traces 404. According to embodiments of the present invention, the coplanar waveguide transmission segment 400A can also be used in interconnect structures.

[0190] Figures 9A to 9C illustrate a grounded coplanar waveguide transmission segment 400B, similar to a coplanar waveguide transmission segment 400. Figures 9A to 9C correspond to Figures 8A to 8C respectively and show how the coplanar waveguide transmission segment 400 of Figures 8A to 8C can be converted into a grounded coplanar waveguide transmission segment 400B. As can be seen by comparing Figures 8A to 8C with Figures 9A to 9C, the only difference between transmission segment 400 and 400B is that transmission segment 400B includes a plurality of ground paths 408 extending between the ground metal layer 406 and each conductive ground trace 404. The ground paths 408 can extend in a row, and adjacent ground paths 408 can be spaced a sufficiently small distance to prevent more than a minimum amount of RF energy from being transferred between adjacent ground paths 408. The grounded coplanar waveguide transmission segment 400B can exhibit a high degree of RF shielding. As discussed above, other grounded coplanar waveguide transmission segments can be used (e.g., grounded coplanar waveguide transmission segments in which ground metal layer 406 is disposed above conductive trace 402 and grounded conductive trace 404).

[0191] Figures 10A to 10G are schematic diagrams illustrating a method of forming a packaged RF transistor amplifier according to certain embodiments of the present invention. As shown in Figure 10A, an RF transistor amplifier die, such as RF transistor amplifier die 210, can be manufactured. Typically, a plurality of RF transistor amplifier dies 210 can be formed on a single semiconductor wafer, which is then diced into individual RF transistor amplifier dies 210.

[0192] Referring next to FIG. 10B, a coupling element, such as coupling element 270, is formed on the upper surface of the RF transistor amplifier die 210. In some cases, the coupling element may be formed using semiconductor processing techniques prior to wafer dicing, in which case the coupling element 270 may be considered part of the RF transistor amplifier die 210. In other cases, the coupling element 270 may be formed separately (e.g., as an RDL stacked structure) and placed on a semiconductor wafer, or formed separately and placed on a separately diced RF transistor amplifier die 210. Next, as shown in FIG. 10C, an interconnect structure (e.g., interconnect structure 300) may be bonded to the coupling element 270 to attach the RF transistor amplifier die 210 to the interconnect structure 300.

[0193] As shown in Figure 10D, a capillary underfill process can be used to inject dielectric material between the conductive structures of the coupling element 270. The dielectric material can help prevent short circuits, enhance the structural integrity of the coupling element, and provide proper impedance matching. As shown in Figure 10E, in other cases, a molding underfill process can be used to inject underfill material between the conductive structures of the coupling element 270 and also encapsulate the RF transistor amplifier die 210 in a protective underfill material. As shown in Figures 10F and 10G, the device of Figure 10D can be encapsulated by an overmolded plastic package. In the embodiment of Figure 10F, only the RF transistor amplifier die 210 and the coupling element 270 are encapsulated in the overmolded plastic material, while in the embodiment of Figure 10G, all three components—the RF transistor amplifier die 210, the coupling element 270, and the interconnect structure 300—are encapsulated. An opening can be formed within the encapsulation material to provide access to various terminals of the device (e.g., an RF input terminal, an RF output terminal, a ground terminal, a bias voltage terminal, etc.).

[0194] Figures 11A and 11B are schematic cross-sectional views of additional package options 500A and 500B for an RF transistor amplifier (e.g., the RF transistor amplifier 200 of Figures 3A to 3I) according to an embodiment of the present invention. Since the RF transistor amplifier 200 has been discussed in detail, the discussion of Figures 11A to 11B will focus on the external package.

[0195] Referring first to Figure 11A, package option 500A encapsulates the RF transistor amplifier 200 in a ceramic package. Package 500A is a so-called open cavity package, which includes a carrier substrate 510, sidewalls 520, and a cover 530 that together define an open cavity 540. The RF transistor amplifier 200 (including interconnect structure 300) is disposed on the carrier substrate 510 within the open cavity 540.

[0196] The carrier substrate 510 may contain materials configured to assist in the thermal management of the package 500A. For example, the carrier substrate 510 may contain copper and / or molybdenum. In some embodiments, the carrier substrate 510 may consist of multiple layers and / or contain vias / interconnects. In an exemplary embodiment, the carrier substrate 510 may be a multilayer copper / molybdenum / copper metal flange comprising a core molybdenum layer and copper overlays on its two main surfaces. The examples of materials provided for the carrier substrate 510 are not intended to limit the invention.

[0197] In some embodiments, the sidewall 520 and / or the cover 530 may be formed of or contain an insulating material. For example, the sidewall 530 and / or the cover 530 may be formed of or contain a ceramic material. In some embodiments, the sidewall 530 and / or the cover 530 may be formed of, for example, Al₂O₃. The cover 530 may be glued to the sidewall 520 using epoxy resin adhesive. The sidewall 520 may be attached to the carrier substrate 510 via, for example, soldering. Leads 515-1, 515-2 may be configured to extend through the sidewall 520, but embodiments of the present invention are not limited thereto.

[0198] In some embodiments, the RF transistor amplifier 200 may be mounted on a carrier substrate 510 and leads 515-1, 515-2 may be attached to the bottom side of the interconnect structure 300. Leads 515-1, 515-2 may be coupled to the interconnect structure 300 using, for example, a conductive die-attach material. As shown in the figures, in some embodiments, wire bonding may be avoided to connect the RF transistor amplifier 200 to leads 515-1, 515-2.

[0199] Referring to FIG. 11B, package option 500B encapsulates the RF transistor amplifier 200 in an overmolded plastic package. Package 500B includes a carrier substrate 510, leads 515-1, 515-2, and an overmolded plastic material 550. The RF transistor amplifier 200 (including interconnect structure 300) is disposed on the carrier substrate 510. Leads 515-1, 515-2 are connected to the interconnect structure (e.g., in the same manner as described above with reference to FIG. 11A). The overmolded material 550 (which may be a plastic or a plastic polymer compound) is injection molded around the RF transistor amplifier 200 (including interconnect structure 300), thereby providing protection from the external environment.

[0200] A method for manufacturing an overmolded plastic package is described in U.S. Patent No. 9,515,011, entitled "Over-mold plastic packaged wide band-gap power transistors and MMICS," published by Wood et al. on December 6, 2016. The disclosure of that patent is incorporated herein by reference as if fully described herein. In package 500B, leads 515-1, 515-2 may extend through the overmolded plastic material 550 to directly connect to interconnect structures. Thus, in some embodiments, wire bonding can be avoided to connect the RF transistor amplifier 200 to leads 515-1, 515-2.

[0201] The carrier substrate 510 of the package 500B may contain materials configured to assist thermal management. For example, the carrier substrate 510 may contain copper and / or molybdenum. In some embodiments, the carrier substrate 510 may consist of multiple layers and / or contain vias / interconnects. In some embodiments, the carrier substrate 510 may include a metal heat sink, which is at least a portion of a lead frame or metal block surrounded by a plastic overmolded plastic 550.

[0202] Although Figures 11A and 11B illustrate the use of an RF transistor amplifier 200 having a coupling element 270, the invention is not limited thereto. In other embodiments, the RF transistor amplifier die 210 may be directly coupled to an interconnect structure (as in Figures 5A to 5F above) and the resulting RF transistor amplifier may be packaged using a package 500A or 500B.

[0203] It should be understood that any of the RF transistor amplifiers discussed herein according to embodiments of the present invention can be mounted in a package such as those shown in Figures 10D to 10G and Figures 11A and 11B. Depending on the embodiment, the packaged RF transistor amplifier may include a single-crystal microwave integrated circuit (MMIC) as the RF transistor amplifier die, wherein the RF transistor amplifier die incorporates multiple discrete circuits in a single integrated die. Additionally and / or alternatively, the package may include multiple RF transistor amplifier dies connected in series to form one path of a multi-stage RF transistor amplifier and / or disposed in multiple paths (e.g., in parallel) to form multiple RF transistor amplifier dies having multiple transistor amplifier dies and RF transistor amplifiers in one of multiple paths, such as in a doherty amplifier configuration. In some embodiments, the packaged RF transistor amplifier may include an RF transistor amplifier die according to an embodiment of the present invention having conductive gate and / or conductive drain paths providing electrical connections to a rear interconnect structure, and a conventional RF transistor amplifier die having gate and drain terminals connected to other structures via wire bonding.

[0204] It should also be understood that multiple RF transistor amplifier chips can be coupled to a single interconnect structure. This configuration is schematically illustrated in Figure 12. As shown in Figure 12, the first RF transistor amplifier chip 210-1 and the second RF transistor amplifier chip 210-2 are coupled to an interconnect structure 300J via their respective coupling elements 270-1 and 270-2. Conductive patterns (e.g., conductive paths and traces) within the interconnect structure 300J can be used to electrically connect each RF transistor amplifier chip 210-1 and 210-2 to, for example, matching circuit systems mounted on and / or implemented within the interconnect structure 300J and to each other (as desired).

[0205] The interconnect structure 300J can be used, for example, to provide interconnections to RF transistor amplifier chips 210-1, 210-2 to implement a multi-stage and / or multi-path amplifier circuit, such as a multi-stage amplifier. The conductive patterns within the interconnect structure 300J can provide electrical connections for the multi-stage and / or multi-path amplifier circuit. Therefore, the interconnect structure 300J can be configured to provide a modular interconnection that can be easily coupled to a plurality of RF transistor amplifiers without the use of wiring.

[0206] The shielded transmission line structure disclosed herein can be used in various RF transistor amplifiers. For example, U.S. Provisional Patent Application No. 63 / 004,765 (“765 Application”), filed April 3, 2020, discloses various RF transistor amplifiers that may include an RF transistor amplifier die, a coupling element, and a selected interconnect structure. The shielded transmission line structure disclosed herein can be incorporated into any RF transistor amplifier disclosed in 765 Application. The entire contents of 765 Application are incorporated herein by reference.

[0207] Compared with conventional RF transistor amplifiers, the RF transistor amplifier according to embodiments of the present invention has many advantages. The provision of a shielded transmission line structure improves the performance of the RF transistor amplifier. Furthermore, reducing wiring (or completely eliminating wiring) reduces costs and simplifies manufacturing, and improves the RF performance of the device because the inductance in the impedance matching network can be precisely controlled, and the problem of excessively large inductance in the matching network can be avoided. Moreover, increasing wafer-level packaging becomes feasible due to the RF transistor amplifier according to embodiments of the present invention, which further simplifies manufacturing and / or reduces production costs.

[0208] Embodiments of the present invention can be used, for example, in RF power products and radar applications for 5G and base station and / or mobile phone applications.

[0209] In some embodiments of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a semiconductor layer structure; a coupling element located on an upper surface of the semiconductor layer structure; and an interconnect structure located on an upper surface of the coupling element, such that the RF transistor amplifier die and the interconnect structure are stacked. The coupling element includes a first shielded transmission line structure. The first shielded transmission line structure may, for example, be electrically connected to a first conductive post of a first input / output terminal of the RF transistor amplifier die and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post. The first conductive ground post and the second conductive ground post may be electrically connected to a ground terminal of the RF transistor amplifier die.

[0210] In some embodiments, the semiconductor layer structure may be a group III nitride-based semiconductor layer structure. The interconnect structure may be, for example, a distributed multilayer structure or a printed circuit board. A plurality of circuit elements (such as, for example, one or more surface mount capacitors or surface mount inductors) may be mounted on the interconnect structure. In some embodiments, the coupling element may have a fan-in configuration.

[0211] In some embodiments, the first shielded transmission line structure may also include a third conductive grounding post and a fourth conductive grounding post on the opposite side of the first conductive post, the third conductive grounding post and the fourth conductive grounding post being electrically connected to the ground terminal of the RF transistor amplifier. The first conductive grounding post to the fourth conductive grounding post may surround the first conductive post. In some embodiments, the second conductive grounding post may perpendicularly overlap with a portion of the RF transistor amplifier die outside an active region of the RF transistor amplifier die. In some embodiments, both the first conductive post and the first conductive grounding post may perpendicularly overlap with the first input / output terminal.

[0212] In some embodiments, the first input / output terminal may be a gate terminal and the ground terminal may be a source terminal, and the coupling element may further include a second shielded transmission line structure, the second shielded transmission line structure including a second conductive post electrically connected to a drain terminal of the RF transistor amplifier chip and a fifth conductive ground post and a sixth conductive ground post on the opposite side of the second conductive post, the fifth conductive ground post and the sixth conductive ground post being electrically connected to the source terminal.

[0213] In some embodiments, the first input / output terminal may be a gate terminal and the ground terminal may be a source terminal, and the RF transistor amplifier die may further include a drain terminal, and the source terminal may be located on the opposite side of the gate terminal and the opposite side of the drain terminal.

[0214] In some embodiments, the first conductive post and the third conductive post may be electrically connected to a gate manifold of the RF transistor amplifier chip, and the first conductive ground post may be located between the first conductive post and the third conductive post.

[0215] In some embodiments, the second conductive grounding post may be a metal block having a cross-sectional area in a first plane parallel to one of the main surfaces of the RF transistor amplifier die, the cross-sectional area being at least five times the cross-sectional area of ​​the first conductive post in the first plane.

[0216] In some embodiments, the first conductive grounding post has a first end and a second end, and the second end is not connected to a conductive element.

[0217] In some embodiments, the coupling element may further include an injectable underfill material surrounding the first conductive post and one of the first conductive ground post and the second conductive ground post.

[0218] In some embodiments, the interconnect structure may include a second shielded transmission line structure. The second shielded transmission line structure may include, for example, a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment.

[0219] In some embodiments, the side of the RF transistor amplifier die that is not connected to the interconnect structure may be encapsulated.

[0220] In some embodiments, the first of the conductive pillars may be surrounded on at least three sides by a plurality of the conductive pillars coupled to a ground voltage source.

[0221] In other embodiments of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate and drain fingers extending on one upper surface of the semiconductor layer structure; and a first shielded transmission line structure extending perpendicularly to the upper surface of the semiconductor layer structure.

[0222] In some embodiments, the first shielded transmission line structure may be electrically connected to one of the gate fingers and the drain fingers.

[0223] In some embodiments, the first shielded transmission line structure may be electrically connected to a first conductive post of one of the gate fingers or one of the drain fingers, and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post, and a third conductive ground post and a fourth conductive ground post on the opposite side of the first conductive post, wherein the first conductive ground post to the fourth conductive ground post are electrically connected to the source finger of the RF transistor amplifier die.

[0224] In some embodiments, the first conductive post may be perpendicularly overlapped with an active region of the RF transistor amplifier die, and / or the first conductive ground post may be perpendicularly overlapped with a manifold of the RF transistor amplifier die electrically connected to the gate fingers or the drain fingers. In some embodiments, both the first conductive post and the first conductive ground post may be perpendicularly overlapped with a gate terminal of the RF transistor amplifier die.

[0225] In some embodiments, the first conductive post and the third conductive post may be electrically connected to a gate manifold of the RF transistor amplifier chip, and the first conductive ground post may be located between the first conductive post and the third conductive post.

[0226] In some embodiments, the RF transistor amplifier die further includes a gate terminal electrically connected to one of the gate fingers, a drain terminal electrically connected to one of the drain fingers, and a source finger electrically connected to a source terminal, wherein the gate terminal, the drain terminal, and the source terminal are all located above the gate fingers, the drain fingers, and the source fingers. In some embodiments, the first shielded transmission line structure includes a first ground terminal and a second ground terminal electrically connected to a gate post of the gate terminal and the opposite side of the gate post, the first ground terminal and the second ground terminal being electrically connected to the source terminal.

[0227] In other embodiments of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate fingers, drain fingers and source fingers extending on an upper surface of one of the semiconductor layer structures; and a plurality of conductive pillars extending perpendicularly to the upper surface of the semiconductor layer structure, the conductive pillars including a first conductive pillar electrically connected to one of the gate fingers or the drain fingers and a first conductive ground pillar and a second conductive ground pillar on the opposite side of the first conductive pillar, the first conductive ground pillar and the second conductive ground pillar being electrically connected to the source fingers.

[0228] These RF transistor amplifiers may further include an interconnect structure. The conductive posts may extend between the interconnect structure and the RF transistor amplifier die to electrically connect the interconnect structure to the RF transistor amplifier die. In some embodiments, the first conductive ground post, the second conductive ground post, and at least one additional conductive ground post may surround the first conductive post. In some embodiments, the first conductive post may perpendicularly overlap with an active region of the RF transistor amplifier die, and / or the second conductive ground post may perpendicularly overlap with a portion of the RF transistor amplifier die outside the active region. In some embodiments, the first conductive ground post may perpendicularly overlap with a manifold of the RF transistor amplifier die.

[0229] In some embodiments, the drain fingers may extend from a drain manifold across one of the active regions of the RF transistor amplifier die, and the first conductive post and a third conductive post may be electrically connected to the drain manifold. In these embodiments, the first conductive ground post may be located between the first conductive post and the third conductive post.

[0230] In some embodiments, the semiconductor layer structure includes a group III nitride-based semiconductor layer structure.

[0231] According to an additional embodiment of the present invention, an RF transistor amplifier is provided, comprising: an RF transistor amplifier die including a gate terminal, a drain terminal and a source terminal on a first surface of the RF transistor amplifier die; and an interconnect structure stacked with the RF transistor amplifier die, the interconnect structure including a shielded transmission line structure, wherein a ground conductor of the shielded transmission line structure is electrically connected to the source terminal and a signal conductor of the shielded transmission line structure is electrically connected to one of the gate terminal and the drain terminal.

[0232] The shielded transmission line structure may be, for example, a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment.

[0233] The interconnect structure may be, for example, a multilayer structure or a printed circuit board. A plurality of circuit elements may be mounted on the interconnect structure. These circuit elements may include at least one of a surface mount capacitor and a surface mount inductor.

[0234] A coupling element electrically connects the RF transistor amplifier die to the interconnect structure. In some embodiments, the coupling element may have a fan-in configuration. The coupling element may include a plurality of conductive pillars. These conductive pillars may be configured to form a second shielded transmission line structure.

[0235] Embodiments of the invention have been described above with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the invention thorough and complete and to fully convey the scope of the invention to those skilled in the art. Identical element symbols refer to all identical elements.

[0236] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, such elements should not be limited by such terms. These terms are used only to distinguish elements from one another. For example, a first element may be referred to as a second element without departing from the scope of the invention, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0237] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the terms "comprising" and / or "including" specifically mean the presence of the said features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0238] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or extends "to another element," it may be directly on the other element or directly extend to the other element, or an intervening element may be present. In contrast, when an element is referred to as "directly on another element" or "directly extend to another element," no intervening element is present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or an intervening element may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intervening element is present.

[0239] Relative terms such as “below” or “above” or “up” or “down” or “horizontal” or “lateral” or “vertical” may be used herein to describe the relationship between one element, layer or region and another element, layer or region. It should be understood that, in addition to the orientation depicted in the figures, these terms are also intended to cover different orientations of the device.

[0240] Typical embodiments of the present invention have been disclosed in the drawings and description, and although specific terms are used, they are used only in a general and descriptive sense and are not intended to be limiting. The scope of the present invention is set forth in the following claims. [Simplified Explanation of the Diagram]

[0059] Figure 1A is a schematic plan view of one of the known group III nitride-based RF transistor amplifier chips.

[0060] Figure 1B is a schematic cross-sectional view obtained along line 1B-1B of Figure 1A.

[0061] Figure 1C is a schematic cross-sectional view of a metallization layer directly formed on the top surface of a semiconductor layer structure, taken along line 1C-1C of Figure 1B.

[0062] Figure 1D is a schematic cross-sectional view obtained along line 1D-1D of Figure 1C.

[0063] Figure 1E is a schematic cross-sectional view of one of the group III nitride-based RF transistor amplifier chips of Figures 1A to 1D packaged in a ceramic package.

[0064] Figure 1F is a schematic cross-sectional view of one of the group III nitride-based RF transistor amplifier chips of Figures 1A to 1D packaged in an overmolded package.

[0065] FIG2 is a schematic cross-sectional view illustrating the components of various RF transistor amplifiers according to embodiments of the present invention.

[0066] Figure 3A is a schematic plan view of one of the group III nitride-based RF transistor amplifier chips according to certain embodiments of the present invention.

[0067] Figure 3B is a schematic cross-sectional view obtained along line 3B-3B of Figure 3A.

[0068] Figure 3C is a schematic plan view of the top side metal plating of the direct contact semiconductor layer structure along line 3C-3C of Figure 3B.

[0069] Figure 3D is a schematic cross-sectional view obtained along line 3D-3D of Figure 3C.

[0070] Figure 3E is a schematic cross-sectional view obtained along line 3E-3E of Figure 3C.

[0071] Figure 3F is a schematic cross-sectional view obtained along line 3F-3F of Figure 3C.

[0072] Figure 3G is a schematic cross-sectional view obtained along line 3G-3G of Figure 3C.

[0073] Figure 3H is a schematic cross-sectional view obtained along line 3H-3H in Figure 3B.

[0074] Figure 3I is a schematic cross-sectional view of one of the group III nitride-based RF transistor amplifiers of Figures 3A to 3H mounted on an interconnect structure.

[0075] Figure 3J is a schematic cross-sectional view of one of the group III nitride-based RF transistor amplifiers of Figures 3A to 3H mounted on an alternative interconnect structure.

[0076] Figure 3K is a schematic cross-sectional view of one of the RF transistor amplifiers, which is a modified version of one of the RF transistor amplifiers in Figures 3A to 3G.

[0077] Figure 3L is a schematic cross-sectional view of another modified version of the group III nitride-based RF transistor amplifiers of Figures 3A to 3H with a fan-out structure.

[0078] Figure 3M is a schematic cross-sectional view of another modified version of the group III nitride-based RF transistor amplifier shown in Figures 3A to 3H.

[0079] Figures 4A and 4B are schematic cross-sectional views of a group III nitride-based RF transistor amplifier, which is a modified version of one of the group III nitride-based RF transistor amplifiers shown in Figures 3A to 3I.

[0080] Figures 5A to 5F are various views of a group III nitride-based RF transistor amplifier die according to a further embodiment of the present invention.

[0081] Figure 5G is a schematic cross-sectional view of one of the RF transistor amplifiers, which is a modified version of one of the RF transistor amplifiers in Figure 5F.

[0082] Figures 5H and 5I are respectively a schematic cross-sectional view and a schematic plan view of an RF transistor amplifier according to a further embodiment of the present invention.

[0083] Figures 6A and 6B are schematic plan views illustrating alternative embodiments of the coupling element according to an embodiment of the present invention.

[0084] Figure 7A is a circuit diagram of an RF transistor amplifier that includes either an impedance matching circuit or a harmonic termination circuit according to an embodiment of the present invention.

[0085] FIG7B is a schematic plan view of an interconnection structure according to an embodiment of the present invention, which is a part of the RF transistor amplifier of FIG7A.

[0086] Figure 7C is a schematic cross-sectional view obtained along line 7C-7C of Figure 7B.

[0087] Figures 8A to 8C are schematic diagrams illustrating an example coplanar waveguide transmission segment that can be used to form some transmission segments in an interconnect structure according to an embodiment of the present invention.

[0088] FIG8D is an end view of another coplanar waveguide transmission segment that can be used to form some transmission segments in an interconnect structure according to an embodiment of the present invention.

[0089] Figures 9A to 9C are schematic diagrams illustrating an example grounded coplanar waveguide transmission segment that can be used to form some transmission segments in an interconnect structure according to an embodiment of the present invention.

[0090] Figures 10A to 10G are schematic diagrams illustrating a method of forming a packaged RF amplifier according to certain embodiments of the present invention.

[0091] Figure 11A is a schematic cross-sectional view of one of the RF transistor amplifiers in a ceramic package containing the RF transistor amplifier in Figure 3I.

[0092] Figure 11B is a schematic cross-sectional view of one of the RF transistor amplifiers in Figure 3I contained in an overmolded plastic package.

[0093] FIG12 is a schematic side view of an RF transistor amplifier according to an embodiment of the present invention, which includes two RF transistor amplifier chips coupled to an interconnect structure.

Claims

1. A radio frequency ("RF") transistor amplifier, comprising: An RF transistor amplifier die includes a gate terminal, a drain terminal, and a source terminal on a first surface of the RF transistor amplifier die; and an interconnect structure stacked with the RF transistor amplifier die, the interconnect structure including a shielded transmission line structure, wherein a ground conductor of the shielded transmission line structure is electrically connected to the source terminal and a signal conductor of the shielded transmission line structure is electrically connected to one of the gate terminal and the drain terminal.

2. The RF transistor amplifier of claim 1, wherein the shielded transmission line structure includes a stripline transmission line segment.

3. The RF transistor amplifier of claim 1, wherein the shielded transmission line structure includes a coplanar waveguide transmission line segment.

4. The RF transistor amplifier of claim 1, wherein the shielded transmission line structure may include a grounded coplanar waveguide transmission line segment.

5. The RF transistor amplifier of claim 1, wherein the interconnect structure includes a redistributed stacked structure.

6. The RF transistor amplifier of claim 1, wherein the interconnect structure includes a printed circuit board.

7. The RF transistor amplifier of claim 1, wherein a plurality of circuit elements are mounted on the interconnect structure.

8. The RF transistor amplifier of claim 7, wherein the circuit elements include at least one of a surface mount capacitor and a surface mount inductor.

9. The RF transistor amplifier of claim 1 further includes a coupling element that electrically connects the RF transistor amplifier die to the interconnect structure.

10. The RF transistor amplifier of claim 9, wherein the coupling element has a fan-in configuration.

11. The RF transistor amplifier of claim 9, wherein the coupling element comprises a plurality of conductive posts.

12. The RF transistor amplifier of claim 11, wherein the conductive pillars are configured to form a second shielded transmission line structure.

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