Semiconductor device and method of stabilizing heat spreader on semiconductor package

Abstract

A semiconductor device has an electrical component and heat sink disposed over the electrical component. A portion of the heat sink extends at least partially down a side surface of the electrical component to prevent lateral movement of the heat sink with respect to the semiconductor die. Alternatively, a portion of the heat sink extends at least partially below a surface of the electrical component. The heat sink can have an angled side, extension, or indentation to stabilize the heat sink on the electrical component to prevent rotation or otherwise shifting position that would impart movement in the lateral direction and possibly contact adjacent components or create defects on the PCB. The portion of the heat sink extending at least partially down does so on at least two side surfaces of the electrical component. The electrical component can be a flipchip semiconductor die.

Description

[Technical Field]

[0001] The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device and a method for stabilizing a semiconductor die or encapsulating a heat sink or heat plate. [Previous Technology]

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and generating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices are susceptible to heat from semiconductor die operation. Some semiconductor dies, such as microprocessors, operate at high clock frequencies and generate heat from rapid transistor switching. Other semiconductor devices, such as power MOSFETs, generate heat by conducting significant current. Figure 1a illustrates a conventional semiconductor die or package 10. In many applications, a thermal interface layer (TIM) 12 is deposited over the surface 14 of the semiconductor die or package 10, and a heat sink 18 is positioned over the TIM layer to dissipate heat. Ideally, the rectangular heat sink 18 is centered and aligned perpendicularly to the rectangular semiconductor die 10, that is, the sides of the heat sink are parallel to the corresponding sides of the semiconductor die, wherein the distances between the sides of the heat sink and the corresponding sides of the semiconductor die are equal, as shown in Figure 1b. Heat sink alignment is particularly important when the heat sink is similar in size to the semiconductor die.

[0004] It is known that a heat sink is moved or displaced relative to a semiconductor die during, for example, a curing process to bond the heat sink to the die. The heat sink may be rotated away from a right-angle alignment or displaced from the semiconductor die in a lateral direction, as shown in Figure 1c. In this case, the sides of the rectangular heat sink are no longer parallel to the corresponding sides of the rectangular semiconductor die, and the distances between the sides of the heat sink and the corresponding sides of the semiconductor die are no longer equal. In other words, the heat sink is skewed relative to the coverage area of ​​the semiconductor die and is no longer aligned above the coverage area of ​​the semiconductor die.

[0005] Semiconductor dies are typically placed on a PCB to interact with other electrical components. Semiconductor dies and heat sinks are positioned close to other electrical components on the PCB to optimize component density and overall functionality. Any misalignment between the heat sink and the semiconductor die—that is, when the heat sink rotates away from a right-angle alignment or shifts laterally from the semiconductor die—can cause the heat sink to extend beyond its intended position relative to the semiconductor die's coverage area and come into contact with adjacent electrical components. The edges 18a and 18b of the heat sink 18 are misaligned and may come into contact with adjacent components on the PCB. This contact is considered a PCB defect due to the potential for short circuits and component damage. [Summary of the Invention]

[0006] One aspect of the present invention is a method of manufacturing a semiconductor device, comprising: providing an electrical component; and placing a heat sink above the electrical component, wherein a portion of the heat sink extends downward along at least partially a side surface of the electrical component to prevent lateral movement of the heat sink relative to a semiconductor die.

[0007] In the method described above in this invention, the heat sink includes an angled side surface.

[0008] In the method described above in this invention, the heat sink includes an extension.

[0009] In the method described above in this invention, the heat sink includes indentations.

[0010] Another aspect of the present invention is a semiconductor device comprising: an electrical component; and a heat sink disposed above the electrical component, wherein a portion of the heat sink extends downward along at least partially a side surface of the electrical component to prevent lateral movement of the heat sink relative to a semiconductor die.

[0011] In another embodiment of the semiconductor device of the present invention, the heat sink includes angled sides.

[0012] In another embodiment of the semiconductor device of the present invention, the heat sink includes an extension.

[0013] In another embodiment of the semiconductor device of the present invention, the heat sink includes indentations.

[0014] In another embodiment of the semiconductor device of the present invention, the portion of the heat sink extends downward at least partially along at least two side surfaces of the electrical component.

[0015] Another aspect of the present invention is a semiconductor device comprising: an electrical component; and a heat sink disposed above the electrical component, wherein a portion of the heat sink extends at least partially below the surface of the electrical component.

[0016] In another embodiment of the semiconductor device, the heat sink includes angled sides.

[0017] In another embodiment of the semiconductor device described in the present invention, the heat sink includes an extension.

[0018] In another embodiment of the semiconductor device described in the present invention, the heat sink includes indentations.

[0019] In another embodiment of the semiconductor device, the portion of the heat sink extends downward at least partially along at least two side surfaces of the electrical component.

[0020] In another embodiment of the semiconductor device described in the present invention, the electrical component includes a flip-chip semiconductor die.

Implementation Method

[0022] The invention is described in one or more specific examples with reference to the figures in the following description, in which the same numbers denote the same or similar elements. Although the invention is described according to the best mode for achieving the objectives of the invention, it will be understood by those skilled in the art that it is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and figures. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and multiple semiconductor devices.

[0023] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, establish a relationship between the voltage and current necessary to perform the circuit function.

[0024] Back-end manufacturing refers to the process of dicing or monolithizing finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. To monolithize semiconductor dies, the wafer is scribed and broken along non-functional areas known as scribe lines or kerfs. Laser cutting tools or saw blades are used for wafer monolithization. After monolithization, the individual semiconductor dies are mounted onto a packaging substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, column bumps, conductive paste, or wire bonding. An encapsulation or other molding material is deposited on top of the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, enabling the functionality of the semiconductor device to be used with other system components.

[0025] FIG. 2a illustrates a semiconductor wafer 100 having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials used for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active inter-die regions or saw tracks 106. The saw tracks 106 provide dicing areas to monolithize the semiconductor wafer 100 into individual semiconductor dies 104. In one specific example, the semiconductor wafer 100 has a width or diameter of 100 to 450 millimeters (mm).

[0026] FIG2b shows a cross-sectional view of a portion of a semiconductor wafer 100. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry, including active devices, passive devices, conductive layers, and dielectric layers, implemented within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), memory, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs such as inductors, capacitors, and resistors for RF signal processing.

[0027] The conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad for electrical connections to circuits on the active surface 110.

[0028] Conductive bump material is deposited on the conductive layer 112 using evaporation, electrolytic plating, electroless plating, drop ball, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one specific example, the bump material is reflowed to form balls or bumps 114 by heating the material above its melting point. In one specific example, bumps 114 are formed on top of an under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 114 may also be bonded to the conductive layer 112 by compression bonding or thermocompression bonding. Bumps 114 represent a type of interconnect structure that can be formed on the conductive layer 112. Interconnection structures may also use bonding wires, conductive paste, cylindrical bumps, micro bumps, or other electrical interconnects.

[0029] In Figure 2c, the semiconductor wafer 100 is monolithically divided into individual semiconductor dies 104 by a saw blade or laser cutting tool 118 via sawing paths 106. The individual semiconductor dies 104 can be detected and electrically tested for identification after KGD monolithization. In one specific example, the semiconductor die 104 is a flip-chip semiconductor die.

[0030] In FIG. 3a, thermal interface material (TIM) 120 is deposited on the back surface 108 of the electrical component 121. In a specific example, the electrical component 121 is the semiconductor die 104 from FIG. 2c. The TIM 120 substantially covers the entire surface area of ​​the back surface 108 of the semiconductor die 104.

[0031] In FIG. 3b, a heat sink or radiator 122 is positioned above the TIM 120 and back surface 108 of the electrical assembly 121. The heat sink 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The heat sink 122 includes an extension or tab 124 extending perpendicularly relative to the surface 126 of the heat sink. The extension 124 is cut from the corner 136 of the heat sink 122 and bends downward at 90 degrees relative to the surface 126. The extension 124 has a flat surface extending downward to contact the side surface 132 of the electrical assembly 121 or otherwise residing outside the side surface 132 of the electrical assembly 121. The bottom view of the heat sink 122 in FIG. 3c shows the extension 124 at the corner 136 of the heat sink away from the inner region 130. The heat sink 122 is secured in place relative to the electrical component 121 by the extension 124 to prevent any lateral movement of the heat sink relative to the electrical component. Figure 3d is a perspective view of the surface 126 of the heat sink 122 with the extension 124 at the corner 136. Figure 3e illustrates the heat sink 122 mounted to the back surface 108 of the semiconductor die 104.

[0032] As discussed in the prior art, it would be undesirable for the heat sink 122 to be moved in place relative to the semiconductor die 104 during the curing process of the TIM 120 to bond the heat sink to the die. The sides of the heat sink 122 should remain parallel to the sides of the semiconductor die 104. If the heat sink 122 is to be rotated away from a right-angle alignment or moved laterally from the semiconductor die 104, the sides of the rectangular heat sink will no longer be parallel to the corresponding sides of the rectangular semiconductor die, wherein the distances between each side of the heat sink and each side of the semiconductor die are equal, as shown in FIG1c. In other words, the heat sink 122 will be skewed relative to the coverage area of ​​the semiconductor die 104 and will no longer be aligned above the coverage area of ​​the semiconductor die 104.

[0033] Specifically and toward this objective, the extension 124 extends at least partially downward along the side surface 132 of the electrical component 121 to hold the electrical component within the internal region 130. In another view, the extension 124 extends at least partially below the surface 108 of the electrical component 121. The extension 124, extending at least partially downward along the side surface 132 or at least partially below the surface 108, holds the heat sink 122 in place relative to the semiconductor die 104 to prevent rotation or other displacement of the heat sink, which would allow for lateral movement and potentially contact with adjacent components. The extension 124 of the heat sink 122 operates as an anchor point to the electrical component 121 to prevent any lateral movement of the heat sink relative to the electrical component.

[0034] FIG. 3f illustrates a perspective view of a semiconductor package 138 having a heat sink 122 mounted to the back surface 108 of a semiconductor die 104. The heat sink 122 has an extension 124 extending at least partially downward along the side surface 132 of the semiconductor die or at least partially below the surface 108 of the semiconductor die. Referring to FIG. 6, the semiconductor package 138 is intended to be mounted to a PCB. The extension 124 stabilizes the heat sink 122 on the electrical component 121 to prevent rotation or other displacement of its position, which would result in lateral movement and could potentially contact adjacent components or create defects on the PCB.

[0035] In another specific example, continuing from FIG3a, a heat sink or radiator 140 is positioned above the back surface 108 of the TIM 120 and the electrical assembly 121, as shown in FIG4a. The heat sink 140 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The heat sink 140 includes angled sides 144 that are bent downwards or angled from the surface 146 of the heat sink on both sides. The angled sides 144 may be formed by bending the edges of the heat sink 140 in a bending machine. The angled sides 144 may have an angle θ of 90 to 135 degrees relative to the surface 146. The bottom view of the heat sink 140 in FIG4b shows the bent or angled sides 144 that continue along the two sides of the heat sink to form the inner region 150. Angled side 144 bends downward to contact or otherwise reside outside the side surface 132 of the electrical component 121. Figure 4c is a perspective view of the surface 146 of a heat sink 140 having angled side 144. Figure 4d illustrates a heat sink 140 mounted to the back surface 108 of a semiconductor die 104, wherein two side surfaces 144 of the heat sink 140 bend downward.

[0036] Specifically, to maintain the alignment of the heat sink 140, the angled side surface 144 extends at least partially downward along the side surface 132 of the electrical component 121 to hold the electrical component within the internal region 150. In another view, the angled side surface 144 extends at least partially below the surface 108 of the electrical component 121. The angled side surface 144, extending at least partially downward along the side surface 132 or at least partially below the surface 108, holds the heat sink 140 in place relative to the semiconductor die 104 to prevent rotation or other displacement of the heat sink, which would allow for lateral movement and potentially contact with adjacent components. The heat sink 140 is secured in place relative to the electrical component 121 by the nature of the angled side surface 144 to prevent any lateral movement of the heat sink relative to the electrical component.

[0037] FIG4e illustrates a perspective view of a semiconductor package 158 having a heat sink 140 mounted to the back surface 108 of a semiconductor die 104. The heat sink 140 has an angled surface 144 extending at least partially downward along the side surface 132 of the semiconductor die or at least partially below the surface 108. Referring to FIG6, the semiconductor package 158 is intended to be mounted to a PCB. The angled side surface 144 stabilizes the heat sink 140 on the electrical component 121 to prevent rotation or other displacement of its position, which would result in lateral movement and could potentially contact adjacent components or create defects on the PCB.

[0038] In another specific embodiment, continuing from FIG3a, a heat sink or radiator 160 is positioned above the back surface 108 of the TIM 120 and the electrical component 121, as shown in FIG5a. The heat sink 160 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The heat sink 160 includes an indentation 164 extending at least partially downward from the surface 166 of the heat sink. The indentation 164 may be formed by driving a punch into the surface 168 of the heat sink 160 to form an indentation. In another view, the indentation 164 extends at least partially below the surface 108 of the electrical component 121. The indentation 164 is stamped to extend downward from the surface 166, thereby contacting the side surface 132 of the electrical component 121 or otherwise residing outside the side surface 132 of the electrical component 121. Figure 5b shows a bottom view of the heat sink 160, illustrating indentations 164 that continue along at least two sides of the semiconductor die 104 to form an internal region 170. In one specific example, the indentation 164 has a height H1 of 50 to 100 μm above the surface 166, as shown in Figure 5c. The indentation 164 may be present on three or four sides of the heat sink 160. Figure 5d is a perspective view of the surface 166 of the heat sink 160 with the indentation 164. Figure 5e illustrates the heat sink 160 mounted to the back surface 108 of the semiconductor die 104.

[0039] Specifically, to maintain the alignment of the heat sink 160, the back surface 108 of the electrical component 121 is completely contained within the internal region 170, such that the indentation 164 extends at least partially downward along the side surface 132 of the semiconductor die or at least partially below the surface 108. The indentation 164, extending at least partially downward along the side surface 132 or at least partially below the surface 108, holds the heat sink 160 in place relative to the semiconductor die 104 to prevent rotation or other displacement of the heat sink, thereby allowing lateral movement and contact with adjacent components. The heat sink 160 is secured in place relative to the electrical component 121 by the nature of the indentation 164 to prevent any lateral movement of the heat sink relative to the electrical component.

[0040] FIG. 5f illustrates a perspective view of a semiconductor package 178 having a heat sink 160 mounted to the back surface 108 of a semiconductor die 104. The heat sink 160 has an indentation 164 extending at least partially downward along the side surface 132 of the semiconductor die or at least partially below the surface 108 of the semiconductor die. Referring to FIG. 6, the semiconductor package 178 is intended to be mounted to a PCB. The indentation 164 stabilizes the heat sink 160 on the electrical component 121 to prevent rotation or other displacement of its position, which would result in lateral movement and could potentially contact adjacent components or create defects on the PCB.

[0041] Figure 6 illustrates an electronic device 300 having a chip carrier substrate or PCB 302, wherein a plurality of semiconductor packages are mounted on the surface of the PCB 302, including semiconductor packages 138, 158 and 178. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0042] Electronic device 300 may be a standalone system that uses semiconductor packaging to perform one or more electrical functions. Alternatively, electronic device 300 may be a sub-component of a larger system. For example, electronic device 300 may be part of a tablet computer, a cell phone, a digital camera, a communication system, or other electronic device. Alternatively, electronic device 300 may be a graphics card, a network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packaging may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor chips or electrical components. Miniaturization and weight reduction are necessary for market-acceptable products. The distance between semiconductor devices can be reduced to achieve higher density.

[0043] In Figure 6, PCB 302 provides a general-purpose substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on or within the surface of PCB 302 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between various components in the semiconductor package, mounting assembly, and other external system components. Trace 304 also provides power and ground connections to various components in the semiconductor package.

[0044] In some specific examples, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other specific examples, the semiconductor device may only have a first-level package, wherein the die is mechanically and electrically mounted directly to the PCB. For illustrative purposes, several types of first-level packages, including wire bond package 306 and flip chip 308, are shown on PCB 302. Additionally, several types of second-level packages, including ball grid array (BGA) 310, bump chip carrier (BCC) 312, land grid array (LGA) 316, multi-chip module (MCM) or SIP module 318, quad flat non-leaded package (QFN) 320, quad flat package 322, embedded wafer level ball grid array (eWLB) 324, and wafer level chip scale package (WLCSP) 326, are shown mounted on PCB 302. In one specific example, eWLB 324 is a fan-out wafer level package (Fo-WLP), and WLCSP 326 is a fan-in wafer level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages configured with first and second level package types and other electronic components can be connected to PCB 302. In some specific instances, electronic device 300 includes a single attached semiconductor package, while other specific instances require multiple interconnect packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, thereby reducing consumer costs.

[0045] Although one or more specific embodiments of the present invention have been described in detail, those skilled in the art will understand that modifications and adaptations can be made to those specific embodiments without departing from the scope of the present invention as set forth in the following claims. [Simplified Explanation of the Diagram]

[0021] [Fig. 1a] to [Fig. 1c] illustrate aligned and misaligned conventional semiconductor dies and heat sinks; [Fig. 2a] to [Fig. 2c] illustrate a semiconductor wafer having a plurality of semiconductor dies separated by saw marks; [Fig. 3a] to [Fig. 3f] illustrate the process of mounting a heat sink with extensions to a semiconductor die or package; [Fig. 4a] to [Fig. 4e] illustrate the process of mounting a heat sink with angled sides to a semiconductor die or package; [Fig. 5a] to [Fig. 5f] illustrate the process of mounting a heat sink with indentations to a semiconductor die or package; and [Fig. 6] illustrates a PCB with different types of packages mounted to the surface of a printed circuit board (PCB).

Claims

1. A method of manufacturing a semiconductor device, comprising: providing an electrical component; and disposing a heat sink above the electrical component, wherein a portion of the heat sink extends downward along at least partially a side surface of the electrical component to prevent lateral movement of the heat sink relative to a semiconductor die.

2. The method of claim 1, wherein the heat sink includes angled sides.

3. The method of claim 1, wherein the heat sink includes an extension.

4. The method of claim 1, wherein the heat sink includes indentation.

5. A semiconductor device comprising: an electrical component; and a heat sink disposed above the electrical component, wherein a portion of the heat sink extends downward along at least partially a side surface of the electrical component to prevent lateral movement of the heat sink relative to a semiconductor die.

6. The semiconductor device of claim 5, wherein the heat sink includes angled sides.

7. The semiconductor device of claim 5, wherein the heat sink includes an extension.

8. The semiconductor device of claim 5, wherein the heat sink includes indentations.

9. The semiconductor device of claim 5, wherein the portion of the heat sink extends downward at least partially along at least two side surfaces of the electrical component.

10. A semiconductor device comprising: an electrical component; and a heat sink disposed above the electrical component, wherein a portion of the heat sink extends at least partially below the surface of the electrical component.

11. The semiconductor device of claim 10, wherein the heat sink includes angled sides.

12. The semiconductor device of claim 10, wherein the heat sink includes an extension.

13. The semiconductor device of claim 10, wherein the heat sink includes indentations.

14. The semiconductor device of claim 10, wherein the portion of the heat sink extends downward at least partially along at least two side surfaces of the electrical component.

15. The semiconductor device of claim 10, wherein the electrical component includes a flip-chip semiconductor die.

Images