Plasma processing apparatus

Abstract

The heater (HT2) is arranged by being divided into the region (HT2a) of being circular when viewed from above, the region (HT2b) of surrounding the periphery of the region (HT2a) when viewed from above and the region (HT2c) of surrounding the periphery of the region (HT2a) when viewed from above. The heater (HT1) is arranged by being divided into several regions (HT1d) of being rectangular when viewed from above. The regions (HT2a-HT2c) and the regions (HT1d) are electrically connected to the controlling part (C0) which can individually control the power supplies of the regions (HT2a-HT2c) and the regions (HT1d).

Description

[Technical Field]

[0001] The present invention relates to a plasma processing apparatus, and more particularly to a plasma processing apparatus having a heater on a sample stage. [Previous Technology]

[0002] Generally speaking, on the surface of a plate-shaped sample such as a semiconductor wafer (hereinafter referred to as a wafer), a plurality of insulating films and a plurality of conductive films are deposited. In a plasma processing apparatus, although these films are etched, the etching process is carried out in the processing chamber of the same plasma processing apparatus without removing the wafer to the outside in order to shorten the time.

[0003] In etching processes like this, the wafer is processed while the temperature of the sample stage placed in the processing chamber is adjusted to a suitable temperature. Therefore, the sample stage of the plasma processing apparatus is equipped with a heater. When processing wafers, the following is performed: the heater is used to adjust the temperature to a suitable processing temperature to improve processing accuracy.

[0004] For example, Patent Document 1 discloses a technique in which an annular heating film is formed on the upper part of a metal substrate constituting a sample stage by means of a melt spraying method. The heating film allows for variations in the temperature distribution within the wafer surface for each etching condition.

[0005] Patent Document 2 discloses a plasma processing apparatus comprising: a first heating element in a concentric circle shape disposed on the upper part of a metal substrate constituting a sample stage; and a second heating element disposed below the first heating element. The second heating element is configured in a concentric circle shape by combining a plurality of fan-shaped heater segments. By dividing the second heating element, the heat generated by the second heating element becomes less than that of the first heating element. Using these two heating elements, temperature control of the wafer disposed on the sample stage can be performed simultaneously, and etching processing can be carried out on the wafer. [Prior Art Documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2007-67036 [Patent Document 2] Japanese Patent Application Publication No. 2017-157855 [Summary of the Invention]

[0007] [The problem that this invention aims to solve]

[0008] In recent years, in order to cope with the high density and miniaturization of semiconductor devices, wafer processing conditions have become more complex. For example, with the miniaturization of semiconductor devices, it is necessary to control the temperature in plasma processing to accommodate various patterns within the semiconductor devices. Therefore, in the sample stage, it is required to control temperature conditions over a wide range and to locally control fine temperature conditions.

[0009] To achieve localized temperature control of tiny semiconductor devices, the number of heater divisions must be increased. However, increasing the number of heater divisions necessitates increasing the power supply structure for each heater, thus complicating the internal structure of the sample stage. Furthermore, the increased power supply structure leads to problems such as "an increase in areas where temperature control is impossible, and a localized increase in regions with temperatures lower than the set temperature." In Patent Document 1, there is a concern that this could impair the temperature uniformity within the wafer surface. This would reduce the wafer manufacturing yield.

[0010] In Patent Document 2, a more precise temperature control than in Patent Document 1 can be achieved by using a second heating element with more divisions and less heat generation than the first heating element. However, the wafer region in which semiconductor elements are formed refers to the region surrounded by the scribed region and is rectangular in shape. Since the second heating element is configured as a concentric circle, when performing more precise temperature control on the semiconductor elements, there is a risk, similar to Patent Document 1, that the uniformity of temperature within the wafer surface may be compromised.

[0011] The main objective of this application is to provide a plasma processing apparatus comprising: a heater, which can improve the temperature uniformity within the wafer surface. Another objective of this application is to "use such a plasma processing apparatus to perform plasma processing (etching process), thereby suppressing the reduction in wafer manufacturing yield".

[0012] Other issues and novel features can be clearly understood from the description and accompanying drawings in this specification. [Means used to solve the issues]

[0013] To briefly summarize the representative content of the embodiments disclosed in this application, the following is a brief description.

[0014] One embodiment of the plasma treatment apparatus includes: a vacuum container; a treatment chamber disposed inside the vacuum container; a cylindrical sample stage disposed in the treatment chamber; and a control unit. Here, the aforementioned sample stage includes: a substrate; and an electrostatic chuck disposed on the surface of the substrate. The electrostatic chuck has a first heater and a second heater respectively covered by a dielectric film. The second heater is disposed above the first heater. The second heater is divided into a first region that is circular in plan view, a second region that surrounds the periphery of the first region in plan view, and a third region that surrounds the periphery of the second region in plan view. The first heater is divided into a plurality of fourth regions that are rectangular in plan view. The first region, the second region, the third region, and the plurality of fourth regions are electrically connected to the aforementioned control unit. The control unit can individually control the power supply to the first region, the second region, the third region, and the plurality of fourth regions. [Effects of the Invention]

[0015] According to one embodiment, a plasma processing apparatus is provided, which includes a heater to improve the temperature uniformity within the wafer surface. Furthermore, by using such a plasma processing apparatus to perform plasma processing, the reduction in wafer manufacturing yield can be suppressed.

Implementation Method

[0017] Hereinafter, the embodiments will be described in detail based on the drawings. Furthermore, in all the drawings used to explain the embodiments, components with the same function are given the same symbol and their repeated descriptions are omitted. Also, in the following embodiments, except where particularly necessary, the descriptions of the same or identical parts will generally not be repeated.

[0018] Furthermore, the X, Y, and Z directions described in this application are intersecting and orthogonal to each other. In this application, the Z direction is described as the vertical direction, height direction, or thickness direction of a structure. Also, the terms "plan view" or "top view" used in this application mean that the surface formed by the X and Y directions is considered a "plane" and that "plane" is viewed from the Z direction.

[0019] (Embodiment 1) <Composition of Plasma Processing Apparatus> Hereinafter, using FIG1, an outline of the plasma processing apparatus 1 in Embodiment 1 will be described.

[0020] The plasma treatment apparatus 1 comprises: a cylindrical vacuum container 2; a treatment chamber 4 disposed inside the vacuum container 2; a cylindrical sample stage 30 disposed inside the treatment chamber 4; and a base ring 5 mounted on the side of the sample stage 30. The upper part of the treatment chamber 4 forms a space for generating plasma 3, namely a discharge chamber. A conductor ring 6 is disposed inside the base ring 5.

[0021] Above the sample stage 30, a circular plate-shaped window member 7 and a circular plate-shaped spray plate 8 are provided. The window member 7 is made of a dielectric material such as quartz or ceramic layer, and airtightly seals the interior of the processing chamber 4. The spray plate 8 is disposed below the window member 7, away from it, and is made of a dielectric material such as quartz. Furthermore, a plurality of holes 9 are provided in the spray plate 8. A gap 10 is provided between the window member 7 and the spray plate 8, and processing gas is supplied to the gap 10 during plasma treatment.

[0022] The sample stage 30 is used to set up the wafer WF when performing plasma treatment on the material to be treated, i.e., the wafer WF. The sample stage 30 refers to a component whose central axis in the vertical direction is arranged in a position that is concentric or approximately concentric with the discharge chamber of the processing chamber 4 when viewed from above, and is cylindrical in shape.

[0023] In addition, a wafer WF is, for example, composed of "a semiconductor substrate like a wafer and semiconductor elements such as transistors formed on the semiconductor substrate and all or part of the insulating film and wiring layer formed on the semiconductor elements".

[0024] The space between the sample stage 30 and the bottom surface of the processing chamber 4 is connected to the space above the sample stage 30 through the gap between the side surface of the sample stage 30 and the side surface of the processing chamber 4. Therefore, the products, plasma 3 or gas particles generated during the processing of the wafer WF set on the sample stage 30 are discharged to the outside of the processing chamber 4 through the space between the sample stage 30 and the bottom surface of the processing chamber 4.

[0025] The sample stage 30 includes: a substrate 50; and an electrostatic chuck 40 disposed on the substrate 50. The substrate 50 and the electrostatic chuck 40 are cylindrical in shape. The main feature of this application is the structure of the heaters HT1 and HT2 contained in the electrostatic chuck 40, but such features will be described in detail later.

[0026] In addition, the central portion of the substrate 50 is a convex portion, and the outer periphery of the substrate 50 is a concave portion. The electrostatic chuck 40 is disposed on the upper surface of the convex portion of the substrate 50, and the base ring 5 is disposed on the upper surface of the concave portion in a manner that surrounds the side surface of the convex portion and the side surface of the electrostatic chuck 40.

[0027] A transfer port 11 is provided in one part of the vacuum container 2. By using a vacuum transfer device such as a robotic arm, the wafer WF can be transferred to the inside or outside of the processing chamber 4 through the transfer port 11.

[0028] The plasma processing apparatus 1 includes: a waveguide 12; a magnetron oscillator 13; and a solenoid coil 14. The waveguide 12 is disposed above the window member 7, and the magnetron oscillator 13 is disposed at one end of the waveguide 12. The magnetron oscillator 13 is capable of oscillating and outputting an electric field of microwaves. The frequency of the microwave electric field is not particularly limited, but is, for example, 2.45 GHz. The waveguide 12 is a conduit for propagating the electric field of microwaves, which is supplied to the interior of the processing chamber 4 via the waveguide 12. The solenoid coil 14 is disposed around the waveguide 12 and the processing chamber 4 and is used as a means of generating a magnetic field.

[0029] A vacuum exhaust port 15 is provided on the bottom surface of the processing chamber 4. By using a turbomolecular pump and a dry pump, the interior of the processing chamber 4 can be vented from atmospheric pressure to a vacuum state through the vacuum exhaust port 15.

[0030] The plasma processing apparatus 1 includes: a load impedance variable box 16; a load matching device 17; and a high-frequency power supply 18. The high-frequency power supply 18 is electrically connected to the conductor ring 6 of the base ring 5 via the load impedance variable box 16 and the load matching device 17. In addition, the high-frequency power supply 18 is connected to the ground potential.

[0031] The high AC voltage generated in the high-frequency power supply 18 is introduced into the conductor ring 6. By combining the load impedance variable box 16, which is adjusted to a suitable impedance value, with the relatively high impedance portion disposed above the base ring 5, the impedance value of the high-frequency power relative to the outer periphery of the wafer WF can be relatively reduced. Therefore, high-frequency power can be effectively supplied to the outer periphery of the wafer WF, and the concentration of the electric field in the outer periphery of the wafer WF can be mitigated. Therefore, in plasma processing, charged particles such as ions can be induced to the surface of the wafer WF in a desired direction.

[0032] The plasma processing apparatus 1 includes a control unit C0. The control unit C0 is electrically connected to the magnetron oscillator 13, the solenoid coil 14, the load impedance variable box 16, the load matching device 17, and the high-frequency power supply 18, and controls these operations.

[0033] <Structure of the Electrostatic Chuck> Hereinafter, the cross-sectional structure of the electrostatic chuck 40 will be described in detail using Figures 2 and 3. Figure 3 is an enlarged view of a portion of the electrostatic chuck 40 shown in Figure 2.

[0034] As shown in Figures 2 and 3, the substrate 50 is composed of convex and concave portions, wherein the upper surface of the concave portion is located at a lower position than the upper surface of the convex portion. Furthermore, the substrate 50 is provided with multiple refrigerant flow paths 51 arranged in a concentric or spiral shape.

[0035] The electrostatic chuck 40 has heaters HT1 and HT2, which are respectively covered by dielectric films 41-45. A dielectric film 41 is formed on a substrate 50 (on a protrusion of the substrate 50). A heater HT1 is formed on the dielectric film 41. A dielectric film 42 is formed on the dielectric film 41, covering the heater HT1. A heater HT2 is formed on the dielectric film 42. A dielectric film 43 is formed on the dielectric film 42, covering the heater HT2.

[0036] A shielding film 46 is formed on the dielectric film 43. The shielding film 46 covers the sides of the protrusions of the dielectric films 41-43 and the substrate 50. In other words, heaters HT1 and HT2 are covered by the shielding film 46. A dielectric film 44 is formed on the shielding film 46. An electrode 47 is formed on the dielectric film 44. A dielectric film 45 is formed on the dielectric film 44, covering the electrode 47. The dielectric film 45 is also formed on the surface of the recesses of the substrate 50, covering the shielding film 46.

[0037] The substrate 50 is made of a metallic material, such as titanium, aluminum, or such compounds. The dielectric films 41-45 are made of a dielectric material like ceramic, such as aluminum oxide. The shielding film 46 is made of a material capable of blocking high frequencies and is made of a non-magnetic metallic material. The electrodes 47 are each made of a non-magnetic metallic material, such as tantalum, tungsten, or molybdenum.

[0038] A protrusion is provided on the outer periphery of the dielectric film 45 in the upper part 40t (the upper part of the dielectric film 45) of the electrostatic chuck 40. The outer periphery of the wafer WF is placed on this protrusion. At this time, a gap is provided between the lower part of the wafer WF and the upper part 40t of the electrostatic chuck 40.

[0039] In the sample stage 30, holes 61 and 62 are formed that penetrate the substrate 50 and the dielectric films 41-45. When the wafer WF is placed on the electrostatic chuck 40, a heat-transferring gas such as helium (He) is supplied through the holes 61 to the gap between the lower surface of the wafer WF and the upper surface 40t of the electrostatic chuck 40. The heat-transferring gas can transfer temperature changes from the electrostatic chuck 40 to the wafer WF.

[0040] Inside the hole 62, a lifting pin 67 that can move vertically (Z-direction) is provided. During the loading and unloading of the wafer WF, the wafer WF is placed on the lifting pin 67 when the lifting pin 67 is moved to a position higher than the protrusion 40t above the electrostatic chuck 40. Subsequently, the lifting pin 67 is moved downwards, thereby placing the outer periphery of the wafer WF on the protrusion 40t above the electrostatic chuck 40. Furthermore, although not shown in the figure, a plurality of holes 62 and lifting pins 67 are provided on the sample stage 30.

[0041] Furthermore, the plasma processing apparatus 1 includes: a high-frequency power supply 70; a DC power supply 71; a DC power supply 72; and a DC power supply 73. The control unit C0 is electrically connected to the high-frequency power supply 70, the DC power supply 71, the DC power supply 72, and the DC power supply 73, and controls these operations.

[0042] In the sample stage 30, a hole 63 is formed that penetrates the substrate 50 and the dielectric films 41-44 to reach the electrode 47. The electrode 47 is electrically connected to a high-frequency power supply 70 and a DC power supply 71 via a cable and connector disposed inside the hole 63. In addition, the high-frequency power supply 70 is connected to ground potential. Furthermore, a plurality of electrodes 47 and holes 63 are formed in the sample stage 30.

[0043] When the wafer WF is placed on the electrostatic chuck 40, a DC voltage is supplied from the DC power supply 71 to the plurality of electrodes 47. This DC voltage causes the wafer WF to adhere to the top 40t of the electrostatic chuck 40, generating an electrostatic force within the electrostatic chuck 40 and the wafer WF to hold it in place. Furthermore, the plurality of electrodes 47 are symmetrically arranged around the central axis of the sample stage 30 in the vertical direction, and voltages of different polarities are applied to each of the plurality of electrodes 47.

[0044] Furthermore, high-frequency power of a predetermined frequency is supplied from the high-frequency power supply 70 to the plurality of electrodes 47 to form an electric field in the plasma processing of the wafer WF to induce charged particles in the plasma to the surface of the wafer WF. The frequency of the high-frequency power supply 70 is preferably set to be the same as the frequency of the high-frequency power supply 18 or a constant multiple of the frequency of the high-frequency power supply 18.

[0045] The shielding film 46 is electrically connected to the substrate 50. Since the substrate 50 is fixed to the ground potential, the shielding film 46 is also fixed to the ground potential in the same way. As a result, the inflow of high frequency to the heaters HT1 and HT2 can be suppressed.

[0046] On the sample stage 30, there is a hole 64 that penetrates the substrate 50 and the dielectric films 41 and 42 to reach the heater HT2. The heater HT2 is electrically connected to the DC power supply 72 through a cable and connector disposed inside the hole 62.

[0047] In the sample stage 30, a hole 65 is formed that penetrates the substrate 50 and the dielectric film 41 to reach the heater HT1. The heater HT1 is electrically connected to the DC power supply 73 via a cable and connector disposed inside the hole 65. In addition, the cable connected to the heaters HT1 and HT2 does not have a filter for high-frequency power.

[0048] Inside the substrate 50 located below the heater HT1, a temperature sensor 52 electrically connected to the control unit C0 is provided. The control unit C0 maintains the temperature detected by the temperature sensor 52 during plasma processing of the wafer WF. In addition, a plurality of temperature sensors 52 are provided according to the number of regions HT1d of the heater HT1, which will be described later.

[0049] Insulating supports 66 are respectively provided on the inner walls of holes 61-65. The insulating supports 66 are made of insulating materials, such as ceramic materials such as alumina or yttrium oxide, or resin materials. In the plasma processing of wafer finning (WF), there is a risk of discharge occurring inside holes 61-65 due to the electric field generated by high-frequency power, but by providing insulating supports 66, such concerns can be suppressed.

[0050] <Detailed Structure of the Heater> Hereinafter, the detailed structure of heaters HT1 and HT2 will be explained using Figures 4 to 9. Figure 4 is a bird's-eye view showing the positional relationship between the wafer WF, heater HT2, heater HT1, and substrate 50. Figures 5 to 7 are plan views showing the wafer WF, heater HT2, and heater HT1. Figure 8 is a plan view formed by superimposing heaters HT1 and HT2.

[0051] As shown in Figure 5, a wafer WF has: a scribing region SR extending in the Y and X directions; and a plurality of wafer regions CR (a plurality of die regions), each surrounded by the scribing region SR. The plurality of wafer regions CR are rectangular in shape when viewed from above. When the entire manufacturing process of the wafer WF is completed, the wafer WF is cut along the scribing region SR using a dicing tool or the like, and monolithically divided into the plurality of wafer regions CR. That is, the plurality of wafer regions CR are the areas actually shipped as finished products, and are the areas where various semiconductor devices are formed.

[0052] The heaters HT1 and HT2 are equipped with the function of selectively changing the temperature of various regions of the wafer WF.

[0053] As shown in Figure 6, the heater HT2 is divided into a circular region HT2a (viewed from above), a region HT2b (viewed from above), and a region HT2c (viewed from above), which surrounds the outer perimeter of region HT2a. That is, region HT2b is an annular shape with an inner diameter and outer diameter larger than the radius of region HT2a, and region HT2c is an annular shape with an inner diameter and outer diameter larger than the outer diameter of region HT2b.

[0054] In regions HT2a to HT2c, each is individually electrically connected to a DC power supply 72 as shown in FIG3. Therefore, the control unit C0 can individually control the power supply to regions HT2a to HT2c. In this way, the temperature of the regions in the wafer WF corresponding to regions HT2a to HT2c can be individually adjusted.

[0055] The main purpose of heater HT2 is to achieve temperature uniformity in the circumferential direction from a top view, and to control the temperature of wafer WF in response to the distribution of reaction products and plasma density distribution during plasma processing.

[0056] As shown in Figure 7, the heater HT1 is divided into a plurality of rectangular regions HT1d, which are arranged in a grid shape when viewed from above. The plurality of regions HT1d are adjacent to each other in the X and Y directions and are arranged in a grid shape.

[0057] Each of the plurality of regions HT1d is individually electrically connected to a DC power supply 73 as shown in FIG3. Therefore, the control unit C0 can individually control the power supply to the plurality of regions HT1d. This allows the temperature of the plurality of wafer regions CR to be adjusted individually. In other words, the plurality of regions HT1d are arranged such that one region HT1d is located below one wafer region CR. Therefore, when the power supply to one region HT1d is changed, the temperature of one wafer region CR is changed.

[0058] The main purpose of heater HT1 is to individually adjust the temperature of multiple wafer regions CR during plasma processing, thereby locally adjusting the etching shape. Therefore, heater HT2 is divided into three regions (regions HT2a to HT2c), and in contrast, heater HT1 is divided into, for example, 120 regions. That is, the number of multiple regions HT1d is, for example, 120.

[0059] In heater HT1, although there are many power supply lines connecting multiple DC power supplies 73 and multiple regions HT1d, there is a problem that regions with temperatures lower than the set temperature (cold spots) are easily increased locally. However, the temperature of the cold spots can be corrected by heater HT2. Furthermore, although it is not possible to perform temperature control of small areas in heater HT2, it is possible to perform temperature control of such small areas by heater HT1.

[0060] In this way, the plasma processing apparatus 1 is equipped with heaters HT1 and HT2, thereby improving the uniformity of the in-plane temperature of the wafer WF.

[0061] Furthermore, regions HT2a to HT2c and the plurality of regions HT1d refer to the regions that become heaters, and not to the shape of the conductors constituting the heaters themselves. Specifically, regions HT2a to HT2c and the plurality of regions HT1d are configured by folding heating wires repeatedly. The heating wires are made of metallic materials, such as titanium, tungsten, or molybdenum.

[0062] Figure 9 is a table comparing the characteristics of heater HT1 and heater HT2. The heating area of ​​heater HT2 is larger than that of heater HT1. However, since heater HT1 is divided into multiple regions HT1d, there are more power supply lines and the current is larger. When the current is large, there is a risk of damage to the device due to heat generation such as melting loss or thermal deformation, given the contact resistance present in the power supply lines. Moreover, with more power supply lines, there is also a risk of the power supply lines themselves overheating. When such heat-generating areas are densely packed, their impact cannot be ignored, necessitating the consideration of heat dissipation methods within the electrostatic chuck 40. As described above, in heater HT1, it is necessary to increase the resistance value and reduce the current.

[0063] On the other hand, in heater HT2, due to its large area and long heating wires, the resistance value tends to be high. Therefore, since the current is reduced, it is necessary to reduce the resistance value.

[0064] When considering the above, it is preferable that the structures of the heating wires constituting heater HT1 (multiple regions HT1d) and heater HT2 (regions HT2a~HT2c) have the following relationship. In addition, here, the material constituting the heating wires of heater HT1 is the same as the material constituting the heating wires of heater HT2.

[0065] The thickness of the heating wire constituting heater HT2 is greater than the thickness of the heating wire constituting heater HT1. Furthermore, the line width of the heating wire constituting heater HT2 is greater than the line width of the heating wire constituting heater HT1. Moreover, it is even better if these relationships are satisfied simultaneously.

[0066] Furthermore, as shown in Figure 8, there are multiple locations where "one region HT1d spans two regions HT2a to HT2c". In such locations, the power supply is adjusted by considering the respective temperatures of regions HT2a to HT2c and region HT1d, as well as the electrical energy around the corresponding region HT1d.

[0067] Furthermore, the heater HT1 and the outermost peripheral region HT1d are irregularly shaped. When temperature control is implemented with an irregular shape, it is difficult to maintain uniformity at the outermost periphery of the wafer WF. Therefore, temperature control is implemented in the outermost periphery of the wafer WF by region HT2c, thereby reducing temperature unevenness. Also, when it is desired to form the wafer region CR at the outermost periphery of the wafer WF, this results in the region becoming irregularly shaped. Therefore, in reality, the outermost periphery of the wafer WF is the region where semiconductor devices are not formed, and is not shipped as a product. Therefore, even if "the outermost peripheral region HT1d of the heater HT1 becomes irregularly shaped, causing temperature unevenness at the outermost periphery of the wafer WF", it will not have a significant impact on the manufacturing yield of the wafer WF.

[0068] <Plasma Processing Method> Hereinafter, using FIG10, a method of “performing an etching process using plasma 3 on a predetermined film pre-formed on the surface of a wafer WF” is illustrated as an example of a plasma processing method.

[0069] First, in step S1, DC voltage is supplied to heaters HT1 and HT2 from DC power supplies 72 and 73 by means of an instruction from control unit C0, and heaters HT1 and HT2 are turned on. Before plasma treatment, the power supply to heaters HT2 (regions HT2a to HT2c) and heaters HT1 (region HT1d) is set to the target temperature.

[0070] In step S2, the pressure inside the vacuum transport container connected to the side wall of the vacuum container 2 is reduced to the same pressure as the processing chamber 4. The wafer WF is placed from outside the plasma processing apparatus 1 at the front end of the arm of the vacuum transport device, which is like a robotic arm, and is transported into the vacuum transport device. By forming an opening in the transport port 11, the wafer WF is transported from inside the vacuum transport container into the processing chamber 4 and placed on the sample stage 30. When the arm of the vacuum transport device retracts from the processing chamber 4, the interior of the processing chamber 4 is sealed.

[0071] In step S3, a DC voltage is supplied from the DC power supply 71 to the electrode 47, and the generated electrostatic force holds the wafer WF on the upper surface 40t of the electrostatic chuck 40. In this state, a heat-transferring gas such as helium (He) is supplied through the orifice 61 to the gap between the wafer WF and the upper surface 40t of the electrostatic chuck 40. Furthermore, a coolant adjusted to a predetermined temperature by a coolant temperature regulator (not shown) is supplied to the coolant flow path 51. This promotes heat transfer between the temperature-adjusted substrate 50 and the wafer WF, and the temperature of the wafer WF is adjusted to a value suitable for initiating plasma processing.

[0072] In step S4, a processing gas with adjusted flow rate and speed is supplied to the gap 10 via a gas supply device (not shown), and diffuses within the gap 10. The diffused processing gas is supplied from a plurality of holes 9 to the top of the sample stage 30. The processing gas is supplied to the interior of the processing chamber 4, and a vacuum is applied to the interior of the processing chamber 4 from the vacuum exhaust port 15. By balancing these two aspects, the pressure inside the processing chamber 4 is adjusted to a value suitable for plasma processing.

[0073] In this state, the electric field of microwaves is oscillated from the magnetron oscillator 13. The electric field of the microwaves propagates inside the waveguide 12 and passes through the window member 7 and the spray plate 8. Moreover, the magnetic field generated by the solenoid coil 14 is supplied to the processing chamber 4. Through the interaction between the above-mentioned magnetic field and the electric field of the microwaves, an electron cyclotron resonance (ECR) is generated. Furthermore, the atoms or molecules of the processed gas are excited, ionized, or dissociated, thereby generating plasma 3 inside the processing chamber 4.

[0074] When plasma 3 is generated, high-frequency power is supplied from high-frequency power supply 70 to electrode 47 to form a bias potential on the surface of wafer WF, and charged particles such as ions in plasma 3 are induced to the surface of wafer WF. In this way, plasma processing (etching processing) is performed on a predetermined film of wafer WF in a manner that follows the pattern shape of the mask layer.

[0075] In step S5, the control unit C0 compares the temperature detected by the plurality of temperature sensors 52 with the target temperature previously set for the plurality of regions HT1d in step S1 during plasma processing of the wafer WF. Furthermore, the control unit C0 individually controls the power supply to the plurality of regions HT1d to minimize the difference. Here, the control unit C0 controls the power supply to only the plurality of regions HT1d without changing the power supply to regions T2a to HT2c. Therefore, the temperature of the wafer region CR corresponding to the region HT1d whose power supply has been changed is individually adjusted.

[0076] In step S6, the etched material is transferred to other films. Therefore, the control unit C0 changes the power supply to regions HT2a to HT2c to adapt to the temperature of the other films. The changed temperature is detected by a plurality of temperature sensors 52 and transmitted to the control unit C0. The control unit C0 adjusts the power supply to regions T2a to HT2c and adjusts the in-plane temperature of the wafer WF in a manner that makes the error of the changed temperature within a predetermined temperature range.

[0077] Here, in the heater HT1, the same process as in step S5 is performed. That is, the power supply to the plurality of regions HT1d is individually controlled, and the temperature of the plurality of wafer regions CR is individually adjusted.

[0078] Subsequently, in step S7, without further etching of the wafer WF, the supply of processing gas to the gap 10 is stopped, the transmission of microwaves from the magnetron oscillator 13 is stopped, and the supply of high-frequency power from the high-frequency power supply 70 is stopped. This stops the plasma processing. In step S8, static electricity is removed, and the adhesion of the wafer WF is released. In step S9, the arm of the vacuum transfer device enters the interior of the processing chamber 4, and the processed wafer WF is transferred to the outside of the plasma processing apparatus 1.

[0079] In this way, since the uniformity of temperature within the wafer WF plane can be improved by using the plasma processing device 1 to perform plasma processing (etching processing), the reduction in wafer manufacturing yield can be suppressed.

[0080] Although the present invention has been specifically described above based on the above embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from its spirit. [Simplified Explanation of the Diagram]

[0016] [Figure 1] shows a schematic diagram of the plasma processing apparatus in Embodiment 1. [Figure 2] shows a cross-sectional view of the sample stage in Embodiment 1. [Figure 3] shows an enlarged cross-sectional view of a portion of the sample stage in Embodiment 1. [Figure 4] shows a bird's-eye view of the positional relationship between the wafer, the two heaters, and the substrate in Embodiment 1. [Figure 5] shows a plan view of the wafer in Embodiment 1. [Figure 6] shows a plan view of the upper heater in Embodiment 1. [Figure 7] shows a plan view of the lower heater in Embodiment 1. [Figure 8] shows a plan view of the two heaters in Embodiment 1 superimposed. [Figure 9] shows a table comparing the characteristics of the two heaters in Embodiment 1. [Figure 10] shows a flowchart of the plasma processing method in Embodiment 1.

Claims

1. A plasma treatment apparatus, characterized by comprising: a vacuum container; a treatment chamber disposed inside the vacuum container; a cylindrical sample stage disposed in the treatment chamber; and a control unit, wherein the sample stage includes: a substrate; and an electrostatic chuck disposed on the surface of the substrate; the electrostatic chuck having a first heater and a second heater respectively covered by a dielectric film; the second heater being disposed above the first heater; the second heater being divided into a first region that is circular in plan view, a second region that surrounds the periphery of the first region in plan view, and a third region that surrounds the periphery of the second region in plan view; the first heater being divided into a plurality of fourth regions that are rectangular in plan view; the first region, the second region, the third region, and the plurality of fourth regions being electrically connected to the control unit. The aforementioned control unit is capable of individually controlling the power supply to the aforementioned first area, the aforementioned second area, the aforementioned third area, and the aforementioned plurality of fourth areas.

2. The plasma treatment apparatus as claimed in claim 1, wherein, The aforementioned first heater and the aforementioned second heater are provided for adjusting the temperature of the aforementioned wafer when the wafer is placed on the aforementioned electrostatic chuck. The aforementioned wafer has: a scribing area; and a plurality of wafer areas, each surrounded by the scribing area and each rectangular in shape when viewed from above. The aforementioned control unit individually controls the power supply to the aforementioned plurality of fourth areas, thereby individually adjusting the temperature of the aforementioned plurality of wafer areas.

3. The plasma treatment apparatus as described in claim 2, wherein, When the aforementioned wafer is placed on top of the aforementioned electrostatic chuck, the plurality of fourth regions are arranged such that one of the aforementioned fourth regions is located below one of the aforementioned wafer regions.

4. The plasma treatment apparatus as claimed in claim 2, wherein, It further includes: a plurality of temperature sensors, each disposed inside the aforementioned substrate located below the plurality of fourth regions, and electrically connected to the aforementioned control unit. The aforementioned control unit, during the plasma processing of the aforementioned wafer, compares the difference between the temperature detected by the plurality of temperature sensors and the target temperature previously set for the plurality of fourth regions before the plasma processing, and individually controls the power supply to the plurality of fourth regions in a manner that reduces the difference.

5. The plasma treatment apparatus as claimed in claim 4, wherein, The aforementioned control unit individually controls the power supply to the aforementioned plurality of fourth regions without altering the power supply to the aforementioned first region, the aforementioned second region, and the aforementioned third region.

6. The plasma treatment apparatus as claimed in claim 1, wherein, The aforementioned first region, the aforementioned second region, the aforementioned third region, and the aforementioned plurality of fourth regions are respectively constructed by folding and reversing heating wires. The heating wires are made of metal material. The thickness of the heating wires that constitute the aforementioned first region, the aforementioned second region, and the aforementioned third region is thicker than the thickness of the heating wires that constitute the aforementioned plurality of fourth regions.

7. The plasma treatment apparatus as claimed in claim 6, wherein, The line width of the heating lines that constitute the aforementioned first region, the aforementioned second region, and the aforementioned third region is wider than the line width of the heating lines that constitute the aforementioned plurality of fourth regions.

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