Semiconductor field effect transistor, power amplifier comprising the same and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-03-14
- Publication Date
- 2023-09-16
Smart Images
Figure TWG2TA000924431_001 
Figure TWG2TA000924431_002 
Figure TWG2TA000924431_003
Abstract
Description
[Technical Field]
[0001] This invention relates primarily to semiconductor devices, but is not limited thereto; in particular, it relates to a semiconductor field-effect transistor, a power amplifier comprising the same, and a method of manufacturing the same. [Previous Technology]
[0002] With the booming development and popularization of wireless communication systems and mobile devices, the industry's demand for radio frequency (RF) power components is gradually increasing; especially in the application market of 5G infrastructure, in order to achieve the goals of reducing costs, improving efficiency and expanding bandwidth, excellent RF components play an indispensable role.
[0003] Among semiconductor field-effect transistors, aluminum gallium nitride (AlGaN) / gallium nitride (GaN) high electron mobility transistors (HEMTs) have advantages such as low on-resistance, high current density, and high breakdown voltage, and are therefore considered a popular technology option for radio frequency power devices. These superior properties are mainly attributed to GaN's excellent material properties, such as wide bandgap, high critical electric field, and high electron saturation velocity. Furthermore, GaN's unique polarization effect allows the AlGaN / GaN heterostructure to induce the formation of two-dimensional electron gases (2DEG) in the interface region even without doping, enabling AlGaN / GaN HEMTs to operate with high current output and very low on-resistance.
[0004] On the other hand, the linearity of power amplifiers is also a very important metric in the field of wireless communication. Improved linearity can reduce intermodulation distortion between different frequency signals of power components, especially third-order intermodulation distortion, thereby reducing noise in communication systems. Studies have found that the more gradual / uniform the distribution of the transconductance (gm) of a component relative to the gate-source voltage (Vgs), or the lower the value of gs, the better the linearity performance of the component. [Summary of the Invention]
[0005] The present invention is intended to provide a simplified summary of the invention so that the reader can have a basic understanding of the invention. This present invention is not a complete overview of the invention, and it is not intended to point out important or key elements of the embodiments of the invention or to define the scope of the invention.
[0006] The inventors have discovered that conventional semiconductor field-effect transistors often exhibit at least one prominent peak in gm within a specific V gs value range, leading to concerns about poor linearity. The inventors have further discovered that the spatial distribution of electron concentration in the transistor is highly correlated with the numerical distribution of gm relative to V gs; wherein the electrons in the transistor specifically refer to electron groups in the channel layer, such as two-dimensional electron gases (2DEG) confined to the potential well; or doped channels formed through doping. The inventors believe that by controlling the distribution of these electron groups, the numerical distribution of the transconductance relative to the gate-source voltage can be effectively adjusted, further improving the linearity of the device. In view of this, the present invention provides a semiconductor field-effect transistor whose channel layer has an n-type doped layer; the n-type doped layer is used to change the spatial distribution of electron concentration in the transistor and improve the overall radio frequency linearity of the device; the semiconductor field-effect transistor manufactured accordingly can not only control the threshold voltage through charge adjustment, but also reduce its resistance.
[0007] Specifically, the present invention provides a semiconductor field-effect transistor, which includes a channel layer, a barrier layer, a gate, a source, and a drain. The barrier layer is disposed above the channel layer, and the channel layer and the barrier layer are made of different materials. A two-dimensional electron gas region is present in the channel layer near the barrier layer. The gate is disposed above the barrier layer. The source and drain are disposed at opposite ends of the gate. The channel layer further includes an n-type doped layer disposed at the boundary of the two-dimensional electron gas region.
[0008] According to one embodiment of the present invention, the n-type doped layer includes a silicon dopant.
[0009] According to one embodiment of the present invention, the n-type doped layer has an electron area concentration between 1.5*10 12 and 6*10 12 ns*cm -2; wherein the n-type doped layer includes a high-concentration electron group with an electron concentration between 1.5*10 19 and 3*10 19 ns*cm -3.
[0010] According to one embodiment of the present invention, the interface between the n-type doped layer and the channel layer and the barrier layer is between 60 and 100 angstroms.
[0011] According to one embodiment of the present invention, the channel layer is made of GaN that is not intentionally doped or undoped, and the barrier layer is made of AlGaN that is not intentionally doped or undoped.
[0012] According to one embodiment of the present invention, the semiconductor field-effect transistor further includes a passivation layer disposed on the barrier layer, and the passivation layer covers at least a portion of the upper surface of the source, the gate and the drain.
[0013] According to one embodiment of the present invention, the semiconductor field-effect transistor further includes a buffer layer disposed below the channel layer.
[0014] According to some embodiments of the present invention, the semiconductor field-effect transistor system is a modulation-doped field-effect transistor (MODFET), a high electron mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-semiconductor field-effect transistor (MESFET), or a metal-insulator-semiconductor field-effect transistor (MISFET).
[0015] In another aspect, the present invention provides a power amplifier comprising a semiconductor field-effect transistor as described above.
[0016] In another aspect, the present invention provides a method for manufacturing a semiconductor field-effect transistor, comprising: forming a buffer layer above a substrate; forming a channel layer above the buffer layer and forming an n-type doped layer within the channel layer; forming a barrier layer above the channel layer; forming a gate above the barrier layer and forming a source and a drain at the two ends of the gate, respectively.
[0017] According to one embodiment of the present invention, the n-type doped layer is formed by doping with a silicon dopant.
[0018] According to one embodiment of the present invention, the n-type doped layer has an electron area concentration after formation, which is between 1.5*10 12 and 6*10 12 ns*cm -2; wherein the n-type doped layer includes a high-concentration electron group, whose electron concentration is between 1.5*10 19 and 3*10 19 ns*cm -3.
[0019] According to one embodiment of the present invention, the location where the n-type doped layer is formed is about 60 to 100 angstroms away from the interface between the channel layer and the barrier layer.
[0020] Another aspect of the present invention provides a linear power amplifier comprising a semiconductor field-effect transistor as described in the present invention.
[0021] The advantages of the semiconductor field-effect transistor and its manufacturing method provided by the present invention are as follows: by means of an n-type doped layer disposed in the channel layer, the electron distribution within the transistor is specifically changed, for example, the electron concentration distribution in the space surrounding the two-dimensional electron gas, and the radio frequency linearity of the device is substantially improved; thereby, the threshold voltage can be controlled by adjusting the charge, and its resistance can be reduced. Accordingly, the present invention not only retains the original advantages of various semiconductor field-effect transistors, but also possesses outstanding linearity, thereby enhancing the potential value of the present invention in the field of radio frequency power amplifiers.
Implementation Method
[0024] To make the description of the present invention more detailed and complete, illustrative descriptions of embodiments and specific examples of the present invention are provided below, but these are not the only forms of implementing or applying the specific examples of the present invention. In this specification and the appended claims, unless the context otherwise requires, "a" and "the" are also to be interpreted as plural. Furthermore, in this specification and the appended claims, unless otherwise stated, "deposited on something" can be considered as direct or indirect contact with the surface of something by attachment or other means, and the definition of that surface should be determined based on the context / paragraph semantics of the specification and ordinary knowledge in the art to which this invention pertains.
[0025] Although the numerical ranges and parameters used to define the present invention are approximate values, the relevant values in the specific embodiments have been presented as precisely as possible. However, any value inevitably contains standard deviations due to individual testing methods. Here, "approximately" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a specific value or range. Alternatively, the term "approximately" means that the actual value falls within the acceptable standard error of the average value, as is the opinion of one skilled in the art to which this invention pertains. Therefore, unless otherwise stated, the numerical parameters disclosed in this specification and the accompanying claims are approximate values and are subject to change as needed. At least these numerical parameters should be understood as the indicated significant digits and the values obtained by applying general rounding.
[0026] This invention relates to a semiconductor field-effect transistor and a method for manufacturing the same; the semiconductor field-effect transistor is preferably a compound semiconductor field-effect transistor; more preferably an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) high electron mobility transistor (HEMTs); however, according to different embodiments, the semiconductor field-effect transistor may also be a modulation-doped field-effect transistor (MODFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-semiconductor field-effect transistor (MESFET), or a metal-insulator-semiconductor field-effect transistor (MISFET). Specifically, the metal-oxide-semiconductor field-effect transistor referred to in this article can be an n-type or p-type silicon-based metal-oxide-semiconductor field-effect transistor (Si-MOSFET) or an n-type or p-type silicon carbide-based metal-oxide-semiconductor field-effect transistor (SiC-MOSFET). This semiconductor field-effect transistor can be a planar transistor or a non-planar transistor, such as a Fin Field-Effect Transistor (FinFET) or a Gate-All-Around Field-Effect Transistor (GAAFET). This semiconductor field-effect transistor includes a channel layer and a barrier layer, and the channel layer and the barrier layer are made of different materials, thus having a heterojunction between them. The block induction at this heterojunction forms a two-dimensional electron gas (2DEG) region. Furthermore, the compound semiconductor field-effect transistor provided by the present invention has an n-type material layer in the channel layer near the boundary of the two-dimensional electron gas region, which substantially changes the electron concentration distribution in the space surrounding the two-dimensional electron gas, thereby improving the linearity of the device.
[0027] As used herein, the term "boundary of the two-dimensional electron gas region" refers to the location in the channel layer where the electron concentration of the two-dimensional electron gas region approaches zero. Generally, the distance between the boundary of the two-dimensional electron gas region and the interface between the channel layer and the barrier layer may vary depending on the material; according to the preferred embodiment of this invention, the distance is 60 to 100 angstroms, for example: 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 or 100.
[0028] Specifically, the "high electron mobility transistor" described in this invention can be a naturally normally on structure with a negative threshold voltage; it can also be converted to a normally off structure with a positive threshold voltage. On the other hand, the "semiconductor material" described in this invention can include chemical compounds of various elements, including but not limited to GaN, which belongs to one or more different groups in the periodic table. These chemical compounds can include pairings of Group 13 elements (i.e., the group containing boron (B), aluminum (Al), gallium (Ga), indium (In) and thallium (Tl)) and Group 15 elements (i.e., the group containing nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi); or pairings of Group 14 elements (i.e., the group containing carbon (C), silicon (Si), germanium (Ge) and tin (Sn), such as silicon carbide (SiC) or silicon-germanium alloys. Groups 13 to 15 of the periodic table can be referred to as Groups III, IV, and V, respectively.
[0029] Another aspect of the present invention relates to a method for manufacturing a semiconductor field-effect transistor. Generally speaking, the layers, doping, masking, and device structures described herein are formed using any suitable technique (e.g., deposition, growth, patterning, or etching) for forming such layers, doping, masking, and device structures.
[0030] In addition, the semiconductor field-effect transistor provided by the present invention can be disposed in a power amplifier.
[0031] Example
[0032] FIG1 is a cross-sectional view of a layer depicted according to a conventional semiconductor device 100. Referring to FIG1, the conventional semiconductor device 100 is substantially a semiconductor device based on aluminum gallium nitride / gallium nitride high electron mobility transistors, and is an epitaxially grown layer. The conventional semiconductor device 100 includes a substrate 110, a buffer layer 120, a channel block 130, a source electrode 140, a gate electrode 150, and a drain electrode 160.
[0033] The channel block 130 is disposed on the surface of the buffer layer 120, and further includes a channel layer 131 and a barrier layer 133. A junction 132 is formed between the channel layer 131 and the barrier layer 133, which is a heterogeneous material interface, allowing a two-dimensional electron gas region 132G to be formed within the channel layer 131 near the junction 132. This two-dimensional electron gas region 132G can form a conduction channel for free electrons when subjected to a bias voltage, thereby achieving, for example, the electrical coupling of the source electrode 140 and the drain electrode 160. Specifically, the compound semiconductor material of the channel layer 131 is undoped or unintentionally doped GaN, while the compound semiconductor material of the barrier layer 133 is undoped or unintentionally doped AlxGa1-xN; where x is in the range of approximately 0.1 to approximately 1.
[0034] Figures 2a to 2d are characteristic analyses based on the conventional semiconductor device 100 described above. Please refer to Figures 1 to 2d together. Figure 2a is a graph showing the variation of electron concentration relative to the channel layer space based on the conventional semiconductor device 100; where the vertical axis is the electron concentration (ns*cm⁻³), and the horizontal axis is the distance (Å) within the channel layer 131 relative to the junction 132. As can be seen from Figure 2a, the electron concentration in the channel layer 131 near the junction 132 exhibits a bell-shaped pattern, which essentially corresponds to the distribution of electron concentration in the two-dimensional electron gas region 132G; more specifically, within a distance of 150 Å between the channel layer 131 and the junction 132, the electron area concentration is 1.1*10¹³ns*cm⁻².
[0035] Figure 2b is a graph showing the change in electron saturation velocity relative to the number of electrons per unit area according to the conventional semiconductor device 100; wherein the vertical axis represents the electron saturation velocity (10⁷ cm / s), and the horizontal axis represents the electron area concentration (ns*cm⁻²). Figure 2c is a graph showing the change in transconductance (gm) relative to the gate-source voltage (V gs) according to the conventional semiconductor device 100; wherein the vertical axis represents the transconductance (mS), and the horizontal axis represents the gate-source voltage (V). As used herein, the term "transconductance" refers to the ratio of the change in source output current to the change in gate-source voltage, which can be used to measure the control capability of the gate-source voltage of a device over the source output current; the unit of transconductance is usually Siemens (S), but the present invention uses millisiemens (mS).
[0036] The inventors of this case further analyzed and found that, without being restricted by a specific theory, based on the change in the electron saturation velocity relative to the electron area concentration of the element (as shown in Figure 2b), the relationship between the transconductance and the gate-source voltage (as shown in Figure 2c) can be derived from the distribution of electron concentration relative to space (the result shown in Figure 2a). In the above example, under the condition of its electron concentration spatial distribution (as shown in Figure 2a), the conventional semiconductor device 100 will exhibit at least one prominent peak in the change of transconductance relative to the gate-source voltage (as shown in Figure 2c), which means that the linearity of the conventional semiconductor device 100 is insufficient. On the other hand, this embodiment presents a one-dimensional simulation diagram (Figure 2d) and a test result diagram (Figure 2e) of the transconductance relative to the gate-source voltage of the conventional semiconductor device 100 based on Figures 2a and 2b. According to Figures 2d and 2e, the vertical axis of both is the transconductance value per unit length (mS / mm), and the horizontal axis is the gate-source voltage (V). It can be seen that the conventional semiconductor device 100 will exhibit a non-smooth numerical pattern in the transconductance versus gate-source voltage performance graph under its electron concentration distribution conditions (i.e., as shown in Figure 2a).
[0037] In view of the above examples, without being limited by any specific theory, the inventors of this case have discovered that: based on the relationship between the change in the electron saturation velocity of a device and the electron area concentration, the state of the device's transduction relative to the gate-source voltage can be derived from the distribution of electron concentration relative to space. Based on this, the inventors propose this embodiment, which involves implanting an electron group near the edge of the two-dimensional electron gas region in the transistor channel layer to adjust the electron concentration distribution in the space surrounding the two-dimensional electron gas region in the semiconductor device, thereby improving the device's performance in the change of transduction relative to the gate-source voltage, and thus enhancing the linearity of the transistor. Specifically, this embodiment provides a graph of the change in electron concentration relative to the channel layer space (Figure 3a), where the vertical axis represents the electron concentration (ns*cm⁻³), and the horizontal axis represents the distance (Å) relative to the junction of the transistor channel layer and the barrier layer. Within a distance of 150 Å from the junction in the channel layer, the original electron area concentration is 1.1*10¹³ns*cm⁻². The electron clusters are implanted at approximately 60 to 100 Å of the interface within the channel layer, with an electron areal concentration of 1.92 × 10¹² ns / cm². These electron clusters include a rapidly increasing high-concentration cluster with an electron concentration of approximately 1.5 × 10¹⁹ ns / cm³. This embodiment also provides a one-dimensional simulation diagram (Figure 3b) and a test result diagram (Figure 3c) corresponding to Figure 3a of the transduction relative to the gate-source voltage; where the vertical axis represents the transduction value per unit length (mS / mm), and the horizontal axis represents the gate-source voltage (V). As can be seen from Figures 3a to 3c, when an electron group is implanted in the transistor channel layer near the boundary of the two-dimensional electron gas region, especially when the electron group includes a suddenly rising high-concentration electron group, the spatial distribution of electron concentration in the transistor can be adjusted, thereby causing the transduction of the transistor to exhibit a smooth numerical pattern relative to the gate-source voltage; this performance means an improvement in the linearity of the transistor.
[0038] According to different embodiments, increasing the electron area concentration of the implanted electron group also helps to make the transducer's transduction relative to the gate-source voltage exhibit a smoother numerical pattern. Specifically, according to one embodiment of the present invention, the electron area concentration of the implanted electron group is 4.0*10 12 ns*cm -2, which is twice the concentration used in the above embodiment, and under a similar distribution pattern, the high-concentration electron group it contains has an electron concentration of 3*10 19 ns*cm -3. Figure 3d is a test result diagram of transduction relative to gate-source voltage, with the vertical axis corresponding to the transduction value per unit length (mS / mm) as solid lines and the drain-source current value (mA / mm) as dashed lines, and the horizontal axis representing the gate-source voltage (V). As can be seen from Figure 3d, by implanting a higher concentration of electron group, the spatial distribution of electron concentration in the transistor is further regulated, and the transistor has better linearity.
[0039] According to different embodiments, the electron area concentration of the implanted electron group can reach 6.0*10 12ns*cm -2, and its specific concentration value can be adjusted by those skilled in the art based on the specific parameters of the component; however, its concentration value is preferably between 1.5*10 12 and 6*10 12ns*cm -2.
[0040] Without affecting the electron area concentration of the aforementioned electron group, the size of the distribution area of the high-concentration electron group can be adjusted according to the user's needs. According to one embodiment of the present invention, the high-concentration electron group exhibits a peak pattern with a width, and its specific distribution area (width) is less than or equal to 30 Å; preferably 10 to 30 Å, for example: 10, 15, 20, 25 or 30 Å.
[0041] In view of the above embodiments, the inventors of this case understand that by implanting electron clusters around the boundary of a two-dimensional electron gas region, the electron concentration distribution within a transistor having a two-dimensional electron gas region can be effectively adjusted, thereby improving the linearity of the transistor. It should be understood that, depending on the different material or structural characteristics of the transistor itself, those skilled in the art can adjust the electron area concentration or implantation position of the implanted electron clusters based on factors such as the change in electron saturation velocity relative to electron area concentration of individual elements, the electron area concentration of the two-dimensional electron gas region, or the size of its distribution area; without contradicting the inventive concept of this case, those skilled in the art can appropriately adjust the details of the invention without considering it as exceeding the scope of the invention.
[0042] In detail, the electron group is located at approximately 60 to 100 Å at the junction of the transistor channel layer and the barrier layer, preferably at 65 to 80 Å, such as: 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79 or 80 Å.
[0043] Under the same concept, those skilled in the art to which this invention pertains can also change the carrier of the above embodiments from electrons to holes as needed; therefore, users can also reasonably change the above-mentioned implanted electron group to a hole group.
[0044] Continuing, the present invention proposes another embodiment, which is a semiconductor device including a transistor applying the above-described concept. FIG4 is a cross-sectional view of the layer presented according to this embodiment. Referring to FIG4, this embodiment provides a semiconductor device 200A, which may be a GaN-based semiconductor device and includes a GaN-based compound semiconductor field-effect transistor; however, other suitable single-crystal silicon compound semiconductor materials may also be used here. The semiconductor device structure 200A may be an epitaxially grown layer, specifically including a substrate 210, a buffer layer 220, a channel block 230, a source electrode 240, a gate electrode 250, and a drain electrode 260.
[0045] The substrate 210 includes a wafer and must be insulating, such as a wafer made of a high-quality single-crystal silicon semiconductor material, such as any polymorph of sapphire, GaN, GaAs, silicon, silicon carbide (SiC) (including wurtzite), AlN, InP or similar substrate materials used for semiconductors.
[0046] The buffer layer 220 is disposed on the surface of the substrate 210, and may have an appropriate lattice structure and / or coefficient of thermal expansion to compensate for mismatches between the substrate 210 and other layers. The buffer layer 220 includes a compound semiconductor material, such as undoped, unintentionally doped (UID), or carbon-doped (C-doped) GaN or AlN, and the material may be formed into a thin film structure by epitaxial growth or by other thin film formation techniques such as chemical vapor deposition; and in terms of parameters, the thickness of the buffer layer 220 is approximately 150 to 250 nm, preferably 200 nm.
[0047] The channel block 230 is disposed on the surface of the buffer layer 220, and further includes a channel layer 231 and a barrier layer 233. There is a junction 232 between the channel layer 231 and the barrier layer 233; and the channel layer 231 and the barrier layer 233 are made of different materials, so the junction 232 is a heterogeneous material interface, which allows a two-dimensional electron gas region 232G to be formed near the junction 232 of the channel layer 231; the two-dimensional electron gas region 232G can form a conduction channel for free electrons when subjected to a bias voltage, thereby achieving, for example, the purpose of electrically coupling the source electrode 240 and the drain electrode 260. Specifically, the compound semiconductor material of the channel layer 231 is undoped or unintentionally doped GaN, while the compound semiconductor material of the barrier layer 233 is undoped or unintentionally doped AlxGa1-xN; wherein x is in the range of approximately 0.1 to approximately 1, and according to some embodiments, x is between 0.15 and 1, while according to different embodiments, x is between 0.20 and 0.25, such as 0.20, 0.21, 0.22, 0.23, 0.24, or 0.25. On the other hand, the thickness of the channel layer 231 is in the range of approximately 150 to 500 nm, preferably 150-250 nm; and the thickness of the barrier layer 233 is in the range of approximately 1.5 to 25 nm, preferably between 1.5 and 20 nm, and the thickness can be adjusted according to different x values.
[0048] It should be noted that an n-type doped layer 234 is provided in the channel layer 231 near the junction 232 (that is, near the two-dimensional electron gas region 232G), which includes an n-type dopant, preferably a silicon dopant; specifically, the n-type doped layer 234 is located at a distance of about 60 to 100 Å from the junction 232, preferably 65 to 80 Å, such as: 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79 or 80 Å. On the other hand, the n-type doped layer 234 has an electron area concentration between 1.5*10 12 and 6*10 12 ns*cm⁻², for example: 1.5*10 12, 2*10 12, 2.5*10 12, 3*10 12, 3.5*10 12, 4*10 12, 4.5*10 12, 5*10 12, 5.5*10 12 or 6*10 12 ns*cm⁻²; wherein the n-type doped layer includes a high-concentration electron cluster with an electron concentration between 1.5*10 19 and 3*10 19 ns*cm⁻³, such as: 1.5*10 19, 2*10 19, 2.5*10 19 or 3*10 19 ns*cm⁻³.
[0049] Under the same concept, those skilled in the art to which this invention pertains can also change the carrier of the above embodiments from electrons to holes as needed; therefore, users can also reasonably change the above-mentioned n-type doped layer to a p-type doped layer.
[0050] The gate electrode 250 is disposed above the barrier layer 233, while the source electrode 240 and the drain electrode 260 are disposed on both sides of the gate electrode 250. Specifically, the gate electrode 250 can be any conductive material capable of biasing or controlling the semiconductor device 200A. Considering the larger valence band gap with the compound semiconductor material used in this invention, it is preferably nickel (Ni) / gold (Au) or zirconium (Zr) / gold (Au). The source electrode 240 and the drain electrode 260 can be any suitable conductive material capable of forming an ohmic contact or other conductive interface with the two-dimensional electron gas region 232G. It is preferably titanium (Ti) / aluminum (Al) / nickel (Ni) / gold (Au). More preferably, in addition to nickel, tantalum (Ta) or molybdenum (Mo) and other high-temperature refractory metals can also be used as a diffusion barrier between aluminum and gold.
[0051] Figure 5 is a cross-sectional view of a semiconductor device 200B according to an embodiment of the present invention. Referring to Figures 4 and 5, the structures presented in both are substantially similar, both being GaN-based semiconductor devices and including GaN-based compound semiconductor field-effect transistors. The difference is that the semiconductor device 200B further provides a passivation layer 270 above the barrier layer 233. The passivation layer 270 covers at least a portion of the upper surfaces of the source electrode 240, the gate electrode 250, and the drain electrode 260; and the passivation layer 270 can also be a gate oxide layer or a silicon nitride (Si3N4) material.
[0052] Figure 6 is a cross-sectional view of a semiconductor device 200C according to an embodiment of the present invention. Referring to Figures 5 and 6, the structures presented in both are substantially similar, both being GaN-based semiconductor devices and including GaN-based compound semiconductor field-effect transistors. The difference is that the semiconductor device 200C further includes a superlattice layer 213 and a nucleation layer 211, both of which are disposed between the substrate 110 and the buffer layer 120; as used herein, a superlattice layer refers to a lattice layer that includes a periodic structure longer than a basic unit lattice by superimposing a plurality of lattices.
[0053] Specifically, the superlattice layer 213 further includes a first superlattice layer 213A and a second superlattice layer 213B. The first superlattice layer 213A contains undoped or unintentionally doped AlN and has a thickness of approximately 4 to 5 nm, preferably 4.5 nm; the second superlattice layer 213B contains undoped or unintentionally doped GaN and has a thickness of approximately 10 to 30 nm, preferably 20 nm. The superlattice layer 213 has approximately 40 periods, so its total thickness is approximately between 560 and 1400 nm, preferably 980 nm. On the other hand, the nucleation layer 211 includes undoped or unintentionally doped AlN compound and has a thickness of approximately 100 nm.
[0054] Figure 7 is a cross-sectional view of a semiconductor device 200D according to an embodiment of the present invention. This embodiment is substantially similar in structure to the aforementioned semiconductor devices 200A to 200C, all of which can be GaN-based semiconductor devices and include GaN-based compound semiconductor field-effect transistors. The difference is that in this embodiment, the semiconductor device 200D only has the nucleation layer 211 between the channel block 230 and the substrate 210, and does not have the buffer layer 220; the semiconductor device 200D manufactured based on the setting conditions of this embodiment can have higher breakdown voltage and power density, and effectively reduce thermal resistance, current breakdown and memory effect.
[0055] According to some embodiments of the present invention, a cap layer may be further provided above the barrier layer 233 of the semiconductor device, which contains an undoped or unintentionally doped compound semiconductor material, preferably an undoped or unintentionally doped GaN.
[0056] In addition, those skilled in the art should be able to apply the concept of the present invention to other transistors that also generate electron group distributions internally; specifically, the semiconductor device using the transistor of the present invention can also be a silicon-based metal oxide semiconductor field-effect transistor (Si-MOSFET) or a silicon carbide-based metal oxide semiconductor field-effect transistor (SiC-MOSFET); in other words, the channel block and substrate and other layer structures in the above embodiments can be an integral silicon or silicon carbide substrate. When a bias voltage is applied to the gate, it will attract charges to generate charge channels below the barrier layer. These charge channels are regarded as channel layers. However, it should be understood that, depending on the material or structural characteristics of the transistor itself, those skilled in the art to which this invention pertains may adjust the electron area concentration or the placement position of the n-type doped layer based on factors such as the change in electron saturation velocity relative to electron area concentration of individual elements, the electron area concentration of the two-dimensional electron gas region, or the size of its distribution area. Without contradicting the inventive concept of this case, those skilled in the art to which this invention pertains may appropriately adjust its detailed definition, and this should not be regarded as exceeding the scope of this invention.
[0057] Manufacturing method
[0058] Figure 8 is a flowchart illustrating the manufacturing process of a semiconductor field-effect transistor according to various embodiments of the present invention. Referring to Figure 8, manufacturing a semiconductor field-effect transistor according to an embodiment of the present invention includes the following steps: Step 1001: forming a buffer layer over a substrate; Step 1002: forming a channel layer over the buffer layer and forming an n-type doped layer within the channel layer; Step 1003: forming a barrier layer over the channel layer; Step 1004: forming a source, a gate, and a drain. It should be particularly noted that the steps in the method described herein are merely exemplarily described based on the inventor's concept. Those with ordinary knowledge in the technical field to which this invention pertains may slightly substitute the content of the above method, or even change the order of the above steps, based on the same or similar concepts; and such substitutions or changes still fall within the scope of the present invention.
[0059] The "suitable epitaxial growth or deposition process" described in this invention includes, but is not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), atomic layer deposition (ALD), molecular layer deposition (MLD), plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, or combinations thereof.
[0060] In step 1001, the substrate may be derived from a previous manufacturing process or may be made according to one or more substrate growth and processing techniques, including a wafer, such as a wafer made of high-quality single-crystal silicon semiconductor material, such as any polymorph of silicon carbide (SiC) (including wurtzite), AlN, InP or similar substrate materials used for semiconductors; the buffer layer includes a compound semiconductor material, such as undoped, unintentionally doped or carbon-doped GaN; the buffer layer is a thin film formed by a suitable epitaxial growth or deposition process, with a thickness of about 150 to 250 nm, preferably 200 nm.
[0061] Depending on the implementation, in step 1001, a nucleation layer and a superlattice layer may be formed on the substrate by an appropriate epitaxial growth or deposition process. The nucleation layer is formed of undoped or unintentionally doped AlN compound, and its thickness is about 100 nm. When forming the superlattice layer, it further includes forming a first superlattice layer and a second superlattice layer. The first superlattice layer is made of undoped or unintentionally doped AlN, and its thickness is about 4 to 5 nm, preferably 4.5 nm; the second superlattice layer is made of undoped or unintentionally doped GaN, and its thickness is about 10 to 30 nm, preferably 20 nm; and the superlattice layer is formed in about 40 cycles, so the total thickness produced is about 560 to 1400 nm, preferably 980 nm.
[0062] In step 1002, the channel layer is formed using undoped or unintentionally doped GaN as the forming material and is fabricated using a suitable epitaxial growth or deposition process; the thickness of the channel layer is approximately in the range of 150 to 500 nm, preferably 150-400 nm. The n-type doped layer can be doped with a dopant, which is a silicon dopant, by means of a suitable epitaxial growth or deposition process; specifically, the dopant can be implanted during the formation of the channel layer. After the n-type doped layer is formed, it has an electron area concentration between 1.5*10 12 and 6*10 12 ns*cm⁻², for example: 1.5*10 12, 2*10 12, 2.5*10 12, 3*10 12, 3.5*10 12, 4*10 12, 4.5*10 12, 5*10 12, 5.5*10 12 or 6*10 12 ns*cm⁻²; wherein the n-type doped layer includes a high-concentration electron cluster with an electron concentration between 1.5*10 19 and 3*10 19 ns*cm⁻³, such as: 1.5*10 19, 2*10 19, 2.5*10 19 or 3*10 19 ns*cm⁻³.
[0063] Under the same concept, those skilled in the art to which this invention pertains can also change the carrier of the above embodiments from electrons to holes as needed; therefore, users can also reasonably change the above-mentioned n-type doped layer to a p-type doped layer and implant p-type dopants accordingly.
[0064] In step 1003, the barrier layer is formed using undoped or unintentionally doped Al xGa 1-xN as the forming material; wherein x is in the range of about 0.1 to about 1, according to some embodiments, x is between 0.15 and 1, and according to different embodiments, x is between 0.20 and 0.25, and is manufactured by a suitable epitaxial growth or deposition process; the thickness of the barrier layer is in the range of about 5 to 20 nm, preferably between 10 and 15 nm.
[0065] Step 1004 may include a preliminary preparation procedure, such as mesa isolation fabrication, which further includes an etching process. The etching process may be dry etching or wet etching, preferably dry etching, such as physical bombardment methods like reactive ion etching (RIE) or inductively coupled plasma etching (ICP). Next, the gate can be made of any conductive material capable of biasing or controlling the semiconductor device, preferably nickel (Ni) / gold (Au) or zirconium (Zr) / gold (Au), and formed on the p-type material layer using appropriate epitaxial growth or deposition processes; while the source and drain can be made of any suitable conductive material capable of forming ohmic contacts or other conductive interfaces, preferably titanium (Ti) / aluminum (Al) / nickel (Ni) / tantalum (Ta) / molybdenum (Mo) / gold (Au), and formed at both ends of the gate using appropriate epitaxial growth or deposition processes. In addition, in some embodiments, step 1004 may further include a passivation process, which prepares a passivation layer, which can be formed using appropriate epitaxial growth or deposition processes, and covers at least a portion of the upper surfaces of the source, the gate, and the drain; and the passivation layer may also be a gate oxide layer, or formed of silicon nitride (Si3N4) material.
[0066] Regarding the above manufacturing method, the specific formation location of the n-type doped layer is about 60 to 100 Å away from the interface between the channel layer and the barrier layer, preferably 65 to 80 Å, such as 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79 or 80 Å.
[0067] In summary, the technical problem solved by the present invention compared to the prior art is that, based on the discovery of the correlation between the electron concentration distribution in the space surrounding the two-dimensional electron gas region in the transistor and the linearity of the device, the channel layer of the semiconductor field-effect transistor provided by the present invention is provided with an n-type doped layer with a specific electron area concentration at the boundary of the two-dimensional electron gas region; the n-type doped layer is used to change the electron concentration distribution in the space surrounding the two-dimensional electron gas region in the transistor, thereby improving the linearity of the overall device.
[0068] The present invention has been described in detail above. However, the above description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should still fall within the scope of the patent of the present invention. [Simplified Explanation of the Diagram]
[0022] To make the above and other objects, features, advantages and embodiments of the present invention more readily understood, the accompanying drawings are described as follows: FIG1 is a cross-sectional view of a conventional semiconductor device layer; FIG2a to 2e are characteristic analysis diagrams presented according to a conventional semiconductor device; FIG3a to 3d are characteristic analysis diagrams presented according to an embodiment of the present invention; FIG4 to 7 are cross-sectional views of a semiconductor device layer presented according to various embodiments of the present invention; FIG8 is a semiconductor field-effect transistor manufacturing process diagram presented according to various embodiments of the present invention.
[0023] In accordance with conventional operating procedures, the various features and elements in the drawings are not drawn to actual scale. The drawing method is to present the specific features and elements related to the present invention in the best possible way. In addition, similar elements and parts are referred to by the same or similar element symbols in different drawings. [Biomaterial Storage]
[0070] None.
Claims
1. A semiconductor field-effect transistor, comprising: One channel layer; A barrier layer is disposed above the channel layer; A gate is disposed above the barrier layer; The gate has a source and a drain, which are disposed at opposite ends of the gate. The channel layer and the barrier layer are made of different materials, and the channel layer has a two-dimensional electron gas region near the barrier layer. The channel layer further includes an n-type doped layer disposed at the boundary of the two-dimensional electron gas region.
2. The semiconductor field-effect transistor as described in claim 1, wherein, The n-type doped layer includes a silicon dopant.
3. The semiconductor field-effect transistor as described in claim 1, wherein, The n-type doped layer has an electron area concentration between 1.5 × 10¹² and 6 × 10¹² ns / cm²; wherein the n-type doped layer includes a high-concentration electron cluster with an electron concentration between 1.5 × 10¹⁹ and 3 × 10¹⁹ ns / cm³.
4. The semiconductor field-effect transistor as described in claim 1, wherein, The interface between the n-type doped layer and the channel layer and the barrier layer is between 60 and 100 angstroms.
5. The semiconductor field-effect transistor as described in claim 1, wherein, The channel layer is made of unintentionally doped or undoped GaN, while the barrier layer is made of unintentionally doped or undoped AlGaN.
6. The semiconductor field-effect transistor as claimed in claim 1, further comprising a passivation layer disposed on the barrier layer, and the passivation layer covering at least a portion of the upper surfaces of the source, the gate and the drain.
7. The semiconductor field-effect transistor as described in claim 1, further comprising a buffer layer disposed below the channel layer.
8. The semiconductor field-effect transistor as described in any one of claims 1 to 7 is a modulation-doped field-effect transistor (MODFET), a high electron mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal epitaxial-semiconductor field-effect transistor (MESFET), or a metal-insulator-semiconductor field-effect transistor (MISFET).
9. A power amplifier comprising a semiconductor field-effect transistor as described in any one of claims 1 to 8.
10. A method for manufacturing a semiconductor field-effect transistor, comprising: A buffer layer is formed on top of a substrate; A channel layer is formed above the buffer layer, and an n-type doped layer is formed within the channel layer; a barrier layer is formed above the channel layer; a gate is formed above the barrier layer, and a source and a drain are formed at the two ends of the gate, respectively.
11. The method for manufacturing a semiconductor field-effect transistor as described in claim 10, wherein, The n-type doped layer is formed by doping with a silicon dopant.
12. The method for manufacturing a semiconductor field-effect transistor as described in claim 10 or 11, wherein, After formation, the n-type doped layer has an electron area concentration between 1.5 × 10¹² and 6 × 10¹² ns / cm⁻²; wherein the n-type doped layer includes a high-concentration electron cluster with an electron concentration between 1.5 × 10¹⁹ and 3 × 10¹⁹ ns / cm⁻³.
13. The method for manufacturing a semiconductor field-effect transistor as described in claim 10 or 11, wherein, The location where the n-type doped layer is formed is approximately 60 to 100 angstroms away from the interface between the channel layer and the barrier layer.