Adapter board, optical chip package, and calculation accelerator and manufacturing method therefor

Abstract

An adapter board, an optical chip package, and a calculation accelerator and a manufacturing method therefor. The adapter board comprises: a glass substrate, which comprises one or more conductive through holes, wherein each conductive through hole comprises a through hole penetrating through the glass substrate and a conductive material filled in the through hole; and an optical waveguide structure, which is arranged on a first surface of the glass substrate, wherein the optical waveguide structure comprises one or more layers of optical waveguides and a coating layer coating the one or more layers of optical waveguides, the one or more layers of optical waveguides being used for performing optical interconnection on a plurality of optical chips which are packaged on the adapter board, and the refractive index of the one or more layers optical waveguides being greater than the refractive indexes of the coating layer and the glass substrate, and the optical waveguide structure further comprises one or more first conductive structures which penetrate through the optical waveguide structure and are respectively electrically connected to the one or more conductive through holes.

Description

[Technical Field]

[0001] This patent application claims priority to Chinese Patent Application No. 202210369385.3, filed on April 8, 2022. This disclosure relates to the field of semiconductor packaging, specifically to an adapter board for optical chip packaging, an optical chip packaging structure, a computing accelerator, and a method for manufacturing the adapter board and the optical chip packaging structure. [Previous Technology]

[0002] When packaging photonic integrated circuits (PICs, also known as photonic chips), electronic integrated circuits (EICs, also known as electronic chips) are typically stacked on top of the photonic integrated circuits to form a photonic-electronic hybrid integrated circuit (photonic-electronic hybrid chip), thereby forming an optoelectronic hybrid system to achieve computing acceleration. In order to reduce the chip size, electrical connections can be transferred to the substrate or printed circuit board (PCB) through vertical interconnects (e.g., through silicon vias (TSVs)).

[0003] However, silicon interposers with embedded TSVs still face cost challenges because silicon wafers are semiconductor substrates with low resistivity and high dielectric constant. Thin silicon wafers are difficult to process, and manufacturing TSVs remains expensive due to the long time required for drilling and filling vias with electroplated copper. Furthermore, prior art typically requires additional optical fibers to achieve optical interconnects between different optical chips, which also contributes to the problem of excessively large package sizes for optoelectronic hybrid modules. [Summary of the Invention]

[0004] In view of the above problems, this disclosure aims to provide an adapter board based on a glass substrate (e.g., a glass wafer) and its manufacturing method, as well as an optical chip packaging structure using this adapter board and its manufacturing method. Because glass substrates have high resistivity, low electrical loss, adjustable coefficients of thermal expansion, and good mechanical strength, the adapter board based on the glass substrate has low manufacturing cost and can be effectively used for optical chip packaging. Furthermore, this disclosure also aims to provide an optical chip packaging structure and its manufacturing method that uses thermally adiabatic coupling to couple optical signals between optical waveguides on the adapter board and optical waveguides on the optical chip. This coupling method occupies a small area, allows for close-fitting waveguide layouts, improves integration, and reduces package size.

[0005] A first aspect of this disclosure provides an adapter board for optical chip packaging, comprising: a glass substrate including one or more conductive vias, the conductive vias including vias penetrating the glass substrate and conductive material filling the vias; and an optical waveguide structure disposed on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a coating layer covering the one or more optical waveguides, the one or more optical waveguides being used for optical interconnection of a plurality of optical chips packaged on the adapter board, and the refractive index of the one or more optical waveguides being greater than the refractive index of the coating layer and the glass substrate, and the optical waveguide structure further including one or more first conductive structures penetrating the optical waveguide structure, which are electrically connected to the one or more conductive vias respectively.

[0006] In some embodiments, the above-mentioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the above-mentioned cladding layer is silicon dioxide.

[0007] In some embodiments, the adapter plate further includes: a dielectric layer disposed on a second surface of the glass substrate; one or more conductive bumps disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

[0008] A second aspect of this disclosure provides another adapter board for optical chip packaging, comprising: a glass substrate including one or more conductive vias, the conductive vias including vias penetrating the glass substrate and conductive material filling the vias; and an optical coupling structure disposed on a first surface of the glass substrate, wherein the glass substrate further includes a three-dimensional waveguide network for optical interconnection of a plurality of optical chips packaged on the adapter board, the optical coupling structure including a coupling optical waveguide covering the optical input / output port of the three-dimensional waveguide network and a coating layer covering the coupling optical waveguide, and the optical coupling structure further includes one or more first conductive structures penetrating the optical coupling structure, which are electrically connected to the one or more conductive vias respectively.

[0009] In some embodiments, the refractive index of the coupled optical waveguide is lower than that of the three-dimensional waveguide network but higher than that of the cladding layer.

[0010] In some embodiments, the above-mentioned coupling optical waveguide is a silicon nitride optical waveguide, and the material of the above-mentioned cladding layer is silicon dioxide.

[0011] In some embodiments, the adapter plate further includes: a dielectric layer disposed on a second surface of the glass substrate; one or more conductive bumps disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

[0012] In some embodiments, the above-mentioned three-dimensional waveguide network is a network structure formed by inducing local glass inside the glass substrate to increase the refractive index of the local glass.

[0013] The cooperating manufacturer disclosed herein provides another adapter board for optical chip packaging, comprising: a glass substrate including one or more first conductive vias, the first conductive vias including vias penetrating the glass substrate and conductive material filling the vias; and an electrical interconnection structure disposed on a first surface of the glass substrate, wherein the electrical interconnection structure includes one or more wiring layers and a covering layer covering the one or more wiring layers, the covering layer being a dielectric material, the one or more wiring layers being used to electrically interconnect multiple electronic chips above the optical chip packaged on the adapter board, and the electrical interconnection structure further including one or more first conductive structures penetrating the electrical interconnection structure, which are electrically connected to the one or more first conductive vias respectively.

[0014] In some embodiments, at least two of the above-mentioned multilayer wiring layers are electrically connected through a second conductive structure.

[0015] In some embodiments, the above-mentioned coating layer is a multilayer structure formed by alternating stacking of silicon nitride layers and silicon dioxide layers.

[0016] In some embodiments, the adapter board further includes: an optical waveguide structure disposed on the surface of the electrical interconnect structure away from the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a surrounding layer surrounding the one or more optical waveguides, the one or more optical waveguides being used for optical interconnection of a plurality of optical wafers packaged on the adapter board, the refractive index of which is greater than the refractive index of the surrounding layer, and the optical waveguide structure further includes one or more third conductive structures penetrating the optical waveguide structure, which are electrically connected to the one or more first conductive structures respectively.

[0017] In some embodiments, the above-mentioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the above-mentioned cladding layer is silicon dioxide.

[0018] In some embodiments, the adapter plate further includes: a dielectric layer disposed on the second surface of the glass substrate; one or more conductive bumps disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more fourth conductive structures penetrating the dielectric layer, which are electrically connected to the one or more first conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more fourth conductive structures respectively.

[0019] A fourth aspect of this disclosure provides a method for manufacturing an adapter board for optical chip packaging, comprising: providing a glass substrate and forming one or more conductive vias in the glass substrate; disposing an optical waveguide structure on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a coating layer covering the one or more optical waveguides; and forming one or more first conductive structures penetrating the optical waveguide structure in the coating layer and electrically connecting them to the one or more conductive vias, wherein the refractive index of the one or more optical waveguides is greater than the refractive index of the coating layer.

[0020] In some embodiments, the above-mentioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the above-mentioned cladding layer is silicon dioxide.

[0021] In some embodiments, configuring an optical waveguide structure on the first surface of the glass substrate includes: a. forming an optical waveguide network on the first surface of the glass substrate using wafer-level nanoimprint lithography; b. depositing a coating material over the optical waveguide.

[0022] In some embodiments, the method of manufacturing the adapter plate further includes: disposing a dielectric layer on a second surface of the glass substrate; forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer and electrically connecting them to the one or more conductive vias respectively; and disposing one or more conductive bumps on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

[0023] In some embodiments, forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias by disposing a conductive material layer on the inner surface of the one or more vias.

[0024] In some embodiments, forming one or more conductive vias by providing a conductive material layer on the inner surface of the vias includes filling the inner surface of the vias with conductive metal by electroplating.

[0025] The fifth aspect of this disclosure provides another method for manufacturing an adapter board for optical chip packaging, comprising: providing a glass substrate and forming a three-dimensional waveguide network within the glass substrate for optical interconnection of a plurality of optical chips packaged on the adapter board; forming one or more conductive vias in the glass substrate; disposing a coupling optical waveguide on a first surface of the glass substrate to cover the optical input / output ports of the three-dimensional waveguide network; covering the coupling optical waveguide with a coating layer to cover the coupling optical waveguide; and forming one or more first conductive structures penetrating the coating layer in the coating layer and electrically connecting them to the one or more conductive vias respectively.

[0026] In some embodiments, the refractive index of the coupled optical waveguide is lower than that of the three-dimensional waveguide network but higher than that of the cladding layer.

[0027] In some embodiments, the above-mentioned coupling optical waveguide is a silicon nitride optical waveguide, and the material of the above-mentioned cladding layer is silicon dioxide.

[0028] In some embodiments, the method of manufacturing the adapter plate further includes: disposing a dielectric layer on a second surface of the glass substrate; forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer and electrically connecting them to the one or more conductive vias respectively; and disposing one or more conductive bumps on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

[0029] In some embodiments, forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias by disposing a conductive material layer on the inner surface of the one or more vias.

[0030] In some embodiments, forming one or more conductive vias by providing a conductive material layer on the inner surface of the vias includes filling the inner surface of the vias with conductive metal by electroplating.

[0031] In some embodiments, forming a three-dimensional waveguide network in the glass substrate includes: irradiating a preset position of the glass substrate with a femtosecond laser to increase the refractive index of the preset position of the glass substrate, wherein the preset position is the location where the three-dimensional waveguide network structure is formed.

[0032] A sixth aspect of this disclosure provides another method for manufacturing an adapter board for optical chip packaging, comprising: providing a glass substrate and forming one or more first conductive vias in the glass substrate; distributing an electrical interconnect structure on a first surface of the glass substrate, wherein the electrical interconnect structure includes one or more wiring layers and a covering layer covering the one or more wiring layers, the covering layer being a dielectric material, the one or more wiring layers being used for electrically interconnecting a plurality of electronic chips packaged above the adapter board; and forming one or more first conductive structures penetrating the electrical interconnect structure in the electrical interconnect structure, which are electrically connected to the one or more first conductive vias respectively.

[0033] In some embodiments, configuring an electrical interconnect structure on the first surface of the glass substrate includes: configuring a first wiring layer on the first surface of the glass substrate; forming a first silicon nitride layer around the first wiring layer; and covering the first silicon nitride layer with a first silicon oxide layer.

[0034] In some embodiments, the electrical interconnect structure disposed on the first surface of the glass substrate further includes: disposing a second wiring layer on the first surface of the first silicon oxide layer; forming a second silicon nitride layer around the second wiring layer; and covering the second silicon nitride layer with a second silicon oxide layer.

[0035] In some embodiments, configuring an electrical interconnect structure on the first surface of the glass substrate further includes forming a second conductive structure between the first wiring layer and the second wiring layer to electrically connect the first wiring layer and the second wiring layer.

[0036] In some embodiments, the manufacturing method of the above-mentioned adapter board further includes: disposing an optical waveguide structure on the surface of the electrical interconnect structure away from the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a surrounding layer surrounding the one or more optical waveguides, the one or more optical waveguides being used for optical interconnection of a plurality of optical wafers packaged on the adapter board, and having a refractive index greater than that of the surrounding layer; and forming one or more third conductive structures penetrating the optical waveguide structure in the optical waveguide structure, and electrically connecting them to the one or more first conductive structures respectively.

[0037] In some embodiments, the above-mentioned one or more optical waveguides are silicon nitride optical waveguides, and the material of the above-mentioned cladding layer is silicon dioxide.

[0038] In some embodiments, the method of manufacturing the adapter plate further includes: disposing a dielectric layer on the second surface of the glass substrate; forming one or more fourth conductive structures penetrating the dielectric layer in the dielectric layer and electrically connecting them to the one or more first conductive vias respectively; and disposing one or more conductive bumps on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more fourth conductive structures respectively.

[0039] In some embodiments, forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias by disposing a conductive material layer on the inner surface of the one or more vias.

[0040] In some embodiments, forming one or more conductive vias by providing a conductive material layer on the inner surface of the vias includes filling the inner surface of the vias with conductive metal by electroplating.

[0041] A seventh aspect of this disclosure provides an optical chip packaging structure, which includes an adapter board as described above, and a plurality of optical chips disposed on the adapter board, wherein the adapter board is used to perform optical interconnection on the plurality of optical chips disposed on the adapter board.

[0042] In some embodiments, the above-mentioned optical wafer packaging structure further includes: one or more electrical wafers disposed on the plurality of optical wafers; the optical wafer includes one or more interconnect structures, the interconnect structure includes a via penetrating the optical wafer and a conductive material filling the via; the one or more interconnect structures are electrically connected to the one or more first conductive structures or electrical interconnect structures on the adapter board respectively.

[0043] The eighth aspect of this disclosure provides an optical chip packaging structure, including: an adapter plate including one or more first optical waveguides embedded therein; and a plurality of optical chips, each optical chip including one or more second optical waveguides embedded therein, wherein the plurality of optical chips are attached to different positions on the upper surface of the adapter plate and are optically interconnected through the one or more first optical waveguides, each of the first optical waveguides includes a first optical coupling portion, each of the second optical waveguides includes a second optical coupling portion, and the first optical coupling portion and the second optical coupling portion are stacked in a direction perpendicular to the upper surface of the adapter plate and spaced apart by a predetermined distance, such that the first optical coupling portion and the second optical coupling portion achieve thermally insulating optical coupling.

[0044] In some embodiments, the first optical coupling part and the second optical coupling part are respectively conical in shape.

[0045] In some embodiments, the first optical coupling part and the second optical coupling part respectively have a shape formed by two tapered shapes of different sizes connected in series.

[0046] In some embodiments, the predetermined distance is less than or equal to 600 nm.

[0047] In some embodiments, the optical chip packaging structure further includes: a plurality of electrical chips disposed on a plurality of first optical chips among the plurality of optical chips, wherein each first optical chip has one or more first electrical connectors on its upper surface, and each electrical chip has one or more second electrical connectors on its lower surface, and the one or more first electrical connectors are respectively electrically connected to the one or more second electrical connectors.

[0048] In some embodiments, the first optical wafer further includes one or more second conductive vias passing through it, and the one or more second conductive vias are electrically connected to one or more conductive structures in the adapter plate, respectively.

[0049] In some embodiments, the first optical chip and the electrical chip are directly bonded; or the first optical chip and the electrical chip are bonded together through a flip-chip.

[0050] In some embodiments, the plurality of optical wafers are split optical wafers obtained after dividing photonic wafers. They are spaced apart from each other on the upper surface of the adapter plate and the gaps between them are filled by a molding material. A dielectric layer for blocking the outward transmission of light in the adapter plate is disposed between the molding material and the upper surface of the adapter plate.

[0051] In some embodiments, the above-mentioned plurality of optical wafers are multiple undivided optical wafers in the same photonic wafer.

[0052] In some embodiments, the plurality of optical chips are undivided optical chips in the same photonic wafer, the plurality of optical chips have a plurality of first optical chips, each first optical chip is disposed on an electrical chip, the plurality of electrical chips on the plurality of first optical chips are a plurality of undivided electrical chips in the same electronic wafer, and the photonic wafer is directly bonded to the electronic wafer.

[0053] In some embodiments, all of the above-mentioned optical chips are provided with corresponding electrical chips, and the corresponding electrical chips on all optical chips are multiple undivided electrical chips in the same electronic wafer, and the above-mentioned optical chips have the same structure, and the above-mentioned electrical chips also have the same structure.

[0054] In some embodiments, the adapter board is the adapter board as described above, and the one or more first optical waveguides are one or more layers of optical waveguides in the optical waveguide structure of the adapter board as described above.

[0055] In some embodiments, the adapter board is the adapter board as described above, and the one or more first optical waveguides are the three-dimensional waveguide network in the adapter board as described above and the coupled optical waveguides covering the optical input and output ports of the three-dimensional waveguide network.

[0056] A ninth aspect of this disclosure provides a computing accelerator, comprising: one or more light sources disposed on a first surface of the adapter plate in the aforementioned optical wafer package structure and configured to provide light waves to the computing accelerator; one or more computing units implemented by the aforementioned optical wafer in the aforementioned optical wafer package structure, or implemented by the aforementioned optical wafer and electrical wafer in the aforementioned optical wafer package structure, or implemented by the aforementioned electrical wafer in the aforementioned optical wafer package structure, and configured to perform computing functions; and one or more memory units implemented by the aforementioned electrical wafer in the aforementioned optical wafer package structure and configured to perform memory functions.

[0057] In some embodiments, the adapter board is the adapter board as described above.

[0058] A ninth aspect of this disclosure provides a computing accelerator, comprising: one or more edge optical couplers configured to optically interconnect the computing accelerator with other devices; one or more light sources configured to provide light waves to the computing accelerator, the light waves being coupled to the one or more edge optical couplers through a light guide structure; one or more computing units implemented by the optical wafer in the aforementioned optical wafer package structure, or by the optical wafer and electrical wafer in the aforementioned optical wafer package structure, or by the electrical wafer in the aforementioned optical wafer package structure, and configured to perform computing functions; and one or more memory units implemented by the electrical wafer in the aforementioned optical wafer package structure, and configured to perform memory functions.

[0059] In some embodiments, each computing unit and the corresponding memory unit are implemented by each optical chip and the corresponding electrical chip in the optical chip packaging structure as described above, serving as a computing-memory unit.

[0060] In some embodiments, the adapter board in the above-described optical wafer packaging structure is the adapter board as described above.

[0061] In some embodiments, the computing accelerator further includes a plurality of high bandwidth memory (HBM) chips stacked on the optical chip in the optical chip package structure, which are configured to perform memory computing functions.

[0062] The tenth aspect of this disclosure provides a method for manufacturing an optical chip package structure, comprising: providing an adapter plate including one or more first optical waveguides embedded therein, each of the first optical waveguides including a first optical coupling portion; and attaching a plurality of optical chips to different positions on the upper surface of the adapter plate, each optical chip including one or more second optical waveguides embedded therein, each of the second optical waveguides including a second optical coupling portion, wherein the first optical coupling portion and the second optical coupling portion are stacked in a direction perpendicular to the upper surface of the adapter plate and spaced apart by a predetermined distance, such that the first optical coupling portion and the second optical coupling portion achieve thermally adiabatic optical coupling, and the plurality of optical chips are optically interconnected through the one or more first optical waveguides.

[0063] In some embodiments, the first optical coupling part and the second optical coupling part are respectively conical in shape.

[0064] In some embodiments, the first optical coupling part and the second optical coupling part respectively have a shape formed by two tapered shapes of different sizes connected in series.

[0065] In some embodiments, the predetermined distance is less than or equal to 600 nm.

[0066] In some embodiments, before attaching the plurality of optical wafers to different positions on the upper surface of the adapter plate, the method further includes: disposing an electrical wafer on a first optical wafer among the plurality of optical wafers, such that the first optical wafer and the electrical wafer thereon form an electron-photon hybrid wafer, wherein the upper surface of the first optical wafer has one or more first electrical connectors, the lower surface of the electrical wafer has one or more second electrical connectors, and the one or more first electrical connectors are respectively electrically connected to the one or more second electrical connectors.

[0067] In some embodiments, configuring an electronic wafer on a first optical wafer among the plurality of optical wafers includes: preparing a photonic wafer and an electronic wafer, wherein the photonic wafer includes a plurality of first optical wafers and the electronic wafer includes a plurality of electronic wafers; directly bonding the electronic wafer to the photonic wafer, such that the plurality of first optical wafers are bonded to the plurality of electronic wafers to obtain an electronic-photonic hybrid wafer; removing the substrate of the photonic wafer; and dicing the electronic-photonic hybrid wafer into a plurality of electronic-photonic hybrid wafers.

[0068] In some embodiments, configuring an electronic wafer on a first optical wafer among the plurality of optical wafers includes: preparing a photonic wafer and an electronic wafer, wherein the photonic wafer includes the plurality of optical wafers and the electronic wafer includes the plurality of electronic wafers; dicing the electronic wafer into the plurality of electronic wafers; directly bonding or flip-chip bonding one or more of the plurality of electronic wafers to the first optical wafer among the photonic wafers to obtain an electronic-photonic hybrid wafer; filling the gaps on the photonic wafer not occupied by the electronic wafers with a molding material; removing the substrate of the photonic wafer; and dicing the electronic-photonic hybrid wafer into the electronic-photonic hybrid wafers.

[0069] In some embodiments, the method further includes: after removing the substrate of the photonic wafer, and before dicing the electron-photonic hybrid wafer into the electron-photonic hybrid wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness.

[0070] In some embodiments, the method further includes: after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer, forming a connecting waveguide on the surface of the photonic wafer away from the electronic wafer, wherein the connecting waveguide and the second optical coupling portion of the second optical waveguide and the first optical coupling portion of the first waveguide are stacked and spaced apart in the vertical direction of the lower surface of the photonic wafer; and covering the connecting waveguide with a dielectric to coat the connecting waveguide. In some embodiments, the method further includes: after preparing the photonic wafer, forming one or more second conductive holes in the photonic wafer; and after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness, so that the one or more second conductive holes are vertically connected to form one or more second conductive vias.

[0071] In some embodiments, attaching the plurality of optical wafers to different positions on the upper surface of the adapter plate further includes: electrically connecting the one or more second conductive vias to one or more conductive structures in the adapter plate respectively.

[0072] In some embodiments, the plurality of electron-photon hybrid wafers are spaced apart from each other on the upper surface of the adapter plate, and the method further includes: forming a dielectric layer on the upper surface of the adapter plate and in the gaps between the plurality of electron-photon hybrid wafers for blocking the outward transmission of light in the adapter plate; and filling the dielectric layer and the gaps between the electron-photon wafers with a molding material.

[0073] In some embodiments, configuring an electronic wafer on a first optical wafer among the plurality of optical wafers includes: preparing a photonic wafer and an electronic wafer, wherein the photonic wafer includes a plurality of first optical wafers and the electronic wafer includes a plurality of electronic wafers, and directly bonding the electronic wafer to the photonic wafer, such that the plurality of first optical wafers are bonded to the plurality of electronic wafers to obtain an electronic-photonic hybrid wafer; and attaching the plurality of optical wafers to different positions on the upper surface of the adapter plate includes: directly bonding the electronic-photonic hybrid wafer to the upper surface of the adapter plate.

[0074] In some embodiments, the adapter board is an adapter board manufactured by the method described above, and the one or more first optical waveguides are one or more layers of optical waveguides in the optical waveguide structure of the adapter board manufactured by the method described above.

[0075] In some embodiments, the adapter board is an adapter board manufactured by the method described above, and the one or more first optical waveguides are a three-dimensional waveguide network in the adapter board manufactured by the method described above and a coupled optical waveguide covering the optical input / output port of the three-dimensional waveguide network.

Implementation Method

[0077] Embodiments of the present disclosure will now be described in more detail with reference to the drawings. While some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0078] It should be understood that the various steps described in the method embodiments disclosed herein may be performed in different sequences and / or concurrently. Furthermore, the method embodiments may include other steps and / or omit certain steps.

[0079] Embodiments of this disclosure provide an adapter board for optical chip packaging. Figure 1 shows a cross-sectional view of the adapter board 100 for optical chip packaging according to an embodiment of this disclosure. Figure 5 shows a process flow diagram of the manufacturing method of the adapter board 100 according to an embodiment of this disclosure. To describe this disclosure more clearly, the specific structure and manufacturing method of the adapter board 100 will be described below in conjunction with Figures 1 and 5.

[0080] As shown in Figure 1, the adapter board 100 can be divided into three layers in its overall structure, which are, from bottom to top, dielectric layer 103, glass substrate 101 and optical waveguide structure 102.

[0081] The glass substrate 101 is typically made of silicon dioxide and includes one or more conductive vias. For ease of description, only one conductive via 101-1 is shown in Figure 1. As shown, the conductive via 101-1 includes a via penetrating the glass substrate 101 and a conductive material filled within the via (indicated by a horizontal shading in the figure).

[0082] The optical waveguide structure 102 is disposed on a first surface (the upper surface shown in the figure) of the glass substrate 101. Typically, the optical waveguide structure 102 includes one or more optical waveguides and a coating layer covering one or more optical waveguides. In Figure 1, for ease of description, only one optical waveguide 102-1 and the coating layer 102-2 covering this optical waveguide are shown. When multiple optical chips are packaged on the adapter board 100, the one or more optical waveguides in the optical waveguide structure 102 can be used for optical interconnection of the multiple optical chips packaged thereon. The refractive index of the one or more optical waveguides in the optical waveguide structure 102 is greater than the refractive index of the coating layer 102-2 and the glass substrate 101. For example, the one or more optical waveguides can be silicon nitride optical waveguides with a higher refractive index, and the materials of the coating layer 102-2 and the glass substrate 101 can be silicon dioxide with a relatively lower refractive index.

[0083] As shown in Figure 1, the optical waveguide structure 102 also includes one or more first conductive structures 102-3 penetrating the optical waveguide structure, which are electrically connected to the one or more conductive vias 101-1 in the glass substrate. The one or more first conductive structures 102-3 shown can be used to make vertical electrical connections to optical wafers or electronic wafers packaged on the adapter board. The first conductive structure 102-3 can be a plug structure, such as a copper plug, and may also include other metal materials or conductive materials.

[0084] A dielectric layer 103 is disposed on a second surface (the lower surface shown in the figure) of the glass substrate 101, and includes one or more second conductive structures penetrating the dielectric layer. One or more conductive bumps 104 are disposed on the surface of the dielectric layer 103 away from the glass substrate 101 (i.e., the lower surface shown in the figure), and are electrically connected to the one or more second conductive structures respectively. For example, depending on the electrical connection requirements, the second conductive structure may include a redistribution layer 103-3 as shown in the figure and a conductive via structure 103-2 below it. The conductive bumps 104 may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) connectors, solder balls, metal pillars, microbumps, etc. The conductive bumps 104 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive bumps 104 may be formed by first forming a solder layer using common methods such as evaporation, electroplating, or printing. In some embodiments, the conductive bump 104 is a metal pillar, such as a copper pillar, formed by sputtering, electroplating, chemical plating, etc.

[0085] It should be noted that the adapter board 100 may also exclude the dielectric layer 103 and the conductive bumps 104.

[0086] The specific structure of the adapter board 100 for optical chip packaging has been described above with reference to Figure 1. The manufacturing method of the adapter board 100 will be described in detail below with reference to Figure 5.

[0087] As shown in Figure 5, in step (a), a glass substrate 101 is first provided, and one or more conductive vias 101-1 are formed in the glass substrate 101. In some embodiments, the conductive vias 101-1 can be formed in the glass substrate 101 by etching and electroplating. For example, one or more vias can be formed first by laser drilling in the glass substrate, and then a conductive material layer can be deposited on the inner surface of the one or more vias to form the aforementioned one or more conductive vias. Specifically, for example, a bottom-up electroplating method can be used to fill the inner surface of one or more vias with conductive metal to form conductive vias.

[0088] After forming the conductive via 101-1 in the glass substrate 101, in steps (b)-(c), an optical waveguide structure can be disposed on the first surface of the glass substrate 101 (the upper surface shown in the figure). For example, as shown in (b)-(c), the optical waveguide structure includes one or more optical waveguides 102-1 and a coating layer 102-2 covering the one or more optical waveguides. For ease of description, only an example of a single-layer optical waveguide is shown in Figure 5.

[0089] Specifically, in step (b), for example, wafer-level nanoimprint optical lithography can be used to form an optical waveguide 102-1 on the first surface of the glass substrate 101.

[0090] It should be noted that, compared with the prior art nanoimprint technology, the wafer-level nanoimprint optical lithography technology disclosed herein has made the following improvements. To achieve wafer-level waveguide wiring without the limitations of typical step-and-repeat optical lithography's marker size, this disclosure uses wafer-level maskless optical lithography techniques, such as electron beam or laser writing. For example, an imprint master can first be fabricated using an oxide-nitride stack, which is patterned using electron beam optical lithography. Then, by using this imprint master, a step-and-repeat operation is performed to generate a polymer-based nanoimprint (e.g., PDMS, polydimethylsiloxane) on the polymer. It should be noted that this nanoimprint is wafer-level; that is, through the step-and-repeat operation described above, the entire optical waveguide pattern is completely and coherently formed in the same nanoimprint. Compared to traditional fabless imprinting, using a generated wafer-level nanoimprint on a nitride-deposited glass wafer allows for the one-time transfer of photoresist patterns onto the glass wafer, facilitating the formation of a monolithic nitride waveguide. Traditional fabless imprinting requires multiple imprinting processes for waveguide splicing, which can easily lead to misalignment issues, affecting the quality of the optical waveguide and resulting in optical signal loss.

[0091] Through the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, and no waveguide splicing is required in the middle, which can minimize the loss of optical signal.

[0092] Then, in step (c), a coating material is deposited over the optical waveguide 102-1 to form a coating layer 102-2. Depending on specific needs, steps (b)-(c) above can be repeated to form an optical waveguide structure with multiple optical waveguides. In addition, in step (c), one or more first conductive structures 102-3 penetrating the optical waveguide structure can be formed in the coating layer 102-2 and electrically connected to one or more conductive vias 101-1 in the glass substrate 101, respectively.

[0093] As described above, the refractive index of the optical waveguide 102-1 is greater than that of the cladding layer 102-2 and the glass substrate 101. For example, the optical waveguide 102-1 can be a silicon nitride optical waveguide with a higher refractive index, and the materials of the cladding layer 102-2 and the glass substrate 101 can be silicon dioxide with a relatively lower refractive index.

[0094] Optionally, the method of manufacturing the adapter plate 100 may further include: disposing a dielectric layer 103 on a second surface of a glass substrate 101, forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer 103 and electrically connecting them to one or more conductive vias 101-1 respectively, and disposing one or more conductive bumps 104 on the surface of the dielectric layer 103 away from the glass substrate.

[0095] Steps (d)-(f) in Figure 5 show exemplary detailed steps of the above processing flow.

[0096] For example, in step (d), a redistribution layer 103-3 can be formed on the bottom surface of the glass substrate 101 for electrical connection. Next, in step (e), a dielectric layer 103 is disposed on the bottom surface of the glass substrate 101, covering a portion of the redistribution layer 103-3 formed in (d). A notch 103-4 corresponding to the redistribution layer 103-3 and the conductive via 101-1 is formed in the dielectric layer 103. In step (f), a conductive via structure 103-2 is formed by filling the notch 103-4 with conductive material, thereby electrically connecting the conductive via structure 103-2 to the redistribution layer 103-3 and the conductive via 101-1 in the glass substrate. In this case, the conductive via structure 103-2 and the redistribution layer 103-3 together constitute the aforementioned second conductive structure, which penetrates the dielectric layer 103 and is electrically connected to the conductive via 101-1 in the glass substrate 101.

[0097] In step (f), one or more conductive bumps 104 are disposed on the surface of the dielectric layer 103 away from the glass substrate, and the conductive bumps 104 are electrically connected to the second conductive structure (i.e., the conductive hole structure 103-2 and the re-layer 103-3).

[0098] Thus far, the specific structure and manufacturing method of the adapter board 100 for the first example of optical chip packaging have been described in conjunction with Figures 1 and 5. By configuring an optical waveguide structure on the surface of a glass substrate, optical interconnection can be achieved between optical chips packaged on this adapter board, thus avoiding the cost and process difficulty issues associated with manufacturing silicon adapter boards for embedded TSVs. Furthermore, since the optical waveguide is formed in the glass substrate using the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, eliminating the need for waveguide splicing in the middle and minimizing optical signal loss.

[0099] The specific structure and manufacturing method of another example of the adapter board for optical wafer packaging will be described below with reference to Figures 2 and 6. Figure 2 shows a cross-sectional view of the adapter board 200 for optical wafer packaging according to an embodiment of the present disclosure. Figure 6 shows a process flow diagram of the manufacturing method of the adapter board 200 according to an embodiment of the present disclosure.

[0100] As shown in Figure 2, the adapter board 200 can be similarly divided into three layers in its overall structure, from bottom to top: dielectric layer 203, glass substrate 201, and optical coupling structure 202.

[0101] The glass substrate 201 is typically made of silicon dioxide and includes one or more conductive vias. For ease of description, only one conductive via 201-1 is shown in Figure 2. As shown, the conductive via 201-1 includes a via penetrating the glass substrate 201 and a conductive material filled within the via (indicated by a horizontal shading in the figure).

[0102] Furthermore, the glass substrate 201 also includes a three-dimensional waveguide network 201-2 (as shown in the curve), used for optical interconnection of multiple optical chips packaged on the adapter board 200. The three-dimensional waveguide network 201-2 is constructed by inducing local glass within the glass substrate 201 to increase the refractive index of the local glass, and it has a three-dimensional network structure formed by multiple pathways distributed throughout the interior of the glass substrate 201. For example, an embedded three-dimensional waveguide network can be created inside the glass substrate using an ultrafast (e.g., femtosecond) laser writing process.

[0103] An optical coupling structure 202 is disposed on a first surface (e.g., the upper surface) of a glass substrate 201. As shown, the optical coupling structure 202 includes a coupling optical waveguide 202-1 covering the optical input / output port of a three-dimensional waveguide network 201-2, and a coating layer 202-2 covering the coupling optical waveguide 202-1. Furthermore, the optical coupling structure 202 also includes one or more first conductive structures 202-3 penetrating the optical coupling structure, which are electrically connected to one or more conductive vias 201-1 in the glass substrate 201.

[0104] It should be noted that the refractive index of the coupling optical waveguide 202-1 can be lower than the refractive index of the three-dimensional waveguide network 201-2, but higher than the refractive index of the cladding layer 202-2. For example, the coupling optical waveguide 202-1 can be a silicon nitride optical waveguide, and the material of the cladding layer 202-2 can be silicon dioxide. Additionally, it should be noted that although the adapter plate 200 includes an embedded optical waveguide 202-1 similar to that in the adapter plate 100 shown in Figure 1, their functions are different. In the adapter plate 100 shown in Figure 1, the optical waveguide 102-1 in the optical waveguide structure 102 is used for optical interconnection between different optical wafers. However, in the adapter plate 200 shown in Figure 2, the coupling optical waveguide 202-1 in the optical coupling structure 202 is used for optical "coupling," which can improve the optical coupling efficiency between the three-dimensional waveguide network and the optical wafer.

[0105] Similar to the adapter board 100, the dielectric layer 203 in the adapter board 200 is disposed on the second surface (lower surface as shown in the figure) of the glass substrate 201, and includes one or more second conductive structures penetrating the dielectric layer. One or more conductive bumps 204 are disposed on the surface of the dielectric layer 203 away from the glass substrate 201 (i.e., the lower surface as shown in the figure), and are electrically connected to the one or more second conductive structures respectively. Depending on the electrical connection requirements, the second conductive structure may include the redistribution layer 203-3 as shown in the figure and the conductive via structure 203-2 below it. The conductive bumps 204 may be controlled collapse wafer interconnect (C4) bumps, ball grid array (BGA) connectors, solder balls, metal pillars, microbumps, etc., which are similar to the conductive bump 104 described in Figure 1, and will not be described again here.

[0106] It should be noted that the adapter board 200 may also exclude the dielectric layer 203 and the conductive bumps 204.

[0107] The specific structure of the adapter board 200 for optical chip packaging has been described above with reference to Figure 2. The manufacturing method of the adapter board 200 will be explained in detail below with reference to Figure 6.

[0108] As shown in Figure 6, in step (a), a glass substrate 201 is first provided, and a three-dimensional waveguide network 201-2 is formed within the glass substrate 201 for optical interconnection of multiple optical wafers packaged on an adapter board. In some examples, an ultrafast (e.g., femtosecond) laser writing process can be used to create an embedded three-dimensional waveguide network inside the glass substrate. For example, a femtosecond laser can be used to irradiate a predetermined position on the glass substrate 201 to increase the refractive index of the predetermined position on the glass substrate 201, thereby forming the three-dimensional waveguide network 201-2. For example, the predetermined position may be the location where the three-dimensional waveguide network structure is formed.

[0109] Then, in step (b), one or more conductive vias 201-1 are formed in the glass substrate 201. In some embodiments, the conductive vias 201-1 can be formed in the glass substrate 201 by etching and electroplating. For example, one or more vias can be formed first by laser drilling in the glass substrate, and then a conductive material layer can be formed on the inner surface of the one or more vias to form the aforementioned one or more conductive vias. Specifically, for example, a bottom-up electroplating method can be used to fill the inner surface of one or more vias with conductive metal to form conductive vias.

[0110] After forming conductive vias 201-1 in the glass substrate 201, in steps (c)-(d), an optical coupling structure can be configured on the first surface of the glass substrate 201 (the upper surface as shown in the figure). For example, as shown in the figure, the optical coupling structure includes a coupling optical waveguide 202-1 and a coating layer 202-2 covering the coupling optical waveguide. Specifically, in step (c), optical lithography can be used to form the coupling optical waveguide 202-1 on the first surface of the glass substrate 201, so that it covers the optical input / output port of the three-dimensional waveguide network 201-2. Then, in step (d), a coating layer material is deposited over the coupling optical waveguide 202-1 to form the coating layer 202-2. In addition, in step (d), one or more first conductive structures 202-3 penetrating the optical coupling structure can be formed in the coating layer 202-2, and electrically connected to one or more conductive vias 201-1 in the glass substrate 201, respectively.

[0111] It should be noted that the refractive index of the coupling optical waveguide 202-1 can be greater than that of the cladding layer 202-2 and the glass substrate 201. For example, the coupling optical waveguide 202-1 can be a silicon nitride optical waveguide with a higher refractive index, and the materials of the cladding layer 202-2 and the glass substrate 201 can be silicon dioxide with a relatively lower refractive index.

[0112] Optionally, the method of manufacturing the adapter plate 200 may further include: disposing a dielectric layer 203 on a second surface of a glass substrate 201, forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer 203 and electrically connecting them to one or more conductive vias 201-1 respectively, and disposing one or more conductive bumps 204 on the surface of the dielectric layer 203 away from the glass substrate.

[0113] Steps (e)-(g) in Figure 6 show a detailed example of the above processing flow.

[0114] For example, in step (e), a redistribution layer 203-3 can be formed on the bottom surface of the glass substrate 201 for electrical connection. Next, in step (f), a dielectric layer 203 is disposed on the bottom surface of the glass substrate 201, covering a portion of the redistribution layer 203-3 formed in (e). A notch 203-4 corresponding to the redistribution layer 203-3 and the conductive via 201-1 is formed in the dielectric layer 203. In step (g), a conductive via structure 203-2 is formed by filling the notch 203-4 with conductive material, thereby electrically connecting the conductive via structure 203-2 to the redistribution layer 203-3 and the conductive via 201-1 in the glass substrate. In this case, the conductive via structure 203-2 and the redistribution layer 203-3 together constitute the aforementioned second conductive structure, which penetrates the dielectric layer 203 and is electrically connected to the conductive via 201-1 in the glass substrate 201.

[0115] In step (g), one or more conductive bumps 204 are disposed on the surface of the dielectric layer 203 away from the glass substrate, and the conductive bumps 204 are electrically connected to the second conductive structure (i.e., the conductive hole structure 203-2 and the re-layer 203-3).

[0116] Thus far, the specific structure and manufacturing method of the adapter plate 200 in the second example of optical chip packaging have been described with reference to Figures 2 and 6. The adapter plate 200 interconnects multiple optical chips packaged on top of it by forming a three-dimensional optical waveguide network inside the glass substrate. Therefore, a richer and more efficient three-dimensional optical waveguide path can be formed without increasing the thickness of the adapter plate, effectively compressing the volume of the optical chip package. Furthermore, since silicon nitride coupled optical waveguides as described above are also configured at the optical input and output of the three-dimensional optical waveguide network, the optical coupling efficiency between the optical chip and the adapter plate can be greatly improved.

[0117] The specific structure and manufacturing method of another example of the adapter board for optical wafer packaging will be described below with reference to Figures 3 and 7A. Figure 3 shows a cross-sectional view of the adapter board 300 for optical wafer packaging according to an embodiment of the present disclosure. Figure 7A shows a process flow diagram of the manufacturing method of the adapter board 300 according to an embodiment of the present disclosure.

[0118] As shown in Figure 3, the adapter board 300 can be divided into three layers in its overall structure, which are, from bottom to top, dielectric layer 303, glass substrate 301 and electrical interconnection structure 302.

[0119] Similarly, the glass substrate 301 is typically made of silicon dioxide and includes one or more conductive vias. For ease of description, only one conductive via 301-1 is shown in Figure 3. As shown, the conductive via 301-1 includes a via penetrating the glass substrate 301 and a conductive material filled within the via (indicated by horizontal shading in the figure).

[0120] An electrical interconnect structure 302 is disposed on a first surface (the upper surface shown in the figure) of a glass substrate 301. In some examples, the electrical interconnect structure 302 may include one or more wiring layers 302-1a, 302-1b, 302-1c and a covering layer 302-2 covering one or more wiring layers. For example, the covering layer 302-2 may be a dielectric material, and one or more wiring layers 302-1a, 302-1b, 302-1c are used to electrically interconnect multiple electrical wafers on an optical wafer packaged on an adapter board. The electrical wafers may be vertically packaged with the optical wafer, that is, the electrical wafers are packaged on the optical wafer, and the electrical wafers may be electrically connected to the wiring layers through conductive vias in the optical wafer to achieve electrical interconnection of the electrical wafers. In addition, the optical wafers disposed on the adapter board may be active optical wafers, and the active optical wafers may also be electrically connected to each other through the electrical interconnect structure 302.

[0121] Figure 3 shows an example of an electrical interconnect structure 302 having three wiring layers (302-1a, 302-1b, 302-1c). As shown, each wiring layer is covered by its respective covering layer. For example, wiring layer 302-1a is covered by a multilayer structure formed by alternating stacks of silicon nitride layer 302-2a and silicon dioxide layer 302-2b. Wiring layers 302-1b and 302-1c are similarly covered by a multilayer structure formed by alternating stacks of silicon nitride layer and silicon dioxide layer. It should be understood that the three wiring layers shown in Figure 3 are merely exemplary, and more (e.g., four or more layers) or fewer (e.g., two or one layer) wiring layers can be selected as needed.

[0122] In addition, as shown in the figure, the electrical interconnect structure 302 also includes one or more first conductive structures 302-3 that penetrate the electrical interconnect structure and are electrically connected to one or more conductive vias 301-1 in the glass substrate.

[0123] Figure 3 also shows a second conductive structure 302-4 for electrically connecting at least two wiring layers in a multilayer wiring layer. The second conductive structure 302-4 may be formed using a method or material similar to the first conductive structure 302-3, for example, it may be a conductive via or a copper plug, or it may include other metallic or conductive materials.

[0124] A dielectric layer 303 is disposed on a second surface (the lower surface shown in the figure) of the glass substrate 301, and includes one or more second conductive structures penetrating the dielectric layer. One or more conductive bumps 305 are disposed on the surface of the dielectric layer 303 away from the glass substrate 301 (i.e., the lower surface shown in the figure), and are electrically connected to the one or more second conductive structures respectively. Depending on the electrical connection requirements, the second conductive structure may include a redistribution layer 303-3 as shown in the figure and a conductive via structure 303-2 below it. The conductive bumps 305 may be controlled collapse wafer interconnect (C4) bumps, ball grid array (BGA) connectors, solder balls, metal pillars, microbumps, etc. The conductive bumps 305 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive bumps 305 may be formed by first forming a solder layer by commonly used methods such as evaporation, electroplating, or printing. In some embodiments, the conductive bump 305 is a metal pillar, such as a copper pillar, formed by sputtering, electroplating, electroless plating, etc.

[0125] It should be noted that the adapter board 300 may also exclude the dielectric layer 303 and the conductive bumps 305.

[0126] The specific structure of the adapter board 300 for optical chip packaging has been described above with reference to Figure 3. The manufacturing method of the adapter board 300 will be described in detail below with reference to Figure 7A.

[0127] As shown in Figure 7A, in step (a), a glass substrate 301 is first provided, and one or more conductive vias 301-1 are formed in the glass substrate 301. In some embodiments, the conductive vias 301-1 can be formed in the glass substrate 301 by etching and electroplating. For example, one or more vias can be formed first by laser drilling in the glass substrate, and then a conductive material layer can be deposited on the inner surface of the one or more vias to form the aforementioned one or more conductive vias. Specifically, for example, a bottom-up electroplating method can be used to fill the inner surface of one or more vias with conductive metal to form conductive vias.

[0128] In step (e), an electrical interconnect structure 302 is disposed on a first surface of the glass substrate 301 (i.e., the upper surface as shown). As shown, the electrical interconnect structure 302 includes one or more wiring layers (302-1a, 302-1b, 302-1c) and a coating layer covering one or more wiring layers. For example, the coating layer may be a dielectric material, and the one or more wiring layers (302-1a, 302-1b, 302-1c) are used to electrically interconnect multiple electrical wafers above the optical wafer packaged on the adapter board.

[0129] Figure 7A shows an example of an electrical interconnect structure 302 having three wiring layers (302-1a, 302-1b, 302-1c). As shown, each wiring layer is covered by its respective covering layer. For example, wiring layer 302-1a is covered by a multilayer structure formed by alternating stacks of silicon nitride layer 302-2a and silicon dioxide layer 302-2b. Wiring layers 302-1b and 302-1c are similarly covered by a multilayer structure formed by alternating stacks of silicon nitride layer and silicon dioxide layer. It should be understood that the three wiring layers shown in Figure 3 are merely exemplary, and more (e.g., four or more layers) or fewer (e.g., two or one layer) wiring layers can be selected as needed.

[0130] Specifically, taking (e) in Figure 7A as an example, configuring the electrical interconnect structure 302 on the first surface of the glass substrate 301 may include the following specific steps: First, a first wiring layer (wiring layer 302-1a) is configured on the upper surface of the glass substrate 301; then, a first silicon nitride layer (silicon nitride layer 302-2a) is formed around the first wiring layer (wiring layer 302-1a). The thickness of the first wiring layer (wiring layer 302-2a) is less than the thickness of the first wiring layer (wiring layer 302-1a). Next, a first silicon dioxide layer (silicon dioxide layer 302-2b) is covered on the first silicon nitride layer (silicon nitride layer 302-2a), such that the total thickness of the first silicon nitride layer (silicon nitride layer 302-2a) plus the first silicon dioxide layer (silicon dioxide layer 302-2b) is equal to the thickness of the first wiring layer (wiring layer 302-1a). Then, depending on specific needs, the above steps can be repeated to sequentially arrange the second wiring layer (wiring layer 302-1b) on the first silicon dioxide layer (silicon dioxide layer 302-2b), form a second silicon nitride layer around the second wiring layer (wiring layer 302-1b), cover the second silicon dioxide layer on the second silicon nitride layer, and so on, thereby forming an electrical interconnect structure with multiple wiring layers.

[0131] Furthermore, the arrangement of the electrical interconnect structure 302 on the first surface of the glass substrate 301 may further include: forming a second conductive structure 302-4 between the first wiring layer (wiring layer 302-1a) and the second wiring layer (wiring layer 302-1b) to electrically connect the first wiring layer (wiring layer 302-1a) and the second wiring layer (wiring layer 302-1b). For example, one or more vias may be formed first by laser drilling at the location of the wiring layer in the electrical interconnect structure 302, and then a conductive material layer may be disposed on the inner surface of the one or more vias to form one or more second conductive structures 302-4. Specifically, for example, a bottom-up electroplating method may be used to fill the inner surface of one or more vias with conductive metal to form the second conductive structure 302-4. Furthermore, as shown in the figure, when the electrical interconnection structure 302 includes three wiring layers (302-1a, 302-1b, 302-1c), the second conductive structure 302-4 also exists between the second wiring layer (wiring layer 302-1b) and the third wiring layer (wiring layer 302-1c), and the second wiring layer (wiring layer 302-1b) and the third wiring layer (wiring layer 302-1c) are also electrically connected.

[0132] Furthermore, the arrangement of the electrical interconnection structure 302 on the first surface of the glass substrate 301 may also include: forming one or more first conductive structures 302-3 through the electrical interconnection structure in the electrical interconnection structure 302, which are electrically connected to one or more first conductive vias 301-1 in the glass substrate 301 respectively.

[0133] Optionally, in some embodiments, the method of manufacturing the adapter plate 300 may further include: disposing a dielectric layer 303 on a second surface of a glass substrate 301, forming one or more fourth conductive structures penetrating the dielectric layer in the dielectric layer 303 and electrically connecting them to one or more conductive vias 301-1 respectively, and disposing one or more conductive bumps 305 on the surface of the dielectric layer 303 away from the glass substrate.

[0134] Steps (b)-(d) in Figure 7A show the detailed steps of the above processing flow.

[0135] For example, in step (b), a redistribution layer 303-3 can be formed on the second surface of the glass substrate 301 for electrical connection. Next, in step (c), a dielectric layer 303 is disposed on the bottom surface of the glass substrate 301, covering a portion of the redistribution layer 303-3 formed in (b). A notch 303-4 corresponding to the redistribution layer 303-3 and the conductive via 301-1 needs to be formed in the dielectric layer 303. In step (d), a conductive via structure 303-2 is formed by filling the notch 303-4 with conductive material, thereby electrically connecting the conductive via structure 303-2 to the redistribution layer 303-3 and the conductive via 301-1 in the glass substrate. In this case, the conductive via structure 303-2 and the redistribution layer 303-3 together constitute the aforementioned fourth conductive structure, which penetrates the dielectric layer 303 and is electrically connected to the conductive via 301-1 in the glass substrate 301.

[0136] In step (d), one or more conductive bumps 305 are disposed on the surface of the dielectric layer 303 away from the glass substrate, and the conductive bumps 305 are electrically connected to the fourth conductive structure (i.e., the conductive hole structure 303-2 and the re-lay layer 303-3).

[0137] Thus far, the specific structure and manufacturing method of the adapter plate 300 for the first example of optical chip packaging have been described in conjunction with Figures 3 and 7A. By configuring electrical interconnect structures on the surface of the glass substrate, electrical interconnection can be achieved between the electrical chips above the optical chip packaged on this adapter plate.

[0138] The specific structure and manufacturing method of another example of the adapter board for optical wafer packaging will be described below with reference to Figure 4 and Figures 7A-7B. Figure 4 shows a cross-sectional view of the adapter board 400 for optical wafer packaging according to an embodiment of the present disclosure. Figures 7A-7B show process flow diagrams of the manufacturing method of the adapter board 400 according to an embodiment of the present disclosure.

[0139] As shown in Figure 4, the adapter board 400 can be divided into four layers in its overall structure, from bottom to top: dielectric layer 303, glass substrate 301, electrical interconnect layer 302 and optical waveguide structure 304. The configuration and function of dielectric layer 303, glass substrate 301 and electrical interconnect layer 302 are similar to the configuration and function of adapter board 300 shown in Figure 3, and will not be described again here.

[0140] Compared to the adapter plate 300 shown in Figure 3, the adapter plate 400 shown in Figure 4 additionally includes an optical waveguide structure 304. As shown, the optical waveguide structure 304 is disposed on the surface (i.e., the upper surface) of the electrical interconnect structure 302 on the side away from the glass substrate 301. In some examples, the optical waveguide structure 304 may include one or more optical waveguides 304-1 and a surrounding layer 304-2 surrounding the one or more optical waveguides 304-1. It should be noted that, for the sake of simplicity, only an example of an optical waveguide structure with one optical waveguide 304-1 is shown in Figure 4, but this is merely exemplary, and two, three, or more optical waveguides may be configured as needed. The optical waveguide 304-1 shown is used for optical interconnection of multiple optical wafers packaged on the adapter plate 400, and the refractive index of the optical waveguide 304-1 is greater than the refractive index of the surrounding layer 304-2.

[0141] In addition, as shown in the figure, the optical waveguide structure 304 also includes one or more third conductive structures 304-3 that penetrate the optical waveguide structure and are electrically connected to one or more first conductive structures in the electrical interconnection structure 302.

[0142] The manufacturing method of the adapter plate 400 shown in Figure 4 includes steps (a)-(e) as shown in Figure 7A, and step (f) as shown in Figure 7B. Steps (a)-(e) have been described in detail in the manufacturing method of the adapter plate 300, and will not be repeated here.

[0143] After forming the adapter board including the electrical interconnect structure 302 as shown in (e) of Figure 7A, the method of manufacturing the adapter board 400 further includes: in step (f), disposing an optical waveguide structure 304 on the surface of the electrical interconnect structure 302 away from the glass substrate 301. As described above with respect to Figure 4, the optical waveguide structure 304 may include one or more optical waveguides 304-1 and a surrounding layer 304-2 surrounding the one or more optical waveguides 304-1. The optical waveguide structure 304 can be formed using a similar technique as described with respect to Figure 5. For example, a surrounding layer material can be deposited on the electrical interconnect structure 302 first, and then the optical waveguide 304-1 can be formed on the deposited surrounding layer material using wafer-level nanoimprint lithography, and then a surrounding layer material can be deposited again on the optical waveguide 304-1 to completely surround the optical waveguide 304-1 to form the surrounding layer 304-2. For simplicity, Figure 7B shows only an example of an optical waveguide structure with a single optical waveguide 304-1, but this is merely exemplary; two, three, or more optical waveguides can be configured as needed. The aforementioned single or multiple optical waveguides 304-1 are used for optical interconnection of multiple optical wafers packaged on an adapter board, and the refractive index of the optical waveguide 304-1 is greater than the refractive index of the surrounding layer 304-2. For example, the single or multiple optical waveguides 304-1 can be silicon nitride optical waveguides, and the material of the surrounding layer 304-2 is silicon dioxide.

[0144] Similarly, it should be noted that, regarding the method for forming the optical waveguide 304-1, compared with the prior art nanoimprint technology, the wafer-level nanoimprint optical lithography technology disclosed herein has made the following improvements. To achieve wafer-level waveguide wiring without the limitations of typical step-and-repeat optical lithography's marker size, this disclosure uses wafer-level maskless optical lithography techniques, such as electron beam or laser writing. For example, firstly, an imprint master can be fabricated using an oxide or nitride stack, which is patterned using electron beam optical lithography. Then, by using this imprint master, a step-and-repeat operation is performed to generate a polymer-based nanoimprint (e.g., PDMS, polydimethylsiloxane) on the polymer. It should be noted that this nanoimprint is wafer-level, meaning that through the step-and-repeat operation described above, the entire optical waveguide pattern is completely and coherently formed in the same nanoimprint. Compared to traditional fabless imprinting, using a generated wafer-level nanoimprint on a nitride-deposited glass wafer allows for the one-time transfer of photoresist patterns onto the glass wafer, facilitating the formation of a monolithic nitride waveguide. Traditional fabless imprinting requires multiple imprinting processes for waveguide splicing, which can easily lead to misalignment issues, affecting the quality of the optical waveguide and resulting in optical signal loss.

[0145] Through the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, and no waveguide splicing is required in the middle, which can minimize the loss of optical signal.

[0146] In addition, the method of manufacturing the adapter board 400 may also include: in step (f), forming one or more third conductive structures 304-3 through the optical waveguide structure 304, and electrically connecting them to one or more first conductive structures in the electrical interconnection structure 302 respectively.

[0147] Thus far, the specific structure and manufacturing method of the adapter plate 400 for the first example of optical chip packaging have been described in conjunction with Figures 4 and 7A-7B. By arranging an electrical interconnect structure on the surface of a glass substrate and arranging an optical waveguide structure on the electrical interconnect structure, electrical interconnection can be achieved between the electrical chips packaged on this adapter plate, and optical interconnection can be achieved between the optical chips packaged on this adapter plate. Furthermore, through the wafer-level nanoimprinting method described above, the formed optical waveguide is continuous throughout the entire glass wafer, eliminating the need for waveguide splicing in the middle, and minimizing optical signal loss.

[0148] It should be understood that the various steps described in the method embodiments and figures disclosed herein may be performed in different sequences and / or concurrently as needed. Furthermore, method embodiments may include other steps and / or omit certain steps.

[0149] It should be noted that, in the above description of the adapter board, although the corresponding conductive structure and its manufacturing method are described for each layer of the adapter board (e.g., the optical waveguide structure 102 and the dielectric layer 103 in Figure 1), such as the first conductive structure 102-3 in the optical waveguide structure 102 and the second conductive structure 103-2 in the dielectric layer 103 in Figure 1, in some embodiments, these conductive structures do not need to be separate and can be integrally formed. For example, the first conductive structure 102-3 and the second conductive structure 103-2 in the dielectric layer 103 can be integrally formed copper plugs that run through the entire adapter board 100. Such integrally formed copper plugs are also applicable to other adapter boards as shown in Figures 2-4.

[0150] The above describes some embodiments of the structure and manufacturing method of the glass wafer-based interposer disclosed herein. Compared with silicon interposers with embedded TSVs, the glass wafer-based interposer has a simpler structure, lower manufacturing cost, and is easier to implement. It can also be effectively used for optical interconnection of optical chips and electrical interconnection of electrical chips, providing a good platform for the integration of optoelectronic chips.

[0151] By using the adapter board in the various embodiments described above, a compact, three-dimensional package structure including optical chips and electronic chips can be realized. Figures 8-11 show cross-sectional views of various optical chip package structures incorporating the adapter board in the embodiments disclosed herein.

[0152] As shown in Figure 8, the package structure 800 includes an adapter board 100 and an optical chip 500. For example, the adapter board 100 may be an adapter board 100 with an embedded optical waveguide as shown in Figure 1. This adapter board 100 can be used to perform optical interconnection of optical chips in a plurality of photonic-electronic hybrid chips disposed thereon, and electrical interconnection of electrical chips in a plurality of photonic-electronic hybrid chips. Preferably, the optical chip is fabricated on an SOI (silicon on insulator) substrate. After the front-end fabrication process of the optical chip is completed, the bottom silicon substrate in the SOI substrate is removed, and the thickness of the buried oxide layer is controlled. The optical chip is then bonded to the adapter board 100. The optical signal is thermally coupled to the optical waveguide on the optical chip through the embedded optical waveguide on the adapter board 100, and vice versa, thereby realizing on-chip optical network communication. It should be understood that, for simplicity, only one optical chip 500 is shown in Figure 8. In practical applications, two or more optical chips can be configured on the adapter board 100, which are interconnected through embedded optical waveguides in the adapter board 100. Furthermore, as shown, the optical chip 500 also includes one or more interconnect structures 501, each including vias penetrating the optical chip and conductive material filling the vias. As shown, the interconnect structures 501 are electrically connected to one or more first conductive structures 102-3 as described above on the adapter board 100.

[0153] In some examples, the package structure 800 may also include one or more optical wafers, each optical wafer having one or more electrical wafers (EICs in Figures 8-11). Typically, one or more electrical wafers (EICs) are positioned above the optical wafer 500 and are vertically electrically connected to the conductive structure in the adapter plate through conductive structures in the electrical wafers (such as UBM (under bump metallization) or other connection structures, such as direct bonding).

[0154] Figures 9 to 11 show example structures of the adapter plates corresponding to Figures 2 to 4 applied to the packaging of optical wafers. The optical wafer 500 is similar to the optical wafer in Figure 8, and will not be described again here. It should be noted that, as shown in Figure 10, when the adapter plate 300 with the electrical interconnection structure shown in Figure 3 is applied to the packaging structure 1000, the interconnection structure 501 in the optical wafer 500 can be electrically connected to the conductive structures 302-3 in the electrical interconnection layer of the adapter plate 300.

[0155] In addition, as mentioned above, the conductive structures in each layer of the adapter board are not necessarily separate, but can be integrally formed. For example, the conductive structure in each layer can be an integrally formed copper plug that runs through the entire adapter board, which facilitates electrical connection between the adapter board and the chip.

[0156] It should be noted that in the adapter boards described above in conjunction with Figures 1-2 and 4, optical waveguides are configured for optical interconnection of multiple optical wafers configured on the adapter board, such as optical waveguide 102-1 in Figure 1, coupling optical waveguide 202-1 and cladding layer 202-2 in Figure 2, and optical waveguide 304-1 in Figure 4. Optical coupling between the optical waveguides in the adapter board and the optical wafers can be achieved, for example, by using external optical fibers; however, this method occupies a large space and is not conducive to miniaturization of the packaging structure. The embodiments disclosed herein propose using thermal coupling to couple the optical wafers to the optical waveguides in the adapter board, thereby achieving product miniaturization. Various embodiments of the optical wafer packaging structure and its manufacturing method using this thermal coupling technology will be described in detail below. It should be noted that in this disclosure, the adapter board used for thermal coupling is not limited to the adapter board described above, but can be any adapter board capable of realizing optical interconnection of optical wafers.

[0157] Figures 12A and 12B show a cross-sectional view and a top view of the optical chip packaging structure 1200 of the present disclosure embodiment, respectively.

[0158] As shown in Figure 12A, the optical chip package structure 1200 includes an adapter plate 1210 and a plurality of optical chips (PICs) disposed on the adapter plate 1210. Typically, the optical chips are fabricated using an SOI substrate, and the optical waveguides in the optical chips are disposed on the buried oxide layer of the SOI substrate. For example, since Figure 12A shows a cross-sectional view cut from a specific location, only two optical chips, PIC 1 and PIC 2, are visible in Figure 12A. However, in reality, as shown in the top view of Figure 12B, the optical chip package structure 1200 may include six optical chips, PIC 1 to PIC 6. It should be understood that the above six optical chips are merely exemplary and not limiting; in practical applications, the optical chip package structure 1200 may include more or fewer optical chips.

[0159] As shown in Figure 12A, the optical chip package structure 1200 includes one or more first optical waveguides embedded therein, such as optical waveguide WG1-1 and optical waveguide WG1-2 shown in Figure 12A. Optical waveguide WG1-1 and optical waveguide WG1-2 can be a waveguide network formed by an array of multiple optical waveguides. Optical waveguide WG1-1 and optical waveguide WG1-2 can be optical waveguides in the aforementioned adapter board, such as optical waveguide 102-1 in Figure 1, coupling optical waveguide 202-1 and cladding layer 202-2 in Figure 2, or optical waveguide 304-1 in Figure 4. Furthermore, the material of optical waveguide WG1-1 and optical waveguide WG1-2 can be silicon nitride as described above, and a silicon oxide cladding layer covers the silicon nitride.

[0160] Each of the optical wafers PIC 1 and PIC 2 includes one or more second optical waveguides embedded therein (for simplicity, only a single optical waveguide is shown for each PIC in Figure 12A), namely optical waveguide WG2-1 and optical waveguide WG2-2. In some examples, the material of optical waveguide WG2-1 and optical waveguide WG2-2 may be silicon. As shown in Figure 12B, multiple optical wafers (PIC 1, ..., PIC 6) are attached to different locations on the upper surface of the adapter plate 1210. As shown, PIC 1-PIC 6 are attached to different locations in the square region R1 on the adapter plate 1210 and are spaced apart from each other.

[0161] Optical interconnects can be formed between any two of the optical chips PIC 1 and PIC 2, or any two of the plurality of optical chips (PIC 1, ..., PIC 6) as shown in Figure 12B, via one or more first optical waveguides in the adapter board 1210. For example, as shown by the dashed line with arrows in Figure 12A, light can originate from PIC 1, then be coupled to optical waveguide WG1-1 in the adapter board 1210 via optical waveguide WG2-1, then be transmitted to optical waveguide WG1-2 via other optical waveguide networks (not shown), and then be coupled to optical waveguide WG2-1 in PIC 2. Specifically, each first optical waveguide may include a first optical coupling portion, and each second optical waveguide may include a second optical coupling portion (not shown). For simplicity, the ends of, for example, optical waveguides WG2-1 and WG1-1 can be considered as their respective optical coupling portions. For example, the optical coupling portions of optical waveguides WG2-1 and WG1-1 are stacked in a direction perpendicular to the upper surface of the adapter plate 1210 and spaced apart by a predetermined distance (e.g., less than 600 nm), enabling thermally adiabatic optical coupling between the optical coupling portions of optical waveguides WG2-1 and WG1-1. Of course, optical wafers PIC1 and PIC2 can also be optically interconnected through a first optical waveguide. For example, optical waveguides WG1-1 and WG1-2 in Figure 12A can be different parts of a first optical waveguide. In the presence of multiple first optical waveguides, different first optical waveguides can achieve optical interconnection between different optical wafers. For example, one first optical waveguide can be used to connect PIC1 and PIC2, ​​and another first optical waveguide can be used to connect PIC1 and PIC3 or PIC3 and PIC4.

[0162] Figures 13 and 14 show schematic side and top views of the optical coupling portion in the optical wafer packaging structure 1200 of the present disclosure, and corresponding optical mode field diagrams, respectively.

[0163] As shown in Figure 13, the coupling part of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling part of the optical waveguide WG1-1 in the adapter board are stacked vertically and spaced apart by a predetermined distance H.

[0164] Furthermore, to achieve high coupling efficiency, as shown in Figure 14, the coupling portion of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling portion of the optical waveguide WG1-1 in the adapter plate can have a tapered shape. Ideally, the coupling portions of the optical waveguide WG2-1 in the optical chip PIC 1 and the optical waveguide WG1-1 in the adapter plate (i.e., the two tapered shapes shown in Figure 14) should be aligned in both the lateral and longitudinal directions to obtain the maximum coupling efficiency. However, in actual manufacturing, due to process limitations, it is impossible to achieve perfect alignment of the coupling portions of the optical waveguide WG2-1 in the optical chip PIC 1 and the optical waveguide WG1-1 in the adapter plate in both the lateral and longitudinal directions. Typically, there will be a lateral misalignment LM and a longitudinal misalignment TM as shown in Figure 14.

[0165] Taking SOI as the substrate of the optical chip and SiN as the optical waveguide on the adapter plate as an example, the main parameters that have a significant impact on the coupling efficiency between the optical chip and the adapter plate are as follows: the width W4 of the optical waveguide WG1-1 in the adapter plate, the length L of the coupling part of the optical waveguide WG2-1 and the coupling part of the optical waveguide WG1-1, the predetermined distance H, and the thickness tSiN of the optical waveguide WG1-1.

[0166] Regarding the width W4 of the optical waveguide WG1-1 in the adapter board, while ensuring that the optical waveguide WG1-1 is a single-mode waveguide, the wider W4 is, the better the coupling effect. Preferably, W4 < 1 μm can be selected, because if it is greater than 1 μm, it is easy to become a multimode waveguide.

[0167] For the length L of the coupling part, the longer L is, the better the coupling effect. Figure 15 shows the relationship between the coupling efficiency and the lateral misalignment for different L values ​​when W4=1μm and H=200nm. When L=200μm, the coupling loss can be controlled within 1dB when the lateral misalignment is 1μm. When L=1800μm, the coupling loss can also be controlled within 1dB when the lateral misalignment is 1.5μm.

[0168] For the predetermined distance H between the coupling part of optical waveguide WG2-1 and the coupling part of optical waveguide WG1-1, the smaller H is, the better the coupling effect. However, H includes the thickness of the buried oxide layer in the SOI of the optical wafer after thinning, plus the thickness of the silicon oxide covering the silicon nitride waveguide in the adapter plate. If H is set too small, the buried oxide layer in the SOI needs to be thinner. Due to the limitations of the thinning process, the thickness of the buried oxide layer will be uneven, which will affect the coupling efficiency. Therefore, preferably, H = 100nm-600nm. Figure 16 shows the relationship between coupling efficiency and lateral misalignment for different H values ​​when W4 = 1μm, L = 200μm, and tSiN = 200nm. It can be seen that the coupling effect is best when H = 200nm. When it is greater than 200nm, the larger the spacing, the greater the decrease in coupling efficiency for the same lateral misalignment.

[0169] Regarding the thickness tSiN of the optical waveguide WG1-1, if the tSiN thickness is too small, it will lead to uneven thickness of the optical waveguide; if the thickness is too large, it will cause cracking due to internal stress. Therefore, preferably, tSiN = 100nm-300nm. Figure 17 shows the relationship between coupling efficiency and lateral misalignment for different tSiN values ​​when W4 = 1μm, L = 200μm, and H = 200nm. It can be seen from the figure that the coupling effect is optimal when tSiN = 200nm.

[0170] In addition to the tapered coupling portion as described above, in some embodiments, the coupling portion of the optical waveguide of the optical wafer and the coupling portion of the optical waveguide of the adapter plate may have a shape formed by two tapered shapes of different sizes connected in series. Figures 18 and 19 show schematic diagrams of such coupling portions having a shape formed by two tapered shapes of different sizes (S1-1, S1-2, S2-1, S2-2) connected in series, and diagrams of the corresponding optical mode fields, respectively.

[0171] As shown in Figure 19, compared with the previous tapered structure, both the coupling part of the optical waveguide of the optical chip and the coupling part of the optical waveguide of the adapter plate have an additional tapered transition structure with a length of L_taper. That is, the optical coupling part has evolved from a single tapered structure to a structure formed by two tapered structures connected in series. The reason for adding the above-mentioned tapered transition structure is that there is an overlap point between the silicon waveguide (optical waveguide WG2-1) and the silicon nitride waveguide (optical waveguide WG1-1) at a length of about 700nm for the silicon waveguide (optical waveguide WG2-1) and about 300nm for the silicon nitride waveguide (optical waveguide WG1-1), for example at the position of the dashed line shown in Figure 19. The dielectric constants (n eff_Si, n eff_SiN) are high. At this overlap point, the two can couple quickly. Furthermore, the coupling length L_trans of this structure can be greatly reduced compared with the previous tapered structure, and optical coupling can be completed with about 10μm. Furthermore, under the same conditions, silicon waveguides (optical waveguide WG2-1) and silicon nitride waveguides (optical waveguide WG1-1) can also allow for larger longitudinal alignment misalignment (previous tapered structures required two waveguides to have a small angular alignment error in the parallel direction) and lateral alignment misalignment.

[0172] The embodiments of the optical chip packaging structure disclosed herein have been described above with reference to Figures 12A-19. In this embodiment, by controlling the spacing between the optical waveguides in the optical chip and the optical waveguides on the adapter board, and by changing the structure of the coupling portion of the two waveguides, multiple optical chips can be optically connected to the adapter board through thermal coupling, thereby realizing optical interconnection between multiple optical chips through the optical waveguide network on the adapter board. Compared with external interconnection methods such as fiber arrays, this packaging structure that uses thermal coupling technology to optically interconnect multiple optical chips can greatly reduce the volume of the packaging structure.

[0173] Optionally, an electronic chip can also be configured in the packaging structure described above to form an optical chip packaging structure that can realize electrical operation (such as logic calculation, memory, etc.).

[0174] Figures 20 and 21 show a cross-sectional view and a top view of an optical chip package structure 2000 containing an electronic chip according to an embodiment of the present disclosure.

[0175] As shown in Figure 20, in addition to the adapter board 1210 and optical chips PIC 1 and PIC 2 similar to those in Figures 12A-12B, the optical chip package structure 2000 also includes multiple electronic chips disposed on multiple first optical chips among multiple optical chips, for example, EIC 1 and EIC 2 disposed on PIC 1 and PIC 2 respectively. Alternatively, as shown in Figure 21, EIC 1, EIC 2, EIC 5, and EIC 6 disposed on PIC 1, PIC 2, PIC 5, and PIC 6 respectively. It should be noted that Figure 20 can be regarded as a cross-sectional view cut through the optical chip package structure 2000 shown in Figure 21 at the position penetrating EIC 1 and EIC 2. In Figure 21, PIC 1, PIC 2, PIC 5, and PIC 6 are covered by the corresponding EIC 1, EIC 2, EIC 5, and EIC 6 respectively, and are therefore not shown. Furthermore, as shown in Figure 21, it is not necessary to set a corresponding EIC for each PIC. For example, EICs may not be configured on PIC 3 and PIC 4 if needed.

[0176] Specifically, each first optical chip (e.g., PIC 1 and PIC 2 as shown in Figure 20) may have one or more first electrical connectors on its upper surface, and each electrical chip (e.g., EIC 1 and EIC 2 as shown in Figure 20) may have one or more second electrical connectors on its lower surface, and the one or more first electrical connectors are electrically connected to the one or more second electrical connectors respectively, thereby realizing the connection between the PIC and the EIC.

[0177] Figures 22 and 23 show cross-sectional views of the optical chip and electronic chip in the optical chip packaging structure of the embodiments disclosed herein.

[0178] As shown in Figure 22(a), the upper surface of the PIC has a plurality of first electrical connectors C1 and the lower surface of the EIC has a plurality of second electrical connectors C2. The PIC and the EIC are directly connected through the first electrical connectors C1 and the second electrical connectors C2.

[0179] In some examples, the first optical chip (i.e., the PIC on which the EIC is configured) also includes one or more second conductive vias therethrough, such as conductive vias TDV (through dielectric via) as shown in Figure 22(a). Through these TDVs, an electrical connection between the EIC and the adapter board can be achieved, for example, by connecting the TDV shown to the conductive structure of the adapter board as previously shown, which will be described in detail later in the introduction of Figures 24-25.

[0180] Figure 22(a) shows a schematic diagram of a single EIC configured on a PIC. In other embodiments, multiple EICs may be configured on a PIC. For example, as shown in Figure 22(b), an analog IC A-EIC and a digital IC D-EIC may be configured on a PIC. Multiple analog IC A-EICs, multiple digital IC D-EICs, or multiple analog IC A-EICs and multiple digital IC D-EICs may be configured on a PIC as needed. In the case of multiple EICs configured on the same PIC, each EIC is connected to the conductive structure of the adapter board via TDV as described above to achieve electrical connection between them.

[0181] In addition to the direct bonding method described above, optical ICs (PICs) and electronic ICs (EICs) can also be bonded using a flip-chip method. Figure 23 shows an optical IC and an electronic IC bonded using a flip-chip method. In this example, instead of direct bonding, a conventional flip-chip process is used, connecting the EIC and PIC through copper pillars, and using underfill for curing between the EIC and PIC. Figure 23(a) shows an example of a PIC with only one flip-chip EIC, and (b) shows an example of a PIC with one flip-chip D-EIC and one A-EIC. Similarly, multiple analog ICs (A-EICs) can be flip-chipped onto a PIC, multiple digital ICs (D-EICs) can be flip-chipped onto a PIC, or multiple analog ICs (A-EICs) and multiple digital ICs (D-EICs) can be flip-chipped onto a PIC. When multiple EICs are flip-chip mounted on the same PIC, each EIC is connected to the conductive structure of the adapter board via TDV as described above to achieve electrical connection between the two.

[0182] To more clearly disclose the optical chip package structure of this disclosure, Figures 24 and 25 show cross-sectional views of the optical chip package structure of the embodiments disclosed. However, it should be noted that, for further detail, only one PIC and one EIC are shown in Figures 24 and 25. Specifically, Figure 24 shows a cross-sectional view of an optical chip package structure using an adapter board as shown in Figure 1. Figure 25 shows a cross-sectional view of an optical chip package structure using an adapter board as shown in Figure 4.

[0183] As shown in Figure 24, when using the adapter board shown in Figure 1, the entire package structure can be divided into three layers from bottom to top: the layer containing the adapter board 1210, the layer containing the PIC, and the layer containing the EIC. For example, in Figure 24, the entire package structure is divided into three layers using two parallel dashed lines. The dashed line between the EIC and the PIC defines the connection interface IF1 between the EIC and the PIC, and the dashed line between the PIC and the adapter board 1210 defines the connection interface IF2 between the PIC and the adapter board 1210. It should be understood that the above division method is only for the purpose of more clearly describing the present invention, and not for limiting the present invention to the three-layer structure described above.

[0184] Assuming the optical wafer PIC shown in Figure 24 is PIC 1 as shown in Figure 20, then the EIC disposed thereon corresponds to EIC 1 as shown in Figure 20. In this case, it can be seen that the optical waveguide WG2-1 in the optical wafer PIC is located near the lower surface of the optical wafer PIC and is covered by a transparent dielectric layer (e.g., a buried silicon oxide layer). The optical waveguide WG1-1 in the adapter plate 1210 is located on the upper surface of the adapter plate 1210 and is also covered by a coating layer (e.g., a silicon oxide layer). The optical wafer PIC has a through-hole conductive via TDV, and this conductive via TDV in the optical wafer PIC is electrically connected to the conductive structure CC in the adapter plate 1210. For example, if the adapter plate 1210 in Figure 24 is similar to the adapter plate 100 shown in Figure 1, the optical waveguide WG1-1 may correspond to the optical waveguide 102-1 in the adapter plate 100 shown in Figure 1, and the conductive structure CC may correspond to the first conductive structure 102-3 in the adapter plate 100 shown in Figure 1.

[0185] Similarly, as shown in Figure 25, when using the adapter board as shown in Figure 4, the entire package structure can also be divided into three layers from bottom to top: the layer where the adapter board 1210 is located, the layer where the PIC is located, and the layer where the EIC is located. For example, in Figure 25, the entire package structure is also divided into three layers using two parallel dashed lines. The dashed line between the EIC and the PIC defines the connection interface IF1 between the EIC and the PIC, and the dashed line between the PIC and the adapter board 1210 defines the connection interface IF2 between the PIC and the adapter board 1210. It should also be understood that the above division method is only for more clearly describing the present invention, and not for limiting the present invention to the three-layer structure as described above.

[0186] Similarly, assuming the optical wafer PIC shown in Figure 25 is PIC 1 as shown in Figure 20, then the EIC disposed thereon corresponds to EIC 1 as shown in Figure 20. In this case, it can be seen that the optical waveguide WG2-1 in the optical wafer PIC is located near the lower surface of the optical wafer PIC and is covered by a dielectric layer (e.g., a silicon oxide layer). The optical waveguide WG1-1 in the adapter plate 1210 is located on the upper surface of the adapter plate 1210 and is also covered by a coating layer (e.g., a silicon oxide layer). The optical wafer PIC has a conductive via TDV that extends through it, and this conductive via TDV in the optical wafer PIC is electrically connected to the conductive structure CC in the adapter plate 1210. For example, if the adapter plate 1210 in Figure 25 is similar to the adapter plate 400 shown in Figure 4, the optical waveguide WG1-1 may correspond to the optical waveguide 304-1 in the adapter plate 400 shown in Figure 4, and the conductive structure CC may correspond to the third conductive structure 304-3 in the adapter plate 400 shown in Figure 4.

[0187] In the example described in Figures 12A-25, the multiple optical wafers shown are separate optical wafers obtained after slicing photonic wafers, and are attached to different positions on the upper surface of the adapter plate and spaced apart from each other (as shown in Figures 12A-12B and Figures 20-21). Therefore, after the optical wafers are attached to the adapter plate, in order to further encapsulate and enhance the stability and strength of the structure, it is necessary to fill the gaps between different optical wafers and different electrical wafers on the upper surface of the adapter plate with molding material.

[0188] Optionally, before filling the molding material, a dielectric layer for blocking the outward transmission of light in the adapter plate can be first disposed on the connection interface between the optical wafer and the adapter plate, and then molding is performed on this dielectric layer to form a molding material layer. The reason for disposing such a dielectric layer between the adapter plate and the optical wafer is that the dielectric layer (e.g., silicon oxide layer) covering the waveguide (e.g., optical waveguide WG1-1 as shown in Figure 24 or Figure 25) in the adapter plate is very thin. When the optical signal is transmitted in the waveguide between different optical wafers, the thin silicon oxide layer will cause light to leak out during transmission, resulting in light loss. Therefore, before molding, a dielectric layer can be prepared in the gap on the adapter plate where the optical wafer is not attached. This dielectric layer has the same preferred material and preparation process as the dielectric layer covering the waveguide. For example, its material can also be silicon oxide, thus ensuring that the light transmitted in the waveguide between different optical wafers does not leak out. Alternatively, for example, a dielectric layer with a thickness of about a few micrometers can be prepared.

[0189] The packaging structures shown in Figures 24 and 25 both exhibit the molded material layer and the dielectric layer for blocking light as described above. For example, the molded material layer MLD and the dielectric layer SHD in Figure 24 or 25. The dielectric layer SHD is located between the adapter plate and the molded material layer MLD, and has a greater thickness than the thin silicon oxide layer above the optical waveguide WG1-1, thus ensuring that the light transmitted between different optical wafers is confined to the adapter plate to the greatest extent.

[0190] It should be understood that although examples of optical wafer packaging structures using the adapter plates shown in Figures 1 and 4 are shown in Figures 24 and 25 respectively, these are merely exemplary and do not imply that the optical wafer packaging structures described above in this disclosure can only use the adapter plates shown in Figures 1 and 4. For example, the optical wafer packaging structures described above in this disclosure can also use the adapter plate 200 with a three-dimensional waveguide network as shown in Figure 2, and in the case of using the adapter plate 200 with a three-dimensional waveguide network as shown in Figure 2, the optical waveguides (e.g., optical waveguide WG1-1) in the adapter plate as described above can correspond to the three-dimensional waveguide network 201-2 in the adapter plate 200 as shown in Figure 2 and the coupling optical waveguide 202-1 covering the optical input / output port of this three-dimensional waveguide network. In addition, various variations or modifications of the adapter plates discussed in this disclosure can also be used, which will not be listed here.

[0191] The above description, in conjunction with Figures 12A-25, illustrates the scenario where multiple optical chips bonded to the adapter plate are separate optical chips obtained after splitting a photonic wafer. It should be noted that the multiple optical chips bonded to the adapter plate can also be multiple undivided optical chips from the same photonic wafer.

[0192] Figures 26-27 show schematic diagrams of an optical chip packaging structure 2600 in which multiple optical chips bonded to the adapter board are located on the same photonic wafer.

[0193] As shown in Figure 26, the optical chip package structure 2600 includes an adapter board 1210 and a plurality of optical chips (PICs) disposed on the adapter board 1210. For example, since Figure 26 shows a cross-sectional view cut from a specific location, only two optical chips, PIC 1 and PIC 2, are visible in Figure 26. However, in reality, as shown in the top view of Figure 27, the optical chip package structure 2600 may include six optical chips, PIC 1 to PIC 6. It should be understood that the above six optical chips are merely exemplary and not limiting; in practical applications, the optical chip package structure 2600 may include more optical chips.

[0194] As shown in Figure 26, the optical chip package structure 2600 includes a plurality of first optical waveguides embedded therein, such as optical waveguide WG1-1 and optical waveguide WG1-2 shown in Figure 26. Optical waveguide WG1-1 and optical waveguide WG1-2 can be optical waveguides in the adapter board as described above, such as optical waveguide 102-1 in Figure 1, coupling optical waveguide 202-1 and cladding layer 202-2 in Figure 2, or optical waveguide 304-1 in Figure 4. Furthermore, the material of optical waveguide WG1-1 and optical waveguide WG1-2 can be silicon nitride as described above.

[0195] Each of the optical wafers PIC 1 and PIC 2 includes one or more second optical waveguides embedded therein (for simplicity, only a single optical waveguide is shown for each PIC in Figure 26), namely optical waveguide WG2-1 and optical waveguide WG2-2. In some examples, the material of optical waveguide WG2-1 and optical waveguide WG2-2 may be silicon. As shown in Figure 27, a photonic wafer PWF comprising multiple optical wafers (PIC 1, ..., PIC 6) is bonded to the upper surface of the adapter plate 1210, and the multiple optical wafers (PIC 1, ..., PIC 6) are located at different positions on the adapter plate 1210 and spaced apart from each other.

[0196] Optical interconnection can be achieved between any two of the optical chips PIC 1 and PIC 2 shown in Figure 26, or between any two of the plurality of optical chips (PIC 1, ..., PIC 6) shown in Figure 27, via first optical waveguides in a plurality of adapter boards 1210. For example, as shown by the dashed line with arrows in Figure 26, light can originate from PIC 1, then be coupled to optical waveguide WG1-1 in adapter board 1210 via WG2-1, then be transmitted to optical waveguide WG1-2 via a series of optical waveguide networks (not shown), and then be coupled to optical waveguide WG2-1 in PIC 2. Specifically, each first optical waveguide may include a first optical coupling portion, and each second optical waveguide may include a second optical coupling portion (not shown in the figure). For simplicity, the ends of, for example, optical waveguides WG2-1 and WG1-1 can be considered as their respective optical coupling portions. For example, the optical coupling parts of optical waveguides WG2-1 and WG1-1 are stacked in a direction perpendicular to the upper surface of the adapter plate 1210 and spaced apart by a predetermined distance (e.g., less than 600 nm), so that thermal coupling of light can be achieved between the optical coupling parts of optical waveguides WG2-1 and WG1-1.

[0197] For the design of the optical coupling section of the first optical waveguide in the adapter plate and the optical coupling section of the second optical waveguide in the optical wafer, please refer to Figures 13 to 19 and their descriptions. The design of the optical coupling section of the optical waveguide applicable to the case of separated optical wafers is also applicable to the case of undivided photonic wafers, unless otherwise stated or clearly unsuitable. For example, the optical coupling section of the first optical waveguide (e.g., WG1-1 or WG1-2) in the adapter plate and the optical coupling section of the second optical waveguide (e.g., WG2-1 or WG2-2) in the optical wafer can have a tapered shape as shown in Figure 14, or it can be a shape formed by two tapered shapes of different sizes connected in series as shown in Figure 19.

[0198] It should be noted that, in order to distinguish it from the optical wafer package structure 1200 in Figure 12A, the gap between PIC 1 and PIC 2 in the optical wafer package structure 2600 shown in Figure 26 is shown as not being filled with shaded lines, thereby indicating that PIC 1 and PIC 2 are located in the same uncut wafer, rather than being filled with molding material as shown in Figure 12A.

[0199] Similar to the case of using a split optical wafer, in the case of using an undivided photonic wafer, electrical wafers can also be arranged on specific optical wafers or all optical wafers in the photonic wafer accordingly.

[0200] Figures 28-29 show schematic diagrams of an optical wafer package structure 2800 in which electronic wafers are simultaneously configured using an undivided photonic wafer.

[0201] As shown in Figure 28, in addition to the adapter board 1210 similar to that in Figures 26-27 and the photonic wafer PWF including optical chips PIC 1 and PIC 2, the optical chip package structure 2800 also includes multiple electrical chips disposed on multiple first optical chips (e.g., PIC 1 and PIC 2) among multiple optical chips, such as EIC 1 and EIC 2 disposed on PIC 1 and PIC 2 respectively. Alternatively, as shown in Figure 29A, the optical chip package structure 2800 may include EIC 1, EIC 2, EIC 5, and EIC 6 disposed on PIC 1, PIC 2, PIC 5, and PIC 6 respectively. It should be noted that Figure 28 can be regarded as a cross-sectional view taken from the position through EIC 1 and EIC 2 of the optical chip package structure 2000 shown in Figure 29A. In Figure 29A, PIC 1, PIC 2, PIC 5, and PIC 6 are already covered by their corresponding EICs 1, 2, 5, and 6, and therefore are not shown. Furthermore, as shown in Figure 29A, it is not necessary to set a corresponding EIC for each PIC. For example, EICs may not be configured above PIC 3 and PIC 4 if needed. It should be noted that the absence of EICs above PIC 3 and PIC 4 does not mean that PIC 3 and PIC 4 are not covered by electronic wafers. Rather, it can be understood that the corresponding positions of the electronic wafers covering PIC 3 and PIC 4 are "dummy chips" without a specific structure, rather than the specific chips or wafers with a concrete structure and capable of performing specific functions, as indicated by EIC 1, EIC 2, EIC 5, and EIC 6.

[0202] Alternatively, in some examples, an EIC can be configured above each PIC. For example, Figure 29B shows a schematic diagram of an EIC configured on each optical chip PIC (EIC 1-EIC 6 as shown). In this case, for example, the corresponding electrical chips on all optical chips can be multiple undivided electrical chips in the same electronic wafer, and the multiple optical chips can have the same structure, and the multiple electrical chips (e.g., EIC 1-EIC 6 as shown) can also have the same structure, such that each PIC-EIC pair stacked vertically forms the same PIC-EIC hybrid wafer. In this case, the multiple first optical chips are equivalent to all optical chips.

[0203] It should be noted that, in the case of using an undivided photonic wafer, the multiple electrical wafers on the multiple first optical wafers as described above (e.g., EIC 1, EIC 2, EIC 3, EIC 4, EIC 5, EIC 6 in Figure 29B) are multiple undivided electrical wafers in the same electronic wafer EWF. In this case, the photonic wafer PWF and the electronic wafer EWF, as shown in Figures 29A-29B, are directly bonded together and then jointly configured on the adapter board 1210. In this case, the flip-chip bonding method shown in Figure 23 is no longer suitable for connecting the photonic wafer and the electronic wafer.

[0204] Additionally, it should be noted that, in order to distinguish it from the photonic wafer package structure 2000 in Figure 20, the gaps between PIC 1 and PIC 2 and between EIC 1 and EIC 2 in the photonic wafer package structure 2800 shown in Figure 28 are shown as not filled with shaded lines, thereby indicating that PIC 1 and PIC 2 are located in the same photonic wafer, and EIC 1 and EIC 2 are located in the same electronic wafer, instead of the gaps between PIC 1 and PIC 2 and between EIC 1 and EIC 2 being filled with molding material as shown in Figure 20.

[0205] Similarly, for the embodiments shown in Figures 28-29, the design of the optical coupling portion of the first optical waveguide in the adapter plate and the optical coupling portion of the second optical waveguide in the optical wafer can also be referred to Figures 13 to 19 and their descriptions. The design of the optical coupling portion of the optical waveguide applicable to the case of separated optical wafers is also applicable to the case of undivided photonic wafers, unless otherwise stated or clearly unsuitable. For example, the optical coupling portion of the first optical waveguide (e.g., WG1-1 or WG1-2) in the adapter plate as shown in Figure 28 and the optical coupling portion of the second optical waveguide (e.g., WG2-1 or WG2-2) in the optical wafer can have a tapered shape as shown in Figure 14, or it can be a shape formed by two tapered shapes of different sizes connected in series as shown in Figure 19, which will not be described further here.

[0206] Furthermore, it should be noted that when using an undivided photonic wafer, the optical wafer packaging structure shown in Figures 26-29 can also employ the adapter boards 100 and 400 previously described with respect to Figures 1 and 4, or the adapter board 200 with a three-dimensional waveguide network as shown in Figure 2. When using the adapter board 200 with a three-dimensional waveguide network as shown in Figure 2, the optical waveguides (e.g., optical waveguide WG1-1) in the adapter boards described in Figures 26 or 28 can correspond to the three-dimensional waveguide network 201-2 in the adapter board 200 as shown in Figure 2, and the coupling optical waveguide 202-1 covering the optical input / output port of this three-dimensional waveguide network. Additionally, various variations or modifications of the adapter boards discussed in this disclosure can also be used, which will not be listed here.

[0207] Various embodiments of the optical chip packaging disclosed herein have been described above. In summary, the optical chip packaging structures described in Figures 12A-12B and Figures 20-21 employ separate optical chips, with the waveguides of the optical chips and the waveguides of the adapter plate coupled in an adiabatic manner. This packaging structure offers extremely high freedom in chip configuration, significantly reducing the size of the packaging structure. In contrast, the optical chip packaging structures shown in Figures 26-29 employ non-separated optical chips on the same photonic wafer. While less flexible in deployment than the separate optical chip approach, the direct wafer-to-glass adapter plate bonding process simplifies the process and improves alignment accuracy, resulting in higher coupling efficiency between the optical chip and the waveguides of the adapter plate. Those skilled in the art can select appropriate implementation methods based on actual needs, or combine various implementation methods, and such combinations also fall within the protection scope of this disclosure.

[0208] By employing the various optical chip packaging structures described above, various computing accelerators can be realized, such as those used for matrix multiplication and other computations in neural networks. Figure 30 shows a schematic diagram of a computing accelerator 3000 according to an embodiment of the present disclosure. Figure 31A shows a schematic diagram of another computing accelerator 3100A according to an embodiment of the present disclosure. Figure 31B shows a schematic diagram of yet another computing accelerator 3100B according to an embodiment of the present disclosure.

[0209] The computing accelerator 3000 shown in Figure 30 may be implemented using a discrete optical wafer package structure as shown in Figures 12A-12B or Figures 20-21. For example, as shown in Figure 30, the computing accelerator 3000 may include one or more light sources LS, one or more computing units CL, and one or more memory units MO. For clarity, different fill patterns are used to distinguish different functional units; for example, pure white filled units (squares as shown) represent memory units MO, grid-filled units represent computing units CL, and scatter-dot filled units represent light sources LS.

[0210] Some units in the computing accelerator 3000 can be implemented in an optical wafer package as shown above with respect to Figures 12A-12B and / or Figures 20-21. For example, one or more computing units CL are configured to perform computing functions, which can be implemented by an optical wafer in the optical wafer package structure 1200 described above with respect to Figures 12A-12B. For example, matrix multiplication operations can be implemented using a Mach-Zehnder interferometer or the like in the optical wafer. Alternatively, one or more computing units CL can be implemented by electronic chips in the optical chip package structure 1200 as described above with respect to Figures 20-21. For example, the optical chip in the optical chip package structure 1200 mainly performs communication functions, while the electronic chip performs computing functions. Alternatively, one or more computing units CL can be implemented by both optical chips and electronic chips in the optical chip package structure 1200 as described above with respect to Figures 20-21. For example, the optical chip in the optical chip package structure 1200 performs both communication functions and some computing functions, while the electronic chip performs other computing functions. One or more memory units MO are configured to perform memory functions and can be implemented by electronic chips in the optical chip package structure 1200 as described above with respect to Figures 20-21.

[0211] Furthermore, preferably, when the computing accelerator 3000 is implemented using an optical wafer package as shown above with respect to Figures 12A-12B and / or Figures 20-21, one or more light sources LS can be integrated into the aforementioned wafer package structure. For example, one or more light sources LS can be attached to the first surface of the adapter plate 1210 in a manner similar to PIC 1 or PIC 2 in the optical wafer package structure 1200 or 2000 described above, and are configured to provide light waves to the computing accelerator 3000 through the waveguide WG in the adapter plate, more specifically, to provide light waves to the respective optical wafers in the computing accelerator 3000.

[0212] For example, light in the light source LS can be thermally coupled to the corresponding optical waveguide in the adapter plate using a method similar to thermal coupling between the optical chip and the adapter plate, thus avoiding the additional interface required for coupling light through other intermediate links (e.g., optical fibers). This light source configuration method also helps to further reduce the size of the computing accelerator.

[0213] Optionally, the computing accelerator 3000 may also include one or more edge optical couplers, i.e., edge optical couplers CP located around the square as shown in Figure 30, which are configured to optically interconnect the computing accelerator with other devices. For example, if the light source LS is not mounted on the adapter plate as described above, but is used as an external light source, the edge optical couplers CP in the computing accelerator 3000 can be used to connect the light source.

[0214] Figure 30 shows that the adapter board 1210 in the computing accelerator can be any of the types of adapter boards described above. For example, it can be adapter boards 100 and 200 as described in Figures 1-2, or adapter board 400 as described in Figure 4. In addition, various variations or modifications of the adapter boards discussed in this disclosure can also be used, which will not be listed here.

[0215] Furthermore, it should be noted that although in Figure 30 the computing accelerator is shown as being implemented in different chips within the same optical chip package structure, this is merely illustrative. In practical applications, multiple different optical chip package structures can be interconnected via the edge optical coupler CP as described above, and various computing units, memory units, or light sources can be implemented or configured in multiple optical chip package structures to form large or ultra-large computing accelerators.

[0216] Compared to the computing accelerator 3000 shown in Figure 30, the computing accelerator 3100A shown in Figure 31A can be implemented using the photonic wafer-level packaging structure shown in Figures 26-29B. For example, as shown in Figure 31A, the computing accelerator 3100A may include one or more light sources LS, one or more computing units CL, and one or more memory units MO. For clarity, different fill patterns are used to distinguish different functional units; for example, pure white filled units (squares as shown) represent memory units MO, and grid-filled units represent computing units CL.

[0217] Some units in the computing accelerator 3100A can be implemented in the optical wafer package structure shown above with respect to Figures 26-29B. For example, one or more computing units CL are configured to perform computing functions, which can be implemented by optical wafers in the optical wafer package structure 2600 described above with respect to Figures 26-27. For example, matrix multiplication operations can be performed using a Mach-Zehnder (MZI) interferometer in the optical wafer. Alternatively, one or more computing units or memory units can be implemented by optical wafers or electronic wafers in the optical wafer package structure 2800 described above with respect to Figures 28-29A. For example, the optical wafers in the optical wafer package structure 2800 mainly perform communication functions, while the electronic wafers perform computing and memory functions; or, one or more computing units CL can be jointly implemented by optical wafers and electronic wafers in the optical wafer package structure 2800 described above with respect to Figures 28-29A. For example, the optical wafers in the optical wafer package structure 2800 simultaneously perform communication functions and some computing and memory functions, while the electronic wafers perform other computing and memory functions.

[0218] Unlike Figure 30, Figure 31A uses a packaging structure with photonic wafers. In addition to the square area shown in Figure 30, there are redundant photonic wafers. Before bonding the photonic wafer to the adapter board, the redundant photonic wafers need to be cut and removed.

[0219] Optionally, the above-mentioned computing unit and memory unit can also be implemented using a packaging structure as shown in Figure 29B. For example, when the computing unit and memory unit in the computing accelerator are implemented using the optical wafer package structure 2900 shown in Figure 29B, since each EIC in the optical wafer package structure 2900 is the same and each PIC is also the same, each PIC and its corresponding EIC (e.g., PIC 1 and EIC 1) can be used to jointly implement each computing unit and its corresponding memory unit, and it can be regarded as a computing-memory unit.

[0220] Figure 31B shows an example of a computing accelerator 3100B in which each computing unit and its corresponding memory unit are implemented as a corresponding computing-memory unit. For example, each computing unit and its corresponding memory unit can be implemented by each optical chip and its corresponding electrical chip in the optical chip package structure 2900 as shown in Figure 29B, and each computing unit and its corresponding memory unit can be regarded as a computing-memory unit CL-MO.

[0221] In this case, as shown in Figure 31B, the combination of the computing unit and the corresponding memory unit can be regarded as a single computing-memory unit CL-MO. For ease of understanding, each computing-memory unit CL-MO in Figure 31B is shown as filled with a checkerboard pattern, indicating that each computing-memory unit CL-MO can have the same hardware resources, i.e., the same memory resources, computing resources, communication resources, etc. For example, when multiple computing-memory units CL-MO as shown are implemented by the optical chip package structure 2900 described above with respect to Figure 29B, the optical chip in the optical chip package structure 2900 can mainly perform the communication function, and the corresponding electronic chip can perform the computing and memory functions; or, the optical chip can simultaneously perform the communication function and some computing and memory functions, and the corresponding electronic chip can perform other computing and memory functions.

[0222] Furthermore, it should be understood that the terms "computing unit," "memory unit," or "computation-memory unit" as described above are intended to describe functional units within a computing accelerator, and not to limit the individual optical wafers, electrical wafers, or combinations of optical and electrical wafers in an optical wafer package to use only for computing, only for memory, or only for computation-memory. For example, the individual optical wafers, electrical wafers, or combinations of optical and electrical wafers in an optical wafer package can also be used to implement functions other than computing, memory, or computation-memory, such as data transmission.

[0223] In addition, it should be noted that since the computing accelerator 3100A or 3100B is a direct bonding of electronic wafer to photonic wafer, the light source LS (e.g., laser chip) cannot be directly bonded to the adapter board. It is necessary to couple light into the computing accelerator through fiber array or other light guide structure. The light source LS is configured to provide light waves to the computing accelerator 3100A or 3100B through the waveguide WG in the adapter board, or more precisely, to provide light waves to each optical chip in the computing accelerator 3100A or 3100B.

[0224] Additionally, the computing accelerator 3100A or 3100B may also include one or more edge optical couplers, i.e., edge optical couplers CP located around a square as shown in Figure 31A or 31B, which are configured to optically interconnect the computing accelerator with other devices. For example, the edge optical couplers CP in the computing accelerator 3100A or 3100B can be used to connect a light source LS.

[0225] The adapter board 1210 shown in Figure 31A or Figure 31B in the computing accelerator can be any of the types of adapter boards described above. For example, it can be adapter boards 100 and 200 as described in Figures 1-2, or adapter board 400 as described in Figure 4. In addition, various variations or modifications of the adapter boards discussed in this disclosure can also be used, which will not be listed here.

[0226] Furthermore, it should be noted that although in Figures 31A or 31B the computing accelerator is shown as being implemented in different chips within the same optical chip package structure, this is merely illustrative. In practical applications, multiple different optical chip package structures can be interconnected via the edge optical coupler CP as described above, and various computing units, memory units, or light sources can be implemented or configured in multiple optical chip package structures to form large or ultra-large computing accelerators.

[0227] Optionally, the computing accelerator described above with respect to Figures 30-31 may further include a plurality of high-bandwidth memory (HBM) chips stacked on the optical chip in the optical chip package structure described above, which are configured to perform memory computing functions.

[0228] The above describes the optical chip packaging structures and computing accelerators implemented using various optical chip packaging structures in various embodiments of this disclosure. In summary, the optical chip packaging structures described in Figures 12A-12B and Figures 20-21, due to their use of discrete optical chips and the thermal coupling of the waveguides of the optical chips and the adapter board, offer extremely high freedom in chip configuration, significantly reducing the size of the packaging structure. Furthermore, computing accelerators implemented through this packaging structure can further integrate the light source within the optical chip packaging structure, which is beneficial for further reducing product size.

[0229] In contrast, the optical chip packaging structure shown in Figures 26-29B uses unseparated optical chips on the same photonic wafer. Although it is less flexible in terms of layout than the separated optical chip solution, the direct wafer-to-glass interposer process is simpler and has higher alignment accuracy, resulting in higher coupling efficiency between the optical chip and the optical waveguide of the interposer. Those skilled in the art can choose appropriate implementation methods according to actual needs, or combine various implementation methods, and such combinations also fall within the protection scope of this disclosure.

[0230] The specific manufacturing methods of the various optical chip packaging structures described above will be described below with reference to Figures 32-36. Figures 32-36 show flowcharts of the manufacturing methods of the optical chip packaging structures of the embodiments disclosed herein.

[0231] It should be noted that the structures and features mentioned in the manufacturing methods described below, such as adapter boards, optical wafers, and electronic wafers, are similar to the various structures or features described in the embodiments of various optical wafer packaging structures above. For the sake of simplicity, repeated descriptions of these structures or features may be omitted in some cases. In such cases, the various structures or features involved in the manufacturing methods described below should not be interpreted narrowly.

[0232] Furthermore, in the following description of the manufacturing method of the optical chip package structure, in order to avoid repetition, some process steps shown in other diagrams will be referenced in certain processes. In this case, the various steps involved in the manufacturing method described above should not be interpreted narrowly.

[0233] Figure 32 shows a flowchart of a method 3200 corresponding to the optical wafer packaging structure 1200 shown in Figures 12A-12B.

[0234] As shown in Figure 32, method 3200 includes: providing an adapter plate (step S3210) and attaching a plurality of optical wafers to different positions on the upper surface of the adapter plate (step S3220). For example, the adapter plate may be adapter plate 1210 as shown in Figure 12A, and the plurality of optical wafers may be PIC 1 to PIC 6 as shown in Figure 12B.

[0235] For example, the adapter board may include one or more first optical waveguides (such as optical waveguides WG1-1 and WG1-2 shown in Figure 12A), and each first optical waveguide includes a first optical coupling portion. Each optical chip may include one or more second optical waveguides (such as optical waveguides WG2-1 and WG2-2 shown in Figure 12A), and each of the aforementioned second optical waveguides includes a second optical coupling portion.

[0236] For example, the first optical coupling portion and the second optical coupling portion described above are respectively conical shapes as shown above with respect to Figure 14. Optionally, the first optical coupling portion and the second optical coupling portion may also each have a shape formed by connecting two conical shapes of different sizes as shown above with respect to Figure 19.

[0237] As mentioned above with respect to Figure 13, the first optical coupling part and the second optical coupling part are stacked in a direction perpendicular to the upper surface of the adapter plate and spaced apart by a predetermined distance (e.g., less than or equal to 600 nm), so that the first optical coupling part and the second optical coupling part achieve thermally adiabatic optical coupling, and multiple optical chips are optically interconnected through multiple first optical waveguides.

[0238] Figures 33-35 show flowcharts of the manufacturing method corresponding to the optical chip package structure 2000 shown in Figures 20-21.

[0239] As shown in Figure 33, method 3300 includes: providing an adapter plate (step S3310), configuring an electrical chip on a first optical chip among a plurality of optical chips, such that the first optical chip and the electrical chip thereon form an electron-photon hybrid chip (step S3320), and attaching the plurality of optical chips to different positions on the upper surface of the adapter plate (step S3330).

[0240] Compared to the manufacturing method shown in Figure 32, the method 3300 shown in Figure 33 adds a step S3320 for forming an electron-photon hybrid wafer. It should be noted that the term "electron-photon hybrid wafer" here does not mean using wafers other than the aforementioned optical and electrical wafers, but can correspond to the overall structure formed by interconnecting PIC 1 and EIC 1 as shown in Figure 20, or the overall structure formed by interconnecting PIC 1 and EIC 1. More precisely, the term "electron-photon hybrid wafer" can correspond to the various wafer structures shown in Figures 22 and 23.

[0241] For example, as shown in Figure 22(a), the PIC together with the EIC disposed thereon can be referred to as an electro-photonic hybrid chiplet or an electro-photonic hybrid chiplet. As shown in Figure 22(a), the upper surface of the PIC has a plurality of first electrical connectors C1, and the lower surface of the EIC has a plurality of second electrical connectors C2, and the PIC and the EIC are directly coupled through the first electrical connectors C1 and the second electrical connectors C2.

[0242] In addition, the electron-photon hybrid chip can also be an integral structure as shown in Figure 22 (b), which includes a PIC and two EICs (D-EIC and A-EIC), and the D-EIC, A-EIC and PIC are directly connected to each other through the first electrical connector C1 and the second electrical connector C2.

[0243] Similarly, the overall structure of the EIC and PIC connected by flip-chip connection as shown in Figure 23 can also be regarded as an electron-photon hybrid chip as described above, and will not be repeated here.

[0244] Figures 34 and 35 show two different methods for configuring electronic wafers on the first optical wafer among the plurality of optical wafers to form an electron-photon hybrid wafer. The process steps in Figures 34 and 35 can be regarded as subdivisions of step S3320 in Figure 33.

[0245] As shown in Figure 34, configuring an electronic wafer on the first optical wafer among the plurality of optical wafers includes: preparing a photonic wafer and an electronic wafer (step S3410), directly bonding the electronic wafer to the photonic wafer (step S3420), removing the substrate of the photonic wafer (step S3430), and cutting the electronic-photonic hybrid wafer into a plurality of electronic-photonic hybrid wafers (step S3440).

[0246] In some examples, the photonic wafer prepared in step S3410 may be similar to the photonic wafer PWF described with respect to Figure 29A, which includes a plurality of optical wafers PIC 1-PIC 6, and the plurality of optical wafers PIC 1-PIC 6 include a plurality of first optical wafers for configuring corresponding electronic wafers thereon. Similarly, the electronic wafer prepared in step S3410 may be similar to the electronic wafer EWF described with respect to Figure 29A, which includes a plurality of electronic wafers (e.g., EIC 1, EIC 2, EIC 5, EIC 6).

[0247] In some examples, for instance, an electron-photonic hybrid wafer can be obtained by bonding the plurality of first optical wafers with the plurality of electrical wafers (e.g., by direct bonding), and then in step S3440 the electron-photonic hybrid wafer is cut into a plurality of electron-photonic hybrid wafers.

[0248] It should be noted that although the specific structures of photonic wafers and electronic wafers have been illustrated above in conjunction with Figure 29A, this is merely for ease of description. In reality, Figure 29A shows that the PWF and EWF do not need to be divided into separate electronic-photonic hybrid wafers; they are directly bonded together and configured as a whole on the adapter board. However, it should be mentioned that although it is not necessary to cut the bonded PWF and EWF into independent electronic-photonic hybrid wafers, it is necessary to remove redundant wafers at the edges for packaging purposes, for example, by cutting them into an internal square shape as shown in Figure 31A or 31B.

[0249] Figure 35 shows another method for forming an electron-photonic hybrid wafer. As shown in Figure 35, configuring an electronic wafer on a first optical wafer among a plurality of optical wafers may specifically include: preparing a photonic wafer and an electronic wafer (step S3510), dicing the electronic wafer into the plurality of electronic wafers (step S3520), directly bonding or flip-chip bonding one or more of the plurality of electronic wafers to the first optical wafer in the photonic wafer to obtain an electron-photonic hybrid wafer (step S3530), filling the gaps on the photonic wafer not occupied by the electronic wafers with a molding material (step S3540), removing the substrate of the photonic wafer (step S3550), and dicing the electron-photonic hybrid wafer into the electron-photonic hybrid wafer (step S3560).

[0250] Similarly, the photonic wafer prepared in step S3510 may be similar to the photonic wafer PWF described with respect to Figure 29A, which includes a plurality of optical wafers PIC 1-PIC 6, and the plurality of optical wafers PIC 1-PIC 6 include a plurality of first optical wafers for mounting corresponding electronic wafers thereon. Similarly, the electronic wafer prepared in step S3510 may be similar to the electronic wafer EWF described with respect to Figure 29A, which includes a plurality of electronic wafers (e.g., EIC 1, EIC 2, EIC 5, EIC 6).

[0251] Unlike method 3400, in method 3500, the electronic wafer including multiple electronic chips is not integrally bonded to the photonic wafer. Instead, it is first cut into multiple separate electronic chips in step S3520, and then in step S3530, the individual electronic chips obtained are directly bonded or flip-chip bonded to the first photonic chip in the photonic wafer to obtain an electronic-photonic hybrid wafer.

[0252] Since each electronic chip is a separate electronic chip, rather than located on the same electronic wafer as described in method 3400, after the corresponding electronic chips are configured on the first optical wafer, the gaps on the photonic wafer not occupied by the electronic chips are filled with molding material to enhance the mechanical strength and stability of the photonic wafer.

[0253] It should also be noted that although the specific structures of photonic wafers and electronic wafers have been described above in conjunction with Figure 29A, this is merely for ease of description. In reality, Figure 29A shows that the PWF and EWF do not need to be divided into separate electronic-photonic hybrid wafers; they are directly bonded together and configured as a whole on the adapter board. However, it should be mentioned that although it is not necessary to cut the bonded PWF and EWF into independent electronic-photonic hybrid wafers, it is necessary to remove redundant wafers at the edges for packaging purposes, for example, by cutting them into an internal square shape as shown in Figure 31A or Figure 31B.

[0254] Furthermore, the above method 3400 or 3500 may also include: after removing the substrate of the photonic wafer and before dicing the electron-photonic hybrid wafer into the electron-photonic hybrid wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness (not shown in the figure). When an optical waveguide has already been fabricated in the photonic wafer, the thinning operation described above is to reduce the thickness of the buried oxide layer on the bottom surface of the optical waveguide in the optical wafer, thereby allowing the optical waveguide in the optical wafer to be as close as possible to the optical waveguide in the adapter plate, thus increasing the coupling efficiency.

[0255] The spacing between the optical waveguide in the optical chip and the optical waveguide in the adapter plate can be less than or equal to 600 nm through the thinning operation described above, as shown in Figure 13.

[0256] In addition, the above method 3400 or 3500 may further include: after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer, and forming a connecting waveguide on the surface of the photonic wafer away from the electronic wafer; and covering the connecting waveguide with a dielectric to coat the connecting waveguide, wherein the connecting waveguide and the second optical coupling portion of the second optical waveguide in the optical wafer and the first optical coupling portion of the first optical waveguide in the adapter plate are stacked and spaced apart in the vertical direction of the lower surface of the photonic wafer (not shown in the figure), and the first optical waveguide, the connecting waveguide, and the second connecting waveguide perform optical communication through thermal coupling of light. By forming a connecting waveguide in the photonic wafer in the above manner, and then covering the connecting waveguide with a dielectric to coat the connecting waveguide, the purpose is also to increase the coupling efficiency by adding a connecting waveguide between the optical waveguide in the optical wafer and the optical waveguide in the adapter plate.

[0257] In some examples, the above method 3400 or 3500 may further include: after fabricating the photonic wafer, forming one or more second conductive vias in the photonic wafer; and after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness, so that the one or more second conductive vias are vertically connected to form one or more second conductive vias (not shown in the figures). For example, the second conductive vias formed by the above method may be TDVs on the PIC as shown in Figure 22 or Figure 23, which are used to electrically connect the EIC chip to the adapter board.

[0258] For example, in some examples, attaching multiple optical wafers to different positions on the upper surface of the adapter plate further includes electrically connecting the aforementioned one or more second conductive vias to one or more conductive structures in the adapter plate. The one or more conductive structures in the adapter plate may be the first conductive structure 102-3 in the adapter plate 100 as shown in Figure 1, the first conductive structure 202-3 in the adapter plate 200 as shown in Figure 2, or the third conductive structure 304-3 in the adapter plate 400 as shown in Figure 4. Specific details regarding the electrical connection of the one or more second conductive vias in the optical wafers to the one or more conductive structures in the adapter plate can be found in Figure 24 or Figure 25, showing the connection method between the TDV and the conductive structure CC, and will not be repeated here.

[0259] Returning to method 3300, after attaching multiple optical chips to different positions on the upper surface of the adapter plate, multiple electron-photon hybrid chips are spaced apart from each other on the upper surface of the adapter plate. Since gaps still exist between the different electron-photon hybrid chips at this time, it is necessary to fill these gaps with molding material to enhance the stability and mechanical strength of the package.

[0260] However, since the dielectric layer (e.g., silicon oxide layer) covering the waveguides (e.g., WG1-1 as shown in Figure 24 or 25) in the adapter plate is very thin, the thin silicon oxide layer can cause light to leak out during transmission, resulting in light loss, when the optical signal is transmitted between the waveguides of different optical wafers. Therefore, a dielectric layer can be prepared in the gaps of the adapter plate where the optical wafers are not attached before molding to block the outward transmission of light in the adapter plate. Preferably, the material of this dielectric layer is the same as the material of the dielectric layer covering the waveguides in the adapter plate, and the same process is used.

[0261] Therefore, method 3300 may further include: before filling the gaps between the optical wafers with a molding material, forming a dielectric layer (not shown) on the upper surface of the adapter plate and in the gaps between the plurality of electron-photon hybrid wafers to block the outward transmission of light in the adapter plate. The material of this dielectric layer may also be silicon oxide, and it may have a predetermined thickness, such as several micrometers, to ensure that light transmitted in the waveguides between the different optical wafers does not leak outward.

[0262] The above description, in conjunction with Figures 33-35, describes the manufacturing method of the optical chip package structure corresponding to Figures 12A-12B and Figures 20-21, wherein the packaged multiple optical chips and multiple electronic chips are separate from each other, i.e., not on the same wafer. The following description, in conjunction with the figures, describes the manufacturing method of the optical chip package structure corresponding to Figures 26-29, in which multiple optical chips or multiple electronic chips are located on the same photonic wafer or the same electronic wafer.

[0263] The method shown in Figure 36 corresponds to the manufacturing method of the optical wafer package structure 2600 shown in Figures 26-27.

[0264] As shown in Figure 36, method 3600 includes: providing an adapter plate (step S3610), fabricating a photonic wafer (step S3620), and directly bonding the photonic wafer to the upper surface of the adapter plate (step S3630). The adapter plate may be similar to any of the adapter plates described above, and will not be repeated here. The fabricated photonic wafer includes multiple optical wafers, and the photonic wafer is connected to the adapter plate by a direct bonding method.

[0265] The method shown in Figure 37 corresponds to the manufacturing method of the optical wafer package structure 2800 shown in Figures 28-29.

[0266] As shown in Figure 37, method 3700 includes: providing an adapter plate (step S3710), preparing a photonic wafer and an electronic wafer (step S3720), directly bonding the electronic wafer to the photonic wafer, such that a plurality of first optical wafers are bonded to a plurality of electronic wafers to obtain an electronic-photonic hybrid wafer (step S3730), and directly bonding the photonic wafer to the upper surface of the adapter plate (step S3740). Similarly, the adapter plate may be similar to any of the adapter plates described above. The prepared photonic wafer includes a plurality of optical wafers, and the prepared electronic wafer may include a plurality of electronic wafers. The electronic wafer is directly bonded to the photonic wafer such that a specific optical wafer (i.e., the first optical wafer as described above) in the photonic wafer is bonded to a plurality of electronic wafers to obtain an electronic-photonic hybrid wafer. Furthermore, the photonic wafer is connected to the adapter plate by a direct bonding method.

[0267] The steps described above regarding Figures 32-35, such as removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness, configuring and covering the connecting waveguide in the photonic wafer, and forming one or more second conductive holes in the photonic wafer, are also applicable to the methods described regarding Figures 36-37, unless otherwise stated or clearly unsuitable.

[0268] The manufacturing methods of various optical chip packaging structures in the embodiments disclosed herein have been described above. It should be noted that the steps in the manufacturing methods described above in conjunction with the flowcharts are merely exemplary, and the order of the steps shown in the flowcharts is not necessarily fixed. Those skilled in the art can adjust the order of the steps, or omit or add additional steps based on their knowledge of the design concept of this application. Methods obtained through such adjustments, omissions, or additions of steps also fall within the protection scope of this application.

[0269] In the foregoing description, embodiments of the present disclosure have been described in conjunction with the accompanying drawings. It should be understood that the above embodiments are merely illustrative, and those skilled in the art to which this invention pertains should understand that the combination of constituent elements and processes of the present embodiments can be modified in various ways, and such modifications also fall within the scope of this disclosure. [Simplified Explanation of the Diagram]

[0076] Figure 1 shows a cross-sectional view of a first example of an adapter board for optical wafer packaging according to an embodiment of the present disclosure. Figure 2 shows a cross-sectional view of a second example of an adapter board for optical wafer packaging according to an embodiment of the present disclosure. Figure 3 shows a cross-sectional view of a third example of an adapter board for optical wafer packaging according to an embodiment of the present disclosure. Figure 4 shows a cross-sectional view of a fourth example of an adapter board for optical wafer packaging according to an embodiment of the present disclosure. Figure 5 shows a process flow diagram of a method for manufacturing the adapter board in the first example of an embodiment of the present disclosure. Figure 6 shows a process flow diagram of a method for manufacturing the adapter board in the second example of an embodiment of the present disclosure. Figure 7A shows a process flow diagram of a method for manufacturing the adapter board in the third example of an embodiment of the present disclosure. Figure 7B shows a process flow diagram of a method for manufacturing the adapter board in the fourth example of an embodiment of the present disclosure. Figure 8 shows a cross-sectional view of an optical wafer packaging structure incorporating the adapter board in the first example of an embodiment of the present disclosure. Figure 9 shows a cross-sectional view of an optical wafer packaging structure incorporating the adapter board in the second example of an embodiment of the present disclosure. Figure 10 shows a cross-sectional view of the optical chip package structure integrating the adapter board in the third example of the embodiments disclosed herein. Figure 11 shows a cross-sectional view of the optical chip package structure integrating the adapter board in the fourth example of the embodiments disclosed herein. Figures 12A and 12B show a cross-sectional view and a top view of the optical chip package structure of the embodiments disclosed herein, respectively. Figures 13 and 14 show a schematic side view and a top view of the optical coupling portion in the optical chip package structure of the embodiments disclosed herein, and a corresponding optical mode field diagram. Figure 15 shows a graph of the optical transmission rate of the optical coupling portion in the optical chip package structure of the embodiments disclosed herein at different lengths. Figure 16 shows a graph of the optical transmission rate of the optical coupling portion in the optical chip package structure of the embodiments disclosed herein at different spacings. Figure 17 shows a graph of the optical transmission rate of the optical coupling portion in the optical chip package structure of the embodiments disclosed herein at different thicknesses. Figures 18 and 19 show another schematic side view and a top view of the optical coupling portion in the optical chip package structure of the embodiments disclosed herein, and a corresponding optical mode field diagram, respectively. Figures 20 and 21 show a cross-sectional view and a top view of the optical chip packaging structure according to an embodiment of the present disclosure, respectively. Figure 22 shows a cross-sectional view of the optical chip and electronic chip in the optical chip packaging structure according to an embodiment of the present disclosure. Figure 23 shows a cross-sectional view of the optical chip and electronic chip in the optical chip packaging structure according to an embodiment of the present disclosure. Figure 24 shows a cross-sectional view of the optical chip packaging structure according to an embodiment of the present disclosure. Figure 25 shows a cross-sectional view of the optical chip packaging structure according to an embodiment of the present disclosure. Figures 26 and 27 show a cross-sectional view and a top view of the optical chip packaging structure according to an embodiment of the present disclosure, respectively. Figures 28 and 29A-29B show a cross-sectional view and a top view of the optical chip packaging structure according to an embodiment of the present disclosure, respectively.Figure 30 shows a schematic diagram of a computing accelerator according to an embodiment of the present disclosure. Figure 31A shows a schematic diagram of another computing accelerator according to an embodiment of the present disclosure. Figure 31B shows a schematic diagram of yet another computing accelerator according to an embodiment of the present disclosure. Figures 32-37 show flowcharts of a method for manufacturing an optical chip packaging structure according to an embodiment of the present disclosure.

Claims

1. An adapter board for optical chip packaging, comprising: A glass substrate includes one or more conductive vias, each conductive via including a through-hole extending through the glass substrate and a conductive material filling the through-hole; and an optical waveguide structure disposed on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a coating layer covering the one or more optical waveguides, the one or more optical waveguides being used for optical interconnection of multiple optical chips packaged on the adapter board, and the refractive index of the one or more optical waveguides being greater than the refractive index of the coating layer and the glass substrate, and the optical waveguide structure further includes one or more first conductive structures extending through the optical waveguide structure, which are electrically connected to the one or more conductive vias respectively.

2. The adapter board as claimed in claim 1, wherein the one or more optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.

3. The adapter board described in request item 1 further includes: A dielectric layer is disposed on the second surface of the glass substrate; and one or more conductive bumps are disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

4. An adapter board for optical chip packaging, comprising: A glass substrate includes one or more conductive vias, each conductive via including a through-hole extending through the glass substrate and a conductive material filling the through-hole; and an optical coupling structure disposed on a first surface of the glass substrate. The glass substrate further includes a three-dimensional waveguide network for optical interconnection of multiple optical wafers packaged on the adapter board. The optical coupling structure includes a coupling optical waveguide covering the optical input / output port of the three-dimensional waveguide network and a coating layer covering the coupling optical waveguide. The optical coupling structure also includes one or more first conductive structures extending through the optical coupling structure, which are electrically connected to the one or more conductive vias.

5. The adapter plate as claimed in claim 4, wherein the refractive index of the coupled optical waveguide is lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer.

6. The adapter board as described in claim 5, wherein the coupled optical waveguide is a silicon nitride optical waveguide and the cladding layer is made of silicon dioxide.

7. The adapter board as described in claim 4 further includes: A dielectric layer is disposed on the second surface of the glass substrate; one or more conductive bumps are disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

8. The adapter board as described in claim 4, wherein: The aforementioned three-dimensional waveguide network is a network structure formed by inducing local glass within the aforementioned glass substrate to increase the refractive index of the local glass.

9. An adapter board for optical chip packaging, comprising: A glass substrate includes one or more first conductive vias, each first conductive via comprising a via penetrating the glass substrate and a conductive material filling the via; and an electrical interconnect structure disposed on a first surface of the glass substrate, wherein the electrical interconnect structure comprises one or more wiring layers and a covering layer covering the one or more wiring layers, the covering layer being a dielectric material, the one or more wiring layers being used for electrically interconnecting a plurality of electrical chips packaged above the adapter board, and the electrical interconnect structure further includes one or more first conductive structures penetrating the electrical interconnect structure, which are electrically connected to the one or more first conductive vias respectively.

10. The adapter board as claimed in claim 9, wherein at least two of the aforementioned multilayer wiring layers are electrically connected through a second conductive structure.

11. The adapter plate as claimed in claim 9, wherein the aforementioned coating layer is a multilayer structure formed by alternating stacks of silicon nitride layers and silicon dioxide layers.

12. The adapter board as described in claim 9, further comprising: An optical waveguide structure is disposed on the surface of the electrical interconnect structure away from the glass substrate. The optical waveguide structure includes one or more optical waveguides and a surrounding layer that surrounds the one or more optical waveguides. The one or more optical waveguides are used to perform optical interconnection on a plurality of optical wafers packaged on the adapter board. The refractive index of the waveguides is greater than that of the surrounding layer. The optical waveguide structure also includes one or more third conductive structures that penetrate the optical waveguide structure and are electrically connected to the one or more first conductive structures respectively.

13. The adapter board as claimed in claim 12, wherein the one or more optical waveguides are silicon nitride optical waveguides, and the material of the surrounding layer is silicon dioxide.

14. The adapter board as described in claim 9, further comprising: A dielectric layer is disposed on the second surface of the glass substrate; one or more conductive bumps are disposed on the surface of the dielectric layer away from the glass substrate, wherein the dielectric layer includes one or more fourth conductive structures penetrating the dielectric layer, which are electrically connected to one or more first conductive vias respectively, and the one or more conductive bumps are electrically connected to one or more fourth conductive structures respectively.

15. A method for manufacturing an adapter board for optical chip packaging, comprising: A glass substrate is provided, and one or more conductive vias are formed in the glass substrate; an optical waveguide structure is disposed on a first surface of the glass substrate, wherein the optical waveguide structure includes one or more optical waveguides and a coating layer covering the one or more optical waveguides; and one or more first conductive structures penetrating the optical waveguide structure are formed in the coating layer and electrically connected to the one or more conductive vias respectively, wherein the refractive index of the one or more optical waveguides is greater than the refractive index of the coating layer.

16. A method for manufacturing an adapter board as claimed in claim 15, wherein the one or more optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.

17. A method for manufacturing an adapter board as described in claim 16, wherein, The optical waveguide structure is disposed on the first surface of the glass substrate by: a. forming an optical waveguide network on the first surface of the glass substrate using wafer-level nanoimprint lithography; and b. depositing a coating material over the optical waveguide.

18. The method of manufacturing the adapter board as described in claim 15 further includes: A dielectric layer is disposed on the second surface of the glass substrate; one or more second conductive structures are formed in the dielectric layer and electrically connected to the one or more conductive vias respectively; and one or more conductive bumps are disposed on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

19. A method for manufacturing an adapter board as described in claim 15, wherein, Forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias by depositing a conductive material layer on the inner surface of the one or more vias.

20. A method for manufacturing an adapter board as described in claim 19, wherein, The formation of the one or more conductive vias by providing the conductive material layer on the inner surface of the vias includes: filling the inner surface of the one or more vias with conductive metal by electroplating.

21. A method for manufacturing an adapter board for optical chip packaging, comprising: A glass substrate is provided, and a three-dimensional waveguide network is formed within the glass substrate for optical interconnection of multiple optical chips packaged on the adapter board; one or more conductive vias are formed in the glass substrate; a coupling optical waveguide is disposed on a first surface of the glass substrate to cover the optical input / output port of the three-dimensional waveguide network; a coating layer is covered on the coupling optical waveguide to cover the coupling optical waveguide; and one or more first conductive structures are formed through the coating layer and electrically connected to the one or more conductive vias respectively.

22. A method for manufacturing an adapter board as described in claim 21, wherein, The refractive index of the aforementioned coupled optical waveguide is lower than that of the aforementioned three-dimensional waveguide network but higher than that of the aforementioned cladding layer.

23. A method for manufacturing an adapter board as described in claim 22, wherein, The aforementioned coupled optical waveguide is a silicon nitride optical waveguide, and the aforementioned cladding layer is made of silicon dioxide.

24. The method of manufacturing the adapter board as described in claim 21 further includes: A dielectric layer is disposed on the second surface of the glass substrate; one or more second conductive structures are formed in the dielectric layer and electrically connected to the one or more conductive vias respectively; and one or more conductive bumps are disposed on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more second conductive structures respectively.

25. A method for manufacturing an adapter board as described in claim 21, wherein, Forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias by depositing a conductive material layer on the inner surface of the one or more vias.

26. A method for manufacturing an adapter board as described in claim 25, wherein, The formation of the one or more conductive vias by providing the conductive material layer on the inner surface of the vias includes: filling the inner surface of the one or more vias with conductive metal by electroplating.

27. A method for manufacturing an adapter board as described in claim 21, wherein, Forming the three-dimensional waveguide network within the glass substrate includes: irradiating a predetermined position on the glass substrate with a femtosecond laser to increase the refractive index of the predetermined position on the glass substrate, wherein the predetermined position is the location where the three-dimensional waveguide network structure is formed.

28. A method for manufacturing an adapter board for optical chip packaging, comprising: A glass substrate is provided, and one or more first conductive vias are formed in the glass substrate; an electrical interconnect structure is disposed on a first surface of the glass substrate, wherein the electrical interconnect structure includes one or more wiring layers and a covering layer covering the one or more wiring layers, the covering layer being a dielectric material, the one or more wiring layers being used to electrically interconnect a plurality of electronic chips packaged above the adapter plate; and one or more first conductive structures are formed in the electrical interconnect structure penetrating the electrical interconnect structure, which are electrically connected to the one or more first conductive vias respectively.

29. A method for manufacturing an adapter board as described in claim 28, wherein, The electrical interconnect structure is disposed on the first surface of the glass substrate by: disposing a first wiring layer on the first surface of the glass substrate; forming a first silicon nitride layer around the first wiring layer; and covering the first silicon nitride layer with a first silicon oxide layer.

30. A method for manufacturing an adapter board as described in claim 29, wherein, The provision of the electrical interconnect structure on the first surface of the glass substrate further includes: providing a second wiring layer on the first surface of the first silicon oxide layer; forming a second silicon nitride layer around the second wiring layer; and covering the second silicon nitride layer with a second silicon oxide layer.

31. A method for manufacturing an adapter board as described in claim 30, wherein, The provision of the electrical interconnect structure on the first surface of the glass substrate further includes: forming a second conductive structure between the first wiring layer and the second wiring layer to electrically connect the first wiring layer and the second wiring layer.

32. The method of manufacturing the adapter board as described in claim 28 further includes: An optical waveguide structure is disposed on the surface of the electrical interconnect structure away from the glass substrate. The optical waveguide structure includes one or more optical waveguides and a surrounding layer that surrounds the one or more optical waveguides. The one or more optical waveguides are used to perform optical interconnection on a plurality of optical wafers packaged on the adapter board. The refractive index of the waveguides is greater than that of the surrounding layer. One or more third conductive structures are formed in the optical waveguide structure and electrically connected to the one or more first conductive structures respectively.

33. The method of manufacturing the adapter board as claimed in claim 32, wherein the one or more optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.

34. The method of manufacturing the adapter board as described in claim 28 further includes: A dielectric layer is disposed on the second surface of the glass substrate; one or more fourth conductive structures are formed in the dielectric layer and electrically connected to the one or more first conductive vias respectively; and one or more conductive bumps are disposed on the surface of the dielectric layer away from the glass substrate, wherein the one or more conductive bumps are electrically connected to the one or more fourth conductive structures respectively.

35. A method for manufacturing an adapter board as described in claim 28, wherein, Forming one or more conductive vias in a glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias by depositing a conductive material layer on the inner surface of the one or more vias.

36. A method for manufacturing an adapter board as described in claim 35, wherein, The formation of the one or more conductive vias by providing the conductive material layer on the inner surface of the vias includes: filling the inner surface of the one or more vias with conductive metal by electroplating.

37. An optical chip package structure, comprising an adapter board as described in any one of claims 1-14, and the plurality of optical chips disposed on the adapter board, the adapter board being used for optical interconnection and / or electrical interconnection of the plurality of optical chips disposed on the adapter board.

38. The optical chip packaging structure as described in claim 37 further includes: One or more electrical wafers disposed on the aforementioned plurality of optical wafers; The aforementioned optical wafer includes one or more interconnect structures, each interconnect structure including a via penetrating the optical wafer and a conductive material filling the via; the aforementioned one or more interconnect structures are electrically connected to the aforementioned one or more first conductive structures and / or the aforementioned one or more electrical interconnect structures on the aforementioned adapter board, respectively.

39. A photoelectric chip packaging structure, comprising: An adapter board includes one or more first optical waveguides embedded therein; and a plurality of optical chips, each optical chip including one or more second optical waveguides embedded therein. The plurality of optical chips are attached to different positions on the upper surface of the adapter board and are optically interconnected through the one or more first optical waveguides. Each first optical waveguide includes a first optical coupling portion, each second optical waveguide includes a second optical coupling portion, and the first optical coupling portion and the second optical coupling portion are stacked in a direction perpendicular to the upper surface of the adapter board and spaced apart by a predetermined distance, such that the first optical coupling portion and the second optical coupling portion achieve thermally adiabatic optical coupling.

40. The optical chip packaging structure as described in claim 39, wherein, The first optical coupling part and the second optical coupling part are both tapered in shape.

41. The optical chip packaging structure as described in claim 39, wherein, The first optical coupling part and the second optical coupling part are respectively formed by two conical shapes of different sizes connected in series.

42. The optical chip packaging structure as described in any one of claims 39 to 41, wherein, The aforementioned predetermined distance is less than or equal to 600 nm.

43. The optical chip packaging structure as described in claim 39 further includes: Multiple electrical wafers are disposed on multiple first optical wafers among the multiple optical wafers, wherein each first optical wafer has one or more first electrical connectors on its upper surface and each electrical wafer has one or more second electrical connectors on its lower surface, and the one or more first electrical connectors are respectively electrically connected to the one or more second electrical connectors.

44. The optical chip packaging structure as described in claim 43, wherein, The first optical chip also includes one or more second conductive vias passing through it, and the one or more second conductive vias are electrically connected to one or more conductive structures in the adapter plate, respectively.

45. The optical chip packaging structure as described in claim 43 or 44, wherein, The first optical chip is directly bonded to the electrical chip; or the first optical chip and the electrical chip are bonded together via flip-chip bonding.

46. ​​The optical chip packaging structure as described in any one of claims 39 to 44, wherein, The aforementioned multiple optical wafers are split optical wafers obtained after slicing photonic wafers. They are spaced apart from each other on the upper surface of the aforementioned adapter plate, and the gaps between them are filled by a molding material. A dielectric layer for blocking the outward transmission of light in the aforementioned adapter plate is disposed between the molding material and the aforementioned upper surface of the aforementioned adapter plate.

47. The optical chip packaging structure as described in any one of claims 39 to 44, wherein, The aforementioned multiple optical chips are multiple undivided optical chips within the same photonic wafer.

48. The optical chip packaging structure as described in claim 43 or 44, wherein, The aforementioned multiple optical chips are undivided optical chips within the same photonic wafer. The aforementioned multiple optical chips include multiple first optical chips, each of which is equipped with an electrical chip. The multiple electrical chips on the aforementioned multiple first optical chips are undivided electrical chips within the same electronic wafer, and the aforementioned photonic wafer is directly bonded to the aforementioned electronic wafer.

49. The optical chip packaging structure as described in claim 48, wherein, All of the aforementioned optical chips are equipped with corresponding electrical chips, and the corresponding electrical chips on all the optical chips are multiple undivided electrical chips in the same electronic wafer. Furthermore, the aforementioned optical chips have the same structure, and the aforementioned electrical chips also have the same structure.

50. The optical chip packaging structure as described in any one of claims 39 to 49, wherein, The aforementioned adapter board is the adapter board as described in any one of claims 1-3 and claims 12-14, and the aforementioned one or more first optical waveguides are one or more optical waveguides in the aforementioned optical waveguide structure of the adapter board as described in any one of claims 1-3 and claims 12-14.

51. The optical chip packaging structure as described in any one of claims 39 to 49, wherein, The aforementioned adapter board is the adapter board as described in any one of claims 4-8, and the aforementioned one or more first optical waveguides are the aforementioned three-dimensional waveguide network in the adapter board as described in any one of claims 4-8 and the aforementioned coupled optical waveguides covering the aforementioned optical input / output ports of the aforementioned three-dimensional waveguide network.

52. A computing accelerator, comprising: One or more light sources are disposed on the first surface of the adapter plate in the optical wafer package structure as described in any one of claims 43-46 and are configured to provide light waves to the computing accelerator; one or more computing units are implemented by the optical wafer in the optical wafer package structure as described in any one of claims 39-42, or by the optical wafer and the electrical wafer in the optical wafer package structure as described in any one of claims 43-46, or by the electrical wafer in the optical wafer package structure as described in any one of claims 43-46, and are configured to perform computing functions; one or more memory units are implemented by the electrical wafer in the optical wafer package structure as described in any one of claims 43-46 and are configured to perform memory functions.

53. The computing accelerator as described in claim 52, wherein, The aforementioned adapter board is the adapter board as described in any one of claims 1-8 and 12-14.

54. A computing accelerator, comprising: One or more edge optical couplers configured to optically interconnect the aforementioned computing accelerator with other devices; One or more light sources are configured to provide light waves to the aforementioned computing accelerator, the light waves being coupled to the aforementioned one or more edge optical couplers through a light guide structure; one or more computing units are implemented by the aforementioned optical wafer in the optical wafer package structure as described in any one of claims 39-42, or by the aforementioned optical wafer and the aforementioned electrical wafer in the optical wafer package structure as described in any one of claims 47-49, or by the aforementioned electrical wafer in the optical wafer package structure as described in any one of claims 47-49, and are configured to perform computing functions; and one or more memory units are implemented by the aforementioned electrical wafer in the optical wafer package structure as described in any one of claims 47-49, and are configured to perform memory functions.

55. The computing accelerator as described in claim 54, wherein, Each computing unit and its corresponding memory unit are implemented by each optical chip and its corresponding electrical chip in the optical chip packaging structure as described in claim 49, serving as a computing-memory unit.

56. The computing accelerator as described in claim 54 or 55, wherein, The aforementioned adapter board in the optical chip packaging structure is the adapter board as described in any one of claims 1-8 and 12-14.

57. The computing accelerator described in any of claims 52 to 56 further includes: Multiple high-bandwidth memory (HBM) chips stacked on the aforementioned optical chip in the aforementioned optical chip packaging structure are configured to perform memory computing functions.

58. A method for manufacturing an optical chip packaging structure, comprising: An adapter board is provided, comprising one or more first optical waveguides embedded therein, each of the first optical waveguides including a first optical coupling portion; and a plurality of optical wafers are attached to different positions on the upper surface of the adapter board, each optical wafer including one or more second optical waveguides embedded therein, each of the second optical waveguides including a second optical coupling portion, wherein the first optical coupling portion and the second optical coupling portion are stacked in a direction perpendicular to the upper surface of the adapter board and spaced apart by a predetermined distance, such that the first optical coupling portion and the second optical coupling portion achieve thermally adiabatic optical coupling, and the plurality of optical wafers are optically interconnected through the one or more first optical waveguides.

59. A method for manufacturing an optical chip packaging structure as described in claim 58, wherein, The first optical coupling part and the second optical coupling part are both tapered in shape.

60. A method for manufacturing an optical chip packaging structure as described in claim 58, wherein, The first optical coupling part and the second optical coupling part are respectively formed by two conical shapes of different sizes connected in series.

61. A method for manufacturing an optical chip packaging structure as described in any one of claims 58 to 60, wherein, The aforementioned predetermined distance is less than or equal to 600 nm.

62. The method for manufacturing an optical chip package structure as described in claim 58, further comprising, before attaching the plurality of optical chips to different positions on the upper surface of the adapter plate: An electrical chip is disposed on the first optical chip among the plurality of optical chips, such that the first optical chip and the electrical chip thereon form an electron-photon hybrid chip. The upper surface of the first optical chip has one or more first electrical connectors, and the lower surface of the electrical chip has one or more second electrical connectors. The one or more first electrical connectors are electrically connected to the one or more second electrical connectors respectively.

63. A method for manufacturing an optical chip packaging structure as described in claim 62, wherein, The method of configuring the electronic wafer on the first optical wafer among the plurality of optical wafers includes: preparing a photonic wafer and an electronic wafer, wherein the photonic wafer includes a plurality of first optical wafers and the electronic wafer includes a plurality of electronic wafers; directly bonding the electronic wafer to the photonic wafer, such that the plurality of first optical wafers are bonded to the plurality of electronic wafers to obtain an electron-photonic hybrid wafer; removing the substrate of the photonic wafer; and dicing the electron-photonic hybrid wafer into a plurality of electron-photonic hybrid wafers.

64. A method for manufacturing an optical chip packaging structure as described in claim 62, wherein, The arrangement of the electronic wafers on the first optical wafer among the plurality of optical wafers includes: preparing a photonic wafer and an electronic wafer, wherein the photonic wafer includes the plurality of optical wafers and the electronic wafer includes the plurality of electronic wafers; dicing the electronic wafer into the plurality of electronic wafers; directly bonding or flip-chip bonding one or more of the plurality of electronic wafers to the first optical wafer in the photonic wafer to obtain an electron-photonic hybrid wafer; filling the gaps on the photonic wafer not occupied by the electronic wafers with a molding material; removing the substrate of the photonic wafer; and dicing the electron-photonic hybrid wafer into the electron-photonic hybrid wafers.

65. The method for manufacturing the optical wafer packaging structure as described in claim 59 or 64 further includes: After removing the substrate of the aforementioned photonic wafer, and before dicing the aforementioned electron-photonic hybrid wafer into the aforementioned electron-photonic hybrid wafer, the buried oxide layer on the bottom surface of the aforementioned photonic wafer is thinned to a predetermined thickness.

66. The method for manufacturing the optical wafer packaging structure as described in claim 63 or 64 further includes: After removing the substrate of the photonic wafer, the buried oxide layer on the bottom surface of the photonic wafer is thinned, and a connecting waveguide is formed on the surface of the photonic wafer away from the electronic chip. The connecting waveguide, the second optical coupling portion of the second optical waveguide, and the first optical coupling portion of the first waveguide are stacked and spaced apart in the vertical direction of the lower surface of the photonic wafer. A dielectric material is then applied to the connecting waveguide to cover it.

67. The method for manufacturing an optical wafer packaging structure as described in claim 63 or 64 further includes: After fabricating the aforementioned photonic wafer, one or more second conductive holes are formed in the aforementioned photonic wafer; After removing the substrate of the photonic wafer, the buried oxide layer on the bottom surface of the photonic wafer is thinned to a predetermined thickness, so that the one or more second conductive holes are connected vertically to form one or more second conductive vias.

68. A method for manufacturing an optical chip packaging structure as described in claim 66, wherein, The process of attaching the plurality of optical wafers to different positions on the upper surface of the adapter plate further includes: electrically connecting the one or more second conductive vias to one or more conductive structures in the adapter plate.

69. A method for manufacturing an optical chip packaging structure as described in claim 62, wherein, The plurality of electron-photon hybrid wafers are spaced apart from each other on the upper surface of the adapter plate, and the method further includes: forming a dielectric layer on the upper surface of the adapter plate and in the gaps between the plurality of electron-photon hybrid wafers to block the outward transmission of light in the adapter plate; and filling the dielectric layer and the gaps between the electron-photon hybrid wafers with a molding material.

70. A method for manufacturing an optical chip packaging structure as described in claim 62, wherein, The arrangement of the electronic wafers on the first optical wafer among the plurality of optical wafers includes: fabricating a photonic wafer and an electronic wafer, wherein the photonic wafer includes a plurality of first optical wafers and the electronic wafer includes a plurality of electronic wafers; and directly bonding the electronic wafer to the photonic wafer, such that the plurality of first optical wafers and the plurality of electronic wafers are bonded to obtain an electron-photonic hybrid wafer; and attaching the plurality of optical wafers to different positions on the upper surface of the adapter plate includes: directly bonding the electron-photonic hybrid wafer to the upper surface of the adapter plate.

71. A method for manufacturing an optical chip packaging structure as described in any one of claims 58 to 70, wherein, The aforementioned adapter board is an adapter board manufactured by the method of any one of claims 15-20 and 28-36, and the aforementioned one or more first optical waveguides are one or more optical waveguides in the aforementioned optical waveguide structure of the adapter board manufactured by the method of any one of claims 15-20 and 28-36.

72. A method for manufacturing an optical chip packaging structure as described in any one of claims 58 to 70, wherein, The aforementioned adapter board is an adapter board manufactured by the method described in any one of claims 21-27, and the aforementioned one or more first optical waveguides are the aforementioned three-dimensional waveguide network in the adapter board manufactured by the method described in any one of claims 21-27 and the aforementioned coupled optical waveguides covering the aforementioned optical input / output ports of the aforementioned three-dimensional waveguide network.

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