Photo mask for extreme ultraviolet lithography and an attenuated phase shift mask for extreme ultraviolet lithography

Abstract

A photo mask for an extreme ultraviolet (EUV) lithography includes a circuit pattern, and sub-resolution assist patterns disposed around and connected to the circuit pattern. A dimension of the sub-resolution assist patterns is in a range from

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Optical lithography is a critical operation in semiconductor manufacturing processes. Optical lithography techniques include ultraviolet lithography, deep ultraviolet lithography, and extreme ultraviolet lithography (EUVL). The photomask is a crucial component in optical lithography. Crucially, EUV photomasks are manufactured using high-reflectivity and high-absorption components, resulting in high contrast. [Summary of the Invention]

[0003] None

Implementation Method

[0005] It should be understood that the following disclosure provides many different embodiments or instances for implementing various features of this disclosure. Specific embodiments or instances of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the size of a component is not limited to the disclosed range or values, but may depend on the processing conditions and / or desired nature of the device. Furthermore, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed to be inserted between the first and second features so that the first and second features do not directly contact each other. Various features may be drawn arbitrarily at different scales for simplicity and clarity.

[0006] In addition, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. Furthermore, the term “made of” may mean “comprising” or “consisting of.” In this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean a component from A, a component from B, and a component from C, unless otherwise described. The materials, configurations, processes, and / or dimensions explained with respect to one embodiment may be used in other embodiments, and their detailed description may be omitted. In this disclosure, the terms master photomask, photomask, or veil are used interchangeably.

[0007] Embodiments of this disclosure provide a method for manufacturing an EUV photomask. EUV lithography (EUVL) uses a scanner that uses light in the extreme ultraviolet (EUV) region with a wavelength of about 1 nm to about 100 nm, for example, 13.5 nm. The photomask is a key component of the EUVL system. Because optical materials are not transparent to EUV radiation, the EUV photomask is a reflective screen. Circuit patterns are formed in an absorber layer disposed above the reflective structure.

[0008] The EUV mask includes a binary mask and a phase-shift mask, and the phase-shift mask includes an alternative phase-shift mask and an attenuated phase-shift mask (APSM). In the APSM, some of the light-blocking patterns (absorber layers) are made translucent or semi-reflective, thereby causing a 180° phase change. In some embodiments, the absorber layer of the EUV APSM includes a low-n and low-k EUV absorber layer for EUV light (e.g., 13.5 nm), the absorber layer having a refractive index n of less than about 0.95 (and greater than about 0.8) and an absorption coefficient k of less than about 0.04 (and greater than about 0.005). In some embodiments, the reflectivity of absorber layer 25 is equal to or greater than about 5% (and less than about 20%). Therefore, a high-reflectivity APSM can cause random printer output as background light from the external absorber pattern to the photoresist layer. In this disclosure, a sub-resolution assist feature (SRAF) is used to suppress background light from the absorber pattern.

[0009] Figures 1A and 1B illustrate an EUV reflective mask according to an embodiment of the present disclosure. Figure 1A is a plan view (viewed from top), and Figure 1B is a cross-sectional view.

[0010] In some embodiments, the EUV photomask 5 includes a substrate 10, a multilayer Mo / Si stack 15 of alternating layers of silicon and molybdenum, a top cap layer 20, and an absorber layer 25. In some embodiments, an anti-reflective layer 27 is disposed above the absorber layer 25 as needed. In addition, a back-side conductive layer 45 is formed on the back side of the substrate 10, as illustrated in Figure 1B.

[0011] In some embodiments, the substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate 10 is a low thermal expansion glass or quartz, such as fused silica or fused silica. In some embodiments, the low thermal expansion glass substrate transmits light at visible wavelengths, a portion of the infrared wavelengths near the visible spectrum (near-infrared), and a portion of the ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths near the extreme ultraviolet. In some embodiments, the size X1 × Y1 of the substrate 10 is approximately 152 mm × approximately 152 mm with a thickness of approximately 20 mm. In other embodiments, the size of the substrate 10 is less than 152 mm × 152 mm and equal to or greater than 148 mm × 148 mm. In some embodiments, the substrate 10 is square or rectangular in shape.

[0012] In some embodiments, the functional layers (multilayer Mo / Si stack 15, top cap layer 20, absorber layer 25, and cover layer 27) above the substrate have a width smaller than that of the substrate 10. In some embodiments, the size X2 × Y2 of the functional layers is in the range of about 138 mm × 138 mm to 142 mm × 142 mm. In some embodiments, the shape of the functional layers is square or rectangular. In other embodiments, the absorber layer 25 and cover layer 27 have a smaller size in the range of about 138 mm × 138 mm to about 142 mm × 142 mm compared to the substrate 10, the multilayer Mo / Si stack 15, and the top cap layer 20. When the individual layers are formed by, for example, sputtering, the smaller size of one or more of the functional layers can be formed by using a frame molding cap having an opening in the range of about 138 mm × 138 mm to about 142 mm × 142 mm. In other embodiments, all layers above substrate 10 have the same size as substrate 10.

[0013] In some embodiments, the Mo / Si multilayer stack 15 comprises approximately 30 to approximately 60 pairs of alternating silicon and molybdenum layers. In some embodiments, the number of pairs is approximately 40 to approximately 50. In some embodiments, the reflectivity is higher than approximately 70% of the wavelength of interest, such as 13.5 nm. In some embodiments, the silicon and molybdenum layers are formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable film formation method. Each silicon and molybdenum layer is approximately 2 nm to approximately 10 nm thick. In some embodiments, the silicon and molybdenum layers are approximately the same thickness. In other embodiments, the silicon and molybdenum layers are approximately different thicknesses. In some embodiments, each silicon layer is approximately 4 nm thick, and each molybdenum layer is approximately 3 nm thick. In some embodiments, the bottom layer of the multilayer stack 15 is a Si layer or a Mo layer.

[0014] In other embodiments, the multilayer stack 15 includes alternating molybdenum and beryllium layers. In some embodiments, the number of layers in the multilayer stack 15 is in the range of about 20 to about 100, although any number of layers is permitted as long as sufficient reflectivity is maintained to image the target substrate. In some embodiments, the reflectivity is higher than about 70% of the wavelength of interest, for example, 13.5 nm. In some embodiments, the multilayer stack 15 includes about 30 to about 60 alternating Mo and Be layers. In other embodiments disclosed herein, the multilayer stack 15 includes about 40 to about 50 alternating layers, each being Mo and Be.

[0015] In some embodiments, the capping layer 20 is disposed over the Mo / Si multilayer stack 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the capping layer 20 is made of the following and has a thickness of about 2 nm to about 10 nm: elemental ruthenium (greater than 99% Ru rather than Ru compounds), ruthenium alloys (e.g., RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV, RuVN, RuIr, RuTi, RuB, RuP, RuOs, RuPd, RuPt, or RuRe), or ruthenium oxides (e.g., RuO2, RuNbO, RuVO, or RuON). In some embodiments, the capping layer 20 is a ruthenium compound Ru xM 1-x, where M is one or more of Nb, Ir, Rh, Zr, Ti, B, P, V, Os, Pd, Pt, or Re, and x is greater than zero and equal to or less than about 0.5.

[0016] In some embodiments, the thickness of the capping layer 20 is about 2 nm to about 5 nm. In some embodiments, the capping layer 20 has a thickness of about 3.5 nm ± 10%. In some embodiments, the capping layer 20 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or any other suitable film formation method. In other embodiments, a Si layer is used as the capping layer 20. As described below in some embodiments, one or more layers are disposed between the capping layer and the multilayer 15.

[0017] In some embodiments, the capping layer 20 comprises two or more layers of different materials. In some embodiments, the capping layer 20 comprises two or more layers of different Ru-based materials. In some embodiments, the capping layer 20 comprises two layers, namely a lower layer and an upper layer, wherein the upper layer has higher carbon absorption resistance than the lower layer, and the lower layer has higher etching resistance during absorber etching. In some embodiments, the capping layer 20 comprises a RuNb-based layer (RuNb or RuNbN) disposed on a RuRh-based layer (RuRh or RuRhN).

[0018] An absorber layer 25 is disposed above the top cover layer 20. The absorber layer 25 includes one or more layers having high EUV absorption. In some embodiments, the absorber layer 25 is a Ta-based material. In some embodiments, the absorber layer 25 is made of TaN, TaO, TaB, TaBO, or TaBN. In some embodiments, the absorber layer 25 has a multilayer structure made of TaN, TaO, TaB, TaBO, or TaBN. In other embodiments, the absorber layer 25 includes a Cr-based material, such as CrN, CrBN, CrO, and / or CrON. In some embodiments, the absorber layer 25 has a multilayer structure with Cr, CrO, or CrON. In some embodiments, the absorber layer is Ir or an Ir-based material, such as IrRu, IrPt, IrN, IrAl, IrSi, or IrTi. In some embodiments, the absorber layer is a Ru-based material, such as IrRu, RuPt, RuN, RuAl, RuSi, or RuTi, or a Pt-based material, such as PtIr, RuPt, PtN, PtAl, PtSi, or PtTi. In other embodiments, the absorber layer includes an Os-based material, a Pd-based material, or a Re-based material. In some embodiments disclosed herein, an X-based material means that the amount of X is equal to or greater than 50 atomic percent. In other embodiments, the absorber layer material is represented by AxBy, where A and B are each one or more of W, Ir, Pt, Ru, Cr, Ta, Os, Pd, Al, or Re, and x:y is from about 0.25:1 to about 4:1. In some embodiments, x is different from y (smaller or larger). In some embodiments, the absorber layer further includes one or more of Si, B, or N in an amount greater than zero to about 10 atomic percent.

[0019] In some embodiments, the thickness of the absorber layer 25 ranges from about 10 nm to about 100 nm, and in other embodiments it ranges from about 25 nm to about 75 nm. In some embodiments, the absorber layer 25 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method. As described below in some embodiments, one or more layers are disposed between the capping layer 20 and the absorber layer 25.

[0020] In some embodiments, a capping or antireflective layer 27 is disposed over the absorber layer 25. In some embodiments, the capping layer 27 comprises a Ta-based material, such as TaB, TaO, or TaBO, silicon, silicon compounds (e.g., silicon oxide, SiN, SiON, or MoSi), ruthenium, or ruthenium compounds (Ru or RuB). In some embodiments, the capping layer 27 is made of tantalum oxide (Ta₂O₅ or non-stoichiometric (e.g., oxygen-deficient) tantalum oxide) and has a thickness from about 2 nm to about 20 nm. In other embodiments, a TaBO layer having a thickness ranging from about 2 nm to about 20 nm is used as the capping layer. In some embodiments, the thickness of the capping layer 27 is from about 2 nm to about 5 nm. In some embodiments, the capping layer 27 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0021] In some embodiments, a back-side conductive layer 45 is disposed on a second main surface of the substrate 10 opposite to a first main surface of the substrate 10, on which a Mo / Si multilayer stack 15 is formed. In some embodiments, the back-side conductive layer 45 is made of TaB (tantalum boride) or other Ta-based conductive materials. In some embodiments, tantalum boride is crystalline. Crystalline tantalum boride includes TaB, Ta5B6, Ta3B4, and TaB2. In other embodiments, tantalum boride is polycrystalline or amorphous titanium. In other embodiments, the back-side conductive layer 45 is made of Cr-based conductive materials (CrN or CrON). In some embodiments, the sheet resistance of the back-side conductive layer 45 is equal to or less than 20 Ω / □. In some embodiments, the sheet resistance of the back-side conductive layer 45 is equal to or greater than 0.1 Ω / □. In some embodiments, the surface roughness Ra of the back-side conductive layer 45 is equal to or less than 0.25 nm. In some embodiments, the surface roughness Ra of the back-side conductive layer 45 is equal to or greater than 0.05 nm. Additionally, in some embodiments, the flatness of the back-side conductive layer 45 is equal to or less than 50 nm. In some embodiments, the flatness of the back-side conductive layer 45 is greater than 1 nm. The thickness of the back-side conductive layer 45 is in the range of about 50 nm to about 400 nm in some embodiments. In other embodiments, the back-side conductive layer 45 has a thickness of about 50 nm to about 100 nm. In some embodiments, the thickness is in the range of about 65 nm to about 75 nm. In some embodiments, the back-side conductive layer 45 is formed by: atmospheric pressure chemical vapor deposition (CVD), low-pressure CVD, plasma-enhanced CVD, laser-enhanced CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition including thermal deposition, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation and sputtering, or any other suitable film formation method. In some embodiments, under CVD conditions, the source gas includes TaCl5 and BCl3.

[0022] As shown in Figure 1B, the EUV mask 5 includes a circuit pattern 42 in the circuit pattern area and a black border 57 surrounding the circuit pattern area.

[0023] Figures 2A to 2F and 3A to 3D schematically illustrate a method for manufacturing an EUV mask for extreme ultraviolet lithography (EUVL). It should be understood that additional operations may be provided before, during, and after the processes illustrated in Figures 2A to 3D, and some additional embodiments of the method described below may be replaced or eliminated. The order of operations / processes may be interchangeable.

[0024] In the manufacture of an EUV photomask, a first photoresist layer 35 is formed over a rigid mask layer 30 of the EUV photomask blank as illustrated in Figure 2A, and the photoresist layer 35 is selectively exposed to photochemical radiation EB, as illustrated in Figure 2B. In some embodiments, the EUV photomask blank is inspected prior to the formation of the first photoresist layer 35. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 in the first photoresist layer 35, as illustrated in Figure 2C. In some embodiments, the photochemical radiation EB is an electron beam or an ion beam. In some embodiments, the pattern 40 corresponds to a pattern of semiconductor device features that the EUV photomask will be used to form in subsequent operations.

[0025] Next, the pattern 40 in the first photoresist layer 35 is extended into the rigid mask layer 30, thereby forming a pattern 41 in the rigid mask layer 30 that exposes multiple portions of the absorber layer 25, as illustrated in Figure 2D. In some embodiments, the pattern 41 extending into the rigid mask layer 30 is formed by etching using a suitable wet or dry etchant selectively applied to the absorber layer 25. After the pattern 41 in the rigid mask layer 30 is formed, the first photoresist layer 35 is removed by a photoresist stripper to expose the upper surface of the rigid mask layer 30, as illustrated in Figure 2E.

[0026] Next, the pattern 41 in the rigid mask layer 30 is extended into the absorber layer 25, thereby forming a pattern 42 in the absorber layer 25 that exposes multiple portions of the top cover layer 20, as illustrated in Figure 2F, and then the rigid mask layer 30 is removed, as illustrated in Figure 3A. The pattern 42 extending into the absorber layer 25 is formed in some embodiments by etching using a suitable wet or dry etchant selectively applied to the absorber layer 25. In some embodiments, plasma dry etching is used.

[0027] As illustrated in Figure 3B, a second photoresist layer 50 is formed in the absorber layer 25 to fill the pattern 42 in the absorber layer 25. The second photoresist layer 50 is selectively exposed to photochemical radiation, such as electron beams, ion beams, or UV radiation. The selectively exposed second photoresist layer 50 is developed to form a pattern 55 in the second photoresist layer 50, as illustrated in Figure 3B. The pattern 55 corresponds to a black boundary surrounding the circuit pattern. The black boundary is a frame-shaped area created by removing all multilayers on the EUV photomask in the area surrounding the circuit pattern area. The black boundary is created to prevent exposure of adjacent fields when printing the EUV photomask on the wafer. In some embodiments, the width of the black boundary is in the range of about 1 nm to about 5 nm.

[0028] Next, the pattern 55 in the second photoresist layer 50 extends into the absorber layer 25, the capping layer 20, and the Mo / Si multilayer 15, thereby forming patterns 57 (see Figure 3D) exposing multiple portions of the substrate 10 in the absorber layer 25, the capping layer 20, and the Mo / Si multilayer 15, as illustrated in Figure 3C. In some embodiments, the pattern 57 is formed by etching using one or more suitable wet or dry etchants selectively applied to each etched layer. In some embodiments, plasma dry etching is used.

[0029] Next, the second photoresist layer 50 is removed by a suitable photoresist stripper to expose the upper surface of the absorber layer 25, as illustrated in Figure 3D. The black boundary patterns 57 in the absorber layer 25, the top cap layer 20, and the Mo / Si multilayer 15 define the black boundaries of the photomask in some embodiments of this disclosure.

[0030] Figure 4A is a plan view or layout view of the EUV mask, and Figure 4B is a cross-sectional view of the EUV mask according to an embodiment of the present disclosure.

[0031] In some embodiments, the EUV photomask includes a circuit pattern 200 as a groove, trench, or opening formed in the absorber layer 25. In some embodiments, the size (e.g., width) of the circuit pattern 200 is equal to or greater than 40 nm on a 4X mask.

[0032] In some embodiments, the EUV photomask further includes a plurality of sub-resolution assist features (SRAFs) 210 formed in the absorber layer 25, as illustrated in Figures 4A and 4B. In some embodiments, when the photomask is a 4X screen, the SRAF 210 includes gratings, such as periodic patterns with a spacing equal to or greater than about 20 nm and less than about 160 nm, and in other embodiments within the range of about 120 nm from about 40 nm. When the photomask is a 5X screen, the SRAF 210 includes periodic patterns having a spacing between about 25 nm and about 200 nm, and in other embodiments between about 50 nm and about 150 nm. In other words, the spacing of the periodic patterns on the wafer is about 5 nm or more and less than about 40 nm. In some embodiments, SRAF 210 includes periodic lines and spatial patterns having the aforementioned spacing, and the width of the line pattern is equal to or greater than about 4 nm and less than 160 nm on a 4X mask, and in other embodiments ranges from about 10 nm to about 80 nm. In some embodiments, the width of SRAF pattern 210 is about 1 / 10 to about 1 / 5 of the minimum line width of the circuit pattern. In some embodiments, the ratio of line width to spacing (aspect ratio) is in the range of about 0.1 to about 0.9. SRAF pattern 210 is not printable as a photoresist pattern on the substrate.

[0033] When the spacing of the SRAF pattern 210 is small enough, the ±1 or higher order diffraction pattern does not enter the pupil (aperture) of the EUV lithography tool, and therefore the light reflected at the absorber layer does not cause random printing output on the photoresist layer.

[0034] Figure 5 illustrates the effect of the SRAF pattern. Figure 5 illustrates the pupil image of a main circuit pattern having a periodic line pattern or a via (square) pattern, and the background intensity in the case of the SRAF pattern. In some embodiments, "horizontal" corresponds to a first periodic line pattern that extends in the X direction and is arranged parallel to each other in the Y direction, "vertical" corresponds to a periodic line pattern that extends in the X direction and is arranged parallel to each other in the X direction, and "via / square" corresponds to a square pattern. In the background intensity diagram, the horizontal axis represents the distance between SRAFs, and the vertical axis represents the width of the SRAF line pattern, with darker areas indicating lower background intensity. As illustrated in Figure 5, it is possible to effectively suppress background intensity (reflected EUV light) by adjusting the distance between SRAF patterns and / or the line width. Therefore, the SRAF pattern is a background intensity suppression pattern.

[0035] In some embodiments, the SRAF pattern 210 surrounds the circuit pattern 200 separated by a distance, and thus the SRAF pattern 210 is separated from the circuit pattern 200, as illustrated in Figure 6A. In Figure 6A, the SRAF 210 includes a line and space pattern periodically arranged in one direction (X). The line and space pattern may have the width and spacing described above. As illustrated in Figure 6A, the SRAF pattern 210 is separated from the circuit pattern 200 by a distance D1, which in some embodiments is in the range of about 10 nm to about 100 nm on the photomask.

[0036] In other embodiments, the SRAF pattern 210 is connected to the circuit pattern 200, thereby forming a continuous groove pattern. Figures 6B and 6C illustrate SRAF patterns according to various embodiments of the present disclosure. In some embodiments, the circuit pattern 200 includes line and space patterns extending in the Y direction and disposed in the X direction. In some embodiments, as illustrated in Figure 6B, the SRAF 210 includes line and space patterns that extend in the X direction and are disposed in the Y direction, i.e., perpendicular to the line and space pattern 200. In other embodiments, as illustrated in Figure 6C, the SRAF 210 includes line and space patterns that extend in the Y direction and are disposed in the X direction, i.e., parallel to the line and space pattern 200.

[0037] In some embodiments, the SRAF pattern 210 is provided in the region surrounding the circuit pattern. In some embodiments, the distance D2 from the outermost edge of the circuit pattern 200 to the outer periphery of the SRAF pattern region in the X and Y directions is in the range of about 4000 nm to about 40,000 nm on the photomask. In some embodiments, an unpatterned absorber layer is present outside this region.

[0038] In some embodiments, as illustrated in Figure 7A, each of the line patterns of the circuit pattern 200 is surrounded by a margin region (space) 220, which corresponds to the absorber layer. The width of the margin region 220 (the distance between the circuit pattern 200 and the SRAF pattern 210) in some embodiments is in the range of about 10 nm to about 100 nm on the photomask.

[0039] In other embodiments, as illustrated in Figure 7B, the group of line and space patterns is surrounded by a margin region 220. The distance between the group of line patterns 200 and the SRAF pattern 210 is, in some embodiments, in the photomask, in the range of about 10 nm to about 100 nm.

[0040] In some embodiments, the SRAF pattern is provided for a larger absorber region. In some embodiments, the SRAF pattern is generated by a photomask data generation device such that absorber patterns equal to or larger than a threshold size do not exist. In some embodiments, the threshold size is in the range of about 100 nm² to 250,000 nm² on the mask, and in other embodiments it is in the range of about 2,500 nm² to about 10,000 nm².

[0041] Figures 8A to 8E illustrate various views of the structure of an EUV mask with an SRAF pattern according to one embodiment of the present disclosure. Figure 8A is a plan view (layout view), and Figures 8B, 8C, 8D, and 8E are cross-sectional views corresponding to lines X1, X2, Y1, and Y2, respectively. As illustrated in Figures 8A to 8E, the circuit pattern includes a line pattern 200 as trenches formed in the absorber layer 25 and the top cover layer 20, and the SRAF also includes a line pattern 210 as trenches formed in the absorber layer 25 and the top cover layer 20.

[0042] In some embodiments, as illustrated in Figures 8E and 8F, although the circuit pattern 200 is formed as an exposed opening in the reflective multilayer structure 15 as illustrated in Figure 8B, the SRAF pattern 210 is formed as an opening with its bottom located in the middle of the absorber layer 25. In some embodiments, because the width of the openings between the circuit patterns 200 is sufficiently greater than the width of the openings of the SRAF pattern 210, the etching of the SRAF pattern continues even after the etching operation of the circuit pattern is completed (thus exposing the reflective multilayer 15 plus additional over-etching). By stopping the etching at an appropriate timing point, it is possible to obtain the structure illustrated in Figures 8B and 8F. In some embodiments, the depth of the openings of the SRAF pattern is approximately 40% to 90% of the thickness of the absorber layer 25. In some embodiments, the depth of the openings of the SRAF pattern is not uniform, and the variation in depth (from maximum to minimum) is in the range of approximately 1 nm to approximately 10 nm.

[0043] In some embodiments, the circuit pattern 200 and the SRAF pattern 210 are formed simultaneously (continuously) by electron beam lithography. In other embodiments, the SRAF pattern is exposed to the same mask photoresist layer after or before the circuit pattern is exposed by electron beam lithography. In other embodiments, another photoresist layer is formed on the photomask before or after the circuit pattern is formed by electron beam lithography and etching operations, and then electron beam lithography or other lithography operations (optical, laser interference, etc.) are performed to form the SRAF pattern.

[0044] Figure 9 illustrates various patterns of SRAF according to embodiments of the present disclosure. In Figure 9, the mask pattern corresponds to the reflective pattern (non-absorber) and the background corresponds to the absorber layer (or substrate).

[0045] In some embodiments, the SRAF pattern is a grating pattern. In some embodiments, the SRAF pattern is a simple line and space pattern in which a constant spacing extends in the X direction (horizontal) or Y direction (vertical). In other embodiments, the spacing varies. In some embodiments, the spacing decreases as the distance to the circuit pattern decreases. In some embodiments, the spacing increases as the distance to the circuit pattern increases. In some embodiments, the spacing changes randomly. When the spacing changes randomly, its average spacing is equal to or greater than about 40 nm and less than about 160 nm.

[0046] In some embodiments, the line width of the line pattern varies. In some embodiments, the width decreases as the distance to the circuit pattern decreases. In other embodiments, the width increases as the distance to the circuit pattern increases. In some embodiments, the width changes randomly. When the width changes randomly, its average width is in the range of about 10 nm to about 50 nm.

[0047] In some embodiments, the line pattern of the SRAF pattern is segmented (cut into pieces) to form a slot array.

[0048] In some embodiments, the SRAF pattern includes a combination of vertical and horizontal patterns.

[0049] In some embodiments, the line pattern of the SRAF is tilted about the X or Y direction (the direction in which the circuit pattern extends). In some embodiments, the tilt angle about the X or Y direction is about 10 degrees to about 80 degrees.

[0050] In some embodiments, the SRAF pattern includes a corrugated pattern, which includes a vertical pattern arranged parallel to the longitudinal side of a circuit pattern that extends vertically or horizontally, and a horizontal pattern arranged parallel to its latitudinal side.

[0051] In some embodiments, the SRAF pattern comprises an array or matrix of square or circular patterns. In some embodiments, the matrix is ​​a regular matrix, and in other embodiments, the matrix is ​​an interlaced matrix. The spacing in the X and / or Y directions is constant in some embodiments and resembles a line pattern as described above in other embodiments.

[0052] In some embodiments, the SRAF pattern includes a zigzag pattern, such as a snake pattern, a crank pattern, and a stepped pattern.

[0053] In some embodiments, one or more sides of the SRAF pattern are bent. In some embodiments, the SRAF pattern is a recessed or raised polygon that is not a rectangle.

[0054] In some embodiments, the SRAF pattern includes any combination of the aforementioned patterns.

[0055] In some embodiments, the SRAF pattern is a layout pattern (e.g., a pattern as GDS layout data) that overlaps with a circuit pattern that is also a layout pattern. In other embodiments, the SRAF layout pattern does not overlap with the circuit layout pattern. In some embodiments, the masking drawing data is a combination, such as a logical OR of the SRAF layout and the circuit layout pattern.

[0056] The SRAF pattern is generated by the photomask data generation device illustrated in Figures 10A and 10B. Figure 10A is a schematic diagram of a computer system performing a photomask data generation process according to one or more embodiments described above. All or part of the processes, methods, and / or operations of the foregoing embodiments can be implemented using computer hardware and computer programs running on the computer hardware. In Figure 10A, the computer system 900 includes a computer 901, which includes an optical disc read-only memory (e.g., CD-ROM or DVD-ROM) drive 905 and a magnetic disk drive 906, a keyboard 902, a mouse 903, and a monitor 904.

[0057] Figure 10B is a diagram illustrating the internal configuration of computer system 900. In Figure 10B, in addition to optical disk drive 905 and magnetic disk drive 906, computer 901 also includes one or more processors 911, such as microprocessor units (MPUs), ROM 912 containing program storage such as a bootloader, random access memory (RAM) 913 connected to MPU 911 and providing temporary storage for application commands, hard disk 914 containing application programs, system programs, and data, and bus 915 connecting MPU 911, ROM 912, and the like. Note that computer 901 may include a network card (not shown) for providing a connection to a LAN.

[0058] The program used to enable the computer system 900 to perform the functions of the photomask data generation device in the foregoing embodiments can be stored on an optical disc 921 or a magnetic disk 922, which is inserted into an optical disc drive 905 or a magnetic disk drive 906 and transferred to a hard disk 914. Alternatively, the program can be transferred to the computer 901 via a network (not shown) and stored on the hard disk 914. During execution, the program is loaded into RAM 913. The program can be loaded from the optical disc 921 or the magnetic disk 922 or directly from the network.

[0059] The program does not necessarily need to include, for example, an operating system (OS) or a third-party program to enable the computer 901 to perform the functions of the photomask data generation device in the aforementioned embodiments. The program may only include a command portion to call appropriate functions (modules) in control mode and obtain the desired results.

[0060] In the program, the functions implemented by the program do not include functions that may be implemented solely by hardware in some embodiments. For example, functions that may be implemented solely by hardware in an information acquisition unit or an information output unit, such as a network interface, are not included in the functions implemented by the program in some embodiments. Furthermore, the computer executing the program may be a single computer or multiple computers.

[0061] In addition, all or part of the program used to implement the photomask data generation device is part of another program used in the photomask manufacturing process in some embodiments. Furthermore, all or part of the program used to implement the functions of the photomask data generation device is implemented by a ROM, which in some embodiments is made of a semiconductor device.

[0062] According to embodiments of the present disclosure, Figure 11A illustrates a flowchart of a method for manufacturing a semiconductor device, and Figures 11B, 11C, 11D, and 11E illustrate sequential manufacturing operations of the method for manufacturing a semiconductor device. A semiconductor substrate or other suitable substrate is provided to be patterned to form an integrated circuit thereon. In some embodiments, the semiconductor substrate comprises silicon. Alternatively or additionally, the semiconductor substrate comprises germanium, silicon germanium, or other suitable semiconductor materials, such as group III-V semiconductor materials. At S801 in Figure 11A, a target layer to be patterned is formed over the semiconductor substrate. In some embodiments, the target layer is the semiconductor substrate. In some embodiments, the target layer includes a conductive layer, such as a metal layer or a polycrystalline layer; a dielectric layer, such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide; or a semiconductor layer, such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed over an underlying structure, such as an isolation structure, a transistor, or a wire. At point S802 in Figure 11A, a photoresist layer is formed over the target layer, as illustrated in Figure 11B. The photoresist layer is sensitive to radiation from the exposure source during subsequent optical lithography exposure processes. In this embodiment, the photoresist layer is sensitive to EUV light used in the optical lithography exposure process. The photoresist layer can be formed over the target layer by spin coating or other suitable techniques. The coated photoresist layer can be further baked to remove solvent from the photoresist layer.

[0063] At S803 in Figure 11A, as explained above, the EUV mask is loaded into an EUV lithography tool (e.g., an EUV scanner), and the mask alignment operation is performed using an alignment system.

[0064] At S804 in Figure 11A, the photoresist layer is patterned using an EUV photomask, as illustrated in Figure 11B. During the exposure process, an integrated circuit (IC) design pattern defined on the EUV photomask is imaged onto the photoresist layer to form a potential pattern thereon. The patterning of the photoresist layer further includes developing the exposed photoresist layer to form a patterned photoresist layer with one or more openings. In one embodiment where the photoresist layer is a positively tuned photoresist layer, the exposed portion of the photoresist layer is removed during the development process. The patterning of the photoresist layer may further include other process steps, such as various baking steps at different stages. For example, a post-exposure-baking (PEB) process may be performed after the optical lithography exposure process and before the development process.

[0065] At S805 in Figure 11A, the target layer is patterned using a patterned photoresist layer as an etching mask, as illustrated in Figure 11D. In some embodiments, patterning the target layer includes applying an etching process to the target layer using the patterned photoresist layer as an etching mask. Several portions of the target layer exposed in the openings of the patterned photoresist layer are etched, while the remaining portions are protected from etching. Alternatively, the patterned photoresist layer may be removed by wet stripping or plasma ashing, as illustrated in Figure 11E.

[0066] In this disclosure, the SRAF pattern is provided above or around the circuit pattern of the EUV photomask, which can suppress background signals (e.g., undesired EUV radiation). Therefore, it is possible to increase signal contrast (e.g., S / N ratio) and improve the pattern accuracy and resolution of the EUV photomask while suppressing defect generation.

[0067] It should be understood that not all advantages need to be discussed herein, no particular advantage is claimed for all embodiments or instances, and other embodiments or instances may offer different advantages.

[0068] According to one embodiment of this application, a photomask for an extreme ultraviolet (EUV) lithography includes: a circuit pattern; and secondary resolution auxiliary patterns disposed around and connected to the circuit pattern. The size of the secondary resolution auxiliary patterns is in the range of 10 nm to 50 nm. In one or more of the foregoing and following embodiments, the secondary resolution auxiliary patterns include periodic patterns having a spacing equal to or greater than 40 nm and less than 160 nm. In one or more of the foregoing and following embodiments, the secondary resolution auxiliary patterns include periodic line patterns having a width in the range of 10 nm to 50 nm and a spacing equal to or greater than 40 nm and less than 160 nm. In one or more of the foregoing and following embodiments, the periodic line patterns of the secondary resolution auxiliary patterns are grooves, trenches, or openings formed in an absorber layer. In one or more of the foregoing and following embodiments, the circuit pattern includes periodic line patterns having a width greater than the width of the periodic line patterns of the secondary resolution auxiliary patterns. In one or more of the foregoing and following embodiments, the periodic line patterns of the circuit pattern extend in a first direction and are arranged parallel to each other in a second direction intersecting the first direction; the periodic line patterns of the secondary resolution auxiliary patterns extend in the first direction and are arranged parallel to each other in the second direction. In one or more of the foregoing and following embodiments, the periodic line patterns of the circuit pattern extend in a first direction and are arranged parallel to each other in a second direction intersecting the first direction; the periodic line patterns of the secondary resolution auxiliary patterns extend in the second direction and are arranged parallel to each other in the first direction. In one or more of the foregoing and following embodiments, the periodic line patterns of the circuit pattern are grooves, trenches or openings formed in an absorber layer, and the periodic line patterns of the secondary resolution auxiliary patterns are connected to at least one of the periodic line patterns of the circuit pattern.

[0069] According to another embodiment of this disclosure, a photomask for an extreme ultraviolet (EUV) lithography includes: a substrate; a reflective multilayer structure disposed above the substrate; a top cover layer disposed above the reflective multilayer structure; and an absorber layer disposed above the top cover layer. The absorber layer has a refractive index equal to or less than 0.95 and an absorption coefficient k equal to or less than 0.04 for EUV light. The photomask includes: a circuit pattern; and a background intensity suppression pattern disposed around and connected to the circuit pattern, the circuit pattern having a size smaller than that of one of the patterns included in the circuit pattern. In one or more of the foregoing and following embodiments, the background intensity suppression pattern includes a grating pattern. In one or more of the foregoing and following embodiments, the circuit pattern includes a periodic line pattern, and the background intensity suppression pattern is disposed in at least a region between two adjacent line patterns of the circuit pattern. In one or more of the foregoing and following embodiments, the grating patterns include periodic line patterns having a width in the range of 10 nm to 50 nm and a spacing equal to or greater than 40 nm and less than 160 nm, and the periodic line patterns of the circuit pattern have a spacing in the range of 3000 nm to 5000 nm and a line width in the range of 100 nm to 300 nm. In one or more of the foregoing and following embodiments, the periodic line patterns of the gratings and the circuit pattern are grooves, trenches, or openings formed in the absorber layer. In one or more of the foregoing and following embodiments, the grating patterns are aperiodic. In one or more of the foregoing and following embodiments, the background intensity suppression pattern comprises a square pattern matrix. In one or more of the foregoing and following embodiments, the reflectivity of the absorber layer is equal to or greater than 5%.

[0070] According to another aspect of this disclosure, an attenuated phase shift mask (APSM) for extreme ultraviolet (EUV) lithography includes: a substrate; a reflective multilayer structure disposed above the substrate; a top cover layer disposed above the reflective multilayer structure; and an absorber layer disposed above the top cover layer. The absorber layer has a reflectivity greater than 5% for EUV light. The APSM includes a circuit pattern formed as a photoresist pattern; and secondary resolution auxiliary patterns not formed as a photoresist pattern and disposed around the circuit pattern. In one or more of the foregoing and following embodiments, the size of the secondary resolution auxiliary patterns is in the range of 10 nm to 40 nm, and for EUV light, a refractive index equal to or less than 0.95 and an absorption coefficient k equal to or less than 0.04. In one or more of the foregoing and following embodiments, the secondary resolution auxiliary patterns include patterns having a spacing equal to or greater than 40 nm and less than 160 nm. In one or more of the foregoing and following embodiments, at least one of the secondary resolution auxiliary patterns is connected to the circuit pattern.

[0071] The foregoing summarizes the features of several embodiments or examples, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments or examples introduced herein and / or achieving the same benefits. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of explanation. Figures 1A and 1B illustrate an EUV reflector according to an embodiment of this disclosure. Figures 2A, 2B, 2C, 2D, 2E, and 2F schematically illustrate a method of manufacturing an EUV reflector according to an embodiment of this disclosure. Figures 3A, 3B, 3C, and 3D schematically illustrate a method of manufacturing an EUV reflector according to an embodiment of this disclosure. Figure 4A illustrates a plan view of an EUV reflector according to an embodiment of this disclosure. Figure 4B illustrates a cross-sectional view of an EUV reflector according to an embodiment of this disclosure. Figure 5 illustrates a simulation or calculation result of background intensity suppression performed by a secondary resolution pattern according to an embodiment of this disclosure. Figures 6A, 6B, and 6C illustrate plan views of a mask pattern according to an embodiment of the present disclosure. Figures 7A and 7B illustrate a layout of secondary resolution auxiliary features according to an embodiment of the present disclosure. Figure 8A is a plan view (layout diagram) according to an embodiment of the present disclosure, and Figures 8B, 8C, 8D, and 8E respectively illustrate cross-sectional views of the EUV mask corresponding to lines X1, X2, Y1, and Y2 in Figure 8A. Figure 8F illustrates a cross-sectional view of the EUV mask according to an embodiment of the present disclosure corresponding to line Y2 in Figure 8A. Figure 9 illustrates various secondary resolution auxiliary features according to an embodiment of the present disclosure. Figures 10A and 10B illustrate a mask data generation apparatus according to an embodiment of the present disclosure. According to the embodiments disclosed herein, Figure 11A illustrates a flowchart of a method for manufacturing a semiconductor device, and Figures 11B, 11C, 11D and 11E illustrate sequential manufacturing operations of the method for manufacturing a semiconductor device. [Biomaterial Storage]

[0073] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A photomask for extreme ultraviolet lithography, the photomask comprising: a circuit pattern; and a plurality of secondary resolution auxiliary patterns disposed around and connected to the circuit pattern, wherein a size of the secondary resolution auxiliary patterns is in the range of 10 nm to 50 nm.

2. The photomask for extreme ultraviolet lithography as described in claim 1, wherein the secondary resolution auxiliary patterns include periodic patterns having a spacing equal to or greater than 40 nm and less than 160 nm.

3. The photomask for extreme ultraviolet lithography as described in claim 1, wherein the secondary resolution auxiliary patterns include periodic line patterns having a width in the range of 10 nm to 50 nm and a spacing equal to or greater than 40 nm and less than 160 nm.

4. The photomask for extreme ultraviolet lithography as described in claim 3, wherein the periodic line patterns of the secondary resolution auxiliary patterns are grooves, trenches or openings formed in an absorber layer.

5. The photomask for extreme ultraviolet lithography as described in claim 4, wherein the circuit pattern includes periodic line patterns having a width greater than the width of the periodic line patterns of the secondary resolution auxiliary patterns.

6. The photomask for extreme ultraviolet lithography as described in claim 5, wherein: The periodic line patterns of the circuit pattern extend in a first direction and are arranged parallel to each other in a second direction intersecting the first direction, and the periodic line patterns of the secondary resolution auxiliary patterns extend in the first direction and are arranged parallel to each other in the second direction.

7. The photomask for extreme ultraviolet lithography as described in claim 5, wherein: The periodic line patterns of the circuit pattern extend in a first direction and are arranged parallel to each other in a second direction intersecting the first direction, and the periodic line patterns of the secondary resolution auxiliary patterns extend in the second direction and are arranged parallel to each other in the first direction.

8. The photomask for extreme ultraviolet lithography as described in claim 5, wherein: The periodic line patterns of the circuit pattern are grooves, trenches or openings formed in an absorber layer, and the periodic line patterns of the secondary resolution auxiliary patterns are connected to at least one of the periodic line patterns of the circuit pattern to form a continuous groove, trench or opening.

9. A photomask for extreme ultraviolet lithography, the photomask comprising: a substrate; a reflective multilayer structure disposed above the substrate; a top cover layer disposed above the reflective multilayer structure; and an absorber layer disposed above the top cover layer, wherein: The absorber layer has a refractive index equal to or less than 0.95 and an absorption coefficient k equal to or less than 0.04 for extreme ultraviolet light, and the photomask includes: a circuit pattern; and a background intensity suppression pattern disposed around and connected to the circuit pattern, the circuit pattern having a size smaller than that of a pattern included in the circuit pattern.

10. The photomask for extreme ultraviolet lithography as described in claim 9, wherein the background intensity suppression pattern comprises a grating pattern.

11. The photomask for extreme ultraviolet lithography as described in claim 10, wherein the circuit pattern comprises a plurality of periodic line patterns, and the background intensity suppression pattern is disposed in at least one region between two adjacent line patterns of the circuit pattern.

12. The photomask for extreme ultraviolet lithography as described in claim 11, wherein: These grating patterns include periodic line patterns having a width in the range of 10 nm to 50 nm and a spacing equal to or greater than 40 nm and less than 160 nm.

13. The photomask for extreme ultraviolet lithography as described in claim 12, wherein the periodic line pattern of the grating and the circuit pattern are a plurality of grooves, trenches or openings formed in the absorber layer.

14. The photomask for extreme ultraviolet lithography as described in claim 10, wherein the grating patterns are aperiodic.

15. The photomask for extreme ultraviolet lithography as described in claim 9, wherein the background intensity suppression pattern comprises a square pattern matrix.

16. The photomask for extreme ultraviolet lithography as described in claim 9, wherein a reflectivity of the absorber layer is equal to or greater than 5%.

17. An attenuation phase-transfer mask for extreme ultraviolet lithography, comprising: a substrate; a reflective multilayer structure disposed above the substrate; a top cover layer disposed above the reflective multilayer structure; and an absorber layer disposed above the top cover layer, wherein: The absorber layer has a reflectivity greater than 5% for extreme ultraviolet light, and the attenuation phase transfer mask includes: a circuit pattern to be formed as a photoresist pattern; and a secondary resolution auxiliary pattern, which is not formed as a photoresist pattern and is disposed around the circuit pattern.

18. The attenuation phase-transfer mask for extreme ultraviolet lithography as described in claim 17, wherein: The size of these secondary resolution auxiliary patterns is in the range of 10 nm to 50 nm, and for extreme ultraviolet light, a refractive index equal to or less than 0.95 and an absorption coefficient k equal to or less than 0.

04.

19. The attenuation phase-transfer mask for extreme ultraviolet lithography as described in claim 17, wherein the secondary resolution auxiliary patterns comprise a plurality of patterns having a spacing equal to or greater than 40 nm and less than 160 nm.

20. The attenuation phase-transfer mask for extreme ultraviolet lithography as described in claim 17, wherein at least one of the secondary resolution auxiliary patterns is connected to the circuit pattern.

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