Systems and methods for a cross-layer key-value store with a computational storage device

Abstract

Provided is a method of data storage, the method including receiving, at a host of a key-value store, a request to access a data node stored on a storage device of the key-value store, locating an address corresponding to the data node in a host cache on the host, and determining that the data node is in a kernel cache on the storage device.

Description

[Technical Field]

[0001] [Cross-reference to related applications]

[0002] This application claims priority over and claims the benefit of U.S. Provisional Application No. 63 / 331,032, filed on April 14, 2022, entitled “CROSS-LAYER KEY-VALUE STORE WITH COMPUTATIONAL STORAGE DEVICE”, the entire contents of which are incorporated herein by reference.

[0003] One or more embodiments of the present disclosure relate to systems and methods for data storage. [Previous Technology]

[0004] This background section is intended to provide context only, and the disclosure of any embodiments or concepts in this section does not constitute an admission that the embodiments or concepts are prior art.

[0005] In the field of computer storage, a key-value store can be implemented on a storage system (e.g., a system) that includes a host (e.g., a mainframe computer) and a storage device (e.g., a device including a storage medium for storing data). The system can store data nodes in the memory (e.g., non-volatile memory) of the storage device. Users of the system can access the data nodes. The system can perform various operations on the data nodes based on requests from users. The system can identify the data node location and the key value location within the data node to perform operations on the data node based on key-value pairs. For example, the system can process a request associated with a key to (i) search for and locate the location of a value (e.g., a data object) corresponding to the key and (ii) perform an operation associated with the request for the value.

[0006] Therefore, there is a need for a method, apparatus and system for efficiently processing requests for key-value stores. [Summary of the Invention]

[0007] The various embodiments disclosed herein relate to computer storage systems and provide improvements to key-value stores.

[0008] According to some embodiments of the present disclosure, a method for storing data is provided, the method comprising: receiving, at a host of a key-value store, a request to access a data node stored on a storage device of the key-value store; locating an address corresponding to the data node in a host cache on the host; and determining that the data node is located in a kernel cache on the storage device.

[0009] The offset of the entry in the host cache that stores the metadata corresponding to the data node may be the same as the offset of the entry in the kernel cache that stores the data node.

[0010] The method may further include: locating the address in a search layer on the host by the host; initiating a kernel call to transfer control for processing the request from the host to the processing circuitry of the storage device; processing the data on the data node by the processing circuitry; writing the data node to the kernel cache as an updated data node; and having the host peer-to-peer write the updated data node from the kernel cache to the memory of the storage device.

[0011] The search layer may include a tree structure, the data layer on the storage device includes the data node, the data node corresponds to the leaf node in the bidirectional link list corresponding to the leaf node of the tree structure, and locating the address in the search layer may include searching for a partial key in the internal nodes of the tree structure.

[0012] The method may further include: determining that the amount of available space in the data node is less than the amount of space used to accommodate the key corresponding to the request; and updating the metadata of the data node to point to an extension node, wherein the metadata of the data node may indicate a first version number, and the metadata of the extension node may indicate the first version number.

[0013] The method may further include having the expansion node assigned by a slab allocator to the data node which is composed of a pool of data pages of different sizes.

[0014] The method may further include: updating the extended node; updating the metadata of the data node to indicate a second version number; updating the metadata of the extended node to indicate the second version number, the second version number identifying the data node as an updated data node and the extended node as an updated extended node; and updating the metadata of the updated data node to point to the updated extended node.

[0015] The method may further include: writing the updated extended node to the storage device in an out-of-place manner; and writing the updated data node to the storage device in an in-place manner.

[0016] The method may further include: obtaining a read lock on the data node by the host; or obtaining a write lock on the data node by the host.

[0017] According to other embodiments of the present disclosure, a system for data storage is provided, the system including a host and a storage device, wherein the host is configured to: receive a request to access a data node stored on the storage device; locate the address corresponding to the data node in a host cache on the host; and determine that the data node is in a kernel cache on the storage device.

[0018] The offset of the entry in the host cache that stores the metadata corresponding to the data node may be the same as the offset of the entry in the kernel cache that stores the data node.

[0019] The host may be configured to: locate the address in a search layer on the host; determine that the data node is in the kernel cache; initiate a kernel call to transfer control for processing the request from the host to the processing circuitry of the storage device; and cause the updated data node to be written peer-to-peer from the kernel cache to the memory of the storage device, wherein the processing circuitry of the storage device may be configured to: process the data on the data node; and write the data node to the kernel cache as an updated data node.

[0020] The search layer may include a tree structure, the data layer on the storage device may include the data node, the data node may correspond to a leaf node in a bidirectional link list corresponding to a leaf node of the tree structure, and the host may be configured to search for the address based on locating a partial key in an internal node of the tree structure.

[0021] The system may be configured to: determine that the amount of available space in the data node is less than the amount of space used to accommodate the key corresponding to the request; and update the metadata of the data node to point to an extension node, wherein the metadata of the data node may indicate a first version number, and the metadata of the extension node may indicate the first version number.

[0022] The system may be configured to: update the extended node; update the metadata of the data node to indicate a second version number; update the metadata of the extended node to indicate the second version number, the second version number being able to identify the data node as an updated data node and the extended node as an updated extended node; and update the metadata of the updated data node to point to the updated extended node.

[0023] According to other embodiments of the present disclosure, a storage device is provided, the storage device including: processing circuitry; persistent memory; and a common memory area linked to the processing circuitry and the persistent memory, wherein the processing circuitry is configured to process requests for accessing data nodes stored on the storage device by reading data nodes from entries in the kernel cache on the common memory area.

[0024] The processing circuitry can be configured to process the request by performing data operations on the data node and writing the data node to the kernel cache as an updated data node.

[0025] The processing circuit may be configured to: update an extension node pointing to the data node, the extension node and the data node indicating a first version number; update the metadata of the data node to indicate a second version number; update the metadata of the extension node to indicate the second version number, the second version number identifying the data node as an updated data node and the extension node as an updated extension node; and update the metadata of the updated data node to point to the updated extension node.

[0026] The processing circuitry may be configured to write the updated extended node to the storage device's memory in a remote manner.

[0027] The processing circuitry can be configured to write the updated data node to the storage device's memory in situ.

Implementation Method

[0029] The features of the inventive concept and the methods for achieving said features can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the nature and features of the inventive concept to those skilled in the art. Therefore, processes, components, and techniques that are unnecessary for those skilled in the art to fully understand the nature and features of the inventive concept are not described.

[0030] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the accompanying drawings and written description, and therefore will not be described again. Furthermore, for clarity, components unrelated to the description of the embodiments may not be shown. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0031] In this detailed description, numerous specific details are set forth for purposes of illustration to provide a thorough understanding of various embodiments. However, it will be apparent that various embodiments may be practiced without using these specific details or with one or more equivalent arrangements.

[0032] It should be understood that although the terms "zeroth," "first," "second," "third," etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used to distinguish individual elements, components, areas, layers, or segments. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first area, first layer, or first segment described below may be referred to as the second element, second component, second area, second layer, or second segment.

[0033] It should be understood that when an element or component is said to be "on," "connected to," or "coupled to" another element or component, the element or component may be directly located on, directly connected to, or directly coupled to the other element or component, or there may be one or more intermediate elements or components. However, "directly connected / directly coupled" means that one component is directly connected to or directly coupled to another component without any intermediate components. Similarly, other expressions describing the relationship between components (e.g., "between," "immediately between," "adjacent to," and "directly adjacent to") can be interpreted in a similar manner. Furthermore, it should also be understood that when an element or component is said to be "between" two elements or components, the element or component may be the only element or component between the two elements or components, or there may be one or more intermediate elements or components.

[0034] The terminology used herein is for the purpose of illustrating particular embodiments only and is not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular form "a (a and an)" as used herein is intended to include the plural form as well. It should be further understood that when the terms "comprises / comprising," "have / having," and "includes / including" are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] The terms “substantially,” “about,” “approximately,” and similar terms used herein are used as approximations, not as terms of degree, and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by someone of ordinary skill in the art. “About” or “approximately” as used herein includes stated values ​​and means within an acceptable range of deviation from a particular value as determined by someone of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within α ± 30%, ± 20%, ± 10%, ± 5% of the stated value. Furthermore, when “may” is used in describing embodiments of this disclosure, it refers to “one or more embodiments of the present disclosure.”

[0036] When one or more embodiments can be implemented in different ways, a particular process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description.

[0037] Any component or any combination of components described herein (e.g., any system diagram included herein) may be used to perform one or more operations of any flowchart included herein. Furthermore, (i) the operation is merely an example and may involve various additional operations not explicitly covered, and (ii) the timing order of the operations may vary.

[0038] Electronic devices or electrical devices and / or any other related devices or components according to embodiments of the present disclosure as set forth herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of hardware, software, and firmware. For example, various components of these devices may be formed on an integrated circuit (IC) wafer or on separate IC wafers. Furthermore, various components of these devices may be implemented on flexible printed circuit films, tape carrier packages (TCPs), printed circuit boards (PCBs), or formed on a substrate.

[0039] Furthermore, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functionalities described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media such as, for example, compact disc-read-only memory (CD-ROM), flash drives, or similar devices. Additionally, those skilled in the art will recognize that the functionality of various computing devices can be combined or integrated into a single computing device without departing from the spirit and scope of the embodiments disclosed herein, or the functionality of a particular computing device can be distributed across one or more other computing devices.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the concepts of this invention pertain. It should be further understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant art and / or this specification, and shall not be construed as having an idealized or overly formal meaning unless expressly defined herein.

[0041] As described above, in the field of computer storage, key-value stores can be implemented on a storage system (e.g., a system). A system may include a host (e.g., a mainframe computer) and a storage device (e.g., a device including a storage medium for storing data). The storage device may store data nodes in its memory (e.g., non-volatile memory or persistent memory). A user of the system may request access to a data node. For example, a user may initiate a data access request (e.g., a write request, a read request, etc.) that will be received by the system. The system may locate the data node based on the data access request and perform operations on the data node (e.g., a write operation, a read operation, etc.).

[0042] A data node may include a set of key-value pairs corresponding to the same partial key. The partial key may be stored in the system's search layer. A data node may include metadata segments and a series of key-value pairs. For example, each data node may store a series of key-value pairs such that the maximum value key in the current data node (e.g., the first data node) is less than the minimum value key in the next data node (e.g., the second data node adjacent to the first data node). Therefore, an ascending order of keys between adjacent data nodes can be maintained (e.g., provided).

[0043] The system can be configured to perform various operations on data nodes. For example, the system can perform insert (key, value), update (key, value), remove (key), lookup (key), or scan (key, range) operations on a data node based on a request from a user. Based on the received key-value pairs, the system can identify the data node and then identify the precise location within the data node where the operation will be performed. The system can then perform the operation associated with the received key-value pairs. For example, the system can process a request associated with the key of a key-value pair to (i) locate the value (e.g., an object) corresponding to the key and (ii) perform the operation associated with the request on the value at the data node.

[0044] Therefore, it is appropriate to develop methods, apparatus and systems for processing requests for key-value stores more efficiently.

[0045] Some key-value stores can be designed to use only the host's computing resources or only the computing resources of a storage device (e.g., a solid-state drive, SSD). For example, some key-value stores can use host computing resources to perform both control plane operations and data manipulation (e.g., data processing) operations. In such key-value stores, the host processor (e.g., central processing unit, CPU) can receive requests from a user (e.g., from an application corresponding to the user) to locate (e.g., position) a key and retrieve the requested data into the host dynamic random access memory (DRAM). The CPU can use the data to manipulate calculations.

[0046] Some key-value stores may have computational storage capabilities. That is, key-value stores may be implemented using storage devices that include processing circuitry (e.g., accelerators such as field-programmable gate arrays (FPGAs)). FPGAs may be used solely as a "service" to manipulate the data layer (e.g., to perform pure computations such as encoding or decoding).

[0047] Some key-value stores implemented with computing storage capabilities can use storage device resources to perform both control plane operations and data manipulation (e.g., data processing) operations. That is, the key-value store can be implemented entirely on the storage device. In such a key-value store, the processing circuitry of the storage device can receive requests from user applications to locate (e.g., position) a key and retrieve the requested data to the DRAM of the storage device for the processing circuitry to perform calculations.

[0048] In order to provide data persistence and operational atomicity (e.g., to prevent data loss due to device failure), key-value stores may be implemented according to crash consistency strategies for data recovery.

[0049] Some key-value stores can be implemented using crash consistency strategies that include write-ahead logging (WAL) (e.g., undo logging and redo logging). For example, in WAL, any writes to the key-value store before the corresponding data location may be modified by a write operation can be stored in a log file (e.g., write-ahead log) that is persistently stored on the non-volatile memory of the storage device.

[0050] With the rapid development of data storage, key-value store designs that rely solely on the computing resources of host or storage devices may suffer from computational and / or network bottlenecks (e.g., CPU bottlenecks). That is, although storage devices have become faster and smarter, their performance may not be fully realized due to limitations in data processing and transfer capabilities, such as insufficient CPU processing and transfer efficiency. In key-value stores implemented using storage devices with computational storage capabilities (hereinafter referred to as computational storage devices), traditional host-based caches may not fully utilize the advantages of peer-to-peer (P2P) transfers between the processing circuitry of the computational storage device (e.g., FPGA) and the memory of the storage device (e.g., non-volatile memory or RAM). Therefore, the computing power of the FPGA may not be fully utilized.

[0051] Regarding crash consistency strategies, key-value stores implemented using log-based consistency strategies may cause various problems, such as increased write amplification, input / output (I / O) interdependencies, and slow request processing.

[0052] To improve the performance of key-value stores, embodiments of the present disclosure provide a key-value store that can be logically divided to utilize both the host processor and the processing circuitry of the computing storage device. For example, the key-value store according to the present disclosure can reduce CPU bottlenecks and data retrieval pauses in preprocessing pipelines (e.g., preprocessing pipelines for artificial intelligence (AI) and machine learning (ML) applications).

[0053] In some embodiments, data plane computing can be offloaded from the host processor to a computing storage device to take advantage of the high-speed bandwidth of the computing storage device.

[0054] In some embodiments, the key-value store may be divided into two parts: (1) a search layer (e.g., internal nodes in a B-tree) processed by a host processor; and (2) a data layer (e.g., leaf nodes in a B-tree) processed by processing circuitry on a computing storage device. Although examples of the search layer and data layer disclosed herein may refer to a B-tree index structure, it should be understood that this disclosure is not limited thereto. For example, the search layer and data layer of the form according to embodiments of this disclosure may be implemented via any suitable sorted index structure (e.g., B+ tree, Trie, or Adaptive Radix Tree).

[0055] The search layer can store partial keys. The data layer can store key fingerprints corresponding to keys belonging to specific data nodes. Therefore, key fingerprints can identify the precise location of the value corresponding to the key-value pair within the data storage.

[0056] As will be further described in detail below with reference to the accompanying drawings, a key-value store (e.g., a cross-layer key-value store) according to one or more embodiments can use a cross-layer method to utilize a host processor in the control plane and offload data plane computation to the processing circuitry of the computing storage device. Therefore, the key-value store can utilize the high bandwidth of the computing storage device.

[0057] The key-value store may also incorporate one or more of the following features discussed in further detail below: (1) cross-layer approach for improving throughput and scalability; (2) cross-layer cache (e.g., mirror cache) for improving data locality (e.g., reducing or eliminating unnecessary (e.g., redundant) data movement); and (3) version-based crash consistency for simplified crash consistency (e.g., crash consistency strategy based on version number rather than write-ahead log).

[0058] In addition to improved efficiency, key-value stores can be integrated into the computing pipeline to significantly reduce data retrieval pauses and achieve the advantage of offloading preprocessing to the computing storage device.

[0059] Furthermore, although this disclosure relates to a host coupled to a computing storage device, it is not limited thereto. For example, in some embodiments, the key-value store according to this disclosure may utilize a heterogeneous system having multiple storage devices and accelerators connected to a server.

[0060] Systems and methods for cross-layer key-value stores with computing storage devices can provide key-value stores with reduced bottlenecks (e.g., larger overall system bandwidth), increased throughput, scalability, and data locality. This improvement can be achieved by logically partitioning the key-value store into: (1) a search layer stored in host memory and manipulated (e.g., processed) by a host processor; and (2) a data layer stored in computing storage devices and processed by the processing circuitry of the computing storage devices. Furthermore, in some embodiments, cross-layer key-value stores can provide simplified crash consistency by utilizing version-based crash consistency rather than log-based crash consistency.

[0061] For example, the key-value store may be implemented as a system including a host and a storage device or implemented on a system including a host and a storage device, the storage device including persistent memory (e.g., a solid-state drive (SSD) or other non-volatile memory portion of the storage device), processing circuitry (e.g., an FPGA), and a common memory region (CMA) linked to the persistent memory and the processing circuitry (e.g., via P2P memory).

[0062] The host can store and manipulate (e.g., process) the search layer, which includes a sorted index (e.g., a tree structure). The host can also store and manipulate (e.g., process) the host cache portion of the "mirror cache" of the key-value store. The storage device can store and process the data layer, which includes leaf nodes (e.g., data nodes) of the tree structure. The storage device can also store and process the kernel cache portion of the mirror cache.

[0063] The host cache can be implemented as a two-dimensional (2D) array. Each entry of the host cache that stores the metadata corresponding to the data node can be stored in a storage device.

[0064] The kernel cache can be implemented as a one-dimensional (1D) array of data nodes stored in the CMA. The host can store each entry of the host cache at the same offset as the data node stored in the kernel cache (e.g., reducing the amount of data movement within the system).

[0065] Key-value stores can distribute responsibility between the host processor (e.g., CPU) and the processing circuitry of the storage device (e.g., FPGA). For example, key-value stores can decentralize control over the processing of requests for accessing data nodes stored on the storage device. Thus, the host processor can operate in the control plane to trigger (e.g., cause or issue) kernel calls, issue data transfers to or from persistent memory (hereinafter referred to as storage), and manage crash consistency. The processing circuitry of the storage device can manipulate data plane operations, allowing key-value stores to take advantage of the relatively high access throughput of the computing storage device.

[0066] In addition, the key-value store can be implemented to provide variable-length key-value support with a version-based crash consistency mechanism that maintains version metadata to avoid the management burden of logging technologies (such as WAL).

[0067] Therefore, compared with other key-value store designs, the key-value store of the form disclosed in this embodiment can provide several improvements and advantages, including: (1) reducing bottlenecks by logically dividing it into a search layer and a data layer to use only the host processor as the control plane and offloading data plane tasks to the processing circuitry; (2) improving I / O bandwidth utilization by transferring data to the processing circuitry through P2P memory, and thus reducing network hops (e.g., reducing the number of data transfers between the memory and the host), thereby increasing total throughput; (3) avoiding logging (e.g., computationally expensive / data-intensive log-based recovery) by implementing version-based crash consistency using atomic updates (e.g., 4 kilobit (KB) size updates); and (4) allowing scalability without synchronization problems because the search layer and data layer are logically and physically separated between the host processor and the processing circuitry.

[0068] FIG1 is a system diagram illustrating a data storage system including a search layer and a data layer according to some embodiments of the present disclosure.

[0069] Referring to FIG1, system 1 may include host 100, which may be coupled to storage device 200 (e.g., computing storage device). Host 100 may include host processor 110 (e.g., host CPU) and host memory 120 (e.g., host DRAM).

[0070] Storage device 200 may include (e.g., may be) computing storage device, which includes memory 210 (e.g., persistent memory or non-volatile memory), memory controller 212 (e.g., non-volatile memory express (NVMe) auxiliary controller), processing circuitry 220 (e.g., accelerator (e.g. FPGA)) and common memory region (CMA) 230 (e.g., P2P memory of computing storage device, which may be a part of the DRAM of processing circuitry 220 linked or shared with memory 210 and processing circuitry 220).

[0071] Storage device 200 may store one or more data nodes DN (see also FIG. 4). Each data node DN may include a set of key-value pairs (e.g., multiple key-value pairs that may be arranged in ascending order and drawn as "AAA" and "AAB" in FIG. 1 and FIG. 4). The set of key-value pairs in the corresponding data node may correspond to the same set of keys in the search layer 150 of the host memory 120.

[0072] System 1 may include (e.g.) a key-value store with a cross-layer architecture, wherein responsibilities such as processing data access requests are separated between the host processor 110 and the processing circuitry 220 to improve the performance of conventional key-value stores. For example, a search layer 150 may be stored on host memory 120, and a data layer 250 may be stored on storage device 200 (e.g., in memory 210). The host processor 110 may manipulate (e.g., process, maintain, or control) the search layer 150. The processing circuitry 220 may process the data layer 250.

[0073] Therefore, the host processor 110 can act as a control plane and perform appropriate operations, such as triggering FPGA kernel calls (e.g., kernel calls directed to processing circuitry 220), issuing (e.g., initiating) data transfers to and from storage 210, and managing parallel control (e.g., managing parallel access to storage device 200 from multiple requests). Furthermore, processing circuitry 220 can manage operations on the data plane, such as manipulating (e.g., processing) and controlling data (e.g., performing data node updates and updating the corresponding metadata of the updated data nodes).

[0074] By delegating the manipulation (e.g., processing) of the search layer 150 to the host processor 110, and simultaneously delegating the operation of the data layer 250 to the processing circuitry 220, different sources of computing power can be used more appropriately. For example, the system 1 can utilize the internal bandwidth (e.g., high internal bandwidth) between the memory 210 and the processing circuitry 220, while also reducing (e.g., minimizing) data movement caused by P2P data transfers (e.g., direct data transfers) between the memory 210 and the processing circuitry 220.

[0075] Search layer 150 may be implemented as, for example, a tree structure on host memory 120, which stores partial keys (e.g., storing partial keys as internal nodes in a B-tree metastructure). Although search layer 150 and data layer 250 are illustrated herein as corresponding to a tree structure, it should be understood that this disclosure is not limited thereto, and other sorted index structures may be suitable.

[0076] The data layer 250 can be implemented as a doubly linked list of leaf nodes (e.g., leaf nodes in a B-tree structure) on the storage device 200 corresponding to the data node DN. The search layer (e.g., a tree structure) helps to quickly find point queries. The data layer, as a doubly linked list, can store key-value pairs in ascending order, thus achieving fast range queries. Therefore, unlike some traditional key-value stores that do not perform range operations, a cross-layer key-value store allows System 1 to be applicable to both point queries (e.g., operations corresponding to a single key-value pair) and range queries (e.g., operations corresponding to more than one consecutive key-value pair).

[0077] The embodiments of the cross-layer key-value store provide the flexibility of host CPU processing (e.g., range query processing) and a framework for near-data processing (e.g., lookup operations in leaf nodes, data compression, and deep learning preprocessing) using processing circuitry 220 (e.g., FPGA on memory). Furthermore, the cross-layer key-value store with decoupled search and data layers allows for easy scaling on networks to non-uniform memory access (NUMA) nodes connected to multiple storage devices 200.

[0078] Figure 2 is a system diagram illustrating a data storage system including a host cache and a kernel cache according to some embodiments of the present disclosure.

[0079] Referring to FIG2, System 1 may include a mirrored cache 7 (or cross-tier cache) partitioned across host memory 120 of host 100 and CMA 230 of storage device 200. Mirrored cache 7 may include host cache 170 (e.g., metadata cache) on host memory 120 and kernel cache 270 (e.g., data cache) on CMA 230. Mirrored cache 7 provides data locality (e.g., improved data locality).

[0080] Maintaining a metadata cache on host 100 enables host processor 110 to operate in the control plane and allows the data cache on CMA 230 to utilize high-speed peer-to-peer data transfer provided by compute storage device 200. By offloading data layer computation to storage device 200 (which can typically be done by a host with a conventional key-value store), the granularity of data access from storage device 210 can be the size of a data page (e.g., 4 kilobits).

[0081] Although using a conventional host-based cache in this case can provide sufficient capacity to store data nodes (DNs) (e.g., data pages), using a cross-layer cache can provide several advantages and improvements over using a host-based cache. For example, using a cross-layer cache can: (1) reduce the latency of accessing data pages; (2) reduce network traffic, as the number of hops (e.g., the number of data transfers between storage 210 and host 100) will be reduced; and (3) take advantage of the P2P transfer between processing circuit 220 and storage device 200, and thus take advantage of the computing power of processing circuit 220.

[0082] The computing storage device 200 can connect the memory 210 and the processing circuitry 220 via an internal data path, thereby achieving high-speed data transfer known as peer-to-peer data transfer. This connection can be achieved via an on-chip peripheral component interconnect express (PCIe) switch and the device memory of the processing circuitry 220. The computing storage device 200 can map both the memory 210 and the memory (e.g., DRAM) of the processing circuitry 220 onto a peripheral component interconnect express (PCIe) strip 260 (e.g., PCIe strip memory). The portion of the memory of the processing circuitry 220 exposed to the PCIe strip 260 may include (e.g., a CMA 230).

[0083] The host cache 170 may be stored as a set-associative cache on the host memory 120. This set-associative cache stores metadata and enables the host processor 110 to perform actions in the control plane to control cache sustaining operations and manage parallel access. The host cache 170 may be a hash table storing metadata for the corresponding data node (DN). For example, each host cache entry 172 may store metadata such as logical block address (LBA), timestamp, occupancy flag, least recently used (LRU) information for eviction, and locking information for parallel cache access. The host cache 170 may be a two-dimensional (2D) array.

[0084] Kernel cache 270 may be stored on CMA 230 to store data node DN and enable cross-layer key-value stores to take advantage of the benefits provided by computing storage device 200 (e.g., P2P access and reduced network latency). Kernel cache 270 may be a flat one-dimensional (1D) array (e.g., a large P2P buffer).

[0085] The name "Mirror Cache" indicates its layout characteristics. For example, each host cache entry 172 on host cache 170 may store its corresponding metadata at the same offset as the kernel cache entry 272 on kernel cache 270 corresponding to the actual data node DN (e.g., the tenth entry in host cache 170 may include metadata corresponding to the data node DN stored at the tenth entry in kernel cache 270). Therefore, the layout of host cache 170 can reflect the layout of kernel cache 270. Therefore, mirror cache 7 can reduce the number of data moves, for example because the presence of LBA in host cache 170 can indicate the presence of the corresponding data node DN in kernel cache 270.

[0086] FIG3A is a combination flowchart and system diagram illustrating the operation of a method for storing data in a system according to some embodiments of the present disclosure.

[0087] Referring to FIG3A, a method 3000A for processing a data access request for accessing a data node DN stored on a storage device 200 in a cross-layer key-value storage system 1 may include the following operations.

[0088] Host 100 may receive data access requests (e.g., insert operations with key-value pairs) (Operation 3001A).

[0089] Control can be transferred to host processor 110, which may have a search layer 150 located inside host memory 120 to enable the search layer 150 to search for keys (e.g., partial keys). Note that the search layer 150 may be narrowed down to the leaf node of the LBA pointing to the data node DN internally (operation 3002A).

[0090] The host processor 110 can use LBA to look up (e.g., search) the host cache 170 that also exists on the host memory 120 to determine whether the corresponding data node DN exists in the kernel cache 270 of the mirror cache 7 (operation 3003A).

[0091] The host processor 110 may search for metadata in the host cache 170, and the search may result in (i) a cache miss, wherein the corresponding data node DN is not present in the kernel cache 270, or (ii) a cache hit, wherein the data node DN is present in the kernel cache 270 (operation 3004A).

[0092] Based on the determination that a cache miss has occurred, the host processor 110 may issue (e.g., trigger or cause) a read (e.g., P2P read) from memory 210 to kernel cache 270 located on CMA 230 (operation 3005A).

[0093] In response to a P2P read, control can be transferred to storage device 200 to populate the data node DN into kernel cache 270 (operation 3006A). After populating the data node DN into kernel cache 270, control can be transferred back to host 100.

[0094] Based on the determination that a cache hit has occurred, or based on the determination that a data node DN has been filled in the kernel cache 270, the host 100 may issue (e.g., trigger or cause) a kernel call (e.g., insert a kernel call), which may pass control to the processing circuitry 220 (operation 3007A).

[0095] In response to a kernel call, the processing circuit 220 may read the data node DN from the kernel cache 270 (e.g., the data node DN may be read into local memory in the processing circuit 220), and may retrieve or generate a fingerprint (fp) of a specific key to narrow down the exact location of the key-value pair within the data node DN (operation 3008A).

[0096] Based on determining the exact location of the key-value pair, the processing circuit 220 can perform operations on the data node DN (e.g., insertion operations) (e.g., the processing circuit 220 can manipulate the data node DN in local memory in the processing circuit 220 (e.g., process or perform one or more operations), and can fill the updated data node DN back onto the kernel cache 270) (operation 3009A).

[0097] Upon completion of the operation performed on the data node DN by the processing circuit 220, control may return to the host 100 to persistently save (e.g., write) the updated data node DN to the storage 210 (e.g., via a P2P write issued from the CMA 230 back to the storage 210) (Operation 3010A).

[0098] Once the updated data node DN has been persistently saved to storage 210, the method can be completed and exited (operation 3011A).

[0099] FIG3B is a flowchart illustrating the operation of a data storage method corresponding to the operation shown in FIG3A according to some embodiments of the present disclosure.

[0100] Referring to Figure 3B, the operations (e.g., operations 3001A to 3011A) described above with reference to Figure 3A are presented in a simplified manner in the form of a flowchart, and the structure of System 1 is not shown.

[0101] For example, host processor 110 may receive a request associated with a key to access a data node DN (operation 3001B).

[0102] The host 100 (e.g., the host processor 110 of the host 100) can search (e.g., locate) a key in the search layer 150 to find information indicating the location of the data node DN (e.g., find the LBA of the data node DN) (operation 3002B).

[0103] Host 100 may look up (e.g., search for or locate) LBA (Operation 3003B) in host cache 170 of mirror cache 7.

[0104] Based on the search of host cache 170, host 100 can determine whether data node DN exists in kernel cache 270 of mirror cache 7 (operation 3004B).

[0105] Based on the determination of a cache miss, host 100 may issue (e.g., trigger or cause) a P2P read from storage 210 to CMA 230 (operation 3005B).

[0106] Storage device 200 can fill data node DN from storage 210 onto kernel cache 270 (operation 3006B).

[0107] Based on determining that a cache hit has occurred or based on determining that a data node DN has been filled into the kernel cache 270, the host 100 may issue (e.g., trigger or cause) a kernel call (operation 3007B) based on a request (e.g., a request received in operation 3001B).

[0108] In response to a kernel call, control may be passed to processing circuitry 220 to perform the requested data manipulation (e.g., data processing) operation on the data node DN, and processing circuitry 220 may obtain a fingerprint (fp) to determine the exact location of the key-value pair within the data node DN (operation 3008B).

[0109] The processing circuit 220 can perform the requested data manipulation (e.g., data processing) operation (operation 3009B) on the data node DN.

[0110] Host 100 may issue (e.g., trigger or cause) a P2P write to persistently save the updated data node DN from CMA 230 to storage 210 (Operation 3010B).

[0111] Once the updated data node DN has been persistently saved to storage 210, the method can be completed and the operation can be exited (operation 3011A).

[0112] Figure 4 is a combination flowchart and system diagram illustrating the operation of a method for storing data in a system that provides variable-length key value support according to some embodiments of the present disclosure.

[0113] Referring to FIG4, in some embodiments, System 1 may provide variable-length key-value support. Additionally, as discussed below with reference to FIG5, variable-length key-value support may be implemented to support version-based crash consistency.

[0114] In some embodiments, AI / ML applications that process relatively large amounts of data (e.g., images, videos, etc.) spanning multiple data pages can utilize the cross-layer key-value store system 1. Since each data node DN can have a fixed size equal to the size of a data page (e.g., 4 kilobits) according to various embodiments of this disclosure, system 1 can be configured to support variable-length key-value pairs to accommodate larger key-value pairs by dispatching (e.g., allocating or linking) extension nodes EN to corresponding data node DNs. Extension nodes EN can be provided and allocated by a slice allocator SA (e.g., a host-side assistance function) from a pool of data pages of different sizes (e.g., 4 kilobits, 8 kilobits, 16 kilobits, 32 kilobits, etc.), and then linked to the corresponding data node DN.

[0115] Therefore, the method 4000 for providing variable-length key-value support may include: receiving at the host 100 a request to access a data node DN stored at the storage device 200 (e.g., using a key-value pair insertion operation) (operation 4001); searching (e.g., locating) the corresponding data node DN corresponding to the key-value pair (operation 4002); determining that the data node DN lacks free space (e.g., determining that the amount of available space in the data node DN is less than the amount of space to accommodate the request) (operation 4003); updating the metadata MD of the data node DN to mark the existence of the extension node EN, and adding the fingerprint of the extension node EN to the data node DN (e.g., implementing a pointer from the data node DN to the extension node EN within the data node DN) (operation 4004); and retrieving the extension page from the slice allocator SA and adding the metadata and key-value pair to the extension node EN (operation 4005).

[0116] Figure 5 is a combined flowchart and system diagram illustrating the operation of a method for storing data in a system that provides variable key value support and version-based crash consistency according to some embodiments of the present disclosure.

[0117] Referring to FIG5, in some embodiments, the cross-layer key-value store system 1 may provide a version-based crash consistency strategy that uses versioning and atomic reads / writes (e.g., 4-kilobyte atomic reads / writes) to avoid the overhead costs associated with conventional log-based crash consistency techniques. A version-based crash consistency model according to embodiments of this disclosure may utilize atomic block reads / writes (e.g., 4-kilobyte block reads / writes) for off-site updates (discussed below) and identify valid data pages by scanning the entire disk (e.g., storage 210) at the time of a crash.

[0118] By using versioning, System 1 can utilize atomic read / write by using the following scheme. Updates to data node DNs can be written "in place". For example, an update to a data node DN can be written to storage at the same file offset as its previous version (e.g., at the original location of the previous version of the data node DN).

[0119] Updates to extended nodes EN that are larger than a data page and are assigned to data nodes DN can be updated to storage "off-site". For example, a previous version of the extended node EN can remain in its original location (e.g., it can be unmodified), and the updated extended node EN can be written to a different location than the previous version of the extended node EN.

[0120] Additionally, to provide correctness (e.g., to guarantee correctness), in the presence of an extended node EN, the data node DN can be written in-situ after the extended node EN is fully persisted on storage 210 to provide crash consistency. In the event of a crash in any state (e.g., power failure), previous versions of the data node DN can be maintained (e.g., undisturbed), and if a newer version of the extended node EN exists on storage 210, it can be garbage collected by the slice allocator SA (e.g., making it available to other processes running on system 1).

[0121] Referring again to FIG5, the method 5000 for providing variable-length key-value support and version-based crash consistency may include the following. System 1 may process an operation to update an extension node EN (e.g., Ext. node 3), which has been assigned by a slice allocator SA to a data node DN (e.g., data node 3), wherein each of the data node DN and the extension node EN is located in storage 210 and has the same version number VN (e.g., 0) (operation 5001).

[0122] System 1 can create copies of the data node DN and its extension node EN on CMA 230 (Operation 5002).

[0123] Based on the copies of the data node DN and the extension node EN existing in CMA 230, the processing circuit 220 can be triggered to (i) read the data node DN and the extension node EN into their local memory, (ii) perform the requested calculation based on the operation, and (iii) update the extension node EN based on the operation (operation 5003).

[0124] Based on the completion of the operation, the processing circuit 220 may use the updated version number VN (e.g., updated to 1, such that the metadata MD of the updated data node DN points to the updated extension node EN) to write the value (e.g., the updated data node DN and the updated extension node EN) back to CMA 230 (operation 5004).

[0125] The updated extended node EN can be persistently stored (e.g., written) to storage 210 in a remote manner, so that the previous version of the extended node EN is maintained (e.g., not tampered with) (operation 5005).

[0126] Based on the updated extended node EN being fully written to storage 210, the updated data node DN can be persistently saved to storage 210 in place (e.g., at the location where the previous version of data node DN existed), so that the previous version of data node DN is overwritten by the updated data node DN, thereby making data node DN point to the updated extended node EN, because its internal metadata MD (see Figure 4) has been internally updated to point to the updated extended node EN (operation 5006).

[0127] By implementing method 5000, system 1 can be resilient to crash events. For example, if a crash occurs while the updated extended node EN is being persistently saved to storage 210 (e.g., in operation 5005), since the updated extended node is being persistently saved to storage 210 remotely, the operation can be aborted and restarted, and garbage collection can be performed on the partially written extended node.

[0128] If a crash occurs while the updated data node DN is being persistently saved in-place to storage 210 (e.g., during operation 5006), the operation can be simply aborted and restarted (garbage collection of the partially written extension node), and system 1 can roll back to a previous version of both the data node DN and the extension node EN. Therefore, data loss can be reduced (e.g., prevented).

[0129] Figure 6 is a flowchart illustrating the operation of a data storage method for a read (or lookup) request including host-side concurrency control, according to some embodiments of the present disclosure.

[0130] Referring to FIG6, host 100 (e.g., see FIG1 and FIG2) may control parallel access to storage device 200 by implementing read parallelism 6000 (e.g., for a lookup operation), the method including: initiating a lock-free lookup at the search layer (operation 6001); traversing the metadata of data node DN by host 100 to acquire a read lock on data node DN (operation 6002); searching (e.g., locating or searching) an LBA in host cache 170 using the found LBA to find the location of data node DN on kernel cache 270 (operation 6003); acquiring a read lock on host cache slot in the case of a cache hit (operation 6004A); issuing (e.g., triggering or causing) a P2P read I / O call in the case of a cache miss to load data node DN from storage 210 into kernel cache 270 (operation 6004B). 1) and acquire a write lock on the host cache slot (operation 6004B2); prepare the data node DN at the found offset based on the kernel cache, trigger the lookup kernel on the processing circuit 220 (e.g., FPGA) (system 1 may issue (e.g., trigger or cause) multiple computing units for each kernel function to achieve parallelism on the kernel side) (operation 6005); based on the completion of kernel execution, control may be transferred back to host 100, and before exiting the application, host 100 may release the read / write (mirror cache) lock on the host cache slot (operation 6006) and the read lock on the data node DN metastructure (operation 6007); and exit the method (operation 6008).

[0131] Figure 7 is a flowchart illustrating the operation of a data storage method for a write (or insert) request including host-side parallel control, according to some embodiments of the present disclosure.

[0132] Referring to FIG7, host 100 (e.g., see FIG1 and FIG2) may control parallel access to storage device 200 by implementing write parallelism 7000 (e.g., for insert operations), the method may include: initiating a lock-free lookup at the search layer (operation 7001); host 100 traversing the metastructure of data node DN to acquire a write lock on data node DN (operation 7002); host 100 using the found LBA to look up (e.g., locate) the LBA in host cache 170, thereby finding the location of data node DN on kernel cache 270 (operation 7003); in the event of a cache miss, issuing (e.g., initiating or triggering) a P2P read I / O call to load data node DN from storage 210 into kernel cache 270 (operation 7004A), and acquiring host... Write lock on cache slot (Operation 7004B); In the event of a cache hit, acquire write lock on host cache slot without issuing (e.g., without triggering or causing) a P2P read I / O call (Operation 7004B); Based on the kernel cache preparing the data node DN at the found offset, trigger the insertion of the kernel on the processing circuitry 220 (e.g., FPGA) (System 1 may issue (e.g., trigger or cause) multiple compute units for each kernel function to achieve parallelism on the kernel side) (Operation 7005); Based on the completion of kernel execution, control may be transferred back to host 100, and before exiting the application, host 100 may release write (mirror cache) lock on host cache slot (Operation 7006) and write lock on data node DN metastructure (Operation 7007); and exit the application (Operation 7008).

[0133] Therefore, referring back to FIG2, the configuration of the disclosed embodiments provides advantages and improvements over conventional key-value stores, such as reducing bottlenecks at the host processor 110 and utilizing the high internal bandwidth and near-data computation of the computing storage device 200. These advantages and improvements can be achieved by logically and physically partitioning the key-value store between the host 100 and the computing storage device 200. Thus, responsibilities associated with the search layer 150 can be performed by the host 100, while responsibilities associated with the data layer 250 can be performed by the computing storage device 200. The disclosed embodiments also provide structural advantages for a mirrored cache 7, which includes a host cache 170 stored on the host 100 and a kernel cache 270 stored on the CMA 230 of the computing storage device 200.

[0134] Although embodiments of the present disclosure have been specifically shown and illustrated with reference to the embodiments set forth herein, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the disclosure as set forth in the following claims and their functional equivalents. [Simplified Explanation of the Diagram]

[0028] Non-limiting and non-exhaustive embodiments of the present disclosure are illustrated with reference to the following figures, wherein, unless otherwise specified, the same reference numerals in the various views always refer to the same components. Figure 1 is a system diagram illustrating a data storage system including a search layer and a data layer according to some embodiments of the present disclosure. Figure 2 is a system diagram illustrating a data storage system including a host cache and a kernel cache according to some embodiments of the present disclosure. Figure 3A is a combined flowchart and system diagram illustrating the operation of a method for storing data in a data storage system according to some embodiments of the present disclosure. Figure 3B is a flowchart illustrating a data storage method corresponding to the operation shown in Figure 3A according to some embodiments of the present disclosure. Figure 4 is a combined flowchart and system diagram illustrating the operation of a method for storing data in a data storage system providing variable-length key-value support according to some embodiments of the present disclosure. Figure 5 is a combined flowchart and system diagram illustrating the operation of a method for storing data in a data storage system providing variable key-value support and version-based crash consistency according to some embodiments of the present disclosure. Figure 6 is a flowchart illustrating a method for data storage including a read (or lookup) request with host-side parallel control, according to some embodiments of the present disclosure. Figure 7 is a flowchart illustrating a method for data storage including a write request with host-side parallel control, according to some embodiments of the present disclosure. In the various views of the figures, corresponding reference characters always indicate corresponding components. Those skilled in the art will understand that the elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements, layers, and areas in the figures may be exaggerated relative to other elements, layers, and areas to help improve the clarity and understanding of the various embodiments. In addition, common but well-known elements and components not related to the description of the embodiments may not be shown in order to obtain a less obstructive view of these various embodiments and to make the description clearer.

Claims

1. A method for storing data, the method comprising: The host of the key-value store receives a request to access a data node stored in the storage device of the key-value store; Locate the address corresponding to the data node in the host cache on the host; and determine that the data node is in the kernel cache on the storage device.

2. The method as described in claim 1, wherein the offset of the entry in the host cache storing metadata corresponding to the data node is the same as the offset of the entry in the kernel cache storing the data node.

3. The method as described in claim 1, further comprising: The host locates the address in the search layer on the host. A kernel call is initiated to transfer control for processing the request from the host to the processing circuitry of the storage device; the processing circuitry processes the data on the data node; the data node is written to the kernel cache as an updated data node; and the host writes the updated data node from the kernel cache to the storage of the storage device in a peer-to-peer manner.

4. The method as described in request item 3, wherein: The search layer includes a tree structure; the data layer on the storage device includes the data nodes; the data nodes correspond to leaf nodes in a bidirectional link list corresponding to leaf nodes of the tree structure; and locating the address in the search layer includes locating a partial key in an internal node of the tree structure.

5. The method as described in claim 1, further comprising: It is determined that the amount of available space in the data node is less than the amount of space needed to accommodate the key corresponding to the request; And update the metadata of the data node to point to the extension node, wherein the metadata of the data node indicates a first version number, and the metadata of the extension node indicates the first version number.

6. The method of claim 5 further includes having the expand node allocated by a shard allocator to the data nodes which are composed of a pool of data pages of different sizes.

7. The method as described in claim 5, further comprising: Update the extended nodes; The metadata of the data node is updated to indicate a second version number; The metadata of the extended node is updated to indicate the second version number, which identifies the data node as an updated data node and the extended node as an updated extended node; and the metadata of the updated data node is updated to point to the updated extended node.

8. The method as described in claim 7, further comprising: The updated and expanded node is written to the storage device's memory in a remote manner; And write the updated data node to the storage in situ.

9. The method as described in claim 1, further comprising: The host obtains the read lock on the data node; Alternatively, the host may acquire a write lock on the data node.

10. A system for data storage, comprising: Host; and a storage device, wherein the host is configured to: receive a request to access a data node stored on the storage device; Locate the address corresponding to the data node in the host cache on the host; and determine that the data node is in the kernel cache on the storage device.

11. The system as claimed in claim 10, wherein the offset of the entry in the host cache storing metadata corresponding to the data node is the same as the offset of the entry in the kernel cache storing the data node.

12. The system of claim 10, wherein the host is configured to: locate the address in a search layer on the host; determine that the data node is in a kernel cache; initiate a kernel call to transfer control for processing the request from the host to the processing circuitry of the storage device; and cause the updated data node to be written peer-to-peer from the kernel cache to the memory of the storage device, wherein the processing circuitry of the storage device is configured to: process the data on the data node; and write the data node to the kernel cache as an updated data node.

13. The system as described in claim 12, wherein: The search layer includes a tree structure; the data layer on the storage device includes the data nodes; the data nodes correspond to leaf nodes in a bidirectional link list corresponding to leaf nodes of the tree structure; and the host is configured to search for the address based on locating a partial key in an internal node of the tree structure.

14. The system of claim 10, wherein the system is configured to: determine that the amount of available space in the data node is less than the amount of space to accommodate the key corresponding to the request; and update the metadata of the data node to point to an extension node, wherein the metadata of the data node indicates a first version number, and the metadata of the extension node indicates the first version number.

15. The system of claim 14, wherein the system is configured to: update the extended node; update the metadata of the data node to indicate a second version number; update the metadata of the extended node to indicate the second version number, the second version number identifying the data node as an updated data node and the extended node as an updated extended node; and update the metadata of the updated data node to point to the updated extended node.

16. A storage device, comprising: Processing circuitry; Persistent memory; And a shared memory region linked to the processing circuitry and the persistent memory, wherein the processing circuitry is configured to process requests for access to the data nodes stored on the storage device by reading data nodes from entries in the kernel cache on the shared memory region.

17. The storage device of claim 16, wherein the processing circuitry is configured to process the request by: performing data operations on the data node; and writing the data node to the kernel cache as an updated data node.

18. The storage device of claim 16, wherein the processing circuitry is configured to: update an extension node pointing to the data node, the extension node and the data node indicating a first version number; update the metadata of the data node to indicate a second version number; update the metadata of the extension node to indicate the second version number, the second version number identifying the data node as an updated data node and the extension node as an updated extension node; and update the metadata of the updated data node to point to the updated extension node.

19. The storage device as claimed in claim 18, wherein the processing circuitry is configured to write the updated extended node to the storage device's memory in a remote manner.

20. The storage device as claimed in claim 18, wherein the processing circuitry is configured to write the updated data node to the storage device's memory in situ.

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