Cell libraries and computing systems

Abstract

A cell library is provided. The cell library is stored in a computer-readable storage medium. The cell library is configured to store: first delay information of a standard cell according to a threshold voltage of a transistor included in the standard cell; and second delay information of the standard cell according to mobility of the transistor included in the standard cell.

Description

[Technical Field]

[0001] This disclosure relates to a cell library, a computing system for designing integrated circuits by considering local layout effects, and a method for designing integrated circuits. Integrated circuits can be designed based on standard cells (i.e., based on standard cells). Specifically, the layout of integrated circuits can be generated by placing standard cells that define the integrated circuits and routing through the placement of these standard cells. [Cross-Reference to Related Applications]

[0002] This application claims priority to Korean Patent Application No. 10-2022-0043612, filed on April 7, 2022, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. [Previous Technology]

[0003] With the miniaturization of semiconductor manufacturing processes, standard cells containing patterns formed in multiple layers can not only contain smaller patterns, but also reduce the size of the standard cells. Therefore, standard cells contained in integrated circuits may be greatly affected by their surrounding structures (i.e., layout), and such effects of the surrounding layout can be called the local layout effect (LLE) or layout-dependent effect (LDE). [Summary of the Invention]

[0004] The present disclosure provides a cell library that stores the change in delay of a standard cell based on the change in the threshold voltage of the transistor of the standard cell, and the change in delay of a standard cell based on the change in the mobility of the transistor of the standard cell.

[0005] This disclosure also provides a computing system for designing integrated circuits, which is capable of analyzing the timing of integrated circuits regardless of the type of local layout effects.

[0006] The present disclosure also provides a method for designing integrated circuits, which is capable of analyzing the timing of integrated circuits regardless of the type of local layout effects.

[0007] According to some embodiments of the present disclosure, the cell library is stored in a computer-readable storage medium, wherein the cell library is configured to store: first delay information of the standard cells based on the threshold voltage of the transistors included in the standard cells; and second delay information of the standard cells based on the mobility of the transistors included in the standard cells.

[0008] According to some embodiments of this disclosure, a computing system includes: a memory configured to store a program for designing an integrated circuit including standard cells, the standard cells including transistors; and a processor. The processor is configured to execute the program to: receive input data from the standard cells; measure a change in a first delay of the standard cells based on a change in a threshold voltage of the transistor; measure a change in a second delay of the standard cells based on a change in the mobility of the transistor; and store the changes in the first delay and the changes in the second delay in a cell library.

[0009] According to some embodiments of the present disclosure, a computing system includes: a memory configured to store a program for designing an integrated circuit; and a processor configured to execute the program to: place and route a plurality of standard cells defining the integrated circuit to generate layout data of the integrated circuit; and calculate the delay of the integrated circuit using a change in the delay of each of the plurality of standard cells based on a change in the threshold voltage of a transistor in each of the plurality of standard cells, and a change in the delay of each of the plurality of standard cells based on a change in the mobility of a transistor in each of the plurality of standard cells.

[0010] According to some embodiments of the present disclosure, a method for designing an integrated circuit includes: receiving input data comprising a standard cell containing a transistor; adding a threshold voltage of the transistor and the mobility of the transistor as variables to the input data; changing the variables, and using the changed variables to measure a first change in the delay of the standard cell according to the change in the threshold voltage of the transistor and a second change in the delay of the standard cell according to the change in the mobility of the transistor; and storing the first change in the delay and the second change in the delay in a cell library.

[0011] However, the forms of this disclosure are not limited to those described above. The above and other forms of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains by referring to the detailed description of this disclosure given below.

Implementation Method

[0013] Figure 1 is a diagram for explaining a computing system for designing integrated circuits according to some embodiments.

[0014] Referring to FIG1, a computing system 100 for designing integrated circuits according to some embodiments may include a processor 110, memory 130, input / output (I / O) device 150, storage device 170, and bus 190. The computing system 100 may be implemented as, for example, an integrated device. For example, the computing system 100 may be provided as a dedicated device for designing integrated circuits. The computing system 100 may be, for example, a computer for driving various simulation tools or design tools.

[0015] The processor 110 can be configured to execute commands that perform at least one of various behaviors / operations for designing integrated circuits. The processor 110 may include, for example, a core capable of executing arbitrary commands, such as a microprocessor, an application processor (AP), a digital signal processor (DSP), and a graphics processing unit (GPU).

[0016] The processor 110 can communicate with the memory 130, I / O device 150, and storage device 170 via bus 190. The processor 110 can drive the placement and routing (P&R) module 210, analog module 220, and static timing analysis (STA) module 230 loaded into the memory 130 to design integrated circuits. The P&R module 210, analog module 220, and STA module 230 can be program or software modules containing multiple commands executed by the processor 110, and can be stored in a non-transitory computer-readable storage medium.

[0017] Memory 130 may store P&R module 210, analog module 220, and STA module 230. P&R module 210, analog module 220, and STA module 230 may be loaded from, for example, storage device 170. Memory 130 may be volatile memory such as SRAM or DRAM, or non-volatile memory such as PRAM, MRAM, ReRAM, and FRAM NOR flash memory.

[0018] The P&R module 210, the analog module 220 and the STA module 230 will be described in detail using Figures 2 to 15.

[0019] The I / O device 150 can control user input and output from a user interface device. For example, the I / O device 150 includes input devices such as a keyboard, mouse, and / or touchpad, and can receive input data defining integrated circuits. For example, the I / O device 150 includes output devices such as a display and / or speaker, and can display placement results, routing results, timing analysis results, and / or the like.

[0020] Storage device 170 can store various data related to P&R module 210, analog module 220, and STA module 230. Storage device 170 can store a cell library. Storage device 170 may include, for example, memory cards (MMC, eMMC, SD, microSD, etc.), solid state drives (SSDs), hard disk drives (HDDs), and / or similar devices.

[0021] Figure 2 is a diagram illustrating a method for designing an integrated circuit according to some embodiments. Figure 3 is a flowchart illustrating a method for designing an integrated circuit according to some embodiments. Figure 2 is a detailed illustration of Figure 1.

[0022] Referring to Figure 2, the P&R module 210 may include a placeholder 211 and a router 212. The STA module 230 may include a Local Layout Effects (LLE) calculator 231 and a timing analyzer 232. As used herein, the processor 110 of Figure 1 executes / controls the P&R module 210 and the STA module 230 to perform the behavior / operation configuration, as represented by the configuration of the P&R module 210 and the STA module 230 performing this behavior / operation.

[0023] Storage device 170 may include cell library 270. Cell library 270 may store delay information (e.g., Delay orig) 271 of each standard cell in a specific environment (e.g., relative to the specific environment of each standard cell), delay information (e.g., Sensitivity_D_Vth) 272 that varies with the threshold voltage of each standard cell (e.g., based on the threshold voltage), delay information (e.g., Sensitivity_D_u0) 273 that varies with the mobility of each standard cell (e.g., based on the mobility), and cell library database 274, which contains information about the layout of standard cells for generating integrated circuits. For ease of description, delay information 272 may be referred to herein as "first" delay information, and delay information 273 may be referred to herein as "second" delay information. Furthermore, storage device 170 is an example of a non-transitory computer-readable storage medium.

[0024] Referring to Figures 2 and 3, a synthesis behavior / operation (S10) can be performed. Synthesis can mean generating a network connection table D10 by converting the input data of an integrated circuit into a hardware form composed of logic gates, and can be called logic synthesis. The input data can be an abstract form of the behavior / operation of the integrated circuit, for example, data defined by the Register Transfer Level (RTL). The network connection table D10 can be generated from RTL code using the cell library 270 stored in the storage device 170, and can be a gate-level network connection table D10. For example, the network connection table D10 can be executed by the processor 110 using a synthesis module. For example, the synthesis module can receive RTL code to output the network connection table D10.

[0025] The standard cells of the integrated circuit can be placed and routed according to the network connection table D10 to generate the layout data D20 (S20) of the integrated circuit. The placer 211 of the P&R module 210 can access the cell library database 274 to place the standard cells according to the network connection table D10. The router 212 of the P&R module 210 can perform routing on the standard cells placed by the placer 211 to generate the layout data D20. The router 212 can store the layout data D20 in the cell library 270. The layout data D20 can be, for example, data of a Graphic Design System (GDS) II type.

[0026] Local Layout Effect (LLE) parameters D30 (S30) can be extracted from the layout data D20. The P&R module 210 can extract the LLE parameters D30 from each standard cell contained in the layout data D20. The P&R module 210 can extract the LLE parameters D30 for each transistor contained in each standard cell. At this time, the P&R module 210 can extract the LLE parameters D30 for each transistor placed at the boundary of each standard cell. The P&R module 210 can receive the network connection table D10 to output the layout data D20 and the LLE parameters D30. The P&R module 210 can store the LLE parameters D30 in the cell library 270.

[0027] The LLE parameter D30 can be a parameter that causes the local layout effect to arise from the layout placed around the standard cell. For example, the LLE parameter D30 can include the presence or absence of active patterns placed around the standard cell, the shape of the active patterns, the size of the active patterns, the distance to the active patterns, and / or similar factors. For example, the LLE parameter D30 can include the distance from the standard cell to an active pattern with a wedge shape, the width of the nanosheet of the active pattern adjacent to the standard cell, and / or similar factors.

[0028] Timing analysis of the integrated circuit can be performed (S40). The STA module 230 can calculate the delay of the standard cells contained in the integrated circuit. The STA module 230 can generate a timing report D50 containing the delay of the standard cells. The STA module 230 can receive layout data D20, LLE parameters D30, LLE model D40, and delay information 271, delay information 272, and delay information 273 stored in the cell library 270 to output the timing report D50. The STA module 230 can further determine whether the calculated delay of the standard cells meets the set (e.g., predetermined) conditions to generate the timing report D50.

[0029] The integrated circuit may include multiple standard cells. The STA module 230 can calculate the delay of each standard cell included in the integrated circuit to generate a timing report D50 including the delay. The STA module 230 can calculate the delay of the integrated circuit based on the delay of each standard cell, and generate a timing report D50 further including the delay. The STA module 230 can further determine whether the delay of the integrated circuit meets the set conditions to generate a timing report D50. This will be described in detail using Figures 3 and 4.

[0030] The method for designing integrated circuits according to some embodiments may further include the step of executing an Engineering Change Order (ECO) based on the timing analysis performed in step S40. Alternatively, the method for designing integrated circuits according to some embodiments may again execute the placement and routing behavior / operation of the standard cells in step S20 based on the timing analysis performed in step S40. For example, clock tree synthesis or optimization included in the placement and routing behavior / operation of the standard cells may be performed. As yet another example, the metal routing included in the placement and routing behavior of the standard cells may be modified.

[0031] Figure 4 is a flowchart for explaining step S40 of Figure 3.

[0032] Referring to Figures 2 and 4, the STA module 230 can receive the LLE model D40 and LLE parameter D30 (S41). The STA module 230 can receive the LLE parameter D30 from the P&R module 210. The STA module 230 can receive the LLE parameter D30 extracted from the P&R module 210 for placing each transistor at the boundary of the standard cell.

[0033] The STA module 230 can receive the LLE model D40 via, for example, the I / O device of FIG1. ​​As another example, the STA module 230 can read the LLE model D40 stored in the storage device 170 of FIG1. ​​The LLE model D40 can receive the LLE parameter D30 to output information about changes in the physical characteristics of the standard cell based on the LLE effect. The information about changes in the physical characteristics of the standard cell may include the change in the threshold voltage of the standard cell and the change in the mobility of the standard cell. The change in the threshold voltage of the standard cell may include the change in the threshold voltage of each transistor placed at the boundary of the standard cell, and the change in the mobility of the standard cell may include the change in the mobility of each transistor placed at the boundary of the standard cell.

[0034] The LLE calculator 231 of the STA module 230 can input the LLE parameter D30 into the LLE model D40 to calculate the change in the threshold voltage of the standard cell and the change in the mobility of the standard cell (S42). The change in the threshold voltage of the standard cell may include the change in the threshold voltage of each transistor placed at the boundary of the standard cell. The change in the mobility of the standard cell may include the change in the mobility of each transistor placed at the boundary of the standard cell.

[0035] The timing analyzer 232 of the STA module 230 can calculate the delay of the standard cell (S43). The timing analyzer 232 can calculate the delay of the standard cell by using the delay information 271 of the standard cell in a specific environment stored in the cell library 270, the delay information 272 based on the threshold voltage of the standard cell, and the delay information 273 based on the mobility of the standard cell, as well as the change in the threshold voltage and the change in the mobility of the standard cell calculated in step S42. The delay information 272 based on the threshold voltage of the standard cell stored in the cell library 270 may include the change in the delay of the standard cell based on the change in the threshold voltage of each transistor placed at the boundary of the standard cell. The delay information 273 based on the mobility of the standard cell stored in the cell library 270 may include the change in the delay of the standard cell based on the change in the mobility of each transistor placed at the boundary of the standard cell.

[0036] For a standard cell, the timing analyzer 232 can use Equation 1 to calculate the delay of the standard cell. Equation 1 represents the delay of a standard cell. In Equation 1, n means the number of transistors placed at the boundary of the standard cell.

[0037] (Equation 1)

[0038] The timing analyzer 232 can calculate the delay of the standard cell by the following operations: multiplying the delay of the standard cell in a specific environment (Delay orig), the change in the delay of the standard cell based on the change in the threshold voltage of each transistor (tr_i) placed at the boundary of the standard cell, and the change in the threshold voltage of each transistor (tr_i) placed at the boundary of the standard cell, and adding the product of the change in the delay of the standard cell based on the change in the mobility of each transistor (tr_i) placed at the boundary of the standard cell, and the change in the mobility of each transistor (tr_i) placed at the boundary of the standard cell.

[0039] The timing analyzer 232 can receive from the cell library 270 the delay orig of a standard cell in a specific environment, the change in delay of the standard cell based on the change in the threshold voltage of each transistor placed at the boundary of the standard cell, and the change in delay of the standard cell based on the change in the mobility of each transistor placed at the boundary of the standard cell, and can receive from the LLE calculator 231 the change in the threshold voltage (ΔVth, tr_i) and the change in the mobility (Δμ0, tr_i) of each transistor placed at the boundary of the standard cell. The LLE calculator 231 can input LLE parameters into the LLE model to calculate the change in the threshold voltage (ΔVth, tr_i) and the change in the mobility (Δμ0, tr_i) of each transistor placed at the boundary of the standard cell.

[0040] The integrated circuit may include multiple standard cells. For each standard cell, the STA module 230 may execute steps S41 to S43. Specifically, the P&R module 210 may extract LLE parameters D30 from each transistor placed at the boundary of each standard cell, and the LLE calculator 231 may calculate the change in threshold voltage and the change in mobility of each transistor placed at the boundary of each standard cell by using the LLE model D40. The timing analyzer 232 may calculate the delay of each standard cell by using the delay information 271 of each standard cell in a specific environment stored in the cell library 270, the delay information 272 based on the threshold voltage of each standard cell, and the delay information 273 based on the mobility of each standard cell, as well as the change in threshold voltage and the change in mobility of each standard cell calculated by the LLE calculator 231. The delay information 272 stored in cell library 270 based on the threshold voltage of each standard cell may include the change in the delay (e.g., a first delay) of each standard cell based on the change in the threshold voltage of each transistor placed at the boundary of each standard cell. The delay information 273 stored in cell library 270 based on the mobility of each standard cell may include the change in the delay (e.g., a second delay) of each standard cell based on the change in the mobility of each transistor placed at the boundary of each standard cell.

[0041] Figure 5 is a diagram illustrating a method for designing an integrated circuit according to some embodiments. Figure 6 is a flowchart illustrating a method for designing an integrated circuit according to some embodiments. Figure 5 is a detailed illustration of Figure 1.

[0042] Referring to Figures 5 and 6, the analog module 220 can receive input data D11 (S110) for the standard unit. The input data D11 can be a network connection table.

[0043] The analog module 220 can add the threshold voltage and mobility of each transistor as variables to the input data D11 (S120). At this time, the analog module 220 can perform step S120 on each transistor placed at the boundary of the standard cell.

[0044] The analog module 220 can measure the change in delay of the standard cell based on the change in the threshold voltage of each transistor and the change in delay of the standard cell based on the change in the mobility of each transistor (S130). At this time, the analog module 220 can perform step S130 on each transistor placed at the boundary of the standard cell.

[0045] The analog module 220 can store the change in delay of the standard cell based on the change in the threshold voltage of each transistor and the change in delay of the standard cell based on the change in mobility of each transistor in the cell library 270 (S140). The change in delay of the standard cell based on the change in the threshold voltage of each transistor can be stored as delay information 272 of the standard cell based on the threshold voltage of the standard cell in the cell library 270. The change in delay of the standard cell based on the change in mobility of each transistor can be stored as delay information 273 of the standard cell based on the mobility of the standard cell in the cell library 270.

[0046] According to some embodiments, methods for designing integrated circuits can characterize (e.g., define) the local layout effects of standard cells by means of transistor threshold voltage and transistor mobility. That is, regardless of (e.g., independent of) the type of local layout effect, the local layout effect of standard cells can be characterized by transistor threshold voltage and transistor mobility. Therefore, it is not necessary to design methods for analyzing the timing of standard cells according to the type of local layout effect. Furthermore, it is not necessary to perform characterization behaviors / operations for each type of local layout effect.

[0047] Figures 7 to 15 are diagrams for explaining the method of designing integrated circuits according to some embodiments of Figure 6.

[0048] Referring to Figure 7, the standard cell may include a first active pattern RX1, a second active pattern RX2, and a first transistor tr1, a first transistor tr2, a second transistor tr3, and a fourth transistor tr4 placed at the boundary of the standard cell.

[0049] Referring to Figures 7 and 8, in the input data D11, the threshold voltage (tr1_p_vta) and mobility (tr1_u0_mult) of the first transistor tr1 can be defined (11), the threshold voltage (tr2_p_vta) and mobility (tr2_u0_mult) of the second transistor tr2 can be defined (12), the threshold voltage (tr3_p_vta) and mobility (tr3_u0_mult) of the third transistor tr3 can be added as a definition (13), and the threshold voltage (tr4_p_vta) and mobility (tr4_u0_mult) of the fourth transistor tr4 can be defined (14). The threshold voltages of the first transistor tr1 (tr1_p_vta), the second transistor tr2 (tr2_p_vta), the third transistor tr3 (tr3_p_vta), the fourth transistor tr4 (tr4_p_vta), the mobility of the first transistor tr1 (tr1_u0_mult), the mobility of the second transistor tr2 (tr2_u0_mult), the mobility of the third transistor tr3 (tr3_u0_mult), and the mobility of the fourth transistor tr4 (tr4_u0_mult) can be added as variables to the input data D11 (10). For example, the threshold voltages (tr1_p_vta) of the first transistor tr1, the second transistor tr2, the third transistor tr3, and the fourth transistor tr4 can be set to 0, and the mobility (tr1_u0_mult) of the first transistor tr1, the second transistor tr2, the third transistor tr3, and the fourth transistor tr4 can be set to 1.

[0050] For example, you can use Layout Versus Schematic (LVS) to add variable 10 to input data D11.

[0051] Referring to Figures 7 and 9, for the input data D11 of Figure 8, the cell library 270 may store the delay 271 of the standard cell in a specific environment 271e. The delay 271 of the standard cell in the specific environment 271e may be, for example, 20 picoseconds (ps). The specific environment 271e may include, for example, the voltage input to the standard cell, the temperature of the standard cell, and / or the like.

[0052] Referring to Figures 7 and 10, the variable 21 of the input data D11 can be changed. For example, the threshold voltage tr1_p_vta of the first transistor tr1 can be changed from 0 to 50 millivolts (mV). That is, the change in the threshold voltage tr1_p_vta of the first transistor tr1 can be 50 millivolts. The change in the delay of the standard cell can be measured when the change in the threshold voltage tr1_p_vta of the first transistor tr1 is 50 millivolts.

[0053] Referring to Figures 7 and 11, the cell library 270 can store the change (22) of the threshold voltage of the first transistor tr1 and the accompanying change (272_v_tr1) of the delay of the standard cell. For example, when the change (22) of the threshold voltage of the first transistor tr1 is 50 millivolts, the change (272_v_tr1) of the delay of the standard cell can be 4 picoseconds. That is, in this case, the delay of the standard cell can be 24 picoseconds, because 20 picoseconds + 4 picoseconds = 24 picoseconds.

[0054] Referring to Figures 7 and 12, the variable 31 of the input data D11 can be changed. For example, the mobility (tr1_u0_mult) of the first transistor tr1 can be changed from 1 to 0.9. That is, the change in the mobility (tr1_u0_mult) of the first transistor tr1 can be -0.1. The change in the delay of the standard cell can be measured when the change in the mobility (tr1_u0_mult) of the first transistor tr1 is -0.1.

[0055] Referring to Figures 7 and 13, the cell library 270 can store the change in mobility (32) of the first transistor tr1 and the accompanying change in delay (273_u0_tr1) of the standard cell. For example, when the change in mobility (32) of the first transistor tr1 is -0.1, the change in delay (273_u0_tr1) of the standard cell can be 3 picoseconds. That is, in this case, the delay of the standard cell can be 23 picoseconds, because 20 picoseconds + 3 picoseconds = 23 picoseconds.

[0056] Subsequently, the changes in the delay of the standard cell based on the change in the threshold voltage and the changes in the mobility can be repeatedly measured for the second transistor tr2, the third transistor tr3, and the fourth transistor tr4. Referring to Figures 7 and 14, the cell library 270 can store the change in the delay of the standard cell (272_v_tr2) when the change in the threshold voltage (22) of the second transistor tr2 is 50 mV, and the change in the delay of the standard cell (273_u0_tr2) when the change in the mobility (32) of the second transistor tr2 is -0.1. For example, when the change in the threshold voltage (22) of the second transistor tr2 is 50 mV, the change in the delay of the standard cell (272_v_tr2) can be 2 picoseconds. That is, in this case, the delay of the standard cell can be 22 picoseconds, because 20 picoseconds + 2 picoseconds = 22 picoseconds. For example, when the change in mobility (32) of the second transistor tr2 is -0.1, the change in delay (273_u0_tr2) of the standard cell can be 5 picoseconds. That is, in this case, the delay of the standard cell can be 25 picoseconds, because 20 picoseconds + 5 picoseconds = 25 picoseconds.

[0057] The cell library 270 can store the change in the delay of the standard cell when the change in the threshold voltage (22) of the third transistor tr3 is 50 mV, the change in the delay of the standard cell when the change in the mobility (32) of the second transistor tr2 is -0.1, the change in the delay of the standard cell when the change in the threshold voltage (22) of the fourth transistor tr4 is 50 mV, and the change in the delay of the standard cell when the change in the mobility (32) of the fourth transistor tr4 is -0.1.

[0058] Therefore, referring to FIG15, the cell library 270 may store the change in the threshold voltage of the first transistor tr1, the second transistor tr2, the third transistor tr3, and the fourth transistor tr4 placed at the boundary of the standard cell (22); the change in the mobility of the first transistor tr1, the second transistor tr2, the third transistor tr3, and the fourth transistor tr4 placed at the boundary of the standard cell (32); the change in the delay of the standard cell based on the change in the threshold voltage of each of the first transistor tr1, the second transistor tr2, the third transistor tr3, and the fourth transistor tr4 (272); and the change in the delay of the standard cell based on the change in the threshold voltage of the first transistor tr1, the second transistor tr2, the third transistor tr3, and the fourth transistor tr4. The change in delay of the standard cell based on the change in mobility (32) of each of the first transistor tr1, the second transistor tr2, the third transistor tr3 and the fourth transistor tr4 in FIG15 can correspond to the delay information 272 of the standard cell based on the threshold voltage of FIG2, and the change in delay of the standard cell based on the threshold voltage of each of the first transistor tr1, the second transistor tr2, the third transistor tr3 and the fourth transistor tr4 in FIG15 can correspond to the delay information 273 of the standard cell based on the mobility of each of the first transistor tr1, the second transistor tr2, the third transistor tr3 and the fourth transistor tr4 in FIG2.

[0059] Actions / operations S110 to S140 of FIG6 can be performed on each standard cell, and the actions / operations can be stored in delay information 272 based on the threshold voltage of the standard cell and delay information 273 based on the mobility of the standard cell in FIG2. That is, as shown in FIG15, delay information 272 based on the threshold voltage of the standard cell and delay information 273 based on the mobility of the standard cell can be stored for each standard cell.

[0060] Figure 16 is a diagram used to explain a computing system for designing integrated circuits according to some embodiments. For ease of explanation, the main differences from those described with reference to Figures 1 to 15 will be described.

[0061] Referring to FIG16, in a computing system 100 for designing integrated circuits according to some embodiments, memory 130 may further include a power analysis module 240. The power analysis module 240 may be loaded from, for example, storage device 170.

[0062] Figure 17 is a diagram used to explain a method for designing an integrated circuit according to some embodiments. Figure 17 is a detailed drawing of Figure 16.

[0063] Referring to FIG17, storage device 170 may include cell library 270. Cell library 270 may further include power information (e.g., Power orig) 281 of each standard cell in a specific environment, power information (e.g., Sensitivity_P_Vth) 282 based on the threshold voltage of each standard cell, and power information (e.g., Sensitivity_P_u0) 283 based on the mobility of each standard cell.

[0064] The power analysis module 240 can calculate the power of the standard cells included in the integrated circuit. The power analysis module 240 can generate a power report D70 including the power of the standard cells. The power analysis module 240 can receive the change in the threshold voltage and the change in the mobility of the standard cells calculated by inputting the LLE parameter D30 from the LLE calculator 231 to the LLE model D40, as well as the power information 281, power information 282 and power information 283 stored in the cell library 270, and output the power report D70. The power analysis module 240 can further determine whether the calculated power of the standard cells meets the set conditions to generate the power report D70.

[0065] The integrated circuit may include multiple standard cells. The power analysis module 230 can calculate the power of each standard cell included in the integrated circuit to generate a power report D70 including said power. The power analysis module 240 can calculate the power of the integrated circuit based on the power of each standard cell, and can generate a power report D70 that further includes said power. The power analysis module 240 can further determine whether the power of the integrated circuit meets the set conditions to generate a power report D70.

[0066] The method for designing integrated circuits according to some embodiments may further include the step of performing ECO according to power report D70. Alternatively, the method for designing integrated circuits according to some embodiments may again perform the placement and routing behavior of standard cells in step S20 according to power report D70. For example, clock tree synthesis or optimization included in the placement and routing behavior of standard cells may be performed. As another example, metal routing included in the placement and routing behavior of standard cells may be modified.

[0067] The power analysis module 240 can calculate the power of a standard cell. The power analysis module 240 can calculate the power of a standard cell by using power information 281 of the standard cell in a specific environment stored in the cell library 270, power information 282 based on the threshold voltage of the standard cell, and power information 283 based on the mobility of the standard cell, and by inputting the LLE parameter D30 into the LLE model D40 to calculate the change in the threshold voltage and the change in the mobility of the standard cell. The power information 282 based on the threshold voltage of the standard cell stored in the cell library 270 may include the change in the power of the standard cell based on the change in the threshold voltage of each transistor placed at the boundary of the standard cell. The power information 283 based on the mobility of the standard cell stored in the cell library 270 may include the change in the power of the standard cell based on the change in the mobility of each transistor placed at the boundary of the standard cell.

[0068] For a standard cell, the power analysis module 240 can use Equation 2 to calculate the power of the standard cell. Equation 2 represents the power of a standard cell. In Equation 2, n means the number of transistors placed at the boundary of the standard cell.

[0069] (Equation 2)

[0070] The power analysis module 232 can calculate the power of the standard cell by the following operation: the power of the standard cell in a specific environment (Power orig), the product of the change in the power of the standard cell based on the change in the threshold voltage of each transistor (tr_i) placed at the boundary of the standard cell and the change in the threshold voltage of each transistor (tr_i) placed at the boundary of the standard cell, and the product of the change in the power of the standard cell based on the change in the mobility of each transistor (tr_i) placed at the boundary of the standard cell and the change in the mobility of each transistor (tr_i) placed at the boundary of the standard cell.

[0071] The power analysis module 232 can receive from the cell library 270 the power orig 281 of the standard cell in a specific environment, the change in delay of the standard cell based on the change in the threshold voltage of each transistor placed at the boundary of the standard cell 282 (e.g., a first change), and the change in delay of the standard cell based on the change in the mobility of each transistor placed at the boundary of the standard cell 283 (e.g., a second change), and can receive from the LLE calculator 231 the change in the threshold voltage of each transistor placed at the boundary of the standard cell and the change in the mobility of each transistor placed at the boundary of the standard cell. The LLE calculator 231 can input the LLE parameter D30 into the LLE model D40 and calculate the change in the threshold voltage of each transistor placed at the boundary of the standard cell and the change in the mobility of each transistor placed at the boundary of the standard cell.

[0072] The integrated circuit may contain multiple standard cells. The power analysis module 240 can calculate the power on each standard cell. Specifically, the P&R module 210 can extract LLE parameters D30 from each transistor placed at the boundary of each standard cell, and the LLE calculator 231 can use the LLE model D40 to calculate the change in threshold voltage and the change in mobility of each transistor placed at the boundary of each standard cell. The power analyzer 232 can calculate the power of each standard cell by using the power information 281 of each standard cell in a specific environment stored in the cell library 270, the power information 282 based on the threshold voltage of each standard cell, and the power information 283 based on the mobility of each standard cell, as well as the change in threshold voltage and the change in mobility of each standard cell calculated by the LLE calculator 231. The power information 282 stored in cell library 270 based on the threshold voltage of each standard cell may include the change in power of each standard cell based on the change in the threshold voltage of each transistor placed at the boundary of each standard cell. The power information 283 stored in cell library 270 based on the mobility of each standard cell may include the change in power of each standard cell based on the change in the mobility of each transistor placed at the boundary of each standard cell.

[0073] Figure 18 is a diagram illustrating a method for designing an integrated circuit according to some embodiments. Figure 19 is a flowchart illustrating a method for designing an integrated circuit according to some embodiments. Figure 18 is a detailed illustration of Figure 16.

[0074] Referring to Figures 18 and 19, the analog module 220 can receive input data D11 (S210) for the standard unit. The input data D11 can be a network connection table.

[0075] The analog module 220 can add the threshold voltage and mobility of each transistor as variables to the input data D11 (S220). At this time, the analog module 220 can perform step S220 on each transistor placed at the boundary of the standard cell.

[0076] The analog module 220 can measure the change in power of the standard cell based on the change in the threshold voltage of each transistor (282) and the change in power of the standard cell based on the change in the mobility of each transistor (283) (S230). At this time, the analog module 220 can perform step S230 on each transistor placed at the boundary of the standard cell.

[0077] The analog module 220 can store the power change of the standard cell based on the change of the threshold voltage of each transistor (282) and the power change of the standard cell based on the change of the mobility of each transistor (283) in the cell library 270 (S240).

[0078] According to some embodiments, the method for designing integrated circuits can characterize the power of a standard cell by means of the threshold voltage of the transistor and the mobility of the transistor.

[0079] Figure 20 is a flowchart for explaining a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, the main differences from those described using Figure 3 will be described.

[0080] Referring to FIG20, after performing timing analysis of the integrated circuit (S40), a mask can be generated based on the layout data (S50). For example, the layout data can be modified based on the timing report generated in step S40 (D50 in FIG3), and a mask can be generated based on the modified layout data. Specifically, optical proximity correction (OPC) can be performed by changing the layout based on the layout data to reflect the error caused by the optical proximity effect. Subsequently, a mask can be generated based on the layout that changes depending on the result of the OPC execution. At this time, a layout reflecting the OPC (e.g., GDS II reflecting the OPC) can be used to generate the mask.

[0081] A semiconductor device on which integrated circuits are mounted using masks can be manufactured (S60). Specifically, a semiconductor device in which integrated circuits are mounted can be formed by performing various semiconductor processes on a semiconductor substrate such as a wafer using multiple masks. For example, a process using masks may mean a patterning process performed via lithography. The desired pattern can be formed on a semiconductor substrate or material layer by this patterning process. On the other hand, semiconductor processes may include vapor deposition processes, etching processes, ion processes, cleaning processes, and / or similar processes. Furthermore, semiconductor processes may include packaging processes that mount semiconductor components on a printed circuit board (PCB) and seal the semiconductor components with a sealing material, and / or may include testing processes that test the semiconductor components or the package.

[0082] In some embodiments, a non-transitory computer-readable storage medium (e.g., storage device 170 (FIG. 2) and / or memory 130 (FIG. 1)) may have computer-readable code implemented in the medium, which, when executed by a processor (e.g., processor 110 (FIG. 1)), causes the processor to perform any of the operations / methods described herein.

[0083] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without departing from the scope of the invention. Therefore, the exemplary embodiments disclosed herein are for general and descriptive purposes only and are not intended to be limiting. [Simplified Explanation of the Diagram]

[0012] The above and other features and characteristics disclosed herein will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: FIG1 is a diagram for explaining a computing system for designing integrated circuits according to some embodiments. FIG2 is a diagram for explaining a method for designing integrated circuits according to some embodiments. FIG3 is a flowchart for explaining a method for designing integrated circuits according to some embodiments. FIG4 is a flowchart for explaining the steps of FIG3. FIG5 is a diagram for explaining a method for designing integrated circuits according to some embodiments. FIG6 is a flowchart for explaining a method for designing integrated circuits according to some embodiments. FIG7 to FIG15 are diagrams for explaining the method for designing integrated circuits according to some embodiments of FIG6. FIG16 is a diagram for explaining a computing system for designing integrated circuits according to some embodiments. FIG17 is a diagram for explaining a method for designing integrated circuits according to some embodiments. FIG18 is a diagram for explaining a method for designing integrated circuits according to some embodiments. FIG19 is a flowchart for explaining a method for designing integrated circuits according to some embodiments. FIG20 is a flowchart for explaining a method for manufacturing a semiconductor device according to some embodiments.

Claims

1. A cell library stored in a non-transitory computer-readable storage medium, wherein the cell library is configured to store: first delay information of the standard cells based on the threshold voltage of a transistor contained in the standard cells; and second delay information of the standard cells based on the mobility of the transistor contained in the standard cells.

2. The cell library as claimed in claim 1, wherein the first delay information includes a change in the first delay of the standard cell based on a change in the threshold voltage of the transistor included in the standard cell, and wherein the second delay information includes a change in the second delay of the standard cell based on a change in the mobility of the transistor included in the standard cell.

3. The cell library as claimed in claim 1, wherein the transistor is located at the boundary of the standard cell, wherein the standard cell is part of an integrated circuit, and wherein the local layout effect (LLE) of the standard cell is defined by the first delay information and the second delay information, independent of the type of the LLE.

4. The cell library as claimed in claim 1, wherein the transistor is a first transistor included in the standard cell, wherein the standard cell further includes a second transistor, wherein the first delay information includes: delay information of the standard cell based on the threshold voltage of the first transistor; and delay information of the standard cell based on the threshold voltage of the second transistor, and wherein the second delay information includes: delay information of the standard cell based on the mobility of the first transistor; and delay information of the standard cell based on the mobility of the second transistor.

5. The cell library as claimed in claim 1, wherein the cell library is further configured to store power information of the standard cell based on the threshold voltage of the transistor contained in the standard cell.

6. The cell library as claimed in claim 1, wherein the cell library is further configured to store power information of the standard cells based on the mobility of the transistors contained in the standard cells.

7. The cell library as claimed in claim 1, wherein the cell library is further configured to store third delay information relative to a specific environment of the standard cell.

8. The cell library as claimed in claim 1, wherein the standard cell is a first standard cell and the transistor is a first transistor, and wherein the cell library is further configured to store: delay information of the second standard cell based on the threshold voltage of the second transistor contained in the second standard cell; and delay information of the second standard cell based on the mobility of the second transistor contained in the second standard cell.

9. A computing system, comprising: The memory is configured to store a program for designing an integrated circuit containing standard cells, which in turn contain transistors. And a processor, configured to execute the program to: receive input data from the standard cell; measure a change in the first delay of the standard cell based on a change in the threshold voltage of the transistor; measure a change in the second delay of the standard cell based on a change in the mobility of the transistor; and store the change in the first delay and the change in the second delay in a cell library.

10. The computing system as claimed in claim 9, wherein the transistor is located at the boundary of the standard cell.

11. The computing system of claim 9, wherein the transistor is a first transistor included in the standard cell, wherein the standard cell further includes a second transistor, wherein the processor is configured to measure a change in the delay of the standard cell based on a change in the threshold voltage of the second transistor, and a change in the delay of the standard cell based on a change in the mobility of the second transistor, and wherein the processor is configured to store the change in the delay of the standard cell based on the change in the threshold voltage of the second transistor, and the change in the delay of the standard cell based on the change in the mobility of the second transistor, in the cell library.

12. The computing system of claim 9, wherein the cell library is configured to store a third delay of the standard cell relative to a specific environment of the standard cell, and wherein the processor is configured to combine the third delay with the change in the first delay and the change in the second delay.

13. The computing system of claim 9, wherein the processor is configured to measure a first change in the power of a standard cell based on a change in the threshold voltage of the transistor, wherein the processor is configured to measure a second change in the power of the standard cell based on a change in the mobility of the transistor, and wherein the processor is configured to store the first change and the second change in power.

14. The computing system of claim 9, wherein the processor is configured to add the threshold voltage of the transistor and the mobility of the transistor as variables to the input data, and wherein the processor is configured to change the variables, and to measure the change in the first delay and the change in the second delay based on the changed variables.

15. A computing system, comprising: Memory, configured to store programs used for designing integrated circuits; The processor is configured to execute the program to: place and route a plurality of standard cells defining the integrated circuit to generate layout data for the integrated circuit; and calculate the delay of the integrated circuit using the change in delay of each of the plurality of standard cells based on the change in the threshold voltage of the transistors included in each of the plurality of standard cells, and the change in delay of each of the plurality of standard cells based on the change in the mobility of the transistors included in each of the plurality of standard cells.

16. The computing system of claim 15, wherein the memory is configured to receive a Local Layout Effect (LLE) model, wherein the processor is configured to extract LLE parameters of each of the plurality of standard cells, and wherein the processor is configured to input the LLE parameters into the LLE model to calculate the change in the threshold voltage of the transistors included in each of the plurality of standard cells, and the change in the mobility of the transistors included in each of the plurality of standard cells.

17. The computing system of claim 16, wherein the cell library is configured to store the delays of the plurality of standard cells relative to a specific environment of each of the plurality of standard cells, and wherein the processor is configured to calculate the delay of the integrated circuit based on the delays of the plurality of standard cells relative to the specific environment.

18. The computing system of claim 16, wherein the LLE parameter includes at least one of the following: the presence or absence of an active pattern around each of the plurality of standard cells; the shape of the active pattern around each of the plurality of standard cells; the size of the active pattern around each of the plurality of standard cells; or the distance between each of the plurality of standard cells and the active pattern around each of the plurality of standard cells.

19. The computing system of claim 15, wherein the processor is configured to calculate the power of the integrated circuit based on a first change in the power of the plurality of standard cells based on a change in the threshold voltage of the transistors included in each of the plurality of standard cells, and a second change in the power of the plurality of standard cells based on a change in the mobility of the transistors included in each of the plurality of standard cells.

20. The computing system of claim 19, wherein the memory is configured to receive a Local Layout Effect (LLE) model, wherein the processor is configured to extract LLE parameters of each of the plurality of standard cells, and wherein the processor is configured to input the LLE parameters into the LLE model to calculate the change in the threshold voltage of the transistors included in each of the plurality of standard cells, and the change in the mobility of the transistors included in each of the plurality of standard cells.

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