Method enabling circuit module to have reliable margin configuration

Abstract

A method enabling a circuit module to have reliable margin configuration, the circuit module may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. The method may include: causing the first auxiliary circuit to turn on, and causing the second auxiliary circuit to turn on or off according to whether a control signal is of a first level or a second level. Wherein when the first and second auxiliary circuits both turn on, the first and second auxiliary circuits may jointly cause an operation parameter of the main circuit to be a first value; when the first auxiliary circuit tuns on and the second auxiliary circuit turns off, the first auxiliary circuit may cause the operation parameter to be a second value, and an operation margin of the main circuit may cover a range between the first value and the second value.

Description

[Technical Field]

[0001] The present invention relates to a method for enabling a circuit module to have a reliable tolerance setting, and more particularly to a method for enabling a circuit module, such as a memory module, comprising a main circuit, a first auxiliary circuit and a second auxiliary circuit to have a reliable tolerance setting; the method involves enabling the second auxiliary circuit to be turned on or off according to a control signal when the first auxiliary circuit is turned on, so that an operating parameter of the main circuit is a first value or a second value, wherein an operating tolerance of the main circuit covers the range between the first value and the second value, so that the main circuit can operate without interruption when switching different operating conditions. [Previous Technology]

[0002] Various circuit modules, such as silicon intellectual property (IP) or memory modules, are important basic building blocks of integrated circuits. To balance power consumption and performance, modern circuit modules must be able to switch between different operating modes, such as a high-efficiency mode with high clock speed and high voltage, and a low-power mode with low clock speed and low voltage. In different modes, the operating parameters of the circuit module will also have different values. For example, the access timing parameters of the memory module will differ at different clock frequencies in different modes; the voltage parameters applied to the word lines and / or bit lines of the memory module will also differ at different supply voltages in different modes.

[0003] To support different modes, conventional circuit modules set up dedicated circuits for different modes, such as a first-mode dedicated circuit for the first mode and a second-mode dedicated circuit for the second mode. When the conventional circuit module operates in the first mode, the first-mode dedicated circuit is turned on, and the second-mode dedicated circuit is turned off; when operating in the second mode, the first-mode dedicated circuit is turned off, and the second-mode dedicated circuit is turned on instead. In conventional technology, the first-mode dedicated circuit sets an operating parameter to a first value, and the second-mode dedicated circuit sets the operating parameter to a different second value; thus, the operating parameter will have the first value in the first mode (because only the first-mode dedicated circuit is turned on), and will have the second value in the second mode (because only the second-mode dedicated circuit is turned on).

[0004] However, this prior art has many drawbacks. For example, a mode transition period is required to completely switch from the first mode to the second mode (or from the second mode to the first mode). During this mode transition period, the on or off of the dedicated circuits for the first and second modes is unpredictable and random; ideally, one is on and the other is off, but there may be periods where both are on, both are off, or the one that should be on is not on and the one that should be off is not off, etc. The uncertainty during the mode transition period makes it difficult to determine the operating parameters of the circuit module. For example, if both the first and second mode dedicated circuits are on, it is difficult to determine whether the operating parameters are the first value, the second value, or some other value.

[0005] Furthermore, each mode-specific circuit requires a transient period to transition from being on to being completely off or from being off to being completely on. During the mode transition, even if the two mode-specific circuits correctly switch from being on to being off and from being off to being on, the transient period between their on / off states can have unpredictable effects on the overall operation of the circuit module. For example, when a conventional circuit module switches from a first mode to a second mode, ideally the operating parameters should be the second value. However, if the first mode-specific circuit is not completely off when the second mode-specific circuit is on, the operating parameters will deviate from the second value, but not the first value.

[0006] To avoid uncertainties caused by mode switching and transients, conventional techniques interrupt the normal operation of the circuit module during mode switching, resuming operation only after the mode switch is complete. For example, a conventional circuit module, such as a memory module, can perform mode switching after an access (read or write) cycle, and completely refrain from access operations during the mode switching period, only starting the next access cycle after the dedicated circuits for different modes have been correctly turned on and off. Because the normal operation of the circuit module is interrupted during mode switching, this conventional technique reduces the operating performance of the circuit module. [Summary of the Invention]

[0007] One object of the present invention is to provide a method for enabling a circuit module (e.g., 100, FIG. 1) to have reliable tolerance settings, so that the circuit module does not need to interrupt its ongoing operation when switching between different operating conditions. The circuit module may include a main circuit (e.g., 110, FIG. 1), a first auxiliary circuit (e.g., 121, y1[p] or x1[k] in FIG. 3a, 4a or 5a) and a second auxiliary circuit (e.g., 122, y2[p] or x2[k] in FIG. 3a, 4a or 5a). The main circuit may include a first node (e.g., n1, al[p] or b1[k] in FIG. 3a, 4a or 5a). The first auxiliary circuit is coupled to the first node, and the second auxiliary circuit is coupled to the first node and a control signal (e.g., dvs_sa_relax in FIG. 3a or dvs_rawa_assert in FIG. 4a or 5a). The method includes: turning on the first auxiliary circuit (e.g., via TWL in Figure 3a, vg3[p] in Figure 4a, or WTG in Figure 5a), and when the first auxiliary circuit is turned on, turning on or off the second auxiliary circuit according to the control signal being a first level or a second level (e.g., v0, v1, Figure 2). When both the first and second auxiliary circuits are turned on, the first and second auxiliary circuits jointly set an operating parameter of the main circuit to a first value (e.g., T31, T42, or v52 in Figures 3b, 4b, or 5b). When the first auxiliary circuit is turned on and the second auxiliary circuit is turned off, the first auxiliary circuit sets the operating parameter to a second value (e.g., T32, T41, or v51 in Figures 3b, 4b, or 5b), which is different from the first value. An operating tolerance of the main circuit covers the range between the first value and the second value, such that even if the control signal switches between the first level and the second level during an operating cycle of the main circuit (e.g., Tp1, Tp2 or Tp3 in Figures 3b, 4b or 5b), the main circuit continues to operate normally during that operating cycle without affecting the correctness of operation during that operating cycle.

[0008] In one embodiment (e.g., FIG2), when the supply voltage (e.g., VDD) of the main circuit is a first supply value (e.g., vdd1) and the period of a clock (e.g., CK) of the main circuit is a first period value (e.g., T1), the control signal is the first level (e.g., v0). When the supply voltage of the main circuit is a second supply value (e.g., vdd2) and the period of the clock of the main circuit is a second period value (e.g., T2), the control signal is the second level (e.g., v1). The first supply value and the second supply value are different, and the first period value and the second period value are different.

[0009] In one embodiment (e.g., FIG. 1), the main circuit may include at least one memory cell (e.g., c[p,q] in FIG. 1), at least one tracking cell (e.g., Tc[p] in FIG. 1), and at least one sense amplifier (e.g., SA[k] in FIG. 1). The memory cell is coupled to a word line (e.g., WL[p]) and a bit line (e.g., BL[q]). The tracking cell is coupled to a tracking word line (e.g., TWL) and a tracking bit line (e.g., TBL). The sense amplifier is coupled to the bit line.

[0010] In one embodiment of the present invention (e.g., Figures 1, 3a, and 3b), the first node (e.g., n1, Figure 3a) is coupled to the following bit line. The first auxiliary circuit (e.g., 121, Figure 3a) may include a first transistor (e.g., M1) and a third transistor (e.g., M3). The first transistor includes a first controlled terminal (e.g., a gate terminal) and two first channel terminals (e.g., a drain terminal and a source terminal); the two first channel terminals are respectively coupled to the first node (e.g., n1) and a third node (e.g., n3). The third transistor includes a third controlled terminal and two third channel terminals; the two third channel terminals are respectively coupled to the third node and a fourth node (e.g., n4), and one of the first controlled terminal and the third controlled terminal is coupled to the following word line. The second auxiliary circuit (e.g., 122, Figure 3a) may include a second transistor (e.g., M2), a fourth transistor (e.g., M4), and an inverter (e.g., 124). The second transistor includes a second controlled terminal and two second channel terminals; the two second channel terminals are respectively coupled to the first node and a second node (e.g., n2). The fourth transistor includes a fourth controlled terminal and two fourth channel terminals; the two fourth channel terminals are respectively coupled to the second node and the fourth node, one of the second controlled terminal and the fourth controlled terminal (via the inverter) is coupled to the control signal (e.g., dvs_sa_relax), and the other is coupled to the following word line. In one embodiment, the operating parameter may be: the time taken for the voltage of the following bit line to change to a second voltage value (e.g., v32) after the following word line is driven (e.g., t30, FIG. 3b). In one embodiment, the operating parameter may be: the time taken for the voltage of the following bit line to change from a first voltage value (e.g., v31, FIG. 3b) to a second voltage value (e.g., v32). In one embodiment, the operating tolerance is the timing tolerance of the sense amplifier.

[0011] In one embodiment of the present invention (e.g., Figures 1, 4a, and 4b), the first node (e.g., a1[p], Figure 4a) is coupled to the character line (e.g., WL[p], Figure 4a). The first auxiliary circuit (e.g., y1[p]) includes a first transistor (e.g., H1[p]) and a third transistor (e.g., H3[p]). The second auxiliary circuit (e.g., y2[p]) includes a second transistor (e.g., H2[p]) and an inverter (e.g., INV[p]). The first transistor includes two first channel terminals, respectively coupled to the first node and a second node (e.g., a2[p]). The third transistor includes two third channel terminals, respectively coupled to the second node and a third node (e.g., a3[p]). The second transistor (e.g., H2[p]) includes a second controlled terminal and two second channel terminals; the second controlled terminal is coupled to the control signal (e.g., dvs_rawa_assert) via the inverter, and the two second channel terminals are respectively coupled to the first node and the second node. In one embodiment, the operating parameter may be: the time taken for the voltage of the bit line to change from a third voltage value (e.g., v41, FIG. 4b) to a fourth voltage value (e.g., v42). In another embodiment, the operating parameter may be: the time taken for the voltage of the bit line to change to a fourth voltage value (e.g., v42) after the word line is driven (e.g., t40). In one embodiment, when the word line is driven, if the control signal is the first level (e.g., v0, FIG. 2), the voltage of the word line is a fifth voltage value (e.g., vw42, FIG. 4b); if the control signal is the second level (e.g., v1, FIG. 2), the voltage of the word line is a sixth voltage value (e.g., vw41, FIG. 4b), and the fifth voltage value is different from the sixth voltage value. In one embodiment, the operating tolerance is the timing tolerance of the sense amplifier.

[0012] In one embodiment of the present invention (e.g., Figures 1, 5a, and 5b), the main circuit further includes a write circuit (e.g., WB[k], Figures 1 and 5a) coupled between the bit line and a negative voltage bit line (e.g., NBL[k], Figure 5a); the first node (e.g., b1[k], Figure 5a) is coupled to the negative voltage bit line. The first auxiliary circuit (e.g., x1[k], Figure 5a) includes a first logic gate (e.g., g1[k]) and a first capacitor (e.g., C1[k]). The first logic gate includes a first input terminal (e.g., i1[k]) and a first output terminal (e.g., o1[k]), and the first capacitor is coupled between the first output terminal and the first node. The second auxiliary circuit (e.g., x2[k]) includes a second logic gate (e.g., g2[k]) and a second capacitor (e.g., C2[k]). The second logic gate includes two second input terminals (e.g., i21[k] and i22[k]) and a second output terminal (e.g., o2[k]), with the two second input terminals respectively coupled to the first input terminal and the control signal (e.g., dvs_rawa_assert). The second capacitor is coupled between the second output terminal and the first node. In one embodiment, the first logic gate is an inverter, and the second logic gate is an inverting gate. In one embodiment, the operating parameter can be the voltage extreme value of the negative voltage bit line after the word line is driven (e.g., t50, FIG. 5b). In one embodiment, the operating tolerance is the negative voltage tolerance of the bit line.

[0013] In one embodiment of the present invention, the circuit module includes not only the first auxiliary circuit (e.g., 121, FIG. 3a) and the second auxiliary circuit (e.g., 122, FIG. 3a) coupled to the control signal (e.g., dvs_sa_relax), but also a third auxiliary circuit and a fourth auxiliary circuit (e.g., y1[p] and y2[p] in FIG. 4a, or x1[k] and x2[k] in FIG. 5a). The third auxiliary circuit is coupled to a fourth node (e.g., a1[p] in FIG. 4a or b1[k] in FIG. 5a), and the fourth auxiliary circuit is coupled to the fourth node and a second control signal (e.g., dvs_rawa_assert). The method further includes: when the third auxiliary circuit is turned on, causing the fourth auxiliary circuit to turn on or off according to the second control signal being a third level or a fourth level (e.g., v0, v1, FIG. 2). When both the third and fourth auxiliary circuits are turned on, they jointly set a second operating parameter of the main circuit to a third value (e.g., T42 in Figure 4b or v52 in Figure 5b). When the third auxiliary circuit is turned on and the fourth auxiliary circuit is turned off, the third auxiliary circuit sets the operating parameter to a fourth value (e.g., T41 in Figure 4b or v51 in Figure 5b), which is different from the third value. A second operating tolerance of the main circuit covers the range between the third and fourth values. The control signal (e.g., dvs_sa_relax, Figure 2) and the second control signal (e.g., dvs_rawa_assert, Figure 2) do not switch levels simultaneously. In one embodiment, when the control signal switches levels (e.g., t1-t2, Figure 2), the second control signal switches levels after a first delay time (e.g., Dt1) (e.g., t3-t4). When the second control signal switches levels again (e.g., t5-t6), the control signal will switch levels again after a second delay time (e.g., Dt2) (e.g., t7-t8).

[0014] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

Implementation Method

[0016] Figure 1 illustrates a circuit module 100 according to an embodiment of the present invention, which may include a main circuit 110; in order to implement the present invention, the circuit module 100 further includes an auxiliary unit 120, y[1] to y[P] and x[1] to x[K]. As shown in Figure 1, in one embodiment of the present invention, the circuit module 100 may be a memory module, such as an embedded static random access memory module; the main circuit 110 may be a memory array, including P*Q memory cells c[1,1] to c[P,Q], P word lines WL[1] to WL[P], Q sets of bit lines such as BL[1] to BL[Q] and BLb[1] to BLb[Q], P following memory cells Tc[1] to Tc[P], a following word line TWL, a set of following bit lines such as TBL and TBLb, K write circuits WB[1] to WB[K], K sense amplifiers SA[1] to SA[K], two peripheral circuits 130 and 140, and a control circuit 150. The quantities P, Q, and K may be integers greater than or equal to 1. With the support of auxiliary units 120, y[1] to y[P] and x[1] to x[K], control circuit 150 can control the operation of main circuit 110. Due to the auxiliary units 120, y[1] to y[P] and x[1] to x[K] of the present invention, main circuit 110 can operate without interruption when switching between different operating conditions (or different modes, such as different supply voltage values ​​and / or different clock frequencies); even if the switching of operating conditions occurs within a certain operating cycle of main circuit 110 (such as a read cycle or a write cycle), main circuit 110 can still continue normal operation (such as reading or writing) in that operating cycle without affecting the correctness of operation in that operating cycle. The technology of the present invention will be further described in detail later.

[0017] In the main circuit 110, each memory cell c[p,q] (for p=1 to P and q=1 to Q) can be a static random access memory cell, coupled to the corresponding word line WL[p] and one or more bit lines, such as BL[q] and BLb[q]. Each memory cell c[p,q] can store one bit of data. Each follower memory cell Tc[p] is coupled to the follower word line TWL and one or more follower bit lines, such as TBL and TBLb. Each follower memory cell Tc[p] has the same circuit structure as each memory cell c[p,q] to reflect the response of each memory cell c[p,q]. Peripheral circuitry 130 is coupled to word lines WL[1] to WL[P], and peripheral circuitry 140 is coupled to bit lines BL[1] to BL[Q] and BLb[1] to BLb[Q], sense amplifiers SA[1] to SA[K], and write circuits WB[1] to WB[K]. Control circuitry 150 provides a signal sn1 to sense amplifiers SA[1] to SA[K] and a signal WTG to write circuits WB[1] to WB[K]. Main circuitry 110 is powered by a supply voltage VDD; for example, each memory cell c[p,q] can draw power from the supply voltage VDD to latch bit data. Control circuitry 150 can control the operating cycle (such as access cycle, including read cycle and write cycle) of main circuitry 110 according to a clock CK.

[0018] As shown in Figure 1, auxiliary unit 120 is coupled to a control signal dvs_sa_relax, following character line TWL, following bit line TBL, and control circuit 150. Each auxiliary unit y[p] is coupled to the corresponding character line WL[p] and a control signal dvs_rawa_assert. Each auxiliary unit x[k] is coupled to signal WTG, signal dvs_rawa_assert, and corresponding write circuit WB[k].

[0019] When data in memory cell c[p,q] needs to be read, peripheral circuit 130 can drive word line WL[p], and peripheral circuit 140 can turn on bit lines BL[q] and BLb[q] to one of the sensing amplifiers SA[1] to SA[K], SA[k], so that sensing amplifier SA[k] can read the data stored in memory cell c[p,q] under the timing control of signal sn1. Among them, auxiliary unit 120 can provide a signal vn1 according to signal dvs_sa_relax, and the timing of signal sn1 is related to signal vn1 (discussed later). When peripheral circuit 130 drives word line WL[p], auxiliary circuit y[p] can adjust the magnitude of the driving voltage according to signal dvs_rawa_assert (discussed later).

[0020] When data is to be written to memory cell c[p,q], peripheral circuit 130 can drive word line WL[p], and peripheral circuit 140 can conduct bit lines BL[q] and BLb[q] to one of the write circuits WB[1] to WB[K], WB[k], so that the write circuit WB[k] can write data to memory cell c[p,q] under the trigger of signal WTG. When signal WTG is triggered, the corresponding auxiliary cell x[p] can generate a negative voltage on bit lines BL[q] and BLb[q] through the write circuit WB[k], and adjust the magnitude of the negative voltage according to signal dvs_rawa_assert (discussed later) to assist the write circuit WB[k] in writing data to memory cell c[p,q].

[0021] The signals dvs_sa_relax and dvs_rawa_assert in Figure 1 are related to the operating conditions of the circuit module 100, including the supply voltage VDD and the clock CK. Continuing from Figure 1, Figure 2 illustrates the switching of the supply voltage VDD and the clock CK in the circuit module 100, as well as the timing of the signals dvs_sa_relax and dvs_rawa_assert. As shown in Figure 2, between time points t20 and t21, the value of the supply voltage VDD can be the supply value vdd1, the value of the period T of the clock CK can be the period value T1, and the signal levels of the signals dvs_sa_relax and dvs_rawa_assert can be level v0.

[0022] Between time points t21 and t22, the supply voltage VDD can be maintained at the supply value vdd1, while the period T can be switched to another period value T2; wherein, the period values ​​T1 and T2 can be different. For example, the period value T1 can be less than the period value T2; that is, the clock CK can switch from the original higher frequency (1 / T1) to a lower frequency (1 / T2) after time point t21. Furthermore, between time points t21 and t22, the signal dvs_sa_relax can switch from level v0 to another different level v1 between time points t1 and t2; after a delay time Dt1, the signal dvs_rawa_assert can switch from level v0 to level v1 between time points t3 and t4.

[0023] Between time points t22 and t23, the period T of the clock CK can be maintained at the period value T2, the signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v1, and the value of the supply voltage VDD can be switched from the supply value vdd1 to another different supply value vdd2; for example, the supply value vdd2 can be lower than the supply value vdd1.

[0024] Between time points t23 and t24, the supply voltage VDD can be maintained at the supply value vdd2, the clock cycle T of CK can be maintained at the cycle value T2, and the signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v1. Before time point t21, the original operating conditions of circuit module 100 are the supply value vdd1 and the cycle value T1 (such as a high-efficiency mode); after the handover preparation between time points t21 and t23, the operating conditions of circuit module 100 can be switched to the supply value vdd2 and the cycle T2 after time point t23 (such as a low-power mode).

[0025] Between time points t24 and t25, the period T of the clock CK can be maintained at the period value T2, the signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v1, and the value of the supply voltage VDD can be switched back from the power supply value vdd2 to vdd1.

[0026] Between time points t25 and t26, the supply voltage VDD can be maintained at the supply value vdd1, and the period T can be maintained at the period value T2. Furthermore, between time points t25 and t26, the signal dvs_rawa_assert can switch from level v1 to level v0 between time points t5 and t6; after a delay time Dt2, the signal dvs_sa_relax can switch from level v1 to level v0 between time points t7 and t8.

[0027] After time point t26, the supply voltage VDD can be maintained at the power supply value vdd1, the signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v0, and the period T switches back to the period value T1. Between time points t23 and t24, the operating conditions of circuit module 100 were originally the power supply value vdd2 and the period value T2; after the handover preparation between time points t24 and t26, the operating conditions of circuit module 100 can switch back to the power supply value vdd1 and the period value T1 after time point t26. As shown in Figure 2, the level switching of signals dvs_sa_relax and dvs_rawa_assert corresponds to the switching of the operating conditions of circuit module 100.

[0028] Continuing with Figures 1 and 2, Figure 3a illustrates an auxiliary unit 120 according to an embodiment of the present invention, and Figure 3b illustrates a waveform timing embodiment of the relevant signals when the auxiliary unit 120 is operating. As shown in Figure 3a, the auxiliary unit 120 may include two auxiliary circuits 121 and 122, coupled to a following bit line TBL at a node n1; the voltage of the following bit line TBL at node n1 is the signal vn1, which can be received by the control circuit 150. The auxiliary circuit 121 may include two transistors M1 and M3, and the auxiliary circuit 122 may include two transistors M2 and M4 and an inverter 124. For example, each transistor M1 to M4 may be an n-type metal-oxide-semiconductor.

[0029] In the auxiliary circuit 121, transistor M1 may include a controlled terminal (such as a gate terminal) and two channel terminals (such as a drain terminal and a source terminal), which are respectively coupled to a signal vg31, node n1 and another node n3. Transistor M3 may include a controlled terminal and two channel terminals, which are respectively coupled to the following word line TWL, node n3 and another node n4 (which may be a ground node).

[0030] In the auxiliary circuit 122, transistor M2 may include a controlled terminal and two channel terminals; the two channel terminals are respectively coupled to node n1 and a node n2, and the controlled terminal is coupled to the signal dvs_sa_relax via inverter 124. Transistor M4 may include a controlled terminal and two channel terminals, respectively coupled to the following word line TWL, node n2 and n4.

[0031] As shown in Figure 3b, in one operating cycle Tp1 of the main circuit 110 (for example, a read cycle, the length of which can be one cycle T of the clock CK, Figure 2), the voltage of the following word line TWL can be driven from one voltage value vw31 to another voltage value vw32 at time point t30, as shown by the waveform vTWL; as the following word line TWL is driven, the voltage of the following bit line TBL (i.e., signal vn1) will change from one voltage value v31 (e.g., decrease). The time taken for the voltage of the following bit line TBL to change from voltage value v31 to another different voltage value v32 can be regarded as an operating parameter of the main circuit 110, hereinafter referred to as the following word line discharge time. The duration of the follow-word line discharge is reflected in the timing of the signal sn1 by the control circuit 150, and the operating timing of the sense amplifiers SA[1] to SA[K] is controlled accordingly, for example, to control when to enable the sense amplifiers SA[1] to SA[K].

[0032] Under different operating conditions, the values ​​of the operating parameters of the main circuit 110 can also be different. As previously described, conventional circuit modules set up different mode-specific circuits for different modes (different operating conditions); ideally, when one of these mode-specific circuits is turned on, the others will be turned off, and the value of the operating parameter depends on the mode-specific circuit that is turned on. However, in reality, when switching modes, the turning on or off of different mode-specific circuits is unpredictable and random, and there will be transients between turning on and off; consequently, the magnitude of the change in operating parameters between different modes is also unpredictable.

[0033] In contrast, in this invention, the duration of the follow-bit line discharge time (the time it takes for the follow-bit line TBL to change from voltage value v31 to voltage value v32) is related to the two auxiliary circuits 121 and 122 in the auxiliary unit 120. However, the opening and closing of the auxiliary circuits 121 and 122 are not mutually exclusive. When the auxiliary circuit 121 is on, the auxiliary circuit 122 can be turned on or off according to different levels of the signal dvs_sa_relax (Figures 1 and 2) (corresponding to different operating conditions / different modes). Thus, the change in the follow-bit line discharge time is no longer difficult to predict. The operation of the two auxiliary circuits 121 and 122 will be further explained below.

[0034] Before time point t30, since the following character line TWL is not driven, transistors M3 and M4 are not turned on, auxiliary circuits 121 and 122 are turned off, and the voltage of the following character line TBL is the voltage value v31.

[0035] After time point t30, as the following character line TWL is driven, transistors M3 and M4 will turn on, and the voltage of signal vg31 will also turn on transistor M1. Since both transistors M1 and M3 are turned on, auxiliary circuit 121 is turned on and can provide a conductive path between nodes n1 and n4.

[0036] After time t30, when auxiliary circuit 121 is turned on, if signal dvs_sa_relax remains at level v0, transistor M2 will continue to conduct. Since both transistors M2 and M4 are turned on, auxiliary circuit 122 is turned on, providing an additional conductive path between nodes n1 and n4. Therefore, after time t30, the following bit line TBL coupled to node n1 can discharge via the parallel conductive path provided by the two auxiliary circuits 121 and 122, and change to voltage value v32 at time t31, as shown by waveform vTBL_0 in Figure 3b. Therefore, the discharge time of the following bit line is time T31 (from time t30 to t31).

[0037] After time t30, when auxiliary circuit 121 is turned on, if signal dvs_sa_relax remains at level v1, transistor M2 remains non-conductive, auxiliary circuit 122 is turned off, and no additional conductive path is provided between nodes n1 and n4. Therefore, after time t30, the following character line TBL discharges to node n4 via a single conductive path provided solely by auxiliary circuit 121, and drops to voltage value v32 at time t32, as shown by waveform vTBL_1 in Figure 3b. Therefore, the discharge time of the following character line is time T32 (from time t30 to t32). As shown in Figure 3b, time T32 is longer than time T31.

[0038] After time t30, when auxiliary circuit 121 is turned on, if the signal dvs_sa_relax changes from level v0 to level v1 at time t3_01 in the same operating cycle Tp1, auxiliary circuit 122 will be turned on from time t30 to t3_01, and then switched off at time t3_01. Therefore, the following character line TBL will first discharge at a faster speed (because both auxiliary circuits 121 and 122 are turned on), and then discharge at a slower speed after time t3_01 (because auxiliary circuit 122 is turned off), and will drop to voltage value v32 at time t3b, as shown by waveform vTBL_01 in Figure 3b. Therefore, the discharge time of the following character line is time T3b (from time t30 to t3b).

[0039] After time t30, when auxiliary circuit 121 is turned on and signal dvs_sa_relax changes from level v0 to level v1 at time t3_01, auxiliary circuit 122 may need a transient period to switch from on to off. Therefore, the following character line TBL will initially discharge at a relatively fast speed, then gradually decrease at time t3_01, and drop to voltage value v32 at time t3a, as shown by waveform vTBL_01t in Figure 3b. Therefore, the discharge time of the following character line will be time T3a (from time t30 to t3a).

[0040] After time t30, when auxiliary circuit 121 is turned on, if the signal dvs_sa_relax changes from level v1 to level v0 at time t3_10 in the same operating cycle Tp1, auxiliary circuit 122 will be turned off from time t30 to t3_10, and then switched on again at time t_10. Therefore, the following character line TBL will first discharge at a slower speed, then at a faster speed after time t3_10, and will drop to voltage value v32 at time t3c, as shown by waveform vTBL_10 in Figure 3b. Therefore, the discharge time of the following character line is time T3c (from time t30 to t3c).

[0041] After time t30, when auxiliary circuit 121 is turned on and signal dvs_sa_relax changes from level v1 to level v0 at time t3_10, auxiliary circuit 122 may need a transient period to switch from off to on. Therefore, the following character line TBL will initially discharge at a slower rate, then gradually increase in rate after time t3_10, and drop to voltage value v32 at time t3d, as shown by waveform vTBL_10t in Figure 3b. Therefore, the discharge time of the following character line is time T3d (from time t30 to t3d).

[0042] As shown in Figure 3b, within the same operating cycle Tp1, regardless of whether the signal dvs_sa_relax is maintaining level v0, maintaining level v1, switching from level v0 to level v1, or switching from level v1 to v0 (i.e., maintaining the same operating conditions / mode or switching to different operating conditions / modes within the same operating cycle Tp1), the auxiliary circuit 121 will always be turned on (after the following character line TWL is driven). The auxiliary circuit 122 will be turned on or off depending on whether the signal dvs_sa_relax is at level v0 or v1, ensuring that the voltage change of the following character line TBL is always enveloped between the waveforms vTBL_0 and vTBL_1, and the discharge time of the following character line will always fall between times T31 and T32. Therefore, when the operating conditions / modes are switched, the present invention can avoid the uncertainty and transients of the opening and closing of the dedicated circuits for different modes in the prior art, which prevent the reliable prediction of the change in operating parameters. In this invention, as long as the operating tolerance of the main circuit 110 can cover the range of time T31 to T32 (for example, the reading timing of the sensing amplifiers SA[1] to SA[K] can tolerate the timing variation of time T31 to T32), regardless of whether the signal dvs_sa_relax is switched in the same operating cycle Tp1 (whether the operating condition / mode is switched in the same operating cycle Tp1), the main circuit 110 can still continue to operate normally in the operating cycle Tp1 (such as data reading) and will not affect the correctness of operation in the operating cycle Tp1 (such as the correctness of data reading).

[0043] Continuing with Figures 1 and 2, Figure 4a illustrates an auxiliary unit y[p] (one of auxiliary units y[1] to y[P]) according to an embodiment of the present invention, and Figure 4b illustrates the waveform timing of related signals when the auxiliary unit y[p] is operating. As shown in Figure 4a, the auxiliary unit y[p] may include two auxiliary circuits y1[p] and y2[p], coupled to a node a1[p] with the corresponding character line WL[p]. The character line WL[p] is also coupled to a character line driver WD[p] (e.g., an inverter) in the peripheral circuit 130. The auxiliary circuit y1[p] may include two transistors H1[p] and H3[p], and the auxiliary circuit y2[p] may include a transistor H2[p] and an inverter INV[p]. For example, the transistors H1[p] and H2[p] may be p-type metal-oxide-semiconductor transistors, and the transistor H3[p] may be an n-type metal-oxide-semiconductor transistor.

[0044] In the auxiliary circuit y1[p], transistor H1[p] may include a controlled terminal and two channel terminals, respectively coupled to a signal vg1[p], node a1[p] and another node a2[p]; in one embodiment, the voltage of signal vg1[p] can turn on transistor H1[p]. Transistor H3[p] may include a controlled terminal and two channel terminals, respectively coupled to a signal vg3[p], node a2[p] and another node a3[p] (which may be a ground node).

[0045] In the auxiliary circuit y2[p], the transistor H2[p] may include a controlled terminal and two channel terminals; the two channel terminals are respectively coupled to nodes a1[p] and a2[p], and the controlled terminal is coupled to the signal dvs_rawa_assert via the inverter INV[p]. When the signal dvs_rawa_assert is at level v0, the transistor H2[p] is not turned on, and the auxiliary circuit y2[p] is turned off. When the signal dvs_rawa_assert is at level v1, the transistor H2[p] is turned on, and the auxiliary circuit y2[p] is turned on.

[0046] As shown in Figure 4b, in one operating cycle Tp2 of the main circuit 110 (for example, a read cycle, the length of which can be one cycle T of the clock CK, Figure 2), when the memory cell c[p,q] on the word line WL[p] is to be read, the word line WL[p] can be driven at time point t40; consequently, the voltage of the bit line BL[q] or BLb[q] will also change from a voltage value v41 (e.g., decrease). For ease of explanation, it is assumed below that the voltage of the bit line BL[q] will change. The time taken for the voltage of the bit line BL[q] to change from voltage value v41 to another voltage value v42 can be regarded as an operating parameter of the main circuit 110, hereinafter referred to as the bit line discharge time.

[0047] When the character line WL[p] is driven at time t40, if the signal dvs_rawa_assert remains at level v0, the character line WL[p] can be driven from voltage value vw40 to another voltage value vw42, as shown in waveform vWL[p]_0; correspondingly, the voltage of the bit line BL[q] will change from voltage value v41 after time t40 (e.g., decrease), and change to voltage value v42 at time t41, as shown in waveform vBL[q]_0. Therefore, the bit line discharge time is time T41 (from time t40 to t41).

[0048] When the character line WL[p] is driven at time t40, if the signal dvs_rawa_assert remains at level v1, the character line WL[p] can be driven from voltage value vw40 to another voltage value vw41, as shown in waveform vWL[p]_1; correspondingly, the voltage of the bit line BL[q] will change to voltage value v42 at time t42, as shown in waveform vBL[q]_1. Therefore, the bit line discharge time is time T42 (from time t40 to t42).

[0049] Voltage values ​​vw41 and vw42 can be different so that the voltage of the character line WL[p] can adapt to different operating conditions during read operation; for example, voltage value vw42 can be greater than voltage value vw41. When the character line WL[p] is driven at time t40, regardless of whether the signal dvs_rawa_assert is at level v0 or v1, signals vg1[p] and vg3[p] (Figure 4a) will turn on transistors H1[p] and H3[p], thereby turning on the auxiliary circuit y1[p].

[0050] When the character line WL[p] is driven at time t40, if the signal dvs_rawa_assert is at level v0, the transistor H2[p] is not turned on, and the auxiliary circuit y2[p] is also turned off. The voltage of the character line WL[p] is made higher by the turned-on auxiliary circuit y1[p]. Conversely, if the signal dvs_rawa_assert is at level v1, the transistor H2[p] will be turned on, and the auxiliary circuit y2[p] will also be turned on. The voltage of the character line WL[p] is made lower by the combined action of the auxiliary circuits y1[p] and y2[p]. When the character line WL[p] is driven to a higher voltage value vw42 (as shown in waveform vWL[p]_0), the voltage change rate of the bit line BL[q] is faster (as shown in waveform vBL[q]_0); when the character line WL[p] is driven to a lower voltage value vw41 (as shown in waveform vWL[p]_1), the voltage change rate of the bit line BL[q] is slower (as shown in waveform vBL[q]_1).

[0051] In one embodiment, the voltage value vw42 may be slightly lower than the supply voltage vdd1 (FIG. 2) to enable read assistance using word line underdrive when the supply voltage VDD is the supply voltage vdd1. In another embodiment, the voltage value vw41 may be substantially equal to the supply voltage vdd2 (FIG. 2) to disable read assistance using word line underdrive when the supply voltage VDD is the supply voltage vdd2.

[0052] As shown in Figure 4b, when the character line WL[p] is driven at time t40, if the signal dvs_rawa_assert switches from level v0 to level v1 at time t4_01, the character line WL[p] will first be driven to voltage value vw42 (auxiliary circuits y1[p] and y2[p] are turned on and off respectively), and then driven to voltage value vw41 at time t4_01 (auxiliary circuits y1[p] and y2[p] are both turned on), as shown in waveform vWL[p]_01; correspondingly, after time t40, the voltage of the bit line BL[q] will first change at a faster speed, then at a slower speed after time t4_01, and reach voltage value v42 at time t4a, as shown in waveform vBL[q]_01. Therefore, the bit line discharge time is time T4a (time t40 to t4a).

[0053] When the character line WL[p] is driven at time t40, if the signal dvs_rawa_assert switches from level v1 to level v0 at time t4_10, the character line WL[p] will first be driven to voltage value vw41 (both auxiliary circuits y1[p] and y2[p] are turned on), and then driven to voltage value vw42 at time t4_10 (auxiliary circuits y1[p] and y2[p] are turned on and off respectively), as shown in waveform vWL[p]_10; correspondingly, after time t40, the voltage of the character line BL[q] will first change at a slower speed, then change at a faster speed after time t4_10, and reach voltage value v42 at time t4b, as shown in waveform vBL[q]_10. Therefore, the discharge time of the character line is time T4b (time t40 to t4b).

[0054] As can be seen from Figure 4b, even if the signal dvs_rawa_assert switches levels within the same operating cycle Tp2 (corresponding to the switching of operating conditions / modes), the bit line discharge time (such as time T4a or T4b) will still fall between time T41 and T42. Furthermore, although not shown in Figure 4b, when the signal dvs_rawa_assert switches levels within the same operating cycle Tp2, causing the auxiliary circuit y2[p] to switch on and off, even if the auxiliary circuit y2[p] has a transient state during the switching, the bit line discharge time will still fall between time T41 and T42. Therefore, in this invention, as long as the operating tolerance of the main circuit 110 can cover the range of time T41 to T42 (for example, the reading timing of the sensing amplifiers SA[1] to SA[K] can tolerate the timing variation of time T41 to T42), regardless of whether the signal dvs_rawa_assert is switched in the same operating cycle Tp2 (whether the operating condition / mode is switched in the same operating cycle Tp2), the main circuit 110 can still continue to operate normally in the operating cycle Tp2 (such as data reading) and will not affect the correctness of operation in the operating cycle Tp2 (such as the correctness of data reading).

[0055] Continuing with Figures 1 and 2, Figure 5a illustrates an auxiliary unit x[k] (one of auxiliary units x[1] to x[K]) according to an embodiment of the present invention, and Figure 5b illustrates the waveform timing of related signals when the auxiliary unit x[k] is operating. As shown in Figure 5a, the auxiliary unit x[k] may include two auxiliary circuits x1[k] and x2[k], coupled to a node b1[k] via a negative bit line NBL[k]. The node b1[k] may be coupled to the write circuit WB[k] via the negative bit line NBL[k]. The auxiliary circuit x1[k] may include a logic gate g1[k] and a capacitor C1[k], and the auxiliary circuit x2[k] may include a logic gate g2[k] and a capacitor C2[k]. Logic gate g1[k] can be an inverter with an input terminal i1[k] and an output terminal o1[k]; capacitor C1[k] is coupled between the output terminal o1[k] and node b1[k]. Logic gate g2[k] can be an inverter with two input terminals i21[k] and i22[k] and an output terminal o2[k]; the two input terminals i21[k] and i22[k] are respectively coupled to input terminal i1[k] and signal dvs_rawa_assert, and capacitor C2[k] is coupled between output terminal o2[k] and node b1[k]. As shown in Figure 5a, signal WTG is coupled to auxiliary circuits x1[k] and x2[k] via input terminals i1[k] and i21[k] respectively, and signal dvs_rawa_assert is coupled to auxiliary circuit x2[k] via input terminal i22[k].

[0056] As shown in Figure 5b, in one operating cycle Tp3 of the main circuit 110 (for example, a write cycle, the length of which can be one cycle T of the clock CK, Figure 2), when data is to be written to the memory cell c[p,q] on the word line WL[p], the peripheral circuit 140 will turn on the corresponding bit lines BL[q] and BLb[q] to the write circuit WB[k]. The bit line word line WL[p] will be driven from one voltage value vw51 to another voltage value vw52 at time t50, as shown by the waveform vWL[p]. The signal WTG (Figure 5a) will trigger the write circuit WB[k] to write data. Consequently, the voltage of the negative voltage bit line NBL[k] will also change from one voltage value v50 (for example, a ground voltage value) to a voltage extreme value, and then reverse (for example, rise) back to the voltage value v50, presenting a pulse waveform. The voltage extreme value of the negative bit line NBL[k] can be regarded as an operating parameter of the main circuit 110, and is referred to as the bit line negative voltage value below. The voltage waveform of the negative bit line NBL[k] is applied to the bit lines BL[q] and BLb[q] through the write circuit WB[k] and the peripheral circuit 140 to realize write assistance.

[0057] As shown in Figure 5b, after time point t50, if the signal dvs_rawa_assert remains at level v1, both auxiliary circuits x1[k] and x2[k] will be turned on; when the signal WTG is triggered, the two will work together to make the voltage change of the negative voltage bit line NBL[k] into waveform vNBL[k]_1, which reaches an extreme value (voltage value v52) at time point t52. Therefore, the negative voltage value of the bit line is the voltage value v52.

[0058] After time point t50, if the signal dvs_rawa_assert remains at level v0, the auxiliary circuit x2[k] will be turned off, and only the auxiliary circuit x1[k] will be turned on. Therefore, when the signal WTG is triggered, the auxiliary circuit x1[k] will independently make the voltage change of the negative voltage bit line NBL[k] into the waveform vNBL[k]_0, which reaches its extreme value (voltage value v51) at time point t51. Therefore, the negative voltage value of the bit line is the voltage value v51.

[0059] After time point t50, if the signal dvs_rawa_assert switches from level v0 to level v1 at time point t5_01 in the same operating cycle Tp3, the auxiliary circuit x2[k] will switch from off to on during the operation of the auxiliary circuit x1[k]. The voltage change of the negative voltage bit line NBL[k] will be in the form of waveform vNBL[k]_01. Therefore, the negative voltage value of the bit line is the voltage value v5a.

[0060] After time point t50, if the signal dvs_rawa_assert switches from level v1 to level v0 at time point t5_10 in the same operating cycle Tp3, the auxiliary circuit x2[k] will switch from on to off during the period when the auxiliary circuit x1[k] is on, and the voltage change of the negative voltage bit line NBL[k] will be the waveform vNBL[k]_10. Therefore, the negative voltage value of the bit line is the voltage value v5b.

[0061] As can be seen from Figure 5b, even if the signal dvs_rawa_assert switches levels within the same operating cycle Tp3 (corresponding to the switching of operating conditions / modes), the bit line negative voltage value (such as voltage value v5a or v5b) will still fall between voltage values ​​v51 and v52. Furthermore, although not shown in Figure 5b, when the signal dvs_rawa_assert switches levels within the same operating cycle Tp3, causing the auxiliary circuit x2[p] to switch on and off, even if the auxiliary circuit x2[p] has a transient state during the switching, the bit line negative voltage value will still fall between voltage values ​​v51 and v52. Therefore, in this invention, as long as the operating tolerance of the main circuit 110 can cover the range of voltage values ​​v51 to v52 (for example, the bit lines BL[q] and BLb[q] can tolerate the negative voltage variation of voltage values ​​v51 to v52), regardless of whether the signal dvs_rawa_assert switches in the same operating cycle Tp3 (whether the operating conditions / modes switch in the same operating cycle Tp3), the main circuit 110 can still continue to operate normally in the operating cycle Tp3 (such as data writing) without affecting the correctness of operation in the operating cycle Tp3 (such as the correctness of data writing).

[0062] Figure 6a illustrates a process 600 according to an embodiment of the present invention; process 600 can be applied to the circuits of circuit module 100 (Figure 1) in Figures 3a, 4a and 5a respectively, and may include steps 610, 620, 630, 640 and 650. Step 610: Process start. With respect to the circuit of Figure 3a, process 600 may start when "following character line TWL is driven", for example, at time point t30 in Figure 3b. With respect to the circuit of Figure 4a, process 600 may start when "signal vg3[p] turns on transistor H3[p]. With respect to the circuit of Figure 5a, process 600 may start when signal WTG is triggered (e.g., when it becomes logic 1).

[0063] Step 620: Turn on the first auxiliary circuit. In the case of the circuit in Figure 3a, the first auxiliary circuit can be auxiliary circuit 121. In the case of the circuit in Figure 4a, the first auxiliary circuit can be auxiliary circuit y1[p]. In the case of the circuit in Figure 5a, the first auxiliary circuit can be auxiliary circuit x1[k].

[0064] Step 630: When the first auxiliary circuit is turned on, the second auxiliary circuit is turned on or off according to the control signal being at the first or second level. For the circuit in Figure 3a, the control signal can be the signal dvs_sa_relax, and the second auxiliary circuit can be auxiliary circuit 122, which can be turned on and off when the control signals are at levels v0 and v1 respectively. For the circuit in Figure 4a, the control signal can be the signal dvs_rawa_assert, and the second auxiliary circuit can be y2[p], which can be turned on and off when the control signals are at levels v1 and v0 respectively. For the circuit in Figure 5a, the control signal can be the signal dvs_rawa_assert, and the second auxiliary circuit can be x2[k], which can be turned on and off when the control signals are at levels v1 and v0 respectively.

[0065] Step 640: To end process 600, proceed to step 650; otherwise, return to step 630. In other words, step 630 can be repeated continuously during process 600; and the first auxiliary circuit can also remain on. In the circuit of Figure 3a, if the control signal continuously turns on the second auxiliary circuit during process 600, both the first and second auxiliary circuits are on, and together they can make the operating parameter "following bit line discharge time" of the main circuit 110 time T31; if the control signal continuously turns off the second auxiliary circuit during process 600, the on first auxiliary circuit can make the following bit line discharge time time T32. Even if the control signal changes level during process 600, the second auxiliary circuit, which is dynamically turned on or off with the control signal, and the continuously on first auxiliary circuit will make the following bit line discharge time fall between time T31 and T32. Therefore, by applying process 600 to the circuit of Figure 3a, the change range of the following bit line discharge time can be clearly and reliably determined.

[0066] In the circuit of Figure 4a, if the control signal continuously turns on the second auxiliary circuit during process 600, both the first and second auxiliary circuits will be turned on, and together they can make the operating parameter "bit line discharge time" of the main circuit 110 time T42. If the control signal continuously turns off the second auxiliary circuit during process 600, the turned-on first auxiliary circuit can make the bit line discharge time time T41. Even if the control signal changes level during process 600, the second auxiliary circuit, which is dynamically turned on or off with the control signal, and the continuously turned-on first auxiliary circuit will make the bit line discharge time fall between time T41 and T42. Therefore, by applying process 600 to the circuit of Figure 4a, the change range of the bit line discharge time can be clearly and reliably determined.

[0067] In the circuit of Figure 5a, if the control signal continuously turns on the second auxiliary circuit during process 600, both the first and second auxiliary circuits will be turned on, and together they can make the operating parameter "bit line negative voltage value" of the main circuit 110 a voltage value v52; if the control signal continuously turns off the second auxiliary circuit during process 600, the turned-on first auxiliary circuit can make the bit line negative voltage value a voltage value v51. Even if the control signal changes level during process 600, the second auxiliary circuit, which is dynamically turned on or off with the control signal, and the continuously turned-on first auxiliary circuit will make the bit line negative voltage value fall between voltage values ​​v51 and v52. Therefore, by applying process 600 to the circuit of Figure 5a, the change range of the bit line negative voltage value can be clearly and reliably determined.

[0068] Step 650: End process 600. For the circuit in Figure 3a, process 600 may end when "the following character line TWL is no longer driven". For the circuit in Figure 4a, process 600 may end when "signal vg3[p] no longer turns on transistor H3[p]. For the circuit in Figure 5a, process 600 may end when signal WTG no longer triggers (e.g., when it becomes logic 0).

[0069] Figure 6b illustrates another embodiment of process 600. In the embodiment of Figure 6b, steps 620 and 630 can be performed synchronously with step 610; during process 600, the first auxiliary circuit is continuously turned on (step 620), while the second auxiliary circuit dynamically turns on and off in response to the control signal (step 630).

[0070] In summary, conventional technology sets up different mode-specific circuits for different modes; when switching modes, one mode-specific circuit needs to switch from off to on, and another mode-specific circuit needs to switch from on to off. Due to the uncertainty and transient nature of the on and off states of different mode-specific circuits, conventional technology cannot reliably determine the range of relevant operating parameters and tolerances, and consequently, cannot continue to operate normally during mode switching. In contrast, the auxiliary unit in this invention may include two auxiliary units; when the relevant control signal switches levels (corresponding to the switching of operating conditions / modes), only one of these two auxiliary units will switch on and off accordingly, while the other auxiliary unit will be on regardless of the control signal. Therefore, this invention can clearly and reliably know the magnitude of the change in relevant operating parameters and the corresponding tolerances, thereby enabling the circuit module of this invention to continue to operate normally during operating condition / mode switching, even if the switching of operating conditions / modes occurs within an operating cycle, the circuit module of this invention can still continue to operate normally within that operating cycle.

[0071] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0015] Figure 1 illustrates a circuit module according to an embodiment of the present invention, which may include three auxiliary units. Figure 2 illustrates a waveform timing embodiment of the relevant signals in Figure 1. Figures 3a, 4a, and 5a respectively illustrate embodiments of the auxiliary units in Figure 1; each auxiliary unit may include two auxiliary circuits. Figures 3b, 4b, and 5b respectively illustrate waveform timing embodiments of the relevant signals in 3a, 4a, and 5a. Figures 6a and 6b illustrate embodiments of the flow of the present invention.

Claims

1. A method for enabling a circuit module to have a reliable margin configuration, the circuit module comprising a main circuit, a first auxiliary circuit, and a second auxiliary circuit, the main circuit comprising a first node, the first auxiliary circuit coupled to the first node, and the second auxiliary circuit coupled to the first node and a control signal; the method comprising: turning on the first auxiliary circuit; and when the first auxiliary circuit is turned on, turning off the second auxiliary circuit according to the control signal being a first threshold or a second threshold; wherein: When both the first auxiliary circuit and the second auxiliary circuit are turned on, the first auxiliary circuit and the second auxiliary circuit together set an operating parameter of the main circuit to a first value; when the first auxiliary circuit is turned on and the second auxiliary circuit is turned off, the first auxiliary circuit sets the operating parameter to a second value, which is different from the first value; and an operating tolerance of the main circuit covers the range between the first value and the second value.

2. The method as described in claim 1, wherein: When the supply voltage of the main circuit is a first power supply value and the period of a clock operating the main circuit is a first cycle value, the control signal is the first level; when the supply voltage of the main circuit is a second power supply value and the period of the clock is a second cycle value, the control signal is the second level; and the first power supply value is different from the second power supply value, and the first cycle value is different from the second cycle value.

3. The method as described in claim 1, wherein, The main circuit includes: at least one memory cell coupled to a word line and a bit line; at least one tracking cell coupled to a tracking word line and a tracking bit line, wherein the first node is coupled to the tracking bit line; and a sense amplifier coupled to the bit line.

4. The method as described in claim 3, wherein, The first auxiliary circuit includes: a first transistor, including a first controlled terminal and two first channel terminals; the two first channel terminals are respectively coupled to the first node and a third node; and a third transistor, including a third controlled terminal and two third channel terminals; the two third channel terminals are respectively coupled to the third node and a fourth node, and one of the first controlled terminal and the third controlled terminal is coupled to the follow word line; and the second auxiliary circuit includes: a second transistor, including a second controlled terminal and two second channel terminals; the two second channel terminals are respectively coupled to the first node and a second node; and a fourth transistor, including a fourth controlled terminal and two fourth channel terminals; the two fourth channel terminals are respectively coupled to the second node and the fourth node; one of the second controlled terminal and the fourth controlled terminal is coupled to the control signal, and the other of the second controlled terminal and the fourth controlled terminal is coupled to the follow word line.

5. The method as described in claim 3, wherein, The operating parameter is the time it takes for the voltage of the following bit line to change to a second voltage value after the following bit line is driven.

6. The method as described in claim 3, wherein, The operating parameter is the time it takes for the voltage of the following bit line to change from a first voltage value to a second voltage value.

7. The method as described in claim 3, wherein, This operational tolerance refers to the timing tolerance of the sense amplifier.

8. The method as described in claim 1, wherein, The main circuit includes: at least one memory cell coupled to a word line and a bit line, with the first node coupled to the word line; and a sense amplifier coupled to the bit line.

9. The method as described in claim 8, wherein, The first auxiliary circuit includes: a first transistor with two first channel terminals respectively coupled to the first node and a second node; and a third transistor with two third channel terminals respectively coupled to the second node and a third node; and the second auxiliary circuit includes: a second transistor with a second controlled terminal and two second channel terminals; the second controlled terminal is coupled to the control signal, and the two second channel terminals are respectively coupled to the first node and the second node.

10. The method as described in claim 8, wherein, This operating parameter refers to the time it takes for the voltage of this bit line to change from a third voltage value to a fourth voltage value.

11. The method as described in claim 8, wherein, This operating parameter refers to the time it takes for the voltage of a bit line to change to a fourth voltage value after the word line is driven.

12. The method as described in claim 8, wherein, When the character line is driven, if the control signal is the first level, the voltage of the character line is a fifth voltage value; if the control signal is the second level, the voltage of the character line is a sixth voltage value, and the fifth voltage value is different from the sixth voltage value.

13. The method as described in claim 8, wherein, This operational tolerance refers to the timing tolerance of the sense amplifier.

14. The method as described in claim 1, wherein, The main circuit includes: at least one memory cell coupled to a word line and a bit line; a write circuit coupled to the bit line and a negative bit line, and the first node is coupled to the negative bit line.

15. The method as described in claim 14, wherein, The first auxiliary circuit includes: a first logic gate, including a first input terminal and a first output terminal; and a first capacitor coupled between the first output terminal and the first node; and the second auxiliary circuit includes: a second logic gate, including two second input terminals and a second output terminal, the two second input terminals being respectively coupled to the first input terminal and the control signal; and a second capacitor coupled between the second output terminal and the first node.

16. The method as described in claim 15, wherein, The first logic gate is an inverter, and the second logic gate is an inverter.

17. The method as described in claim 14, wherein, This operating parameter refers to the extreme voltage value of the negative voltage bit line after the word line is driven.

18. The method as described in claim 14, wherein, This operational tolerance is the negative pressure tolerance of this bit line.

19. The method of claim 1, wherein the circuit module further includes a third auxiliary circuit and a fourth auxiliary circuit, the third auxiliary circuit being coupled to a fourth node, and the fourth auxiliary circuit being coupled to the fourth node and a second control signal; and the method further includes: when the third auxiliary circuit is turned on, causing the fourth auxiliary circuit to turn on or off according to the second control signal being a third level or a fourth level; wherein: When both the third auxiliary circuit and the fourth auxiliary circuit are turned on, the third auxiliary circuit and the fourth auxiliary circuit jointly make a second operating parameter of the main circuit a third value; when the third auxiliary circuit is turned on and the fourth auxiliary circuit is turned off, the third auxiliary circuit makes the operating parameter a fourth value, which is different from the third value; a second operating tolerance of the main circuit covers the range between the third value and the fourth value; and the control signal and the second control signal will not switch levels simultaneously.

20. The method as described in claim 19, wherein: When the control signal switches levels, the second control signal will switch levels after a first delay time; and when the second control signal switches levels again, the control signal will switch levels again after a second delay time.

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