Memory module with improved timing adaptivity of sensing amplification
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-04-13
- Publication Date
- 2023-10-16
Smart Images
Figure TWG2TA000928448_001 
Figure TWG2TA000928448_002 
Figure TWG2TA000928448_003
Abstract
Description
[Technical Field]
[0001] This invention relates to a memory module that can improve the timing adaptability of sensing amplification, and more particularly to a memory module that can adapt the duration of the sensing amplifier's enable to the number of input and output and / or the supply voltage of the sensing amplifier. [Previous Technology]
[0002] Memory modules, such as embedded static random access memory modules, are important basic building blocks of integrated circuits (semiconductor chips).
[0003] The memory module has multiple memory cells and multiple sense amplifiers; these sense amplifiers are controlled by a single enable signal. When the enable signal is activated, each sense amplifier is enabled and operates; when the enable signal is deactivated, each sense amplifier is disabled and does not operate.
[0004] When the memory module needs to read data stored in a memory cell during a read cycle, the bit line corresponding to the memory cell is turned on to a corresponding sensing amplifier. An enable signal is then activated, enabling the sensing amplifier to sense the voltage of the corresponding bit line and determine the data stored in the memory cell. Afterward, the enable signal is deactivated, disabling the sensing amplifier and stopping sensing, thus ending the read cycle. The duration of the sensing amplifier's activation in each read cycle depends on the duration of the enable signal activation, i.e., the pulse width of the enable signal. If the pulse width of the enable signal is insufficient, the sensing amplifier's activation time will be insufficient, consequently affecting the accuracy of data reading.
[0005] In the prior art, a fixed number of series-connected inverters are used in the prior art, and the pulse width of the enable signal depends on the sum of the gate delays of these series-connected inverters. Therefore, in the prior art, the pulse width of the enable signal lacks flexibility and is difficult to adapt to the different needs of various memory modules. Furthermore, these series-connected inverters also occupy a considerable amount of layout area. [Summary of the Invention]
[0006] One object of the present invention is to provide a memory module (e.g., 100, FIG. 1) that improves the adaptability of sensing amplification timing, comprising at least one bit line (e.g., BL[q]), at least one word line (e.g., WL[p]), a following bit line (e.g., TBL), a following word line (e.g., TWL), at least one memory cell (e.g., c[p,q]), at least one following cell (e.g., tc[p]), at least one sensing amplifier (e.g., SA[k]), and a pulse width controller (e.g., 300, FIG. 4). The following word line includes a preceding node (e.g., w1) and a following node (e.g., w3), and the length between the preceding node and the following node is positively correlated with the length of each word line. Each memory cell is coupled to one of the at least one bit line and one of the at least one word line. Each following cell is coupled to the following bit line. Each of the sensing amplifiers is coupled to one of the at least one bit line and receives a consistent enable signal (e.g., GS). Each sensing amplifier is controlled to be enabled when the enable signal is activated and disabled when the enable signal is deactivated. A pulse width controller is coupled to the following bit line, the preceding node, and the following node and provides the enable signal. Specifically, when the voltage of the following bit line (e.g., vTBL, FIG. 5) changes to a preset voltage (e.g., vt0, at time t3, FIG. 5), the pulse width controller activates the enable signal (e.g., at time t6, FIG. 5) and causes the voltage of the preceding node (e.g., vw1, FIG. 5) to change (e.g., switching from voltage v4 to voltage v3 starting at time t7, FIG. 5). When the voltage of the preceding node changes, the following word line causes the voltage of the following node (e.g., vw3, FIG. 5) to change (e.g., switching from voltage v4 to voltage v3 starting at time t8, FIG. 5) after a first delay time (e.g., d1, FIG. 5). When the voltage of the downstream node changes, the pulse width controller stops firing the enable signal after a second delay time (e.g., d2, Figure 5) (e.g., at time t12, Figure 5).
[0007] In one embodiment (e.g., FIG. 6), a portion of the pulse width controller (e.g., logic gate G1, FIG. 6) is powered by a first supply voltage (e.g., Vdd1, FIG. 6), and at least a portion of each sense amplifier (e.g., SA[k], FIG. 6) (e.g., s2[k], FIG. 6) is powered by a second supply voltage (e.g., Vdd2, FIG. 6). In one embodiment, the first supply voltage and the second supply voltage are different, and the length of the second delay time is negatively correlated with the magnitude of the second supply voltage.
[0008] In one embodiment (e.g., FIG. 6), the pulse width controller has two parts (e.g., logic gate G1 and delay circuit 500, FIG. 6) which are respectively powered by two different supply voltages (e.g., Vdd1 and Vdd2, FIG. 6), and the length of the second delay time is negatively correlated with one of the two different supply voltages (e.g., Vdd2, FIG. 6).
[0009] In one embodiment (e.g., FIG. 4), the pulse width controller includes a first logic gate (e.g., G1, FIG. 4). The first logic gate includes a first input (e.g., i1), a second input (e.g., i2), and a first output (e.g., o1), respectively coupled to the following bit line, the subsequent node, and a first node (e.g., n1). The pulse width controller generates the enable signal at a third node (e.g., n3), which is coupled to the at least one sense amplifier. When the memory module reads data, the voltage of the third node is controlled by the voltage of the first node. When the pulse width controller activates the enable signal, it switches the enable signal from a first level (e.g., v1, FIG. 5) to a second level (e.g., v2, FIG. 5); when the pulse width controller stops activating the enable signal, it switches the enable signal back from the second level to the first level. In one embodiment (e.g., FIG. 4), the pulse width controller further includes a first inverter (e.g., iv1, FIG. 4) coupled between the follow bit line and the first input. In one embodiment (e.g., FIG. 4), the first logic gate is an inverting gate.
[0010] In one embodiment (e.g., FIG. 4), the pulse width controller further includes a third logic gate (e.g., G3, FIG. 4) and a delay circuit (e.g., 500, FIG. 4). The third logic gate includes a fifth input (e.g., i5), a sixth input (e.g., i6), and a third output (e.g., o3). The fifth input is coupled to a second node (e.g., n2), the delay circuit is coupled between the second node and the sixth input, and the third output is coupled to the third node. When the memory module reads data, the voltage of the second node is controlled by the voltage of the first node. In one embodiment (e.g., FIG. 4), the pulse width controller further includes a third inverter (e.g., iv3, FIG. 4), coupled between the third output and the third node.
[0011] In one embodiment (e.g., FIG. 6), the first logic gate and the delay circuit are powered by a first supply voltage (e.g., Vdd1, FIG. 6) and a second supply voltage (e.g., Vdd2, FIG. 6), respectively, and the first supply voltage and the second supply voltage are different. In one embodiment (e.g., FIG. 6), at least a portion of each sense amplifier (e.g., s2[k], FIG. 6) is powered by the second supply voltage.
[0012] In one embodiment (e.g., FIG. 4), the pulse width controller further includes a second logic gate (e.g., G2, FIG. 4). The second logic gate includes a third input (e.g., i3), a fourth input (e.g., i4) and a second output (e.g., o2), which are respectively coupled to the first node, the fourth node (e.g., n4) and the second node.
[0013] In one embodiment (e.g., FIG. 4), the pulse width controller further includes a fourth logic gate (e.g., G4, FIG. 4). The fourth logic gate includes a seventh input (e.g., i7), an eighth input (e.g., i8), and a fourth output (e.g., o4), which are respectively coupled to a first indication signal (e.g., SCANEN), a second indication signal (e.g., WEI), and the fourth node. In one embodiment (e.g., FIG. 4), the second logic gate, the third logic gate, and the fourth logic gate are all inverse OR gates.
[0014] In one embodiment (e.g., FIG. 4), the memory module further includes a finite state machine circuit (e.g., 400, FIG. 4) coupled between the pulse width controller and the previous node. When the pulse width controller changes the voltage of the previous node, it causes the finite state machine circuit to change the voltage of the previous node.
[0015] In one embodiment (e.g., FIG4), the finite state machine circuit includes a fifth node (e.g., n5, FIG4) and a sixth node (e.g., n6, FIG4); wherein the fifth node is coupled to the first node and the sixth node is coupled to the previous node.
[0016] In one embodiment (e.g., FIG. 4), the finite state machine circuit further includes a seventh node (e.g., n7) coupled to a clock (e.g., CLK). In one embodiment (e.g., FIG. 4), the memory module further includes a second inverter (e.g., iv2, FIG. 4) coupled between the sixth node and the previous node.
[0017] One object of the present invention is to provide a memory module (e.g., 100, FIG. 1) that can improve the timing adaptability of sensing amplification, which may include at least one bit line (e.g., BL[q]), at least one word line (e.g., WL[p]), a following bit line (e.g., TBL), a following word line (e.g., TWL), at least one memory cell (e.g., c[p,q]), at least one following cell (e.g., tc[p]), at least one sensing amplifier (e.g., SA[k]), and a first logic gate (e.g., G1, FIG. 4). The following word line extends from a previous node (e.g., w1) to a next node (e.g., w3), and the length from the previous node to the next node is positively correlated with the length of each word line. Each memory cell is coupled to one of the at least one bit line and one of the at least one word line. Each following cell is coupled to the following bit line. Each sensing amplifier is coupled to one of the at least one bit line and further coupled to a third node (e.g., n3). Each of the sense amplifiers is disabled when the voltage of the third node is at a first level (e.g., v1, Figure 6) and controlled to be enabled when the voltage of the third node is at a second level (e.g., v2, Figure 6). The first logic gate includes a first input (e.g., i1, Figure 4), a second input (e.g., i2, Figure 4), and a first output (e.g., o1, Figure 4), which are respectively coupled to the follow bit line, the next node, and the previous node. When the memory module reads data, the voltage of the third node is controlled by the voltage of the first output.
[0018] In one embodiment (Figure 4), the memory module further includes a third logic gate (e.g., G3, Figure 4) and a delay circuit (e.g., 500, Figure 4). The third logic gate includes a fifth input terminal (e.g., i5), a sixth input terminal (e.g., i6), and a third output terminal (e.g., o3); the fifth input terminal is coupled to a second node (e.g., n2), the delay circuit is coupled between the second node and the sixth input terminal, the third output terminal is coupled to the third node, and the second node is coupled to the first output terminal. In one embodiment (e.g., Figure 6), the first logic gate and the delay circuit are powered by two different supply voltages (e.g., Vdd1 and Vdd2, Figure 6).
[0019] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:
Implementation Method
[0021] Figure 1 illustrates a memory module 100 according to an embodiment of the present invention, which may include P*Q memory cells c[1,1] to c[P,Q], P word lines WL[1] to WL[P], Q sets of bit lines BL[1], BLb[1] to BL[Q], BLb[Q], P follower cells tc[1] to tc[P], an auxiliary word line w0, a set of follower bit lines TBL and TBLb, a follower word line TWL, K buffers bf[1] to bf[K], K sense amplifiers SA[1] to SA[K], K write circuits WB[1] to WB[K], two peripheral circuits 130 and 140, and a control circuit 200. The numbers P, Q, and K may be preset integers. The number Q may be an integer multiple of the number K; for example, the number Q may be one, two, or four times the number K, etc. The number K (number of sense amplifiers and write circuits) represents the number of inputs and outputs of memory module 100.
[0022] In the memory module 100, each memory cell c[p,q] (p = 1 to P, q = 1 to Q) is coupled to a corresponding word line WL[p] and a set of corresponding bit lines BL[q] and BLb[q], and can store one bit of data. Continuing from Figure 1, Figure 2 illustrates one embodiment of each memory cell c[p,q]; each memory cell c[p,q] may include a set of inverters iA[p,q] and iB[p,q], and a set of pass-gate transistors A[p,q] and B[p,q] (such as an n-channel metal-oxide-semiconductor). Inverters iA[p,q] and iB[p,q] form a latch L[p,q]. Transistor A[p,q] has a controlled terminal (such as a gate terminal) and two channel terminals (such as a drain terminal and a source terminal), which are respectively coupled to one end of word line WL[p], bit line BL[q], and latch L[p,q]. Transistor B[p,q] has a controlled terminal and two channel terminals, which are respectively coupled to the other end of word line WL[p], bit line BLb[q], and latch L[p,q].
[0023] In the memory module 100 of Figure 1, each follower cell tc[p] is coupled to the auxiliary word line w0 and the follower bit lines TBL and TBLb. The circuit of each follower cell tc[p] can be the same as the circuit of each memory cell c[p,q], so that each follower cell tc[p] can reflect (follow) the properties (such as response time) of each memory cell c[p,q].
[0024] As shown in Figure 1, in the memory module 100, the following character line TWL can extend from one node w1 to another node w2, and then from node w2 to yet another node w3. The length of the following character line TWL from node w1 (via node w2) to node w3 can be positively correlated with the length of each character line WL[p]. In one embodiment, the circuit structure (such as line length and line width) of the following character line TWL can approximate or substantially equal the circuit structure of each character line WL[p] to reflect the properties of each character line WL[p], such as equivalent impedance, equivalent load, and response. As shown in Figure 1, the following character line TWL can extend horizontally from node w1 by a distance D1 to node w2, and then extend in the opposite direction from node w2 by the same distance D1 (or an approximate distance) to node w3. In other words, the length of the following character line TWL between nodes w1 and w3 can be twice the distance D1. As shown in Figure 1, distance D1 can horizontally span the space between bit lines BL[J+1], BLb[J+1] and BL[Q], BLb[Q], and the number J can be a preset integer; for example, the number Q can be even, and the number J can be equal to half the number Q. Thus, twice the distance D1 will be equal to (or close to) the length of each word line WL[p], because each word line WL[p] will horizontally span bit lines BL[1], BLb[1] to BL[J], BLb[J] and bit lines BL[J+1], BLb[J+1] to BL[Q], BLb[Q]. The following word line TWL does not need to be coupled to any memory cell c[p,q]; that is, the following word line TWL can be insulated from any of the memory cells c[1,1] to c[P,Q].
[0025] Peripheral circuit 130 is coupled to word lines WL[1] to WL[P] and is controlled by control circuit 200. Peripheral circuit 140 is coupled to each group of bit lines BL[1], BLb[1] to BL[Q], BLb[Q], sense amplifier SA[1] to SA[K] and write circuit WB[1] to WB[K], and is also controlled by control circuit 200.
[0026] The control circuit 200 receives a clock CLK and controls the operation of the memory module 100 accordingly; the control circuit 200 is coupled to peripheral circuits 130 and 140, coupled to nodes w1 and w3 of the following word line TWL, coupled to the following bit line TBL at one node n0, and coupled to buffers bf[1] to bf[K] at another node n3.
[0027] The control circuit 200 outputs a signal GS from node n3, which is the enable signal of the sense amplifiers SA[1] to SA[K]. Each sense amplifier SA[k] is coupled to the peripheral circuit 140 and is also coupled to node n3 via the corresponding buffer bf[k] to receive the signal GS.
[0028] When data is to be written to a memory cell c[p,q] in a data write cycle, the control circuit 200 controls the peripheral circuits 130 and 140. The peripheral circuit 140 turns on the corresponding bit lines BL[q] and BLb[q] to one of the write circuits WB[1] to WB[K], WB[k], and the peripheral circuit 130 drives the corresponding word line WL[p] so that the latch L[p,q] (Figure 2) in the memory cell c[p,q] can be turned on to the bit lines BL[q] and BLb[q]. In this way, the write circuit WB[k] can write data to the memory cell c[p,q] via the bit lines BL[q] and BLb[q].
[0029] Continuing from Figures 1 and 2, Figure 3 illustrates the waveform timing of relevant signals when the memory module 100 reads data. As shown in Figure 3, in one cycle T1 of the clock CLK, the voltage of the clock CLK alternates once between voltages vck1 and vck2. When the memory cell c[p,q] (Figure 1) is to be read, as the clock CLK switches from voltage vck1 to voltage vck2 at a time ta1, the control circuit 200 controls the peripheral circuits 130 and 140, so that the peripheral circuit 140 turns on the corresponding bit lines BL[q] and BLb[q] to one of the sense amplifiers SA[1] to SA[K] SA[k], and at a later time ta2, the peripheral circuit 130 drives the voltage vWL[p] of the corresponding word line WL[p] from one voltage vWL1 (e.g., a voltage that cannot turn on the gate-on transistor) to another voltage vWL2 (e.g., a voltage that is sufficient to turn on the gate-on transistor), so that the latch L[p,q] (Figure 2) in the memory cell c[p,q] can be turned on to the bit lines BL[q] and BLb[q]. At another time point ta3, the control circuit 200 begins to activate the signal GS, that is, to switch the signal GS from a level v1 representing no activation to a level v2 representing activation. The activated signal GS enables the sense amplifiers SA[1] to SA[K], and the enabled sensor SA[k] senses the voltage difference between bit lines BL[q] and BLb[q], thereby determining the data stored in the memory cell c[p,q]. At the next time point ta4, the control circuit 200 causes the peripheral circuit 130 (Fig. 1) to stop driving the word line WL[p], causing the voltage vWL[p] to switch from voltage vWL2 back to voltage vWL1. At the next time point ta5, the control circuit 200 stops activating the signal GS, that is, to switch the signal GS from level v2 back to level v1. As the signal GS stops activating, the sense amplifiers SA[1] to SA[K] also become disabled and cease operation. At the next time point ta6, the period T1 of the clock CLK ends. As shown in Figure 3, the pulse width pw1 during which the signal GS is maintained at level v2 is the period during which the sense amplifier SA[1] to SA[K] can be controlled to be enabled.
[0030] Continuing from Figures 1 to 3, Figure 4 illustrates an embodiment of the control circuit 200 of the present invention. As shown in Figure 4, in one embodiment of the present invention, the control circuit 200 may include a pulse width controller 300, a finite state machine circuit 400, two buffers bf1 and bf2, and an inverter iv2. The pulse width controller 300 may include four logic gates G1 to G4, inverters iv1 and iv3, and a delay circuit 500. The delay circuit 500 may include a buffer bf3. The finite state machine circuit 400 may be coupled between a supply voltage Vdd1 and a ground voltage Vss1, and may include nodes n5, n6, and n7; the clock CLK may be coupled to node n7. The control circuit 200 may also include other circuit elements, but these have been omitted without affecting the disclosure of the present invention.
[0031] As shown in Figure 4, in the control circuit 200, buffer bf1 is coupled between node n1 of the pulse width controller 300 and node n5 of the finite state machine circuit 400. Inverter iv2 and buffer bf2 are connected in series between node n6 of the finite state machine circuit 400 and node w1 of the following word line TWL. The finite state machine circuit 400 can control the operating state of the memory module 100 under the trigger of the clock CLK, while the pulse width controller 300 can control the timing of the signal GS, including its pulse width pw1 (Figure 3).
[0032] In the pulse width controller 300, logic gate G1 can be an inverting gate, and logic gates G2 to G4 can be inverting gates. Logic gate G1 may include two input terminals i1 and i2 and one output terminal o1; logic gate G2 may include two input terminals i3 and i4 and one output terminal o2; logic gate G3 may include two input terminals i5 and i6 and one output terminal o3; and logic gate G4 may include two input terminals i7 and i8 and one output terminal o4. Inverter iv1 is coupled between node n0 and input terminal i1, delay circuit 500 is coupled between node n2 and input terminal i6, and inverter iv3 is coupled between output terminal o3 and node n3. The voltage at node n3 can form signal GS.
[0033] As shown in Figure 4, regarding logic gate G1, the following bit line TBL can be coupled to input terminal i1 via node n0 and inverter iv1, the following word line TWL can be coupled to input terminal i2 via node w3, and the output terminal o1 can be coupled to node n1. The voltage of node n1 can form a signal TBL_LB. As shown in Figure 4, two circuit paths can be branched from node n1. One circuit path can couple the output terminal o1 of logic gate G1 to node w1 of following word line TWL via buffer bf1, nodes n5 and n6 of finite state machine circuit 400, inverter iv2 and buffer bf2. The other circuit path can couple the output terminal o1 of logic gate G1 to node n3 that forms signal GS via logic gate G2, node n2 and delay circuit 500, logic gate G3 and inverter iv3.
[0034] In the pulse width controller 300, the input terminal i3 and output terminal o2 of logic gate G2 can be coupled to nodes n1 and n2 respectively, and the input terminal i4 can be coupled to another node n4. The input terminal i5 of logic gate G3 can be coupled to node n2. The input terminals i7 and i8 and the output terminal o4 of logic gate G4 can be coupled to an indicator signal SCANEN, an indicator signal WEI, and node n4 respectively. The signal SCANEN indicates whether the memory module 100 (Figure 1) is performing a scanning operation. When the signal SCANEN is logic 1, the memory module 100 performs a scanning operation; when it is logic 0, the memory module 100 does not perform a scanning operation, so data reading or data writing can be performed. The signal WEI indicates whether the memory module 100 is performing data reading. When the signal WEI is logic 0, the memory module 100 performs data writing; when it is logic 1, the memory module 100 performs data reading.
[0035] Figures 7a and 7b illustrate the state list and state diagram of the finite state machine circuit 400 in one embodiment. As shown in Figures 7a and 7b, in one embodiment of the present invention, the finite state machine circuit 400 can switch between states S0, P0, Launch, Idle0, Idle1, and P1; the logic values of nodes n5 and n7 (Figure 4) can be regarded as the inputs of the finite state machine circuit 400, and the logic value of node n6 can be regarded as the output of the finite state machine circuit 400. The logic values of nodes n5, n7, and n6 are represented in the form of xy / z in Figures 7a and 7b.
[0036] Continuing from Figures 1 to 4, Figure 5 illustrates the waveform timing of various related signals in the control circuit 200 (Figure 4) when the memory module 100 (Figure 1) is reading data. Voltages vw1, vw3, vTBL, vi5, and vi6 represent the voltages at nodes w1, w3, the following bit line vTBL (node n0), and input terminals i5 and i6, respectively. At a time point t0, the clock CLK begins to switch from voltage vck1 (e.g., a voltage representing logic 0) to voltage vck2 (e.g., a voltage representing logic 1). When the clock CLK switches from voltage vck1 to voltage vck2, the finite state machine circuit 400 (Figure 4) can change the voltage at node n6 from the supply voltage Vdd1 (which can represent logic 1) to the ground voltage Vss1 (which can represent logic 0). As the voltage at node n6 changes, the operation of inverter iv2 and buffer bf2 will, at a later time t1, cause the voltage vw1 (Figure 5) at node w1 to switch from voltage v3 (e.g., a voltage representing logic 0) to voltage v4 (e.g., a voltage representing logic 1). Due to the length of the word line TWL, the voltage vw3 at node w3 will switch from voltage v3 to voltage v4 after a delay time d1.
[0037] As the voltage of the following character line TWL switches to voltage v4, the voltage vTBL of the following bit line TBL at node n0 will change from an initial voltage vpr0 (e.g., decrease) after a time point t2, and then change to a preset voltage vt0 at another time point t3. For example, voltage vt0 can be the toggle voltage of inverter iv1; before the voltage of node n0 changes to this voltage vt0 (i.e., before time point t3), inverter iv1 will determine the voltage of node n0 as logic 1; after the voltage of node n0 changes to this voltage vt0 (i.e., after time point t3), inverter iv1 will then determine the voltage of node n0 as logic 0. Therefore, inverter iv1 will switch the logic 0 output to input i1 to logic 1 after time point t3. In response to the change in input at input terminal i1, logic gate G1 will cause the signal TBL_LB of node n1 to switch from voltage v6 (for example, a voltage representing logic 1) to voltage v5 (for example, a voltage representing logic 0) at the next time point t4.
[0038] During data reading, the signals SCANEN (Fig. 4) and WEI cause logic gate G4 to continuously output logic 0 from output terminal o4 to input terminal i4 of logic gate G2. Therefore, when signal TBL_LB starts switching from voltage v6 to voltage v5 at time t4, logic gate G2 will cause the voltage vi5 (Fig. 5) at input terminal i5 to start switching from voltage v7 (e.g., a voltage representing logic 0) to voltage v8 (e.g., a voltage representing logic 1) at the next time t5. When the voltage vi5 (Fig. 5) at input terminal i5 starts switching from voltage v7 to voltage v8 at time t5, the voltage vi6 at input terminal i6 will remain at voltage v7 due to the delay circuit 500 (Fig. 4) between node n2 and input terminal i6. Therefore, as voltage vi5 switches from voltage v7 to voltage v8 at time t5, the operation of logic gate G3 and inverter iv3 will cause the signal GS of node n3 to switch from level v1 (e.g., a level representing logic 0) to level v2 (e.g., a level representing logic 1) at a slightly later time t6, which means the signal GS will begin to be activated. That is, as the following bit line TBL changes to the preset voltage vt0 at time t3, inverter iv1, logic gates G1, G2, G3 and inverter iv3 will be driven to operate in a series, thereby activating the signal GS at time t6.
[0039] When the signal TBL_LB of node n1 starts to switch from voltage v6 to voltage v5 at time t4, the buffer bf1 will cause the voltage of node n5 to switch accordingly; in response to the voltage switch of node n5, the finite state machine circuit 400 will change the voltage of node n6 to the supply voltage Vdd1; the operation of inverter iv2 and buffer bf2 will cause the voltage vw1 of node w1 to start switching from voltage v4 back to voltage v3 at time t7. That is, as the following bit line TBL changes to the preset voltage vt0 at time t3, inverter iv1, logic gate G1 and buffer bf1, finite state machine circuit 400, inverter iv2 and buffer bf2 will also be driven to perform a series of operations, thereby causing the voltage vw1 of node w1 to start changing (switching from voltage v4 back to voltage v3) at time t7.
[0040] When the voltage vw1 of node w1 begins to change at time t7, the following character line TWL will cause the voltage vw3 of node w3 to also begin to change at another time t8 (=t7+d1) after a delay time d1, switching from voltage v4 back to voltage v3. As the voltage of the following character line TWL returns to voltage v3, the voltage vTBL of the following bit line TBL can be restored to voltage vpr0.
[0041] As voltage vw3 switches back from voltage v4 to voltage v3 at time t8, logic gate G1 will cause signal TBL_LB to switch back from voltage v5 to voltage v6 at a slightly later time t9. Simultaneously, logic gate G2 will cause voltage vi5 at input i5 to switch back from voltage v8 to voltage v7 at a later time t10, and delay circuit 500 will cause voltage vi6 at input i6 to switch back from voltage v8 to voltage v7 at another time t11 (=t10+d2) after a delay time d2. As voltages vi5 and vi6 at inputs i5 and i6 both switch back to voltage v7, the operation of logic gate G3 and inverter iv3 will cause signal GS to switch back from level v2 to level v1 at a time t12, stopping the activation of signal GS. That is, as the voltage vw3 of node w3 begins to change at time t8, logic gates G1, G2, delay circuit 500, logic gate G3 and inverter iv3 will be driven to operate in a series, and the excitation signal GS will stop at time t12.
[0042] As described above, the pulse width control of signal GS in this invention can be summarized as follows. When the voltage vTBL of the following bit line TBL changes to the preset voltage vt0 (time point t3), the pulse width controller 300 will activate the enable signal GS at time point t6 (through the operation of inverter iv1, logic gates G1, G2, G3 and inverter iv3 from time point t3 to t6), and at time point t7, change the voltage vw1 of node w1 (through the operation of inverter iv1, logic gate G1, buffer bf1, finite state machine circuit 400, inverter iv2 and buffer bf2 from time point t3 to t7). When the voltage vw1 of node w1 changes at time point t7, the voltage vw3 of node w3 changes at time point t8 after a delay time d1, following the word line TWL. When the voltage vw3 at node w3 changes at time t8, the pulse width controller 300 stops generating the enable signal GS at time t12 after the delay time d2 (through the operation of logic gates G1, G2, delay circuit 500, logic gate G3 and inverter iv3 from time t8 to t12).
[0043] As shown in Figure 5, through the operation of the pulse width controller 300, the time interval (hereinafter referred to as the excitation time interval AT1) between the "start excitation signal GS" (time point t6) and the "start stop excitation signal GS" (time point t12) will cover the sum of the delay times d1 and d2. Since a transient time (e.g., rise time) is required after the "start excitation signal GS" for the signal GS to truly reach the excitation level (e.g., the level of logic 0) from the unexcited level (e.g., the level of logic 0), the pulse width system for the signal GS to truly maintain at the excitation level depends on the result of the excitation time interval minus the transient time. Since the signal GS needs to be transmitted to all sense amplifiers SA[1] to SA[K] (via buffers bf[1] to bf[K]), if the number of input and output of the memory module (the number of sense amplifiers K) is greater, the impedance faced by the excitation signal GS will be greater, and consequently, the transient time will also be longer.
[0044] In the prior art, the excitation time interval between the "start excitation signal GS" and the "start stop excitation signal GS" is fixed; therefore, if the number of input and output of the memory module is large and the transient time is long, the pulse width of the signal GS (the difference between the fixed excitation time interval and the long transient time) will be relatively short, resulting in the problem of insufficient pulse width of the signal GS.
[0045] Compared to the fixed excitation interval of the prior art, in the present invention, the excitation interval AT1 between the "start excitation signal GS" and the "start stop excitation signal GS" is adaptive. If the number of input / output K of the memory module is large, the length of each character line WL[p] and the following character line TWL (Fig. 1) will be longer, so the delay time d1 (Fig. 5) will also be longer, and the excitation interval AT1 covering the delay time d1 will also become longer. In this way, even if the transient time is long, the pulse width of the signal GS (the difference between the longer excitation interval and the longer transient time) will not be insufficient.
[0046] In the memory module 100, the control circuit 200 already utilizes the characteristics and performance of the following character line TWL following each character line WL[p] to dynamically adjust the control of the memory module 100. The pulse width controller 300 of the present invention further expands the application of the following character line TWL by using the existing following character line TWL for feedback (from the output terminal o1 to the input terminal i2) so that the excitation interval AT1 is positively correlated with the number of input and output K, thereby ensuring that the signal GS has sufficient pulse width. In this way, the pulse width controller 300 of the present invention can be applied to various memory modules with different numbers of input and output. Furthermore, the delay circuit 500 in the pulse width controller 300 does not require too many cascaded inverters to extend the excitation interval AT1, thereby reducing the layout area of the pulse width controller 300. In one embodiment, the buffer bf3 in the delay circuit 500 can be simply formed by two cascaded inverters (not shown).
[0047] Continuing from Figures 1 to 5, Figure 6 illustrates a supply voltage configuration according to an embodiment of the present invention. Due to specific requirements for power consumption, performance, and / or operation, some memory modules may span different power domains, and different parts may use different supply voltages. For example, as shown in Figure 6, each sense amplifier SA[k] (k=1 to K) may include two parts s1[k] and s2[k], which belong to two power domains respectively; part s1[k] may be biased between the supply voltage Vdd1 and the ground voltage Vss1, and is powered by the supply voltage Vdd1 (e.g., a memory supply voltage), while part s2[k] may be biased between another supply voltage Vdd2 and another ground voltage Vss2, and is powered by the supply voltage Vdd2 (e.g., an interface supply voltage).
[0048] In an embodiment employing a dual-rail sensing amplification mechanism, the supply voltages Vdd1 and Vdd2 are different, with Vdd1 potentially being greater than or less than Vdd2, and the ground voltages Vss1 and Vss2 potentially being coupled together. Since a portion s2[k] of each sensing amplifier SA[k] is powered by the supply voltage Vdd2, the operating speed of the sensing amplifier SA[k] is related to the level of the supply voltage Vdd2; consequently, the pulse width requirement of the signal GS is also related to the level of the supply voltage Vdd2. If the supply voltage Vdd2 is lower, the operating speed of the sensing amplifier SA[k] is slower, and the pulse width of the signal GS should also be longer, allowing the slower sensing amplifier SA[k] more time to sense; if the supply voltage Vdd2 is higher, the operating speed of the sensing amplifier SA[k] is faster, and the pulse width of the signal GS can be shortened accordingly.
[0049] In order to accommodate the supply voltage Vdd2 of the sensing amplifier SA[k], the delay circuit 500 (buffer bf3) in the pulse width controller 300 can be biased between the supply voltage Vdd2 and the ground voltage Vss2, just like the portion s2[k] of the sensing amplifier SA[k], and is powered by the supply voltage Vdd2. On the other hand, the logic gates G1 to G4 and the inverters iv1 and iv3 in the pulse width controller 300, as well as the finite state machine circuit 400, inverter iv2 and buffers bf1 and bf2 in the control circuit 200, can be biased between the supply voltage Vdd1 and the ground voltage Vss1, just like the portion s1[k] of the sensing amplifier SA[k], and is powered by the supply voltage Vdd1. Thus, the delay time d2 of the delay circuit 500 is negatively correlated with the level of the supply voltage Vdd2. If the supply voltage Vdd2 is lower, the operating speed of the delay circuit 500 is slower, and the delay time d2 is extended accordingly. If the supply voltage Vdd2 is higher, the operating speed of the delay circuit 500 is faster, and the delay time d2 is shortened accordingly. Since the excitation interval AT1 of the signal GS covers the delay time d2 of the delay circuit 500 (Figure 5), the length of the excitation interval AT1 is also negatively correlated with the level of the supply voltage Vdd2, just like the delay time d2. If the supply voltage Vdd2 is lower, the excitation interval AT1 and the pulse width of the signal GS will be extended accordingly. If the supply voltage Vdd2 is higher, the excitation interval AT1 and the pulse width of the signal GS will be shortened accordingly.
[0050] In another embodiment of the dual-track sensing amplification mechanism, buffers bf1 and / or bf2 can also be biased between the supply voltage Vdd2 and the ground voltage Vss2, together with the auxiliary delay circuit 500, to make the excitation time interval AT1 (Figure 5) negatively correlated with the supply voltage Vdd2. In yet another embodiment, buffers bf1 and / or bf2 are biased between the supply voltage Vdd2 and the ground voltage Vss2, the delay circuit 500 can be omitted, and the logic gate G3 can be an inverter coupled between node n2 and inverter iv3.
[0051] Compared to the dual-track sensing amplification mechanism, in another type of single-track sensing amplification mechanism embodiment, the supply voltage Vdd2 can be equal to the supply voltage Vdd1. That is, the control circuit 200 and each sensing amplifier SA[k] belong to the same power supply domain and are uniformly powered by the supply voltage Vdd1.
[0052] In summary, in the prior art, the enable signal of the sense amplifier is limited by a fixed excitation interval, which cannot adapt to the different needs of various memory modules. In contrast, the technology of the present invention can extend the application of existing follower word lines. In the pulse width controller of the present invention, the feedback of the follower word lines is used to make the excitation time positively correlated with the number of inputs and outputs, so as to adapt to various memory modules with different numbers of inputs and outputs. Furthermore, due to the dual-track sense amplification mechanism, different parts of the pulse width controller of the present invention can also belong to different power supply domains, so that the excitation interval of the enable signal can be negatively correlated with the supply voltage of the sense amplifier, thereby adapting to various memory modules with different supply voltage configurations.
[0053] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]
[0020] Figure 1 illustrates a memory module according to an embodiment of the present invention, which may include a plurality of memory cells and a control circuit. Figure 2 illustrates an embodiment of the memory cell of Figure 1. Figure 3 illustrates an embodiment of the waveform timing sequence of the memory module of Figure 1 during data reading. Figure 4 illustrates an embodiment of the control circuit of Figure 1. Figure 5 illustrates an embodiment of the waveform timing sequence of the control circuit of Figure 4. Figure 6 illustrates an embodiment of the supply voltage configuration in Figure 4. Figures 7a and 7b illustrate a state list and state diagram of the finite state machine circuit in Figure 4 in one embodiment.
Claims
1. A memory module with improved sensing amplification timing adaptability, comprising: at least one bit line, at least one word line, a following bit line, and a following word line; the following word line includes a preceding node and a following node, and the length between the preceding node and the following node is positively correlated with the length of each word line; at least one memory cell, each memory cell being coupled to one of the at least one bit line and one of the at least one word line; at least one following cell being coupled to the following bit line; at least one sensing amplifier, each sensing amplifier being coupled to one of the at least one bit line and receiving an enable signal; each sensing amplifier being controlled to be enabled when the enable signal is activated (asserted) and disabled when the enable signal is deactivated; and a pulse width controller being coupled to the following bit line, the preceding node, and the following node, and providing the enable signal; wherein: When the voltage of the following bit line changes to a preset voltage, the pulse width controller activates the enable signal and changes the voltage of the preceding node; when the voltage of the preceding node changes, the following bit line changes the voltage of the following node after a first delay time; and when the voltage of the following node changes, the pulse width controller stops activating the enable signal after a second delay time.
2. The memory module as claimed in claim 1, wherein a portion of the pulse width controller is powered by a first supply voltage, and at least a portion of each of the sensing amplifiers is powered by a second supply voltage; the first supply voltage and the second supply voltage are different, and the length of the second delay time is negatively correlated with the magnitude of the second supply voltage.
3. The memory module as described in claim 1, wherein, The pulse width controller has two parts that are powered by two different supply voltages, and the length of the second delay time is negatively correlated with one of the two different supply voltages.
4. The memory module as claimed in claim 1, wherein the pulse width controller includes a first logic gate, the first logic gate including a first input terminal, a second input terminal and a first output terminal, respectively coupled to the follow bit line, the subsequent node and a first node; the pulse width controller generates the enable signal at a third node, and when the memory module reads data, the voltage of the third node is controlled by the voltage of the first node.
5. The memory module as described in claim 4, wherein, The pulse width controller further includes a first inverter coupled between the follow bit line and the first input.
6. The memory module as claimed in claim 4, wherein the first logic gate is an inverse gate.
7. The memory module as described in claim 4, wherein, The pulse width controller further includes a third logic gate and a delay circuit; the third logic gate includes a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal is coupled to a second node, the delay circuit is coupled between the second node and the sixth input terminal, and the third output terminal is coupled to the third node; when the memory module reads data, the voltage of the second node is controlled by the voltage of the first node.
8. The memory module as described in claim 7, wherein, The pulse width controller further includes a third inverter coupled between the third output and the third node.
9. The memory module as described in claim 7, wherein, The first logic gate and the delay circuit are powered by a first supply voltage and a second supply voltage, respectively, and the first supply voltage and the second supply voltage are different.
10. The memory module as described in claim 9, wherein, At least a portion of each of the sensing amplifiers is powered by the second supply voltage.
11. The memory module as described in claim 7, wherein, The pulse width controller further includes a second logic gate; the second logic gate includes a third input terminal, a fourth input terminal and a second output terminal, which are respectively coupled to the first node, the fourth node and the second node.
12. The memory module as described in claim 11, wherein, The pulse width controller further includes a fourth logic gate; the fourth logic gate includes a seventh input terminal, an eighth input terminal and a fourth output terminal, which are respectively coupled to a first indication signal, a second indication signal and the fourth node.
13. The memory module as described in claim 12, wherein, The second, third, and fourth logic gates are all inverse OR gates.
14. The memory module as described in claim 1 further includes a finite state machine circuit coupled between the pulse width controller and the previous node; wherein, When the pulse width controller changes the voltage of the preceding node, it causes the finite state machine circuit to change the voltage of the preceding node.
15. The memory module as described in claim 14, wherein, The finite state machine circuit includes a fifth node and a sixth node; the fifth node is coupled to the first node, and the sixth node is coupled to the previous node.
16. The memory module as described in claim 15, wherein, The finite state machine circuit further includes a seventh node coupled to a clock.
17. The memory module as described in claim 14 further includes a second inverter coupled between the sixth node and the previous node.
18. A memory module with improved sensing amplification timing adaptability, comprising: at least one bit line, at least one word line, a following bit line, and a following word line; the following word line extends from a preceding node to a following node, and the length from the preceding node to the following node is positively correlated with the length of each word line; at least one memory cell, each memory cell being coupled to one of the at least one bit line and one of the at least one word line; at least one following cell being coupled to the following bit line; at least one sensing amplifier, each sensing amplifier being coupled to one of the at least one bit line and further coupled to a third node; each sensing amplifier being timed disabled when the voltage of the third node is a first bit and timed enabled when the voltage of the third node is a second bit; and a first logic gate, comprising a first input terminal, a second input terminal, and a first output terminal, respectively coupled to the following bit line, the following node, and the preceding node; wherein: When the memory module reads data, the voltage of the third node is controlled by the voltage of the first output terminal.
19. The memory module as described in claim 18 further includes a third logic gate and a delay circuit; wherein, The third logic gate includes a fifth input, a sixth input, and a third output; the fifth input is coupled to a second node, the delay circuit is coupled between the second node and the sixth input, the third output is coupled to the third node, and the second node is coupled to the first output.
20. The memory module as described in claim 19, wherein, The first logic gate and the delay circuit are powered by two different phase supply voltages, respectively.