Semiconductor device and fabrication method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-06-22
- Publication Date
- 2023-10-16
Smart Images
Figure TWG2TA000928600_001 
Figure TWG2TA000928600_002 
Figure TWG2TA000928600_003
Abstract
Description
[Technical Field]
[0001] This disclosure relates to semiconductor technology, and in particular to a semiconductor device comprising a trench power transistor and a method for manufacturing the same. [Previous Technology]
[0002] Power transistors are commonly used in power electronics technology. Power MOSFETs are the most commonly used components in power conversion systems. They include horizontal structures, such as laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs), and vertical structures, such as planar gate MOSFETs and trench gate MOSFETs. Trench gate MOSFETs have the gate located in a trench. Compared with planar gate MOSFETs, trench gate MOSFETs have advantages such as smaller component size and lower parasitic capacitance. However, in terms of on-state resistance (Ron) and breakdown voltage, traditional trench gate MOSFETs still cannot fully meet the various requirements of power electronics applications. [Summary of the Invention]
[0003] In view of this, the present disclosure proposes a semiconductor device including a trench power transistor and a method for manufacturing the same, to meet the various requirements of trench power transistors in power electronics applications, such as reducing on-resistance, reducing unit spreading resistance (Rsp), increasing or maintaining breakdown voltage, etc., so as to meet the needs of high current, low voltage components and make them more efficient in the application of power management systems (BMS).
[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a well region, a trench, a first trench gate, a second trench gate, a dielectric separator, and a dielectric liner. The substrate has a first conductivity type, the well region has a first conductivity type and is disposed within the substrate, and the trench is disposed within the substrate and located directly above the well region. The first trench gate and the second trench gate are laterally separated from each other and are disposed within the trench. The dielectric separator is disposed within the trench and located between the first trench gate and the second trench gate, wherein the centerline region of the bottom surface of the dielectric separator protrudes downward and is lower than the side regions of the bottom surface of the dielectric separator. The dielectric liner is disposed within the trench and located below the bottom surfaces of the first trench gate and the second trench gate, wherein the thickness of the dielectric separator is greater than the thickness of the dielectric liner below the horizontal line of the bottom surfaces of the first trench gate and the second trench gate.
[0005] According to one embodiment of this disclosure, a semiconductor device is provided, including a substrate, a well region, a trench, a first trench gate, a second trench gate, a dielectric separator, a first doped region, and a second doped region. The substrate has a first conductivity type, the well region has a first conductivity type and is disposed within the substrate, and the trench is disposed within the substrate and located directly above the well region. The first trench gate and the second trench gate are laterally separated from each other and are disposed within the trench. The dielectric separator is disposed within the trench and is located between the first trench gate and the second trench gate. The first doped region and the second doped region have a first conductivity type, are laterally separated from each other, and are disposed within the substrate, wherein the first doped region and the second doped region are located on opposite sides of the well region, and the doping concentration of the well region is higher than the doping concentration of the first doped region and the second doped region, respectively.
[0006] According to one embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a well region, a trench, a first trench gate, a second trench gate, and a dielectric separator. The substrate has a first conductivity type, the well region has a first conductivity type and is disposed within the substrate, and the trench is disposed within the substrate and located directly above the well region. The first trench gate and the second trench gate are laterally separated from each other and are disposed within the trench, the dielectric separator is disposed within the trench, and the space between the first trench gate and the second trench gate is filled by the dielectric separator.
[0007] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a substrate having a first conductivity type; forming a trench within the substrate; orientedly forming a dielectric liner on the sidewalls and bottom surface of the trench; forming a first trench gate and a second trench gate laterally separated from each other within the trench, and exposing a portion of the dielectric liner located on the bottom surface of the trench; forming a well region within the substrate, wherein the well region is located directly below the region between the first trench gate and the second trench gate; performing a thermal oxidation process to form an oxide layer within the trench; and filling the trench with a dielectric material layer, wherein the dielectric material layer and the oxide layer constitute a dielectric separator, the dielectric separator being located between the first trench gate and the second trench gate, and the bottom centerline region of the dielectric separator protruding downward below the regions on both sides of the bottom surface of the dielectric separator.
Implementation Method
[0009] This disclosure provides several different embodiments that can be used to implement different features of this disclosure. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature is formed on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.
[0010] Furthermore, regarding the spatially related descriptive terms mentioned in this disclosure, such as "below," "low," "down," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the diagram. In addition to the orientation shown in the diagram, these spatially related terms are also used to describe the possible orientation of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation of 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.
[0011] Although this disclosure uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.
[0012] The terms "about" or "substantially" used in this disclosure generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" may be implied even without specific description of "about" or "substantially".
[0013] The terms “coupled,” “coupled,” and “electrically connected” used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.
[0014] Although the invention disclosed herein is described below by way of specific embodiments, the inventive principles of this invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details have been omitted, and these omitted details are within the knowledge scope of those skilled in the art.
[0015] This disclosure relates to a semiconductor device including a trench-type gate power transistor, wherein two trench gates, laterally separated from each other, are disposed within a trench of a repeating cell. A dielectric separator is disposed between the two trench gates, and a well region is disposed directly below the trench. The doping concentration of the well region is higher than that of the doped regions on both sides of the well region, and the bottom of the substrate also has a higher doping concentration than the well region. The embodiments of this disclosure utilize the well region with higher doping concentration and the bottom of the substrate together as a common drain region. By disposing of two trench gates within the trench, the source-to-source on-resistance and unit resistance of the semiconductor device are reduced. This is beneficial for high-current (maximum current density, for example, 5.0E-2A / cm² to 1.0A / cm²) and low-voltage (source-to-source voltage, for example, 12-30V) devices, enabling the semiconductor device of this disclosure to be efficiently applied in a power management system (BMS).
[0016] Figure 1 is a schematic cross-sectional view of a repeating cell of a semiconductor device according to an embodiment of the present disclosure. As shown in Figure 1, in one embodiment, the semiconductor device 100 includes a substrate 101 having a first conductivity type and including a bottom 102 of the substrate and an epitaxial layer 107 disposed above the bottom 102 of the substrate. The bottom 102 of the substrate is a heavily doped substrate of the first conductivity type, such as an n-type heavily doped substrate (N+substrate). An epitaxial layer 107 is formed on the bottom 102 of the substrate. The epitaxial layer 107 has a first conductivity type, such as an n-type silicon epitaxial layer. A well region 103 and a first doped region 107-1 and a second doped region 107-2 located on both sides of the well region 103 are formed in the epitaxial layer 107. The first doped region 107-1 and the second doped region 107-2 are laterally separated from each other and are disposed in the epitaxial layer 107 of the substrate 101. The well region 103, the first doped region 107-1, and the second doped region 107-2 all have a first conductivity type. The doping concentration of the well region 103 is higher than the doping concentration of the first doped region 107-1 and the second doped region 107-2, while the doping concentration of the bottom 102 of the substrate is higher than the doping concentration of the well region 103. According to the embodiment disclosed herein, the bottom 102 of the substrate and the well region 103 can together serve as a common drain region 110. The drain electrode 105 of the semiconductor device 100 is disposed on the bottom surface of the substrate 101, located below the bottom 102 of the substrate. In one embodiment, the first doped region 107-1 and the second doped region 107-2 have the same doping concentration, for example, the doping concentration of the epitaxial layer on the bottom 102 of the substrate. The doping concentration of the well region 103 is higher than this same doping concentration of the first doped region 107-1 and the second doped region 107-2. Alternatively, in one embodiment, the doping concentration of the bottom 102 of the substrate can gradually decrease from the bottom surface of the substrate 101 towards the well region 103; that is, the doping concentration of the bottom 102 of the substrate can be a gradient.
[0017] Furthermore, the semiconductor device 100 also includes a trench 114 disposed in the epitaxial layer 107 of the substrate 101, and the trench 114 is located directly above the well region 103. According to an embodiment of the present disclosure, a first trench gate 115-1 and a second trench gate 115-2, which are laterally separated from each other, are disposed in the trench 114, and a dielectric separator 117 is also disposed in the trench 114, which is located between the first trench gate 115-1 and the second trench gate 115-2. According to one embodiment of the present disclosure, the space between the first trench gate 115-1 and the second trench gate 115-2 is filled by the dielectric separator 117, that is, there are no other components in the dielectric separator 117 between the first trench gate 115-1 and the second trench gate 115-2, such as no other gate electrodes or field plates. In some embodiments, as shown in Figure 1, the upper end of the first trench gate 115-1 has a first rounded apex angle 115-1C adjacent to the dielectric separator 117, and the upper end of the second trench gate 115-2 has a second rounded apex angle 115-2C adjacent to the dielectric separator 117. Please refer to the enlarged view of a partial region E in Figure 1, where the bottom centerline region 117B1 of the dielectric separator 117 protrudes downwards and is lower than the bottom side regions 117B2 of the dielectric separator. Additionally, a dielectric liner 118 is provided within the trench 114, lining the sidewalls and bottom surface of the trench 114, and located below the bottom surfaces of the first trench gate 115-1 and the second trench gate 115-2. The dielectric liner 118 includes a first dielectric liner 118-1 disposed on the outer side and below the bottom surface of the first trench gate 115-1, and a second dielectric liner 118-2 disposed on the outer side and below the bottom surface of the second trench gate 115-2. As shown in the enlarged view of a partial area E in Figure 1, according to the embodiment disclosed herein, below the horizontal line P that aligns with the lowest bottom surfaces of the first trench gate 115-1 and the second trench gate 115-2, the thickness T1 of the dielectric separator 117 is greater than the respective thickness T2 of the first dielectric liner 118-1 and the second dielectric liner 118-2.
[0018] According to the embodiments disclosed herein, since the doping concentration of the bottom 102 of the substrate and the doping concentration of the well region 103 are both higher than the doping concentrations of the first doped region 107-1 and the second doped region 107-2, and the well region 103 is adjacent to the bottom surface of the trench 114, the on-resistance of the semiconductor device 100 can be reduced. In addition, since the bottom centerline region 117B1 of the dielectric separator 117 protrudes downward and has a larger thickness T1, current breakdown between the well region 103 and the trench gate (e.g., the first trench gate 115-1 and / or the second trench gate 115-2) can be avoided, thereby improving the withstand voltage capability of the semiconductor device 100.
[0019] Referring again to Figure 1, in one embodiment, the semiconductor device 100 further includes a first substrate region 109-1 and a second substrate region 109-2 disposed in the substrate 101. The first substrate region 109-1 and the second substrate region 109-2 have a second conductivity type opposite to the aforementioned first conductivity type, such as a p-type substrate region (p-body). The first substrate region 109-1 and the second substrate region 109-2 are respectively disposed directly above the first doped region 107-1 and the second doped region 107-2, and are located on both sides of the trench 114. In addition, the semiconductor device 100 also includes a first source region 111-1 and a second source region 111-2, respectively adjacent to the first substrate region 109-1 and the second substrate region 109-2. The first source region 111-1 and the second source region 111-2 have a first conductivity type, such as an n-type heavily doped region. The semiconductor device 100 further includes an interlayer dielectric layer 119 covering the epitaxial layer 107 of the substrate 101, and the interlayer dielectric layer 119 covering the first source region 111-1, the second source region 112-1, the dielectric separator 117, and other components formed in the epitaxial layer 107. The first source electrode 113-1 and the second source electrode 113-2 penetrate the interlayer dielectric layer 119 and extend into the first substrate region 109-1 and the second substrate region 109-2, respectively. The first source region 111-1 is adjacent to the first source electrode 113-1, and the second source region 112-1 is adjacent to the second source electrode 113-1.
[0020] As shown in Figure 1, in some embodiments, the well region 103 of the semiconductor device 100 is laterally separated from the first substrate region 109-1 and the second substrate region 109-2, and the top surface of the well region 103 is lower than the lowest bottom surface of the first substrate region 109-1 and the second substrate region 109-2. Furthermore, the lowest bottom surface of each of the first substrate region 109-1 and the second substrate region 109-2 is higher than the bottom surface of the trench 114. According to some embodiments disclosed herein, the first substrate region 109-1 and the second substrate region 109-2 may each have a first inclined bottom surface 109-1B and a second inclined bottom surface 109-2B. The first inclined bottom surface 109-1B and the second inclined bottom surface 109-2B may be multi-step bottom surfaces or multi-arc bottom surfaces. The first inclined bottom surface 109-1B is higher at the first source region 111-1 and lower at the first source electrode 113-1. The second inclined bottom surface 109-2B is higher at the second source region 111-2 and lower at the second source electrode 113-2.
[0021] According to the embodiments disclosed herein, the first substrate region 109-1 located directly below the first source electrode 113-1 may have a high doping concentration, and the second substrate region 109-2 located directly below the second source electrode 113-2 may also have a high doping concentration, thereby preventing current from directly penetrating from the first doped region 107-1 and the second doped region 107-2 to the bottom of the first source electrode 113-1 and the second source electrode 113-2.
[0022] Figure 2 is a schematic cross-sectional view and an enlarged view of a repeating unit of a semiconductor device according to an embodiment of the present disclosure, used to illustrate the dimensions of the components of the semiconductor device. As shown in Figure 2, in some embodiments, the width W1 of the top surface of the trench 114 of the semiconductor device 100, which is also the width of the top surface of the dielectric separator 117, in the lateral direction (e.g., the X-axis direction) can be from about 425 nanometers (nm) to about 475 nm, for example, about 455 nm. The depth H1 of the dielectric separator 117 can be from about 500 nanometers (nm) to about 650 nm, for example, about 570 nm. The width W2 of most of the region and bottom surface of the dielectric separator 117 can be from about 135 nanometers (nm) to about 175 nm, for example, about 150 nm. The width W3 of most regions of the first trench gate 115-1 and the second trench gate 115-2 can be substantially the same, ranging from approximately 100 nanometers (nm) to approximately 130 nm, for example, approximately 125 nm. The width W4 of the first source region 111-1 and the second source region 111-2 between the first source electrode 113-1, the second source electrode 113-2, and the trench 114 can be substantially the same, ranging from approximately 75 nanometers (nm) to approximately 125 nm, for example, approximately 100 nm. In a repeating cell, the width W5 of the first source electrode 113-1 and the second source electrode 113-2 can be substantially the same, ranging from approximately 50 nanometers (nm) to approximately 100 nm, for example, approximately 75 nm. The width W6 of the drain electrode 105 can be from approximately 700 nanometers (nm) to approximately 900 nm, for example, approximately 800 nm. The depth H2 of the substrate 101 (including the bottom 102 of the substrate and the epitaxial layer 107 thereon), that is, the distance from the top surface of the first source region 111-1 and the second source region 111-2 to the bottom surface of the bottom 102 of the substrate, can be from about 900 nanometers (nm) to about 1100 nm, for example, about 1000 nm. The depth H3 of the first source electrode 113-1 and the second source electrode 113-2 extending into the first substrate region 109-1 and the second substrate region 109-2, that is, the distance from the top surface of the first source region 111-1 and the second source region 111-2 to the bottom surface of the first source electrode 113-1 and the second source electrode 113-2, can be from about 100 nanometers (nm) to about 200 nm, for example, about 150 nm. The above dimensions are for illustrative purposes only and are not limited thereto. The dimensions of the above components can be adjusted according to the actual electrical requirements of the semiconductor device 100. Furthermore, according to the embodiments disclosed herein, the width W1 of the top surface of the dielectric separator 117 of the semiconductor device 100 is greater than the width W2 of the bottom surface of the dielectric separator 117.In addition, the maximum width of the first trench gate 115-1 (e.g., width W3) and the maximum width of the second trench gate 115-2 (e.g., width W3) are both smaller than the minimum width of the dielectric separator 117 (e.g., width W2).
[0023] Referring again to Figure 2, which also shows an enlarged view of a partial region F, the dielectric separator 117 and the adjacent dielectric liner 118 can form a bird's beak structure. The thickness T4 of the portion of the dielectric liner 118 adjacent to the dielectric separator 117 is greater than the thickness T3 of the portion of the dielectric liner 118 away from the dielectric separator 117. In some embodiments, the thickness T4 can be from about 300 angstroms (Å) to about 400 Å, for example, about 350 Å, and the thickness T3 can be from about 200 angstroms (Å) to about 300 Å, for example, about 250 Å. In addition, below the horizontal line L that aligns with the lowest bottom surface of the dielectric liner 118, that is, below the downward protruding portion of the dielectric separator 117, the thickness T5 can be from about 100 angstroms (Å) to about 200 Å, for example, about 150 Å. The thickness values above are for illustrative purposes only, but are not limited to these values. The thickness values can be adjusted according to the actual electrical requirements of the semiconductor device 100.
[0024] Figures 3, 4, and 5 are schematic cross-sectional views illustrating various stages of a semiconductor device manufacturing method according to an embodiment of the present disclosure. First, referring to Figure 3, a substrate 101 is provided, including a bottom 102 of the substrate and an epitaxial layer 107 formed on the bottom 102 of the substrate. In one embodiment, the bottom 102 of the substrate is a heavily doped substrate of a first conductivity type, such as an n-type heavily doped silicon substrate (N+Si substrate), and the epitaxial layer 107 is a silicon epitaxial layer of the first conductivity type. The doping concentration of the epitaxial layer 107 is lower than the doping concentration of the bottom 102 of the substrate. For example, the highest doping concentration of the bottom 102 of the substrate is approximately 6E19 cm⁻³, and the doping concentration of the epitaxial layer 107 is approximately 7E16 cm⁻³, but this is not limited to these. According to the embodiment of the present disclosure, the bottom 102 of the substrate and the epitaxial layer 107 may be composed of the same semiconductor material, such as silicon epitaxial layers. Next, a patterned hard mask 120 is formed on the top surface of the substrate 101. The patterned hard mask 120 can be formed by photolithography and etching processes, such that the openings of the patterned hard mask 120 correspond to the predetermined areas for the subsequent formation of trenches. Then, in step S301, the substrate 101 is etched to form trenches 114 in the epitaxial layer 107. Next, in step S303, a dielectric substrate 118 is conventionally formed on the sidewalls and bottom surface of the trenches 114, and on the top surface and sidewalls of the patterned hard mask 120. In some embodiments, the dielectric substrate 118 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant. The dielectric substrate 118 can be formed by thermal oxidation, chemical vapor deposition (CVD), or physical vapor deposition (PVD). The thickness of the dielectric substrate 118 can be from about 200 Å to about 350 Å, but is not limited thereto.
[0025] Then, referring to Figure 4, in step S305, a first trench gate 115-1 and a second trench gate 115-2 that are laterally separated from each other are formed in the trench 114. According to the embodiments disclosed herein, a conductive material layer can be deposited oriented on the dielectric substrate 118 within the trench 114 and on the patterned hard mask 120. The conductive material layer can be polysilicon, doped polysilicon, metal silicide, metal, alloy, or other suitable conductive material. Then, an anisotropic etching process is used to remove the horizontal portion of the conductive material layer, for example, removing the conductive material layer on the bottom surface of the trench 114 and the top surface of the patterned hard mask 120, leaving the vertical portion of the conductive material layer in the trench 114 to form the first trench gate 115-1 and the second trench gate 115-2, exposing a portion of the dielectric substrate 118 located on the bottom surface of the trench 114. The first trench gate 115-1 and the second trench gate 115-2 formed by the anisotropic etching process each have rounded apex angles 115-1C and 115-2C on their respective inner sides. Next, in step S307, an ion implantation process is performed on the epitaxial layer 107 through the opening between the first trench gate 115-1 and the second trench gate 115-2, implanting ions of a first conductivity type to form a well region 103, such as an n-type heavily doped region (N+ region), so that the well region 103 is located directly below the region between the first trench gate 115-1 and the second trench gate 115-2. Since the first trench gate 115-1 and the second trench gate 115-2 can serve as a mask for the ion implantation process, the width of the well region 103 can be approximately equal to the width of the region between the first trench gate 115-1 and the second trench gate 115-2.
[0026] Then, referring to Figure 4, in step S309, a thermal oxidation process is performed to form an oxide layer 104 in the trench 114. At this time, the exposed surfaces of the first trench gate 115-1 and the second trench gate 115-2 will be oxidized, so that the width of the first trench gate 115-1 and the second trench gate 115-2 is slightly reduced compared to the initial width formed when step S305 is completed. And this thermal oxidation process can also be used to oxidize part of the top surface of the well region 103, while the first trench gate 115... In the region below the opening between the first trench gate 115-1 and the second trench gate 115-2, an oxide layer 104 is formed that protrudes downwards from the initial bottom surface of the trench 114. This increases the thickness of the dielectric portion in the middle region of the bottom surface of the trench 114, for example, by adding the initial thickness of the dielectric substrate 118 to the thickness of the oxide layer 104. Simultaneously, the width of the well region 103 can also be widened by this thermal oxidation process; for example, the width of the well region 103 can be greater than the width of the region between the first trench gate 115-1 and the second trench gate 115-2. Furthermore, the epitaxial layers 107 located on both sides of the well region 103 respectively constitute the first doped region 107-1 and the second doped region 107-2 as shown in Figure 1. In some embodiments, the bottom 102 of the substrate, the epitaxial layer 107, and the well region 103 are all of the first conductivity type, and the doping concentration of the bottom 102 of the substrate can gradually decrease in the direction from the bottom surface to the top surface. The doping concentration of the epitaxial layer 107 is lower than the lowest doping concentration of the bottom 102 of the substrate, that is, the doping concentration of the substrate 101 gradually decreases in the direction from the bottom to the top surface. The epitaxial layer 107 with a lower doping concentration near the top surface of the substrate 101 constitutes the first doped region 107-1 and the second doped region 107-2, while the well region 103 is a heavily doped region. Therefore, the doping concentration of the well region 103 is higher than the doping concentration of the first doped region 107-1 and the second doped region 107-2.
[0027] Then, referring to Figure 5, in step S311, a dielectric material layer 106 is filled in the trench 114, and the dielectric material layer 106 is also deposited on the top surface of the patterned hard mask 120. Next, in step S313, a chemical mechanical planarization (CMP) process or an etching back process is performed to remove the patterned hard mask 120 and part of the dielectric material layer 106, so that the top surface of the oxide layer 104 and the dielectric material layer 106 in the trench 114 is flush with the top surface of the epitaxial layer 107 of the substrate 101. The oxide layer 104 and the dielectric material layer 106 remaining in the trench 114 constitute a dielectric separator 117. The dielectric separator 117 is located between the first trench gate 115-1 and the second trench gate 115-2, and the bottom center line region 117B1 of the dielectric separator 117 protrudes downward, lower than the two side regions 117B2 of the bottom surface of the dielectric separator 117 (see Figure 1).
[0028] Referring again to Figure 5, in step S315, a first substrate region 109-1 and a second substrate region 109-2 are formed in the epitaxial layer 107 of the substrate 101. A multi-channel ion implantation process with different implantation energies, different ion beam densities, and the same conductivity type can be used to implant ions of the second conductivity type into the epitaxial layer 107, so that the first substrate region 109-1 and the second substrate region 109-2 are formed simultaneously on both sides of the trench 114, and the first substrate region 109-1 and the second substrate region 109-2 each have a multi-step bottom surface or a multi-arc bottom surface. Then, ions of the first conductivity type are implanted into the first substrate region 109-1 and the second substrate region 109-2 to form a first source region 111-1 and a second source region 111-2, which are adjacent to and directly above the first substrate region 109-1 and the second substrate region 109-2, respectively. Next, an interlayer dielectric layer 119 is deposited above the substrate 101, and openings 122 for the first source electrode and the second source electrode are formed in the interlayer dielectric layer 119 using photolithography and etching processes. The openings 122 penetrate the interlayer dielectric layer 119 and the first source region 111-1, or the interlayer dielectric layer 119 and the second source region 111-2, and extend downward into the first substrate region 109-1 and the second substrate region 109-2, reaching a certain depth position in the first substrate region 109-1 and the second substrate region 109-2. Subsequently, an ion implantation process of the second conductivity type is performed through the opening 122 to form heavily doped regions 112-1 and 112-2, for example, p-type heavily doped regions (P+ regions), in the first substrate region 109-1 and the second substrate region 109-2, respectively. Then, metal material is filled into the opening 122 to form the first source electrode 113-1 and the second source electrode 113-2 as shown in Figure 1, thus completing the semiconductor device 100.
[0029] Figure 6 is a perspective view of four consecutive repeating units of a semiconductor device according to an embodiment of the present disclosure. As shown in Figure 6, the four consecutive repeating units 100U of the semiconductor device are arranged along a transverse direction (e.g., the X-axis direction). The long axis of the first source region 111-1 of the semiconductor device extends substantially along a longitudinal direction (e.g., the Y-axis direction) and is located on both sides of the bottom of the first source electrode 113-1. The long axis of the second source region 111-2 also extends substantially along a longitudinal direction (e.g., the Y-axis direction) and is located on both sides of the bottom of the second source electrode 113-2. The long axes of the first source electrode 113-1 and the second source electrode 113-2 also extend substantially along a longitudinal direction (e.g., the Y-axis direction).
[0030] Figure 7 is a schematic diagram of the voltage equipotential line distribution in a local area of a semiconductor device when the switch is turned on, according to an embodiment of the present disclosure. In Figure 7, VSS is the turn-on voltage, for example, 0.1 volts (V). As shown in Figure 7, according to the embodiment of the present disclosure, when the semiconductor device 100 is turned on, the well region 103 of the semiconductor device and the bottom 102 of the substrate have a good barrier effect, so that the first source region 111-1 still maintains a higher voltage, thereby improving the on-resistance of the semiconductor device 100, reducing the channel region resistance by about 50%, and achieving the effect of reducing the unit resistance (Rsp) of the semiconductor device, which is beneficial for the application of high-current, low-voltage components.
[0031] Figure 8 is a schematic diagram illustrating the current intensity distribution in a local area of a semiconductor device when the switch is turned on, according to an embodiment of the present disclosure. As shown in Figure 8, according to the embodiment of the present disclosure, when the semiconductor device 100 is turned on, the current path 801 flows downward from the first source region 111-1 along the side of the first trench gate 115-1, and flows along the bottom of the first trench gate 115-1 to the bottom of the second trench gate 115-2, and then flows upward along the side of the second trench gate 115-2 to the second source region 111-2. The channel region along the entire periphery of the trench has a higher current intensity, proving that the semiconductor device 100 of the embodiment of the present disclosure can effectively reduce the on-resistance, which is beneficial for the application of high-current, low-voltage components.
[0032] Figure 9 is a schematic diagram illustrating the on-resistance distribution of a semiconductor device according to an embodiment of the present disclosure. As shown in Figure 9, in one embodiment, the source-to-source on-resistance (Rss) of the semiconductor device 100 is composed of the resistance 113-1R of the first source electrode 113-1, the channel resistance 109-1R along the periphery of the first trench gate 115-1, the resistance 101R of the epitaxial layer 107, the channel resistance 109-2R along the periphery of the second trench gate 115-2, and the resistance 113-2R of the second source electrode 113-2. Because the semiconductor device 100 disclosed herein has a first trench gate 115-1 and a second trench gate 115-2 disposed in the same trench, the cell pitch of the semiconductor device 100 disclosed herein can be reduced to approximately 80% compared to the cell pitch of a conventional single trench gate structure, thereby reducing the channel resistances 109-1R and 109-2R of the semiconductor device disclosed herein to approximately 80%. Furthermore, as shown in Figure 1, because the dielectric separator 117 of the semiconductor device 100 disclosed herein has a bottom centerline region 117B1 that protrudes downwards from the bottom side regions 117B2, i.e., the dielectric separator 117 has a thicker bottom, and a heavily doped well region 103 of a first conductivity type is located directly below the dielectric separator 117, the resistance 101R of the epitaxial layer 107 of the semiconductor device disclosed herein can be reduced to approximately 55% compared to a conventional single trench gate structure MOS device. Furthermore, since the source electrodes 113-1 and 113-2 on the top surface of the semiconductor device disclosed herein can form a common source layout using a redistribution layer (RDL), the carrier substrate can be omitted, thus eliminating the carrier substrate resistance of the semiconductor device disclosed herein. Therefore, compared to traditional MOS devices with a single trench gate structure, the semiconductor device disclosed herein can significantly reduce the source-to-source on-resistance, thereby reducing the unit resistance (Rsp) of the semiconductor device, and can also maintain a certain breakdown voltage. This is beneficial for the application of high-current, low-voltage devices and can improve the efficiency of power management systems. The above description is only a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. [Simplified Explanation of the Diagram]
[0008] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed textual descriptions while reading this disclosure. The specific embodiments described herein, along with the corresponding drawings, are explained in detail to illustrate the working principles of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 is a cross-sectional schematic diagram and an enlarged view of a repeating unit of a semiconductor device according to an embodiment of this disclosure. Figure 2 is a cross-sectional schematic diagram and an enlarged view of a repeating unit of a semiconductor device according to an embodiment of this disclosure, used to indicate the dimensions of the components of the semiconductor device. Figures 3, 4, and 5 are cross-sectional schematic diagrams of various stages of a semiconductor device manufacturing method according to an embodiment of this disclosure. Figure 6 is a perspective view of four consecutive repeating units of a semiconductor device according to an embodiment of this disclosure. Figure 7 is a schematic diagram of the voltage equipotential line distribution in a local area of a semiconductor device when the switch is turned on, according to an embodiment of the present disclosure. Figure 8 is a schematic diagram of the current intensity distribution in a local area of a semiconductor device when the switch is turned on, according to an embodiment of the present disclosure. Figure 9 is a schematic diagram of the on-resistance distribution of a semiconductor device according to an embodiment of the present disclosure.
Claims
1. A semiconductor device, comprising: A substrate having a first type of conductivity; A well region, having the first conductivity type, is disposed within the substrate; A trench is disposed within the substrate and located directly above the well area; a first trench gate and a second trench gate are laterally separated from each other and disposed within the trench; a dielectric separator is disposed within the trench and located between the first trench gate and the second trench gate, wherein the center line region of the bottom surface of the dielectric separator protrudes downward and is lower than the two sides of the bottom surface of the dielectric separator; and a dielectric liner is disposed within the trench and located below the bottom surfaces of the first trench gate and the second trench gate, wherein the thickness of the dielectric separator is greater than the thickness of the dielectric liner below the horizontal line of the bottom surfaces of the first trench gate and the second trench gate.
2. The semiconductor device as described in claim 1, further comprising: A first doped region and a second doped region, having the first conductivity type, are laterally separated from each other and disposed within the substrate, wherein the first doped region and the second doped region are located on opposite sides of the well region.
3. The semiconductor device as claimed in claim 2, wherein the first doped region and the second doped region have the same doping concentration, and the well region has a higher doping concentration than the same doping concentration.
4. The semiconductor device as described in claim 2, further comprising: A first substrate region and a second substrate region, having a second conductivity type opposite to the first conductivity type, are respectively disposed directly above the first doped region and the second doped region, and located on both sides of the trench.
5. The semiconductor device as claimed in claim 4, wherein the well region is laterally separated from the first substrate region and the second substrate region, and the top surface of the well region is lower than the bottom surface of the first substrate region and the second substrate region.
6. The semiconductor device as described in claim 4, further comprising: A first source region and a second source region, having the first conductivity type, are respectively adjacent to the first substrate region and the second substrate region; It also includes a first source electrode and a second source electrode, which extend into the first substrate region and the second substrate region, respectively. The first source region is adjacent to the first source electrode, and the second source region is adjacent to the second source electrode.
7. The semiconductor device as claimed in claim 6, wherein the first source region extends on both sides of the bottom of the first source electrode, and the second source region extends on both sides of the bottom of the second source electrode.
8. The semiconductor device as claimed in claim 6, wherein the first substrate region and the second substrate region each have a first inclined bottom surface and a second inclined bottom surface, the first inclined bottom surface being higher at the location corresponding to the first source region and lower at the location corresponding to the first source electrode, and the second inclined bottom surface being higher at the location corresponding to the second source region and lower at the location corresponding to the second source electrode.
9. The semiconductor device as claimed in claim 8, wherein the first inclined bottom surface and the second inclined bottom surface are a multi-step bottom surface or a multi-arc bottom surface.
10. The semiconductor device as claimed in claim 4, wherein the lowest bottom surfaces of the first substrate region and the second substrate region are higher than the bottom surface of the trench.
11. The semiconductor device of claim 1, wherein the dielectric liner is lining the sidewalls and bottom surface of the trench, and the thickness of the portion of the dielectric liner adjacent to the dielectric separator is greater than the thickness of the portion of the dielectric liner away from the dielectric separator.
12. The semiconductor device as claimed in claim 1, wherein the width of the top surface of the dielectric separator is greater than the width of the bottom surface of the dielectric separator.
13. The semiconductor device as claimed in claim 1, wherein the maximum width of the first trench gate and the maximum width of the second trench gate are both less than the minimum width of the dielectric separator.
14. The semiconductor device as claimed in claim 1, wherein the first trench gate electrode has a first rounded apex adjacent to the dielectric separator, and the second trench gate electrode has a second rounded apex adjacent to the dielectric separator.
15. A semiconductor device, comprising: A substrate having a first type of conductivity; A well region, having the first conductivity type, is disposed within the substrate; A trench is disposed within the substrate and located directly above the well region; a first trench gate and a second trench gate are laterally separated from each other and disposed within the trench; a dielectric separator is disposed within the trench and located between the first trench gate and the second trench gate; and a first doped region and a second doped region, having the first conductivity type, are laterally separated from each other and disposed within the substrate, wherein the first doped region and the second doped region are located on opposite sides of the well region, and the doping concentration of the well region is higher than the respective doping concentrations of the first doped region and the second doped region.
16. A semiconductor device, comprising: A substrate having a first type of conductivity; A well region, having the first conductivity type, is disposed within the substrate; A trench is disposed within the substrate and located directly above the well area; a first trench gate and a second trench gate are laterally separated from each other and disposed within the trench; and a dielectric separator is disposed within the trench, and the space between the first trench gate and the second trench gate is filled by the dielectric separator.
17. The semiconductor device of claim 16 further includes a first doped region and a second doped region having the first conductivity type, laterally separated from each other and disposed within the substrate, wherein the first doped region and the second doped region are located on opposite sides of the well region, and the doping concentration of the well region is higher than the doping concentration of the first doped region and the second doped region, respectively.
18. The semiconductor device as claimed in claim 15 or 17 further includes a first substrate region and a second substrate region having a second conductivity type opposite to the first conductivity type, respectively disposed directly above the first doped region and the second doped region and located on both sides of the trench, wherein the top surface of the well region is lower than the bottom surface of the first substrate region and the second substrate region.
19. The semiconductor device as described in claim 18, further comprising: A first source region and a second source region, having the first conductivity type, are respectively adjacent to the first substrate region and the second substrate region; It also includes a first source electrode and a second source electrode, which extend into the first substrate region and the second substrate region, respectively. The first source electrode region is located on both sides of the first source electrode, and the second source electrode region is located on both sides of the second source electrode.
20. A semiconductor device as claimed in any one of claims 1, 15 and 16, wherein the doping concentration at the bottom of the substrate is higher than the doping concentration at the well region, and the bottom of the substrate and the well region together serve as a common drain region.
21. The semiconductor device as claimed in claim 15 or 16 further includes a dielectric liner lining the sidewalls and bottom surface of the trench, and located below the bottom surfaces of the first trench gate and the second trench gate, wherein the thickness of the portion of the dielectric liner adjacent to the dielectric separator is greater than the thickness of the portion of the dielectric liner away from the dielectric separator.
22. A method for manufacturing a semiconductor device, comprising: A substrate is provided having a first conductivity type; A trench is formed within the substrate; A dielectric liner is formed oriented in the direction of the trench sidewalls and bottom surface; a first trench gate and a second trench gate are formed in the trench, laterally separated from each other, and a portion of the dielectric liner located on the bottom surface of the trench is exposed; a well region is formed in the substrate, wherein the well region is located directly below the region between the first trench gate and the second trench gate; a thermal oxidation process is performed to form an oxide layer in the trench; and a dielectric material layer is filled in the trench, wherein the dielectric material layer and the oxide layer constitute a dielectric separator, the dielectric separator being located between the first trench gate and the second trench gate, and the bottom centerline region of the dielectric separator protrudes downward below the regions on both sides of the bottom surface of the dielectric separator.
23. A method of manufacturing a semiconductor device as claimed in claim 22, wherein the doping concentration of the substrate gradually decreases in a direction from bottom to top, and a portion near the top surface of the substrate with a lower doping concentration constitutes a first doped region and a second doped region, the first doped region and the second doped region being located on both sides of the well region, and the doping concentration of the well region being higher than that of the first doped region and the second doped region.
24. The method of manufacturing a semiconductor device as described in claim 23 further includes: A first substrate region and a second substrate region are formed, having a second conductivity type opposite to the first conductivity type, and located directly above the first doped region and the second doped region, respectively.
25. The method of manufacturing a semiconductor device as described in claim 24 further includes: A first source region and a second source region are formed, having the first conductivity type, and respectively adjacent to the first substrate region and the second substrate region; and a first source electrode and a second source electrode are formed, extending into the first substrate region and the second substrate region respectively, wherein the first source region is on both sides of the bottom of the first source electrode, and the second source region is on both sides of the bottom of the second source electrode.
26. A method of manufacturing a semiconductor device as claimed in claim 25, wherein the first substrate region and the second substrate region are formed together by a plurality of ion implantation processes, and the first substrate region and the second substrate region each have a multi-step bottom surface or a multi-arc bottom surface, wherein the bottom surface of the first substrate region is higher at the first source region and lower at the first source electrode, and the bottom surface of the second substrate region is higher at the second source region and lower at the second source electrode.
27. A method of manufacturing a semiconductor device as claimed in claim 22, wherein the materials of the first trench gate and the second trench gate include polysilicon, doped polysilicon, metal, or alloy.