Transistor device with buried conductive layer and source / drain area and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-04-07
- Publication Date
- 2023-10-16
Smart Images
Figure TWG2TA000928246_001 
Figure TWG2TA000928246_002 
Figure TWG2TA000928246_003
Abstract
Description
[Technical Field]
[0001] This invention relates primarily to embedded conductive layers for transistor devices, particularly for fin FETs and fully enclosed gate transistors, including embedded conductive layers for nanowire FETs, nanosheet FETs, forksheet FETs and complementary FETs. [Previous Technology]
[0002] US Patent No. 20200411436, published on December 31, 2020, discloses a method for forming embedded power lines 212 "between" transistor elements. See the original text of US Patent No. 20200411436 and its Figure 1 for details. This method includes forming a pair of adjacent transistor elements (from bottom to top including a base pillar 110, a tunnel bottom dielectric layer 230, a nanosheet sacrificial layer 140, and a nanosheet tunnel layer 150) on a substrate 110, wherein the pair of adjacent transistor elements are separated by a trench, and the trench is filled with a trench fill layer 170 (see the original text of US Patent No. 20200411436 for details). This method further includes forming a dielectric panel 172 between the pair of adjacent transistor elements by removing part of the trench fill layer 170, and forming a protective layer 195 on each transistor element. This method further includes forming a sidewall protective layer 202 (a precursor to the sidewall protective post 204, details can be found in the original text of US Patent No. 20200411436 and its Figure 6) on the protective layer 195, and forming an embedded power line 212 between the sidewall protective layer and the protective layer 195. This method further includes removing the sidewall protective layer 202 above the embedded power line to form the sidewall protective post 204 on the dielectric panel 172, and forming a power line cover 215 over the embedded power line and the sidewall protective post. This power line cover 215 may be made of the same metal material as the embedded power line 212, and a dielectric material block 227 is used to cover the power line cover 215 as an insulating layer to prevent leakage current. Therefore, the power line can be surrounded by dielectric material (including sidewall protective pillars 204, protective layer 195, and dielectric material block 227), which provides sufficient protection for the power line. As mentioned in one of the disclosed embodiments (see U.S. Patent No. 20200411436 and its Figure 19), the epitaxial region (i.e., source / drain region) and the embedded power line can be connected by metal vertical contact pillars (Contact / Via) and then protected by the surrounding dielectric material, eliminating the need for additional photolithography processes. Therefore, the embedded power line simplifies the complex and dense metal wire structure above the transistor element and provides an opportunity to reduce the overall transistor element area. The numbers, names, etc., mentioned in this paragraph refer to the content of U.S. Patent No. 20200411436 and are not necessarily the same as those in this invention.
[0003] Although this patent (US Patent No. 20200411436) provides a method for forming embedded power lines between transistor elements, since the power lines can only be located between transistor elements, therefore...
[0003] 1) It has limited effect on reducing the area occupied by the overall component (including the area occupied by the transistor component and the area occupied by the metal line above the transistor).
[0003] 2) There are limitations on the areas where power cords can be buried.
[0003] 3) Because the embedded power line is located at the bottom of the transistor element, while the metal wire is located above the transistor element, the length of the metal vertical contact post (Contact / Via) used for connection needs to reach the overall height of the transistor element structure. This increases the difficulty of manufacturing the metal vertical contact post and the resistance value, and may therefore reduce the performance of the transistor element. The numbers, names, etc. mentioned in this paragraph refer to the content of US Patent No. 20200411436, and are not necessarily the same as those in this invention.
[0004] US Patent No. 20170243957, published on August 24, 2017, discloses a semiconductor device comprising a fin field-effect transistor (FinFET) with a fin structure. The fin structure includes a base layer protruding from the substrate (including substrate 10, device bottom pillars 111 and 211), an intermediate layer 114 disposed on the base layer, and a channel layer disposed on the intermediate layer 114 (including a silicon-germanium layer 115 and a silicon top layer 213), as detailed in the accompanying drawings. This fin structure further includes a first protective layer 140A and a second protective layer 150A made of a different material than the first protective layer 140A. The intermediate layer 114 includes a first semiconductor layer (including 112 and 212) and a silicon top layer disposed thereon (including 113 and 213). The first protective layer 140A covers the sidewalls of the first semiconductor layer (including 112 and 212), and the second protective layer 150A covers the first semiconductor layer 140A. The numbers, names, etc., mentioned in this paragraph refer to the contents of US Patent No. 20170243957 and are not necessarily the same as those in this invention.
[0005] This patent (US Patent No. 20170243957) provides a method for controlling the number of protective layers and partially removing the protective layer to protect the transistor element structure beneath the protective layer. Unlike the method in this patent, which removes the upper half of the protective layer to expose the semiconductor layer, this invention modifies the process of removing the protective layer structure to remove the lower half, thereby retaining the upper half of the protective layer to protect the upper half of the semiconductor layer (190 / 330) of the transistor structure. Furthermore, this invention additionally fills the lower portion of the protective layer structure as a protective layer for the embedded conductive layer 150, thereby achieving leakage protection for the embedded conductive layer 150. Thus, this invention expands the protective layer structure from only protecting continuous surfaces with a single material to being able to segmentally change the material of the protective layer structure to protect continuous surfaces with multiple materials. The numbers, names, etc., mentioned in this paragraph refer to the content of US Patent No. 20170243957 and are not necessarily the same as those in this invention.
[0006] For the structure of advanced components, if there is an effective mechanism for constructing an embedded conductive layer, it can simplify the complexity of the metal wire connection above the field-effect transistor, reduce the overall area of the component, and achieve a denser logic circuit with stronger computational performance per unit area. [Summary of the Invention]
[0007] The present invention provides a transistor element having an embedded conductive layer and a method for connecting a portion of the transistor element structure to the embedded conductive layer.
[0008] The method includes forming one or more transistor elements on a substrate, wherein the transistor elements are separated by a filling layer 210. Each transistor element includes a substrate 100, an intermediate layer 160, and a finned nanosheet stack layer 190. The intermediate layer includes a bottom insulating layer 130, an embedded conductive layer 150, and a top insulating layer 140.
[0009] One embodiment includes an intermediate layer 160, a source / drain region 250, and a patterned gate region 540. The patterned gate region 540 is located above the embedded conductive layer 150 and the top insulating layer 140. The source / drain region 250 may be composed of multiple layers of different materials, including a source / drain epitaxial layer 220, a silicon-based alloy layer 230 surrounding the source / drain epitaxial layer 220, and an adhesion layer 240 surrounding the silicon-based alloy layer 230. A portion of the adhesion layer 240 serves as a connection between the silicon-based alloy layer 230 and the exposed embedded conductive layer 150.
[0010] In this invention,
[0010] 1. Unlike traditional transistor components, the metal interconnect or metal layer connecting the source / drain regions 250 is embedded. This provides more freedom and simplicity in component design.
[0010] 2. By performing multiple rounds of etching / epitaxy manufacturing processes, even in the source / drain regions 250, it is possible to partially remove the top isolation layer 140 to prevent the component from touching the material of the underlying embedded conductive layer 150.
[0010] 3. The connection block between the embedded conductive layer 150 and the source / drain region 250 can be adjusted and controlled by the patterning of the previous layer, such as the patterning of the top insulating layer 140 above the epitaxial source / drain region 250 manufacturing process, such as the etching / epitaxy manufacturing process of the multiple constituent layers inside the source / drain region 250, so as to achieve the most efficient use of the space of the source / drain region 250.
[0011] These features and advantages can be better explained by the textual description and illustrations of the detailed embodiments below. [Simplified Explanation of the Diagram]
[0012] Figure 1 illustrates the gate structure and tunnel structure of a transistor element in the direction of a parallel patterned nanosheet stack 190, according to some embodiments.
[0013] Figures 2-4 illustrate the manufacturing process of a nanochip transistor device in the direction of a vertically patterned nanochip stack 190, according to some embodiments.
[0014] Figure 5-13 illustrates the manufacturing process of a nanochip transistor device in the direction of a parallel patterned nanochip stack 190, according to some embodiments.
Implementation Method
[0015] Figure 1 illustrates the gate structure and tunnel structure of a transistor element in the direction of a parallel patterned nanosheet stack 190 according to an embodiment.
[0016] According to one or more embodiments, the component may be placed on a substrate, wherein the component includes a transistor element. These transistor elements may be horizontal fin field-effect transistors, horizontal nanosheet type, nanowire type, or fork-shaped nanosheet field-effect transistors, or other types of transistor elements. The fins, nanowires, nanosheets, or fork-shaped nanosheets may be separated or surrounded by an insulating layer to achieve protection of their electrical and physical properties.
[0017] In one or more embodiments, a hard mask 330 (shown in FIG. 2) may be deposited on a nanosheet stack 190. The nanosheet stack 190 includes interleaved sacrificial nanosheet layers 170 and channel nanosheet layers 180. The nanosheet stack 190 may be deposited on an intermediate layer 160 and a substrate 100.
[0018] The pattern transfer technique for component manufacturing can be performed in two different ways, but is not limited to. One is direct writing, which includes extreme ultraviolet light, electron beam, and / or combinations thereof. The other is self-aligned single patterning, self-aligned double patterning, or self-aligned quadruple patterning and / or combinations thereof.
[0019] In this invention, the substrate 100 includes a silicon substrate layer 110 and a buffer layer 120. This combination can serve as a pressure adjustment mechanism at the bottom of the channel nanosheet layer 180.
[0020] In various embodiments, the substrate 100 may comprise a plurality of materials, such as single-element semiconductors Si and Ge (e.g., single-crystal Si, single-crystal Ge, polycrystalline Si, polycrystalline Ge, amorphous Si, amorphous Ge, etc.), group III-V compound semiconductor materials (e.g., GaAs, GaP, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, etc.), group IV-IV compound semiconductors (e.g., SiC, SiGe, etc.), or different substrate structures (e.g., silicon-on-insulator substrate) and / or combinations thereof. Different regions of the substrate 100 may be doped with n-type, p-type, neutral impurities, or combinations thereof to improve the conductivity of the substrate 100.
[0021] In some embodiments, the embedded conductive layer 150 of the intermediate layer 160 is surrounded and protected by a bottom insulating layer 130 and a top insulating layer 140. The bottom insulating layer 130 may be composed of different layers, including a first dielectric layer 132 and a first insulating layer 131. Similarly, the top insulating layer 140 includes a second dielectric layer 142 and a second insulating layer 141. However, in practice, more layers may be added to achieve the best protection for the embedded conductive layer 150.
[0022] In some embodiments, the embedded conductive layer 150 of the intermediate layer 160 is first surrounded by a first insulating layer 131 and a second insulating layer 141, and then protected on the outside by a first dielectric layer 132 and a second dielectric layer 142. The intermediate layer 160 further separates the substrate 100 below and the nanosheet stack layer 190 above.
[0023] In one or more embodiments, the embedded conductive layer 150 may be disposed between the substrate 100 and the nanosheet stack 190. The embedded conductive layer 150 may be uniformly deposited by atomic layer deposition (ALD) or plasma-assisted atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), monolithic deposition, and / or combinations thereof.
[0024] In one or more embodiments, the embedded conductive layer 150 may include, but is not limited to, different conductive materials, such as semiconductor materials (doped single-crystal Si, doped polycrystalline Si, doped amorphous Si, Ge, SiGe and / or combinations thereof), metallic materials (e.g., W, Ti, Ta, Ru, Hf, Zr, Co, Ni, Cu, Al, Pt, Sn, Ag, Au, etc.), metal compounds (e.g., GeSn, TaN, TiN, WN, RuO2, etc.), silicon-based metal alloys (e.g., CoSi, NiSi, ZrSi, RuSi, WSi, etc.), transition metal-aluminum alloys (e.g., Ti3Al, ZrAl), conductive carbon materials (e.g., TaC, TiC, TiAlC, TaMgC, etc.), carbon nanotubes, graphene, or any material that meets the criteria, and / or combinations thereof. The doping process may be further incorporated into or after the deposition process of the conductive material.
[0025] The first dielectric layer 132 and the second dielectric layer 142 may be composed of the same or similar materials. Many different types of dielectric materials can be used, such as phosphosilicate glass (PSG), SiON, SiCN, SiOCN, SiC, etc. The dielectric material used for the metal interconnects of the front-end of line may be similar to the dielectric material used for the metal interconnects of the back-end of line. In other words, low-k-value materials may be used. Low-k-value materials include fluorine-doped silicon oxide (SiO₂:F), carbon-doped silicon oxide (SiO₂:C), silane trioxide (HSQ), methyl silsesquioxane (MSQ), tetraethyl orthosilicate (TEOS), and combinations thereof. The doped compounds are represented in the form of doped:dopant, for example, fluorine-doped silicon oxide (SiO₂:F).
[0026] The first insulating layer 131 and the second insulating layer 141 may contain one or more layers of insulating material, including SiON, SiCN, SiOCN, SiC and / or combinations thereof.
[0027] In one or more embodiments, the nanosheet stack 190 includes interleaved sacrificial nanosheet layers 170 and channel nanosheet layers 180. In various embodiments, the sacrificial nanosheet layer 170 may be a semiconductor material, including, but not limited to, Si, Ge, GeSn, SiGe, SiC, Si:C and / or combinations thereof, wherein the material of the sacrificial nanosheet layer 170 is generally different from that of the second dielectric layer 142 and the channel nanosheet layer 180. The sacrificial nanosheet layer 170 may be SiGe with a [Ge] concentration of, but not limited to, approximately 20 atomic percentages (at.%) to approximately 40 atomic percentages (at.%).
[0028] In several embodiments, the channel nanosheet 180 may be a semiconductor material, including, but not limited to, Si, Ge, GeSn, SiGe, SiC, Si:C and / or combinations thereof, wherein the material of the channel nanosheet 180 is generally different from that of the second dielectric layer 142 and the sacrificial nanosheet 170.
[0029] In this embodiment, the channel nanosheet 180 may be composed of single crystal Si or different [Ge] SiGe.
[0030] In various embodiments, the filler layer 210 may comprise a variety of different deposition methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), fluid chemical vapor deposition (FCVD), plasma-assisted chemical vapor deposition (PECVD), atmospheric chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDPCVD), and combinations thereof. In one or more embodiments, the CVD precursor includes silicates, siloxanes, MSQ, HSQ, MSQ / HSQ, fully hydrogenated silazanes (TCPS), fully hydrogenated polysilazanes (PSZ), tetraethyl orthosilicate (TEOS), or silylamines such as trisilaneamine (TSA). After CVD film deposition, excess elements are typically removed by heating to form silicon oxide. As excess elements leave the film, the film density increases and the volume decreases. In some embodiments, multiple annealing processes are used. The CVD thin film may be doped with boron (B) or phosphorus (P). In some embodiments, the filler layer 210 may consist of one or more layers of different materials, such as spin-on glass (SOG), SiO, SiON, SiOCN, and / or fluorine-doped silicate glass (FSG). After the filler layer 210 is filled, an annealing process is usually performed to achieve the best quality insulating layer.
[0031] In some embodiments, the filler layer 210 may be patterned or partially etched away to meet different process requirements.
[0032] In some embodiments, the gate layer 290 may include a gate dielectric layer, a work function adjustment layer, and a gate electrode, but for simplicity, these are not shown in the figures. The gate layer 290 may become more complex depending on the intended use. In this invention, the gate layer 290, the outer gate protective layer 520, and the inner protective layer 530 are illustrated to separate the gate region 540 from the source / drain region 250, so detailed information about the gate layer 290 is not included here.
[0033] In some embodiments, the gate protection layer 550 includes an outer gate protection layer 520 and an inner protection layer 530. Although both the outer gate protection layer 520 and the inner protection layer 530 have the function of physically protecting against leakage current, they are completed in different manufacturing processes, and therefore their material composition, shape, and construction mechanism are not consistent. Typically, in order to reduce the electrical losses caused between the gate region 540 and the source / drain region 250, the outer gate protection layer 520 usually uses a low dielectric constant (k-value) material, such as SiO:F, SiO:C, HSQ, MSQ, TEOS, SiON, SiCN, SiOCN, SiC, etc., and / or combinations thereof.
[0034] The construction mechanism of the inner protective layer 530 is not entirely the same as that of the gate outer protective layer 520. Usually, the inner protective layer 530 is located close to the sacrificial nanosheet 170, and its construction mechanism requires a combination of different types of manufacturing processes, such as etching, annealing, thin film forming, etc.
[0035] The material used in the inner protective layer 530 can be a dielectric material based on one or more semiconductor materials, depending on the complexity of the manufacturing process, such as SiO:F, SiO:C, HSQ, MSQ, TEOS, SiON, SiCN, SiOCN, SiC, SiGe:O, Ge:O, SiO2, SiGeON, GeON and / or combinations thereof.
[0036] For the sake of simplification, the illustrations in this invention use the same pattern for both the outer protective layer 520 and the inner protective layer 530, but as mentioned above, they are not entirely the same in terms of manufacturing, materials and shape.
[0037] In one or more embodiments, the source / drain region 250 includes a source / drain epitaxial layer 220, a silicon-based alloy layer 230, and an adhesion layer 240. The source / drain epitaxial layer 220 can be Si:P in an n-type transistor and Si:B in a p-type transistor. The source / drain epitaxial layer 220 can also act as a pressure regulator for the channel nanosheet 180 to achieve optimal carrier mobility within the tunnel. In terms of current transport, the doped semiconductor has a lower resistance value and better adaptability to connecting metals / alloys.
[0038] The material of the source / drain epitaxial layer 220 includes, but is not limited to, semiconductor materials (e.g., doped single-crystal Si, doped polycrystalline Si, doped amorphous Si, Ge, SiGe and / or combinations thereof) and / or conductive carbon-based materials (e.g., TaC, TiC, TiAlC, TaMgC, carbon nanotubes (CNTs), graphene, etc.) or any suitable material and / or combination thereof. The doping process may be further incorporated into or after the deposition process of the conductive material.
[0039] The silicon-based alloy layer 230 is made of materials including, but not limited to, silicon-based alloys (e.g., CoSi, NiSi, ZrSi, RuSi, WSi, etc.) and / or combinations thereof. The silicon-based alloy layer 230, situated between the source / drain epitaxial layer 220 and the adhesion layer 240, can mediate the material and electrical differences between the semiconductor layer and the metal layer.
[0040] The adhesion layer 240 serves as a buffer between the alloy and the metal material. The adhesion layer 240 can be one or more layers of conductive material, such as semiconductor materials (e.g., doped single-crystal Si, doped polycrystalline Si, doped amorphous Si, Ge, SiGe and / or combinations thereof), metallic materials (e.g., W, Ti, Ta, Ru, Hf, Zr, Co, Ni, Cu, Al, Pt, Sn, Ag, Au, etc.), metal compounds (e.g., GeSn, TaN, TiN, WN, RuO2, etc.), silicon-based alloys (e.g., CoSi, NiSi, ZrSi, RuSi, WSi, etc.), transition metal-aluminum alloys (e.g., Ti3Al, ZrAl), conductive carbides (e.g., TaC, TiC, TiAlC, TaMgC, CNT, graphene, or any suitable conductive material and / or combinations thereof). The doping process may be further incorporated into or after the deposition process of the conductive material.
[0041] Figures 2-4 illustrate the manufacturing process of a nanochip transistor device in the direction of a vertically patterned nanochip stack 190, according to some embodiments. Although Figures 2-17 are embodiments of some manufacturing processes, more manufacturing processes can be inserted before, in the middle, or after these manufacturing processes indicated in Figures 2-17, and the manufacturing processes indicated in Figures 2-17 can be replaced, deleted, and their order can be interchanged.
[0042] As shown in FIG2, one embodiment of the structure includes a substrate 100, an intermediate layer 160, a nanosheet stack layer 190 and a hard mask 330.
[0043] In one or more embodiments, substrate 100 includes a silicon substrate 110 and a buffer layer 120. This dual-layer structure has been shown to effectively improve leakage current (e.g., SOI) or control the pressure behavior of layers located above the substrate (e.g., strain-relaxed buffer, SRB). In this invention disclosure, substrate 100 includes a silicon substrate 110 and a buffer layer 120 to achieve optimal pressure control for the channel nanosheet layer 180.
[0044] Typically, the buffer layer 120 can be approximately 50 nm to 2000 nm thick, so the upper channel nanosheet 180 can be in an environment where the pressure is completely released. Depending on the requirements, the [Ge] concentration within the buffer layer 120 can range from approximately 0 atomic concentration (at.%) to approximately 100 atomic concentration (at.%).
[0045] In some embodiments, the embedded conductive layer 150 of the intermediate layer 160 is surrounded and protected by a bottom insulating layer 130 and a top insulating layer 140. The bottom insulating layer 130 may be composed of different layers, including a first dielectric layer 132 and a first insulating layer 131. Similarly, the top insulating layer 140 includes a second dielectric layer 142 and a second insulating layer 141. However, in practice, more layers may be added to achieve the best protection for the embedded conductive layer 150.
[0046] In some embodiments, the embedded conductive layer 150 of the intermediate layer 160 is first surrounded by a first insulating layer 131 and a second insulating layer 141, and then protected on the outside by a first dielectric layer 132 and a second dielectric layer 142. The intermediate layer 160 further separates the substrate 100 below and the nanosheet stack layer 190 above.
[0047] In one or more embodiments, the hard mask 330 can be used to determine the component channel width W1. The hard mask 330 may be, but is not limited to, composed of two different materials, including a padding oxide layer 310 and a padding nitride layer 320. The padding oxide layer 310 is typically silicon dioxide, and the padding nitride layer 320 is typically silicon nitride.
[0048] In some embodiments, the hard mask 330 may be a multilayer structure used to protect and define active regions within the semiconductor. However, a multilayer structure can be used to provide better definition capabilities for active regions within the semiconductor.
[0049] The deposition method of the hard mask 330 may be, but is not limited to, ALD, CVD, PECVD, APCVD, LPCVD, HDPCVD and / or other suitable processes.
[0050] Typically, the thickness of the padding oxide layer 310 ranges from about 2 nm to about 15 nm, while the thickness of the padding nitride layer 320 ranges from about 10 nm to about 50 nm.
[0051] In some embodiments, the thickness of the embedded conductive layer 150 ranges from about 5 nm to about 200 nm. The thicknesses of the first insulating layer 131 and the second insulating layer 141 range from about 5 nm to about 50 nm.
[0052] The thicknesses of the first dielectric layer 132 and the second dielectric layer 142 range from approximately 5 nm to approximately 50 nm.
[0053] According to the embodiment in FIG3, the hard mask 330 includes portions of the padding oxide layer 310 and the padding nitride layer 320, which are partially etched away, thus defining the preliminary structure of the device. Furthermore, the space created by the etched nanosheet stack 190 will be used to create source / drain regions or insulating blocks in subsequent manufacturing processes, depending on requirements. The remaining portion of the nanosheet stack 190 will be fabricated as the active region, i.e., the region where the gate or channel region of the transistor device is located.
[0054] The process rounds mentioned in the embodiments are also known as hard mask patterning. They can be applied to different areas to achieve different purposes through multiple implementations (i.e., repeating Figures 2-4). Hard mask patterning includes, but is not limited to, hard mask deposition, hard mask patterning, partial etching of defined regions, and hard mask removal. More manufacturing processes can be inserted before, during, or after the manufacturing processes indicated in Figures 2-4, and the manufacturing processes indicated in Figures 2-4 can be replaced, deleted, and their order can be interchanged.
[0055] Hard mask patterning can indirectly define the width of the transistor channel. Furthermore, because the second insulating layer 141 and the second dielectric layer 142 have different etch rates for the etching method, both can serve as etch stop layers. The structure of the buried conductive layer 150 can therefore also be protected by the hard mask 330 structure.
[0056] The transistor channel width W1 is typically between approximately 5 nm and approximately 100 nm.
[0057] As shown in Figure 4, the etched area is filled with filler layer 210 to completely cover the entire structure. Although the interface between the filler layer and the nanosheet stack 190 is not shown separately, there is usually an additional structure inserted between them to ensure that the nanosheet stack 190 is completely protected. Therefore, the channel nanosheet layer 180 will not be oxidized when the filler layer 210 is filled.
[0058] In this invention, the filler layer 210 is silicon dioxide, and it also undergoes an additional annealing step to ensure the stability and quality of the film deposition.
[0059] Figure 5-13 illustrates the manufacturing process of a nanochip transistor device in the direction of a parallel patterned nanochip stack 190, according to some embodiments.
[0060] Next, as shown in FIG5, a polycrystalline silicon mask 510 is deposited, thus defining the gate region 540 and the underlying protected nanosheet stack 190.
[0061] Typically, the polycrystalline silicon mask 510 may include, but is not limited to, doped or annealed polycrystalline silicon, and the thickness may range from less than about 100 nm to more than about 1000 nm.
[0062] As shown in Figure 6, the gate outer protective layer 520 can be used to cover the sidewalls of the polycrystalline silicon mask 510. The construction of the gate outer protective layer 520 typically includes, but is not limited to, deposition, annealing, etching, etc. Due to the etching amount and rate of different patterns, the gate outer protective layer 520 can self-align on the sidewalls of the polycrystalline silicon mask 510. This process is also known as a self-aligned gate protective layer.
[0063] As shown in Figure 7, the partial polysilicon removal mask 420 can be removed, thus exposing the underlying source / drain region 250. Conversely, the portion of the fill layer 210 and the entire gate layer 290, including the channel nanosheet layer 180, remain protected by the polysilicon removal mask 420. Photolithography masks are rarely disclosed in patents, but are included here because this step has a significant impact on some critical dimensions.
[0064] The partially removed source / drain mask is the main factor in defining the source / drain width W2. Typically, the source / drain regions symmetrical to both sides of the gate region 540 have the same size, which facilitates subsequent IC design.
[0065] As shown in FIG8, in this embodiment, the first source / drain region etching process removes a portion of the nanosheet stack 190, the second dielectric layer 142, and the filler layer 210. In other words, a portion of the channel nanosheet layer 180 and the second insulating layer 141 are partially exposed. Typically, the second insulating layer 141, due to its different material from the second dielectric layer, can be used as an etching stop layer and can provide accurate etching amount, ensuring the quality of the etching process.
[0066] However, this entire etching process can also penetrate the intermediate layer 160 to reach the buffer layer 120 or even the silicon substrate 110. In other words, the distance H1 between the top surface of the adhesion layer 240 and the bottom surface of the silicon-based alloy layer 230 may be redefined, and the total etching depth may reach or even exceed the micrometer dimension. In this case, better protection for the buried conductive layer 150 is necessary.
[0067] Although the sidewalls of the multiple channel nanosheets 180 and the sacrificial nanosheets 170 are exposed, the second insulating layer 141 or the partially etched second dielectric layer 142 can prevent important blocks from being affected by the exposed buried conductive layer 150.
[0068] The partially etched filler layer 215 and the partially exposed second insulating layer 141 can be used as a mold for the deposition source / drain region 250 in subsequent manufacturing processes.
[0069] Typically, the source / drain region width W2 is defined here and typically ranges from about 3 nm to about 500 nm, depending on the characteristics of the device.
[0070] The distance H1 between the top surface of the attachment layer 240 and the bottom surface of the silicon-based alloy layer 230 in this step ranges from approximately 10 nm to approximately 1000 nm, depending on the characteristics of the device. Although H1 is defined in the figures and text as the distance between the top surface of the attachment layer 240 and the bottom surface of the silicon-based alloy layer 230, the actual etching depth H1 can be greater if the epitaxial quality parameters H1 / W2 of the source / drain region 250 are sufficient to handle the subsequent epitaxial and etching processes.
[0071] As shown in Figure 9, part of the sacrificial nanosheet 170 will be removed and replaced with an inner protective layer 530.
[0072] The material used and the size of the inner protective layer 530 are related to the composition of the sacrificial nanosheet 170. Typically, the inner protective layer 530 is attached to the sacrificial nanosheet 170 and the channel nanosheet 180, and the inner protective layer 530 provides sufficient physical and electrical barriers to ensure no leakage current.
[0073] As shown in Figure 10, the source / drain epitaxial layer 220 is typically deposited on the sidewall of the channel nanosheet 180 and is separated by the inner protective layer 530 without contacting the underlying second insulating layer 141 or the second dielectric layer 142. However, the source / drain epitaxial layer 220 does not necessarily have to be suspended. On the contrary, the source / drain epitaxial layer 220 can actually touch the underlying surface, such as the top surface of the second insulating layer 141 (in other words, the distance H2 between the bottom surface of the source / drain epitaxial layer 220 and the top surface of the second insulating layer 141 can be 0 or even negative. If it is negative, H2 may need to be redefined).
[0074] In fact, additional processes, such as dry / wet etching, annealing, doping, deposition, etc., may be added before, during, or after this step. Some steps may reduce the size of the source / drain epitaxial layer 220. Therefore, the indexing effect of H2 is relatively weakened. To reiterate, the source / drain epitaxial layer 220 does not necessarily have to be suspended.
[0075] Other surfaces, such as the plurality of sidewalls of the inner protective layer 530, the partially etched fill layer 215, and the top surface of the second insulating layer 141, can serve as a model for the source / drain region 250 manufacturing process.
[0076] Typically, the height EPI_H1 of the source / drain epitaxial layer 220 ranges from about 10 nm to about 500 nm, depending on the characteristics of the device and the height of the nanosheet stack 190.
[0077] Usually EPI_W1 is smaller or about the same as W2, and ranges from about 3nm to about 500nm.
[0078] H2 ranges from approximately 0 nm to approximately 40 nm.
[0079] The angle between the bottom of the source / drain epitaxial layer 220 and the second dielectric layer 142 is R1. Since the epitaxial / etching process has different rates on different surfaces / interfaces, R1 may be less than 90 degrees. In addition, H2 may be 0 or even negative under certain conditions. In these cases, R1 may not exist, and therefore other indicators may be needed for quality monitoring.
[0080] The silicon-based alloy layer 230 is formed according to Figure 11. Typically, the silicon-based alloy layer 230 can be a homogeneous layer of uniform thickness. The bottom thickness of the formed silicon-based alloy layer 230 may be limited by H2; in other words, the silicon-based alloy layer 230 may not be a homogeneous layer of uniform thickness at this time. Furthermore, the silicon-based alloy layer 230 may simultaneously contact the partially etched filler layer 215 and the second insulating layer 141. Therefore, the height EPI_H2 and width EPI_W2 of the silicon-based alloy layer are only conceptual indicators; additional indicators may be required in actual manufacturing. Additionally, H1 represents the aspect ratio of the distance between the partially etched filler layer 215 and the silicon-based alloy layer 230. This indicator is not universally applicable to different situations (e.g., adjacent transistor elements sharing the same source / drain region 250), and therefore is not specifically described here.
[0081] The height EPI_H2 of the silicon-based alloy layer can be larger, equal to, or smaller than the height EPI_H1 of the source / drain epitaxial layer 220, because the silicon-based alloy layer 230 may sometimes consume part of the surface of the source / drain epitaxial layer 220.
[0082] The height EPI_H2 of the silicon-based alloy layer ranges from approximately 10 nm to approximately 750 nm.
[0083] The width of the silicon-based alloy layer, EPI_W2, ranges from approximately 3 nm to approximately 500 nm.
[0084] As shown in Figure 12, the second insulating layer 141 is partially etched away, exposing the embedded conductive layer 150. It is best to assume that the embedded conductive layer 150 is not necessarily composed of metal. Therefore, this layer-by-layer removal process, in addition to preventing the exposure of metal atoms, is more importantly designed to prevent unnecessary interactions between layers. The same concept can be applied to different manufacturing processes.
[0085] According to Figure 12, the distance H3 between the embedded conductive layer 150 and the silicon-based alloy layer 230 can be determined by the thickness of the second insulating layer 141, and is typically close to the thickness of the second insulating layer 141, ranging from approximately 1 nm to approximately 20 nm. However, the silicon-based alloy layer 230 does not necessarily need to contact the top surface of the second insulating layer 141. In other words, H3 can be greater than the thickness of the second insulating layer 141. Depending on the adjustment of the source / drain epitaxial layer 220, H3 can range from approximately 0 nm to approximately 40 nm.
[0086] As shown in Figure 13, the adhesion layer 240 covers the silicon-based alloy layer 230. Typically, the adhesion layer 240 is composed of a metallic material and is ductile and can be matched with different materials. In this invention, some materials are quite good adhesives, such as Co, Cu, W, etc.
[0087] As previously stated, the key dimensions shown in Figure 13 are conceptual indicators. This is because the bottom surface of the source / drain epitaxial layer 220 may be higher than the top surface of the second dielectric layer 142 or the second insulating layer 141, depending on the distance between the buried conductive layer 150 and the bottom surface of the nanosheet stack 190. In other words, one or more layers can be inserted between the intermediate layer 160 and the nanosheet stack 190, thus providing sufficient space to optimize the bottom shape of the source / drain region 250 and the conductive connection layer between the bottom of the source / drain region 250 and the buried conductive layer 150.
[0088] Typically, the width EPI_W3 of the adhesion layer 240 is close to the width W2 of the source / drain region, ranging from about 3 nm to about 500 nm.
[0089] The height EPI_H3 of the adhesion layer 240 ranges from approximately 10 nm to approximately 1000 nm.
[0090] As shown in Figure 14, the gate layer 290 replaces the polysilicon mask 510 and the etched sacrificial nanosheet 170, and surrounds a portion of the channel nanosheet 180. Typically, the gate layer 290 consists of one or more layers, such as a gate dielectric layer, a work function adjustment layer, and a metal electrode. However, for simplicity, Figures 14-15 only show a single pattern to illustrate the difference between the gate layer 290 as the gate region 540 and the source / drain region 250.
[0091] As shown in Figure 15, the metal interconnect layer 600 is typically constructed in the gate region 540 and the source / drain region 250 in a typical transistor structure. Another filling layer, the intermetallic dielectric layer 610, is used to fill the spaces between the metal interconnect layers 600, providing physical and electrical protection for the underlying components and the metal interconnect layer 600.
[0092] Since the metal interconnect layer 600 and the intermetal dielectric layer 610 are only used to illustrate how a conventional transistor structure completes the relationship between the metal interconnect layer and the transistor element, the size and shape are only conceptual markings and do not fully represent the actual situation.
[0093] As shown in Figure 15, by adding the embedded conductive layer 150, a model that can increase the complexity of the connection between the transistor and the metal is completed.
[0094] The above method can be used for integrated circuit chip manufacturing. Manufacturers can package and distribute the manufactured integrated circuit chips in wafer form, bare die form, or packaged die form. Packaged die forms are divided into single-chip packages and multi-chip packages. Chips can be integrated into different types of chips, such as discrete circuit components, signal processing components, or can be integrated into motherboards or even client products. Client products can be any product that uses integrated circuit chips, from the most basic applications such as traditional refrigerators to advanced computer products.
[0095] The elemental concentration in a compound is expressed as SixGe(1-x), where x is less than or equal to 1. Different concentration ratios are all contained in the simplest chemical formula, SiGe. If the compound contains other elements, it can also be referred to as an alloy.
[0096] "In one embodiment" does not necessarily refer to the same embodiment, but rather to a single feature. "In some embodiments" does not necessarily refer to the same set of embodiments, but rather to a few features.
[0097] When the description includes "containing A, B, C or a combination thereof", it means that the text contains individual items A, B, and C, or A and B, A and C, B and C, or A and B and C. This concept can be extended further, as the listed content may only be a partial list of possible ways.
[0098] As used herein, when referring to the structure of a field-effect transistor device (FET), spatial adjectives such as below, above, bottom, top, vertical, horizontal, etc., may be used for convenience. These references are intended to be used only in accordance with the accompanying drawings for illustrative purposes and are not intended to be absolute references to the FET. For example, the FET may be spatially oriented in any manner different from the orientation shown in the accompanying drawings. When referring to the accompanying drawings, "vertical" is used to refer to a direction perpendicular to the surface of the semiconductor layer, while "horizontal" is used only to refer to a direction horizontal to the surface of the semiconductor layer. "Above" refers to a vertical direction away from the semiconductor layer. An element located "above" ("below") another element is further away (closer to) the surface of the semiconductor layer than that other element.
[0099] Since the present invention can be modified and implemented in different but equivalent ways as will be apparent to those skilled in the art from the teachings herein, the specific embodiments disclosed above are merely exemplary. For example, the above process steps may be performed in different orders. Moreover, the present invention is not intended to be limited to the details of the structure or design shown in the text, but rather as described in the claims above. Therefore, it is obvious that modifications or alterations can be made to the specific embodiments disclosed above, and such alterations fall within the scope and spirit of the present invention. It should be noted that the use of terms such as “first,” “second,” “third,” or “fourth,” used to describe various processes or structures in this specification and the appended claims, is only used as a quick reference to such structures / steps and does not necessarily imply an order of arrangement / formation of such steps / structures. Of course, depending on the precise language of the claims, the order of such processes may or may not be required. Therefore, the scope of protection claimed by the present invention is as described in the claims above.
Claims
1. A method for forming an embedded conductive layer 150 of a transistor element, comprising: Forming substrate 100; A transistor element structure is formed on the substrate 100; a filler layer 210 is formed.
2. The method of claim 1, wherein forming a transistor element structure on substrate 100 includes: An intermediate layer 160 is formed; a nanosheet stack layer 190 is formed.
3. The method of claim 2, wherein forming the intermediate layer 160 includes: forming a bottom insulating layer 130; forming an embedded conductive layer 150; and forming a top insulating layer 140.
4. The method of claim 2, wherein forming an intermediate layer 160 includes: a patterned substrate 100; forming a patterned bottom insulating layer 130; forming a patterned embedded conductive layer 150; and forming a patterned top insulating layer 140.
5. The method of claim 1 further includes: patterning the gate region 540; patterning the source / drain region 250; forming the source / drain region 250.
6. The method of claim 5, wherein the patterned source / drain region 250 includes: etching away a portion of the nanosheet stack 190; and etching away a portion of the structure located below the nanosheet stack 190.
7. The method of claim 5, wherein forming source / drain region 250 comprises: forming source / drain epitaxial layer 220; forming silicon-based alloy layer 230; etching away a portion of the structure located below nanosheet stack layer 190; and forming adhesion layer 240.
8. The method of claim 5, wherein forming a source / drain region 250 comprises: forming a source / drain epitaxial layer 220; etching away a portion of the structure located below the nanosheet stack layer 190; forming a silicon-based alloy layer 230; and forming an adhesion layer 240.
9. The method of claim 5, wherein forming a source / drain region 250 includes: forming a source / drain epitaxial layer 220; forming a silicon-based alloy layer 230; forming an adhesion layer 240; and etching away a portion of the structure located below the nanosheet stack layer 190.
10. The method of claim 5, wherein forming a source / drain region 250 comprises: etching away a portion of the structure located below the nanosheet stack layer 190; forming a source / drain epitaxial layer 220; forming a silicon-based alloy layer 230; and forming an adhesion layer 240.
11. The method of claim 6, wherein the etched portion of the structure located below the nanosheet stack 190 includes an intermediate layer 160, a substrate 100 and / or one or more additional insert layers.
12. The method of claim 6, wherein the etched portion of the structure located below the nanosheet stack 190 may be inserted more than once before, during, after, and / or a combination thereof, the formation of the source / drain epitaxial layer 220, the formation of the silicon-based alloy layer 230, the formation of the adhesion layer 240.
13. The method of claim 5, forming a source / drain region 250, wherein the distance between the embedded conductive layer 150 and the silicon-based alloy layer 230 is H3 and ranges from about 1 nm to about 20 nm.
14. The method of claim 5, wherein a source / drain region 250 is formed, wherein the distance between the bottom surface of the source / drain epitaxial layer 220 and the top surface of the second insulating layer 141 is H2 and ranges from about 0 nm to about 40 nm.
15. The method of claim 5 further includes: forming a metal interconnect layer 600 of the source / drain region 250; forming an intermetallic dielectric layer 610.
16. The method of claim 5 further includes: forming an intermetallic dielectric layer 610.