Interposer, semiconductor package assembly and method of forming the same

Abstract

An embodiment semiconductor package assembly may include an interposer, an integrated passive device electrically coupled to a first side of the interposer, an underfill material portion formed between the integrated passive device and the first side of the interposer, and a dam protruding from the first side of the interposer and configured to constrain a spatial extent of the underfill material portion. The dam may include a first portion extending above a surface of the first side of the interposer and a second portion embedded below the surface of the first side of the interposer. The dam may be formed in a dielectric layer that also includes a component of a redistribution interconnect structure. The dam may further be electrically isolated from the redistribution interconnect structure and may be configured to form a connected or disconnected boundary of a two-dimensional region of the first side of the interposer.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor manufacturing technology, and more particularly to an interposer, a semiconductor packaging assembly and a method for forming the same, wherein the interposer includes a dam structure for constraining the spatial extent of the bottom filling material portion. [Previous Technology]

[0002] The semiconductor industry has developed due to the continuous increase in the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, these increases in integrated density come from the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area.

[0003] In addition to smaller electronic components, improvements have been made to the packaging of components in an effort to provide smaller packages that occupy less area than previous packages. These packaging improvements can include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer-level packages (WLPs), package-on-package (PoP), system-on-chip (SoC), or system-on-integrated circuit (SoIC) devices. Some of these three-dimensional devices (e.g., 3DIC, SoC, SoIC) are fabricated by placing a die on top of another die on a semiconductor wafer level. These three-dimensional devices offer higher integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced interconnect lengths between stacked dies. However, many challenges also exist associated with three-dimensional devices. [Summary of the Invention]

[0004] This disclosure provides a semiconductor packaging assembly in some embodiments, including: an interposer; an integrated passive device electrically coupled to a first side of the interposer; an underfill material portion formed between the integrated passive device and the first side of the interposer; and a dam protruding from the first side of the interposer and configured to constrain the spatial extent of the underfill material portion.

[0005] This disclosure provides an interposer layer comprising: one or more dielectric layers; a redistributed interconnect structure formed in the one or more dielectric layers; a first plurality of bonding structures formed on a first side of the interposer layer and electrically connected to the redistributed interconnect structure, wherein the first plurality of bonding structures are configured to electrically connect an integrated passive device to the interposer layer; and a dam protruding from the first side of the interposer layer.

[0006] This disclosure provides a method for forming a semiconductor package assembly, comprising: forming an interposer by performing the following operations, including: forming a first dielectric layer on a carrier substrate; forming a dam and a first portion of a redistribution interconnect structure in the first dielectric layer; forming one or more additional dielectric layers and one or more corresponding additional portions of the redistribution interconnect structure; removing the carrier substrate to expose a first side of the interposer including a package-side dielectric layer; and removing a portion of the package-side dielectric layer to expose a first portion of the dam, such that the dam includes a first portion extending over the first side of the interposer and a second portion embedded below the first side of the interposer.

Implementation Method

[0008] The following disclosure provides many different embodiments or examples to implement different features of this invention. Specific examples of components and their arrangements are described below to illustrate this disclosure. Of course, these embodiments are merely examples and should not be construed as limiting the scope of this disclosure. For example, the specification may describe a first feature formed on or above a second feature, which may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, repeated reference numerals and / or designations may be used in different examples of this disclosure; this repetition is for simplification and clarity and is not intended to limit any specific relationship between the various embodiments and / or structures discussed.

[0009] Furthermore, spatial terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate the description of the relationship between one element or feature and another element(s) in the diagram. In addition to the orientation shown in the diagram, these spatial terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial terms used herein may be interpreted in the same way. Unless otherwise explicitly stated, it is assumed that each element having the same reference numeral has the same material composition and a thickness within the same thickness range.

[0010] The various embodiments disclosed herein provide an improved method for attaching an integrated passive device to an interposer in a semiconductor package assembly. After attaching the integrated passive device to the interposer, an underflow material can be formed between the integrated passive device and a first side of the interposer. A dam formed in the interposer can be configured to constrain the spatial extent of the underfill material portion. This prevents the underfill material portion from overlapping with adjacent bonding structures, which could otherwise degrade the performance of the semiconductor package assembly. In some embodiments, the dam may include multiple disconnected segments, which can help reduce stress caused by thermal expansion during various processing steps. Furthermore, in some embodiments, the dam can be fabricated together with a redistribution interconnect layer, thus requiring only minimal modifications to existing manufacturing processes.

[0011] One embodiment of a semiconductor package assembly may include: an interposer; an integrated passive device electrically coupled to a first side of the interposer; an underfill material portion formed between the integrated passive device and the first side of the interposer; and a dam protruding from the first side of the interposer and configured to constrain the spatial extent of the underfill material portion. The dam may include a first portion extending above a surface of the first side of the interposer and a second portion embedded below the surface of the first side of the interposer. The dam may be formed in a dielectric layer, which also includes components of a redistributed interconnect structure. The dam may be further electrically isolated from the redistributed interconnect structure and may be configured to form a connected or disconnected boundary of a two-dimensional region of the first side of the interposer.

[0012] In another embodiment, an interposer is provided. The interposer may include: one or more dielectric layers; a redistribution interconnect structure formed in the one or more dielectric layers; a first plurality of bonding structures formed on a first side of the interposer and electrically connected to the redistribution interconnect structure, wherein the first plurality of bonding structures are configured to electrically connect an integrated passive device to the interposer; and a dam protruding from the first side of the interposer. The dam may be formed in the interposer and may be partially embedded in a dielectric layer, which also includes components of the redistribution interconnect structure. The interposer may further include: an integrated passive device coupled to the first side of the interposer and electrically connected to the first plurality of bonding structures; and an underfill material portion formed in a volume between the integrated passive device and the first side of the interposer, such that the dam is configured to constrain the spatial extent of the underfill material portion.

[0013] In another embodiment, a method for forming a semiconductor package assembly is provided. The method may include forming an interposer by performing the following operations: forming a first dielectric layer on a carrier substrate; forming a dam and a first portion of a redistribution interconnect structure in the first dielectric layer; forming one or more additional dielectric layers and one or more corresponding additional portions of the redistribution interconnect structure; removing the carrier substrate to expose a first side of the interposer including a package-side dielectric layer; and removing a portion of the package-side dielectric layer to expose a first portion of the dam, such that the dam includes a first portion extending over the first side of the interposer and a second portion embedded below the first side of the interposer. The method may further include: forming a first plurality of bonding structures on the redistribution interconnect structure, such that the first plurality of bonding structures are configured to protrude from the first side of the interposer; electrically connecting an integrated passive device to the first plurality of bonding structures; and distributing an underfill material portion, such that the underfill material portion is configured to be formed in a volume between the integrated passive device and the first side of the interposer, and such that the dam is configured to constrain the spatial extent of the underfill material portion.

[0014] Figure 1A is a top view of a semiconductor device 100a according to one of various embodiments. The semiconductor device 100a may include one or more integrated circuit (IC) semiconductor devices. For example, the semiconductor device 100a may include a first plurality of semiconductor dies 102 and a second plurality of semiconductor dies 104. Each of the first plurality of semiconductor dies 102 may be configured as a three-dimensional device, such as three-dimensional integrated circuits (3DICs), system-on-a-chip (SOC) devices, or system-on-a-chip (SoIC) devices. The semiconductor device 100a may further include one or more additional semiconductor dies 106. For example, the one or more additional semiconductor dies 106 may be integrated passive devices (e.g., containing passive components such as capacitors, inductors, resistors, etc.) or other components, as described in more detail below with reference to Figure 3.

[0015] Each of the first plurality of semiconductor dies 102 can be formed by placing a wafer on top of a wafer on a semiconductor wafer level to form a three-dimensional device. These three-dimensional devices offer higher bulk density and other advantages, such as faster speed and higher bandwidth, due to the reduced interconnect length between stacked wafers. In some embodiments, each of the first plurality of semiconductor dies 102 may also be referred to as a "first die stack". In some embodiments, each of the first plurality of semiconductor dies 102 can be a die or a wafer, such as a logic die or a power management die.

[0016] In the semiconductor device 100a of Figure 1A, the first plurality of semiconductor dies 102 may include four first die stacks, each of which may be configured as a system-on-a-chip (SOC) device. In various embodiments, each of the first plurality of semiconductor dies 102 may be adjacent to each other and may be located in the central portion of the semiconductor device 100a. The second plurality of semiconductor dies 104 may be located in the periphery surrounding the first plurality of semiconductor dies 102, as shown in Figure 1A.

[0017] In this example embodiment, the second plurality of semiconductor dies 104 may include twelve semiconductor dies. In some embodiments, the second plurality of semiconductor dies 104 may be a three-dimensional integrated circuit semiconductor device and may also be referred to as a "second die stack". In some embodiments, each of the second plurality of semiconductor dies 104 may be a semiconductor memory device, such as a high bandwidth memory (HBM) device. Although the first plurality of semiconductor dies 102 includes four (4) semiconductor dies and the second plurality of semiconductor dies 104 includes twelve (12) semiconductor dies, in other embodiments, semiconductor devices 100a, 100b, 100c may include more or fewer die stacks.

[0018] Figure 1B is a vertical cross-sectional view of a semiconductor device 100b according to one of various embodiments. As shown, the semiconductor device 100b may include a first plurality of semiconductor dies 102 mounted to a package substrate 108. The package substrate 108 may include suitable materials, such as semiconductor materials (e.g., semiconductor wafers, such as silicon wafers), ceramic materials, organic materials (e.g., polymers and / or thermoplastic materials), glass materials, combinations thereof, etc. Other suitable substrate materials are also within the scope of this disclosure. In various embodiments, the package substrate 108 may include a redistributed interconnect structure 110.

[0019] A first plurality of semiconductor dies 102 may be electrically coupled to a package substrate 108 via a first plurality of solder portions 112, the first plurality of solder portions 112 connecting corresponding bonding pads or microbumps (not shown) of the respective first plurality of semiconductor dies 102 and the package substrate 108. A redistribution interconnect structure 110 may be configured to electrically couple each of the first plurality of semiconductor dies 102 to each other and allow signals to be transmitted between them. The package substrate 108 may be further electrically coupled to a printed circuit board (PCB) (not shown) via a second plurality of solder portions 114, the second plurality of solder portions 114 connecting corresponding bump structures of the package substrate 108 and the printed circuit board.

[0020] Figure 1C is a vertical cross-sectional view of yet another semiconductor device 100c according to various embodiments. The semiconductor device 100c may include an interposer 116 having a redistributed interconnect structure 118. A first plurality of semiconductor dies 102 may be electrically coupled to the interposer 116 via a plurality of solder portions 112, the plurality of solder portions 112 connecting each of the first plurality of semiconductor dies 102 to a corresponding bonding pad or microbump (not shown) of the interposer 116. The semiconductor device 100c including the first plurality of semiconductor dies 102 and the interposer 116 may be further coupled to a package substrate 108 via a plurality of solder portions 120, the plurality of solder portions 120 coupling the interposer 116 to a corresponding bonding pad or bump structure of the package substrate 108.

[0021] The package substrate 108 may be further electrically coupled to a printed circuit board (PCB) (not shown) via a plurality of solder portions 114, the plurality of solder portions 114 connecting corresponding bump structures of the package substrate 108 and the printed circuit board. The semiconductor device 100c may be similar to various other structures described in more detail below. For example, the interposer 116 may be an organic interposer, or the interposer 116 may be a silicon interposer.

[0022] Figure 2A is a vertical cross-sectional view of an exemplary semiconductor package assembly 200 including a plurality of semiconductor dies (102, 104) and an integrated passive device 336 according to various embodiments. The exemplary semiconductor package assembly 200 may include an interposer 116 having a redistributed interconnect structure 110. The plurality of semiconductor dies (102, 104) are electrically coupled to the interposer 116 via a plurality of solder portions 112, the plurality of solder portions 112 connecting the respective semiconductor dies (102, 104) and the respective bonding pads (344a, 344b) of the interposer 116.

[0023] The integrated passive device 336 can similarly be electrically coupled to the interposer 116 via a plurality of solder portions 120a, the plurality of solder portions 120a connecting the respective integrated passive device 336 and the corresponding bonding pads or microbumps (not shown) of the interposer 116. As described above, at least one underfill material portion 216 can be formed around each bonding array of solder portions (112, 120a). Furthermore, an epoxy molding compound (EMC) can be applied to the gap formed between the interposer 116, the semiconductor dies (102, 104), and the integrated passive device 336 to form a polycrystalline epoxy molding compound (EMC) frame 218.

[0024] An exemplary semiconductor package assembly 200, including a plurality of semiconductor dies (102, 104), an interposer 116, and an integrated passive device 336, may be further coupled to a package substrate 108 via a plurality of solder portions 120b, the plurality of solder portions 120b being coupled to corresponding interposers 116 and corresponding bonding pads or bump structures (not shown) of the package substrate 108. The package substrate 108 may be further electrically connected to a printed circuit board (not shown) via a plurality of solder portions 114, the plurality of solder portions 114 connecting the package substrate 108 and corresponding bump structures of the printed circuit board.

[0025] The exemplary semiconductor package assembly 200 may resemble the various other structures described above. For example, the interposer 116 may be an organic interposer, or the interposer 116 may be a silicon interposer. The integrated passive device 336 may be configured in various ways. For example, the integrated passive device 336 may include one or more passive components, such as capacitors, inductors, resistors, etc. Furthermore, the integrated passive device 336 may be coupled to the bottom surface of the interposer 116, as shown in Figures 2A and 2B. Alternatively, the integrated passive device 336 may be coupled to the top surface of the interposer.

[0026] Figure 2B is a bottom view of a portion of an exemplary semiconductor package assembly 200 according to Figure 2A of various embodiments, such that the plane of the figure is parallel to the cross section B-B' shown in Figure 2A. In this regard, a portion of a first side 502 of the interposer 116 is shown. The portion of the first side 502 may include a plurality of solder portions 120b coupled to the bottom surface of the interposer 116 and an integrated passive device 336. As described above, the solder portions 120a (e.g., see Figure 2A) can be bonded to the integrated passive device 336 and corresponding bonding pads or bumps (not shown) of the interposer 116 by performing a reflow operation, such that the integrated passive device 336 is coupled to the first side 502 of the interposer 116.

[0027] The at least one underfill material portion 216 can be formed by injecting an underfill material around the integrated passive device 336. In this way, the at least one underfill material portion 216 can be formed between the integrated passive device 336 and the first side 502 of the interposer 116 after the solder portion 120a (e.g., see Figure 2A) located between the integrated passive device 336 and the interposer 116 has been reflowed. Any of a variety of underfill material application methods can be used, which may include, for example, capillary underfill methods, molded underfill methods, or printed underfill methods. In some embodiments, the underfill material portion 216 may extend to a region 216r that may physically contact a subset of the solder portion 120r. The presence of the region 216r of the underfill material portion 216 may degrade the performance of the subset of the solder portion 120r affected by the region 216r of the underfill material portion 216. In some cases, the presence of region 216r of the underfill material portion 216 may render a subset of the solder portion 120r inoperable. Thus, it may be advantageous to provide additional physical structures that can constrain the spatial extent of the underfill material portion 216, as described in more detail below.

[0028] Figure 3A is a vertical cross-sectional view of a semiconductor package assembly 300 having a fan-out wafer-level package including a plurality of semiconductor dies (102, 104), an integrated passive device 336, and a dam 602 according to various embodiments. Figure 3B is a bottom view of a portion of the semiconductor package assembly 300 of Figure 3A according to various embodiments, such that the plane of the view is parallel to the cross-section B-B' shown in Figure 3A. The dam 602 may be configured to protrude from a first side 502 of the interposer 116, as shown in Figure 3A, and described in more detail below. Furthermore, as shown in Figure 3B, the dam 602 may be configured to constrain the spatial extent of the at least one underfill material portion 216 by forming a connected boundary of a two-dimensional region of the first side 502 of the interposer 116 when viewed in a plan view. In this way, the at least one underfill material portion 216 is prevented from contacting the solder portion 120b.

[0029] Figure 3C is a vertical cross-sectional view of a portion of the interposer 116 according to Figures 3A and 3B of various embodiments, the portion being defined by cross section C-C' indicated in Figure 3B. Figure 3D is an enlarged view of a portion of the dam shown in Figures 3A to 3C of various embodiments. As shown in Figures 3C and 3D, the dam 602 protrudes from a first side 502 of the interposer 116 and may have a first portion extending above the surface of the first side 502 of the interposer 116 and a second portion embedded below the surface of the first side 502 of the interposer 116. The first portion may have a first width 604 (W1) and a first height 606 (H1). The second portion may have a second height 608 (H2). The first height 606 (H1) may have a value in a first range of about 1 micrometer to about 15 micrometers. The second height 608 (H2) may have a value such that the ratio (H1 / H2) of the first height 606 (H1) to the second height 608 (H2) has a value in a second range of about 0.1 to about 0.5. The first width 604 (W1) may have a value in a third range of about 5 micrometers to about 50 micrometers.

[0030] As shown in Figure 3C, a dam 602 may be spaced apart from the first edge 612 of the integrated passive device 336 by a second width 610 (W2). The second width 610 (W2) may have a value in a fourth range of about 10 micrometers to about 200 micrometers. Thus, the dam 602 may be used to constrain the bottom filler portion 216 to a spatial region within the second width 610 (W2) of the integrated passive device 336. As shown in Figure 3C, the first side 502 of the interposer layer 116 may include a plurality of bonding structures 614 having solder portions 120b. As shown, the first edge 612 of the integrated passive device 336 may be spaced apart from one of the plurality of bonding structures 614 by a third width 616 (W3). The third width 616 (W3) may have a value such that the ratio (W2 / W3) of the second width 610 (W2) to the third width 616 (W3) is in a fifth range of about 0.1 to about 0.8.

[0031] According to one embodiment, a plurality of bonding structures 614 may have a spacing spanning a fourth width 618 (W4), the fourth width 618 (W4) being in a sixth range of about 50 micrometers to about 200 micrometers. The integrated passive device 336 may have a fifth width 620 (W5), which has a value in a seventh range of about 500 micrometers to about 4000 micrometers. The second portion of the dam 602 (e.g., see Figure 3D) may have a sixth width 622 (W6) in an eighth range of about 5 micrometers to about 50 micrometers, as shown in Figure 3D. Furthermore, as shown in Figures 3C and 3D, the dam 602 may be formed in an interposer 116 and may be partially embedded in a dielectric layer, which also includes a component of the redistributed interconnect structure 110, as described in more detail below with reference to Figures 4 through 11.

[0032] Figure 3E is a bottom view of a portion of an exemplary semiconductor package assembly similar to Figure 3A according to various embodiments, showing a dam having a plurality of unconnected dam segments (e.g., segments 602a, 602b, 602c, 602d), while Figure 3F is a bottom view of a portion of an exemplary semiconductor package assembly similar to Figure 3A according to various embodiments, showing another dam having a plurality of unconnected segments 602i. In each embodiment, the dam (602a, 602b, 602c, 602d, 602i) forms a boundary of a two-dimensional region on a first side of the interposer layer when viewed in a plan view (i.e., the bottom view shown in Figures 3E and 3F). In an example embodiment, the plurality of unconnected segments 602i of the dam in Figure 3F may each have a square or rectangular cross-section (e.g., a square segment 602i of 20 micrometers by 20 micrometers) with a characteristic length on the order of 20 micrometers.

[0033] Embodiments of a dam that may include multiple unconnected dam segments (e.g., 602a, 602b, 602c, 602d) can help reduce stress caused by thermal expansion during various processing steps. For example, the dam 602 in Figure 3B may experience thermal expansion stress concentration at the corners of the dam 602. In contrast, the dam (602a, 602b, 602c, 602d) in Figure 3E avoids such stress concentration because the corners are disconnected. Similarly, the dam in Figure 3F that includes multiple unconnected segments 602i can similarly avoid stress concentration, which would otherwise occur in the four segments 602a, 602b, 602c, 602d of the dam shown in Figure 3E. The size and spacing of the unconnected dam sections (e.g., 602a, 602b, 602c, 602d, 602i) of the dam in Figures 3E and 3F can be determined by the characteristics of the bottom filler portion 216. For example, the viscosity and surface tension of the bottom filler portion 216 can prevent leakage of the bottom filler portion 216 from the dam in Figures 3E and 3F, provided that the gaps between the unconnected dam sections (e.g., 602a, 602b, 602c, 602d, 602i) are sufficiently small. For example, if the gaps between the unconnected dam sections (e.g., 602a, 602b, 602c, 602d, 602i) are 10 micrometers or less, leakage of the bottom filler portion 216 can be avoided.

[0034] Figure 4 illustrates an intermediate structure 400, according to various embodiments, that can be used to form a semiconductor package assembly. The intermediate structure 400 may include a first carrier substrate 212a on which a first redistribution dielectric layer 704a is formed. The first carrier substrate 212a may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The first carrier substrate 212a may be transparent or opaque. The thickness of the first carrier substrate 212a is sufficient to provide mechanical support for an interposer layer 116 subsequently formed thereon (e.g., see Figures 2A, 3A, and 3C). For example, the thickness of the first carrier substrate 212a may range from approximately 60 micrometers to approximately 1 millimeter (mm). Alternative embodiments may include carrier substrates with greater or lesser thicknesses.

[0035] The intermediate structure 400 of Figure 4 may include a first adhesive layer 214a applied to the top surface of the first carrier substrate 212a. In various embodiments, the first carrier substrate 212a may include an optically transparent material, such as glass or sapphire. In this example, the first adhesive layer 214a may include a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer may form a layer that converts ultraviolet light into heat, causing the LTHC layer to lose its adhesiveness. Alternatively, the first adhesive layer 214a may include an adhesive material configured to decompose thermally. For example, the first adhesive layer 214a may include an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The thermally decomposable adhesive material may have a debonding temperature in the range of about 150 °F to about 400 °F. Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also within the scope of this disclosure.

[0036] As shown in Figure 4, a first redistributed interconnect layer 110a may be formed in the first redistributed dielectric layer 704a. A dam 602 may also be formed in the first redistributed dielectric layer 704a. The first redistributed dielectric layer 704a may be a dielectric polymer material, such as PI, BCB, or PBO. The first redistributed dielectric layer 704a may be formed by spin-coating and drying the dielectric polymer material.

[0037] The thickness of the first redistribution dielectric layer 704a may range from approximately 2 micrometers to approximately 40 micrometers, for example, from 4 micrometers to 20 micrometers. The first redistribution dielectric layer 704a may be patterned, for example by applying and patterning a corresponding photoresist layer (not shown) thereon, and transferring the pattern in the photoresist layer into the first redistribution dielectric layer 704a by using an etching process, for example, an anisotropic etching process. The photoresist layer may then be removed, for example by ashing.

[0038] The redistribution interconnect layer 110a and dam 602 can be formed by sputtering a metal seed layer, applying and patterning a photoresist layer over the metal seed layer to form a pattern of openings through the photoresist layer, electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the metal seed layer located between portions of the electroplated metal filler material. The metal seed layer may include, for example, a stack of titanium barrier layers and copper seed layers. The thickness of the titanium barrier layer may range from 50 nanometers (nm) to 150 nanometers, while the thickness of the copper seed layer may range from 100 nanometers to 500 nanometers. The metal filler material of the grain-side redistribution interconnect layer 110a may include copper, nickel, or a stack of copper and nickel. In many embodiments, the redistribution interconnect layer 110a and dam 602 can be formed in a common process, including: depositing a common (identical) metal seed layer by sputtering; applying and patterning a photoresist layer over the metal seed layer to form a pattern of openings through the photoresist layer; electroplating a common metal filler material (e.g., copper, nickel, or a stack of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching portions of the common metal seed layer located between portions of the electroplated metal filler material. Therefore, the redistribution interconnect layer 110a and dam 602 can have a common material. In other embodiments, the redistribution interconnect layer 110a and dam 602 may be formed in different processes, including: depositing different metal seed layers in separate processes by sputtering; applying and patterning a photoresist layer over the different metal seed layers to form a pattern of openings through the photoresist layer; electroplating different metal filler materials (e.g., copper, nickel, or a stack of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching portions of the different metal seed layers located between portions of the electroplated metal filler material. Therefore, in these other embodiments, the redistribution interconnect layer 110a and dam 602 may be formed of different materials.

[0039] Figure 5 is another intermediate structure 500 according to various embodiments, which can be used to form a semiconductor package assembly. The intermediate structure 500 can be formed from the intermediate structure 400 of Figure 4 by forming additional redistribution dielectric layers (e.g., redistribution dielectric layers 704b, 704c, 704d, and 704e) and additional redistribution interconnect layers (e.g., redistribution interconnect layers 110b, 110c, 110d, and 110e) over the first redistribution dielectric layer 704a and the first redistribution interconnect layer 110a. Each additional redistribution dielectric layer (704b, 704c, 704d, 704e) can be formed by spin-coating and drying a corresponding dielectric polymer material. The thickness of each additional redistribution dielectric layer (704b, 704c, 704d, 704e) can range from approximately 2 micrometers to approximately 40 micrometers, for example, from 4 micrometers to 20 micrometers.

[0040] Each additional redistribution dielectric layer (704b, 704c, 704d, 704e) can be patterned, for example by applying and patterning a corresponding photoresist layer thereon, as described above for the first redistribution dielectric layer 704a. The photoresist layer can then be removed, for example by ashing. Although in this example embodiment, the intermediate structure 500 may include five redistribution dielectric layers (704a, 704b, 704c, 704d, 704e) and five redistribution interconnect layers (110a, 110b, 110c, 110d, 110e), in other embodiments, more or fewer redistribution dielectric layers and redistribution interconnect layers may be provided.

[0041] Furthermore, as shown in Figure 5, the bonding pad 334b ​​may be formed as part of the final redistribution interconnect layer 110e. Solder portions 112 may be further formed over the bonding pad 334b. As described above, each redistribution interconnect layer (110a, 110b, 110c, 110d, 110e) and bonding pad 334b ​​may be formed by: depositing a metal seed layer by sputtering; applying and patterning a photoresist layer over the metal seed layer to form a pattern of openings through the photoresist layer; electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching portions of the metal seed layer located between portions of the electroplated metal filler material.

[0042] The thickness of the metal filler material deposited in each redistributed interconnect layer (110a, 110b, 110c, 110d, 110e) can range from about 2 micrometers to about 40 micrometers, for example, 4 micrometers to 20 micrometers, although smaller or larger thicknesses may also be used. The total number of wiring layers in each redistributed interconnect layer (110a, 110b, 110c, 110d, 110e) (i.e., the number of layers of the grain-side redistributed interconnect structure 110 in Figures 2A, 3A, and 3C) can range from 1 to 12, for example, 2 to 5. The total height of the redistributed interconnect layers (110a, 110b, 110c, 110d, 110e) can range from 30 micrometers to 300 micrometers, although smaller or larger heights may also be used.

[0043] In one embodiment, the thickness of the redistributed dielectric layers (704a, 704b, 704c, 704d, 704e) and the redistributed interconnect layers (110a, 110b, 110c, 110d, 110e) can be selected such that the redistributed interconnect layers (110a, 110b, 110c, 110d, 110e) disposed on different wiring layers have different thicknesses. Thicker redistributed interconnect layers (e.g., the first redistributed interconnect layer 110a) can be used to provide low-resistance conductive paths. Thinner die-side redistributed interconnect layers (e.g., the fifth redistributed interconnect layer 110e) can be used to provide electromagnetic interference shielding.

[0044] The description of Figures 4 and 5 above relates to embodiments in which the interposer 116 (e.g., see Figures 2A, 3A and 3C) is formed as an organic interposer. In other embodiments, the interposer 116 may be formed as a silicon interposer using back-end-of-line (BEOL) semiconductor device processing techniques.

[0045] For example, the redistributed interconnect layers (110a, 110b, 110c, 110d, 110e) and dam 602 can be formed via a dual damascene process or via multiple single damascene processes. A single damascene process typically forms and fills a single feature with copper at each damascene stage. A dual damascene process typically forms and fills two features with copper simultaneously. For example, trenches and overlapping vias can be filled using a single copper deposition in a dual damascene process. In an alternative embodiment, the redistributed interconnect layers (110a, 110b, 110c, 110d, 110e) and dam 602 can be formed via an electroplating process, as described above with reference to the formation of organic interposers.

[0046] The redistribution dielectric layers (704a, 704b, 704c, 704d, 704e) can be formed by continuously depositing and patterning dielectric materials such as silicon oxide, silicon nitride, and silicon carbide using a deposition process such as PECVD. Each redistribution dielectric layer (704a, 704b, 704c, 704d, 704e) can be patterned by applying a photoresist (not shown) and patterning the photoresist using photolithography, and then using the patterned photoresist to form openings, such as trenches and / or vias (e.g., vias). The openings can be formed, for example, by etching the redistribution dielectric layers (704a, 704b, 704c, 704d, 704e) using anisotropic etching (e.g., by performing reactive ion etching).

[0047] A deposition process can be performed to deposit a conductive material (e.g., copper) in the opening. A planarization process, such as chemical-mechanical planarization (CMP), can then be performed to remove excess copper (e.g., a capping layer) disposed on top of the redistributed dielectric layers (704a, 704b, 704c, 704d, 704e). Patterning, metal deposition, and planarization processes can be performed on each redistributed dielectric layer (704a, 704b, 704c, 704d, 704e) to form redistributed interconnect layers (110a, 110b, 110c, 110d, 110e) and / or dam 602.

[0048] Figure 6 illustrates another intermediate structure 600 that can be used to form a semiconductor package assembly according to various embodiments. In this regard, a first plurality of semiconductor dies 102 and a second plurality of semiconductor dies 104 may be coupled to an interposer 116. Each of the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104 may be a system-on-a-chip (SoC) die, a high-bandwidth memory (HBM) die, an integrated passive device die, etc. In a further embodiment, one or more of the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104 may be a serializer / de-serializer device die. Each of the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104 may be attached to a bonding pad 344b of the interposer 116 via an array of at least one first solder portion 112.

[0049] At least one underfill material portion 216 may be formed around each bonding array of the first solder portions 112. Each underfill material portion 216 may be formed by injecting an underfill material around the array of the first solder portions 112 after reflowing the first solder portions 112. Various underfill material application methods may be used, including, for example, capillary underfill, molding underfill, or printing underfill.

[0050] Figure 7 illustrates another intermediate structure 700 that can be used to form a semiconductor package assembly according to various embodiments. The intermediate structure 700 may include an epoxy molding compound (EMC) material that may be applied to the gap formed between the interposer 116 and the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104, thereby forming an epoxy molding compound (EMC) frame 218. The EMC material may include an epoxy compound that can be hardened (i.e., cured) to provide a dielectric material portion with sufficient rigidity and mechanical strength. The EMC material may include epoxy resin, hardener, silicon dioxide (as a filler), and other additives. Depending on viscosity and flowability, the EMC material may be provided in liquid or solid form.

[0051] Liquid EMC offers better workability, good flowability, fewer voids, better filling, and fewer flow marks. Solid EMC offers less curing shrinkage, better stand-off, and less die drift. High filler content (e.g., 85% by weight) in EMC materials reduces molding time, mold shrinkage, and mold warpage. Uniform filler size distribution in EMC materials reduces flow marks and improves flowability. The curing temperature of EMC materials can be lower than the release (debonding) temperature of the first adhesive layer 214a. For example, the curing temperature of EMC materials can be in the range of 125 °C to 150 °C.

[0052] The epoxy molding compound framework 218 can be cured at a curing temperature to form an EMC matrix that laterally surrounds each of the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104. The EMC matrix may include a plurality of epoxy molding compound frameworks 218 that may be laterally adjacent to each other. Each epoxy molding compound framework 218 may be configured to laterally surround and embed into a corresponding one of the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104. Excess portions of the epoxy molding compound framework 218 may be removed from above a horizontal plane comprising the top surface of the semiconductor device die by a planarization process (e.g., CMP).

[0053] Figure 8 illustrates another intermediate structure 800 that can be used to form a semiconductor package assembly according to various embodiments. The intermediate structure 800 can be formed from the intermediate structure 700 of Figure 7 by attaching a second carrier substrate 212b to a first plurality of semiconductor dies 102 and a second plurality of semiconductor dies 104, removing the first carrier substrate 212a, and flipping the resulting structure such that the first side 502 of the interposer 116 faces upward as shown (e.g., shown in Figure 8).

[0054] By deactivating the first adhesive layer 214a, the first carrier substrate 212a (e.g., see Figures 4 to 7) can be separated from the assembly of the interposer 116, the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104, and the epoxy molding compound frame 218. In this regard, the first adhesive layer 214a can be deactivated, for example, by performing a thermal annealing process at a high temperature. In various embodiments, the first adhesive layer 214a may include a heat-deactivated adhesive material. In other embodiments where the first carrier substrate 212a may be transparent, the first adhesive layer 214a may include a UV-deactivated adhesive material.

[0055] The second carrier substrate 212b may have similar characteristics to the first carrier substrate 212a. In this respect, the second carrier substrate 212b may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The second carrier substrate 212b may be transparent or opaque. The thickness of the second carrier substrate 212b is sufficient to provide mechanical support for the intermediate structure 800 (e.g., see Figure 8) and the intermediate structures 900 and 1000 subsequently formed thereon (e.g., see Figures 9 and 10 below and related descriptions) and the semiconductor package assembly 1100 (e.g., see Figure 11). For example, the thickness of the second carrier substrate 212b may range from approximately 60 micrometers to approximately 1 millimeter. Alternative embodiments may include carrier substrates with greater or lesser thicknesses.

[0056] The intermediate structure 800 of Figure 8 may further include a second adhesive layer 214b applied to the top surface of the second carrier substrate 212b. In various embodiments, the second carrier substrate 212b may include an optically transparent material, such as glass or sapphire. In this example, the second adhesive layer 214b may include a photothermal conversion (LTHC) layer configured to convert ultraviolet light into heat, causing the photothermal conversion layer to lose its adhesiveness, as described above with reference to the first adhesive layer 214a. Alternatively, the second adhesive layer 214b may include an adhesive material configured to thermally decompose as described above (e.g., having a debonding temperature in the range of approximately 150 °F to approximately 400 °F). Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also within the scope of this disclosure.

[0057] Figure 9 illustrates another intermediate structure 900 that can be used to form a semiconductor package assembly according to various embodiments. The intermediate structure 900 can be formed from the intermediate structure 800 of Figure 8 by performing an etching process to etch a portion of the topmost redistribution dielectric layer 704e to expose a first portion of the dam 602 (e.g., see Figure 3D above and related description). As described above with reference to Figure 3D, the first portion of the dam 602 may have a height 606 (H1), which may have a value in a first range of about 1 micrometer to about 15 micrometers. Thus, the etching process can be configured to remove a similar thickness of the topmost redistribution dielectric layer 704e, thereby exposing a similar thickness of the various portions of the topmost redistribution interconnect layer 110e.

[0058] The exposed portion of the topmost redistribution interconnect layer 110e may include a first plurality of metal features 1202 and a second plurality of metal features 1204. Like dam 602, the first plurality of metal features 1202 and the second plurality of metal features 1204 may have a first portion exposed on the surface of the first side 502 of the interposer layer 116 (including the surface of the topmost redistribution dielectric layer 704e), and a second portion embedded in the topmost redistribution dielectric layer 704e.

[0059] The first plurality of metal features 1202 and the second plurality of metal features 1204 can be electrically connected to other layers (110a, 110b, 110c, 110d) in the redistribution interconnect layer. Thus, the first plurality of metal features 1202 and the second plurality of metal features 1204 can be electrically connected to the first plurality of semiconductor dies 102 and the second plurality of semiconductor dies 104 via electrical connections formed with bonding pads 344a (e.g., see Figure 3A). The dam 602 can be electrically isolated from the redistribution interconnect layers (110a, 110b, 110c, 110d, 110e). As described in further detail below, the first plurality of metal features 1202 and the second plurality of metal features 1204 can be configured as a bonding structure.

[0060] Figure 10 illustrates another intermediate structure 1000, which can be used to form a semiconductor package assembly according to various embodiments. The intermediate structure 1000 is formed from the intermediate structure 900 of Figure 9 by forming a plurality of bonding structures 614 and attaching an integrated passive device 336 to a first plurality of metal features 1202. In this regard, the plurality of bonding structures 614 can be formed over the second plurality of metal features 1204 using a technique similar to that used for forming the redistributed interconnect layers (110a, 110b, 110c, 110d, 110e). In this regard, a mask layer (not shown) can be deposited over the intermediate structure 900 and can be patterned to form a patterned mask layer (e.g., a patterned dielectric layer or a patterned photoresist). A metal layer can then be deposited in the via structure formed in the patterned mask layer, thereby forming the bonding structures 614 over the second plurality of metal features 1204. The solder portion 120b can then be provided above the bonding structure 614. Thus, the bonding structure 614 can be configured as a C4 bump structure.

[0061] The patterned mask layer can then be removed by etching to expose a first portion of the dam 602 and the first plurality of metal features 1202. The first plurality of metal features 1202 may be configured as microbumps for bonding the integrated passive device 336 to the interposer layer 116. In this regard, the first plurality of solder portions 112 may be disposed on the top surface of the first plurality of metal features 1202. The integrated passive device 336 may then be bonded to the first plurality of metal features 1202 such that the package-side bonding pads 344c of the integrated passive device 336 may be bonded to the first plurality of metal features 1202. In this regard, a reflow operation may be performed to melt the first plurality of solder portions 112, thereby forming a bond between the first plurality of metal features 1202 and the package-side bonding pads 344c.

[0062] Figure 11 illustrates a semiconductor package assembly 1100 according to one of various embodiments. The semiconductor package assembly 1100 can be formed from the intermediate structure 1000 of Figure 10 by forming an underfill material portion 216. As described above, the underfill material portion 216 can be formed by injecting an underfill material around a first plurality of solder portions 112, which can be coupled to a first plurality of metal features 1202 after reflow soldering. Various underfill material application methods can be used, including, for example, capillary underfill, molding underfill, or printed underfill. As described above, the dam 602 can be configured to constrain the spatial extent of the underfill material portion 216. In this way, physical contact between the underfill material portion 216 and the bonding structure 614 can be prevented.

[0063] Figure 12 is a flowchart illustrating various operations of a method 1200 for manufacturing a semiconductor device structure according to various embodiments. In a first operation 1210, method 1200 may include forming a first dielectric layer (e.g., a redistribution dielectric layer 704a) on a carrier substrate (e.g., a first carrier substrate 212a). In a second operation 1220, method 1200 may include forming a dam 602 and a first portion of a redistribution interconnect structure (e.g., a first redistribution interconnect layer 110a) in the first dielectric layer 704a. In operation 1230, method 1200 may include forming one or more additional dielectric layers (e.g., redistribution dielectric layers (704b, 704c, 704d, 704e)) and one or more corresponding additional portions of the redistribution interconnect structure (e.g., redistribution interconnect layers (110b, 110c, 110d, 110e)). In operation 1240, method 1200 may include removing the first carrier substrate 212a to expose a first side 502 of an interposer 116 including a package-side dielectric layer (e.g., a first redistribution dielectric layer 704a). In operation 1250, method 1200 may include removing a portion of the package-side dielectric layer (e.g., the first redistribution dielectric layer 704a) to expose a first portion of a dam 602, such that the dam 602 includes a first portion extending over the first side 502 of the interposer 116 and a second portion embedded beneath the first side 502 of the interposer 116 (e.g., see Figure 3D).

[0064] In other embodiments, method 1200 may further include: forming a first plurality of bonding structures (e.g., a first plurality of metallic features 1202) on the redistributed interconnect structure 110, such that the first plurality of bonding structures are configured to protrude from a first side 502 of the interposer layer 116; electrically connecting an integrated passive device 336 to the first plurality of bonding structures 1202; and distributing an underfill material portion 216 such that the underfill material portion 216 is configured to be formed in a volume between the integrated passive device 336 and the first side 502 of the interposer layer 116. In this manner, dam 602 may be configured to constrain the spatial extent of the underfill material portion 216.

[0065] In other embodiments, method 1200 may further include: forming a via in a first dielectric layer (e.g., redistribution dielectric layer 704a); and depositing a conductive material in the via to form a dam 602 (e.g., see Figure 4). Method 1200 may further include: configuring the dam 602 to have a shape that forms a boundary of a two-dimensional region of a first side 502 of the interposer layer 116 when viewed in a plan view (e.g., see Figures 3B, 3E, and 3F). Thus, the dam 602 may be configured to form one of: a connected boundary (e.g., see Figure 3B) surrounding a rectangular region of the first side 502 of the interposer layer 116 when viewed in a plan view; and a disconnected boundary (e.g., see Figures 3E and 3F) including a plurality of disconnected dam segments (e.g., 602a, 602b, 602c, 602d, 602i).

[0066] In other embodiments, method 1200 may further include: forming a second plurality of bonding structures (e.g., bonding pads 344b) on the redistributed interconnect structure 110, such that the second plurality of bonding pads 344b are configured to protrude from a second side of the interposer 116 (e.g., see Figures 3A and 5 to 11); and electrically bonding one or more semiconductor dies (102, 104) to the second plurality of bonding pads 344b. In some embodiments, forming the second plurality of bonding structures (e.g., bonding pads 344b) on the redistributed interconnect structure 110 and electrically bonding one or more semiconductor dies (102, 104) to the second plurality of bonding pads 344b may be performed prior to removing the carrier substrate (e.g., the first carrier substrate 212a).

[0067] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor package assembly (300, 1100) is provided (see, for example, Figures 3A and 11). The semiconductor package assembly (300, 1100) may include: an interposer 116; an integrated passive device 336 electrically coupled to a first side 502 of the interposer 116; an underfill material portion 216 formed between the integrated passive device 336 and the first side 502 of the interposer 116; and a dam 602 protruding from the first side 502 of the interposer 116 and configured to constrain the spatial extent of the underfill material portion 216.

[0068] In one embodiment, the dam 602 may include a first portion and a second portion, the first portion extending above the surface of the first side 502 of the interposer 116, and the second portion embedded below the surface of the first side 502 of the interposer 116 (e.g., see Figure 3D). In one embodiment, the first portion may include a first height 606 (H1) in a first range of about 1 micrometer to about 15 micrometers, and the second portion may include a second height 608 (H2) such that the ratio (H1 / H2) of the first height 606 (H1) to the second height 608 (H2) is in a second range of about 0.1 to about 0.5.

[0069] In one embodiment, the first portion of the dam 602 may include a first width 604 (W1) in a third range of about 5 micrometers to about 50 micrometers. In one embodiment, the dam 602 may be spaced from the first edge 612 of the integrated passive device 336 by a second width 610 (W2), and the second width 610 (W2) may have a value in a fourth range of about 10 micrometers to about 200 micrometers. In one embodiment, the first side 502 of the interposer layer 116 may further include a plurality of bonding structures 614 such that the first edge 612 of the integrated passive device 336 is spaced from one of the plurality of bonding structures 614 by a third width 616 (W3), and the ratio (W2 / W3) of the second width 610 (W2) to the third width 616 (W3) is in a fifth range of about 0.1 to about 0.8.

[0070] In one embodiment, a plurality of bonding structures 614 may be configured to have a spacing spanning a fourth width 618 (W4), the fourth width 618 (W4) being in a sixth range of about 50 micrometers to about 150 micrometers, or about 50 micrometers to about 200 micrometers; the integrated passive device 336 may include a fifth width 620 (W5) in a seventh range of about 500 micrometers to about 4000 micrometers; and a second portion of the dam 602 may include a sixth width 622 (W6) in an eighth range of about 5 micrometers to about 50 micrometers (see, for example, Figure 3D). As shown (for example, as shown in Figures 4 to 11), in one embodiment, the dam 602 may be formed in an interposer 116, for example, partially embedded in a dielectric layer (e.g., a redistribution dielectric layer 704a), the redistribution dielectric layer 704a also including a component of a redistribution interconnect structure 110 (e.g., a first redistribution interconnect layer 110a). In one embodiment, the dam 602 and the redistribution interconnection structure 110 may be formed of a common material.

[0071] In a further embodiment (e.g., see Figure 5), an interposer 116 may be provided. The interposer 116 may include: one or more dielectric layers (e.g., redistributed dielectric layers (704b, 704c, 704d, 704e)); a redistributed interconnect structure 110 (e.g., redistributed interconnect layers (110a, 110b, 110c, 110d, 110e)) formed in the one or more dielectric layers; a first plurality of bonding structures (e.g., a first plurality of metal features 1202) formed on a first side 502 of the interposer 116 and electrically connected to the redistributed interconnect structure 110; and a dam 602 protruding from the first side 502 of the interposer 116, wherein the first plurality of bonding structures 1202 are configured to electrically connect an integrated passive device 336 to the interposer 116.

[0072] In one embodiment, the interposer 116 may further include: an integrated passive device 336 coupled to a first side 502 of the interposer 116 and electrically connected to a first plurality of bonding structures 1202; and a bottom filler portion 216 formed in the volume between the integrated passive device 336 and the first side 502 of the interposer 116, such that a dam 602 is configured to constrain the spatial extent of the bottom filler portion 216. As described above, in one embodiment, the dam 602 may be formed in the interposer 116 and may be partially embedded in a dielectric layer (e.g., a redistribution dielectric layer 704a), the redistribution dielectric layer 704a also including a component of a redistribution interconnect structure (e.g., a redistribution interconnect layer 110a). In one embodiment, the dam 602 and the redistribution interconnect structure 110 include a common material. Furthermore, as shown in Figures 3B, 3E, and 3F, in some embodiments, the dam 602 may be configured to form the boundary of a two-dimensional region of the first side 502 of the interposer 116 when viewed in a plan view. In this respect, dam 602 may be configured to form a connected boundary (e.g., see Figure 3B) surrounding a rectangular region of the first side 502 of the intermediate layer 116 when viewed in plan view. Alternatively, dam 602 may include a plurality of unconnected dam segments (e.g., 602a, 602b, 602c, 602d, 602i) forming an unconnected boundary (e.g., see Figures 3E and 3F).

[0073] The disclosed embodiments offer advantages over existing semiconductor package assemblies due to the presence of a dam 602 configured to constrain the spatial extent of the underfill material portion 216. This prevents the underfill material portion 216 from overlapping with adjacent bonding structures 614, which could otherwise degrade the performance of the semiconductor package assembly. In some embodiments, the dam 602 may include multiple unconnected dam segments (e.g., 602a, 602b, 602c, 602d, 602i), which can help reduce stress caused by thermal expansion during various processing steps. Furthermore, the dam can be manufactured together with the redistributed interconnect layers (110a, 110b, 110c, 110d, 110e), requiring only minimal modifications to existing manufacturing processes.

[0074] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from the inventive spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0007] The following detailed description, in conjunction with the accompanying drawings, provides a complete disclosure. It should be noted that, in accordance with the general practice of the industry, the drawings are not drawn to scale. In fact, the dimensions of the components may be arbitrarily enlarged or reduced for clarity. Figure 1A is a top view of a semiconductor device according to various embodiments. Figure 1B is a vertical sectional view of one semiconductor device according to various embodiments. Figure 1C is a vertical sectional view of yet another semiconductor device according to various embodiments. Figure 2A is a vertical sectional view of an exemplary semiconductor package assembly having a fan-out wafer-level package including a plurality of semiconductor dies and an integrated passive device die according to various embodiments. Figure 2B is a bottom view of a portion of the exemplary semiconductor package assembly of Figure 2A according to various embodiments, such that the plane of the figure is parallel to cross section B-B' shown in Figure 2A. Figure 3A is a vertical sectional view of an exemplary semiconductor package assembly having a fan-out wafer-level package including a plurality of semiconductor dies, an integrated passive device, and a dam according to various embodiments. Figure 3B is a bottom view of a portion of an exemplary semiconductor package assembly according to Figure 3A of various embodiments, such that the plane of the figure is parallel to the cross section B-B' shown in Figure 3A. Figure 3C is a vertical cross-sectional view of a portion of the interposer layer according to Figures 3A and 3B of various embodiments, the portion being defined by the cross section C-C' indicated in Figure 3B. Figure 3D is an enlarged view of a portion of a dam shown in Figures 3A to 3C of various embodiments. Figure 3E is a bottom view of a portion of an exemplary semiconductor package assembly similar to Figure 3A of various embodiments, showing a dam having a plurality of unconnected segments. Figure 3F is a bottom view of a portion of an exemplary semiconductor package assembly similar to Figure 3A of various embodiments, showing another dam having a plurality of unconnected segments. Figure 4 is a vertical cross-sectional view of an intermediate structure that can be used to form a semiconductor package assembly according to various embodiments. Figure 5 is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor package assembly according to various embodiments. Figure 6 is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor package assembly according to various embodiments. Figure 7 is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package assembly according to various embodiments. Figure 8 is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package assembly according to various embodiments. Figure 9 is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package assembly according to various embodiments. Figure 10 is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package assembly according to various embodiments. Figure 11 is a vertical cross-sectional view of a semiconductor package assembly according to various embodiments. Figure 12 is a flowchart illustrating various operations of a method for manufacturing a semiconductor device structure according to various embodiments.

Claims

1. A semiconductor packaging component, comprising: One intermediary layer; An integrated passive device is electrically coupled to a first side of the intermediate layer; A bottom filling material portion is formed between the bulk passive device and the first side of the intermediate layer; And a dam, protruding from the first side of the intermediate layer, and configured to constrain a spatial range of the bottom filling material portion.

2. The semiconductor package assembly of claim 1, wherein the dam includes a first portion and a second portion, the first portion extending over a surface of the first side of the interposer, and the second portion embedded below the surface of the first side of the interposer.

3. The semiconductor package assembly of claim 2, wherein the first portion includes a first height in a first range of about 1 micrometer to about 15 micrometers, and wherein the second portion includes a second height such that a ratio of the first height to the second height is in a second range of about 0.1 to about 0.

5.

4. The semiconductor package assembly of claim 2, wherein the first portion includes a first width in a third range of about 5 micrometers to about 50 micrometers.

5. The semiconductor package assembly of claim 2, wherein the dam is separated from a first edge of the integrated passive device by a second width, and wherein the second width includes a value in a fourth range of about 10 micrometers to about 200 micrometers.

6. The semiconductor package assembly of claim 5, wherein the first side of the interposer further includes a plurality of bonding structures, wherein the first edge of the integrated passive device is spaced apart from one of the bonding structures by a third width, and wherein a ratio of the second width to the third width is in a fifth range of about 0.1 to about 0.

8.

7. The semiconductor package assembly of claim 6, wherein the bonding structures include a spacing spanning a fourth width in a sixth range of about 50 micrometers to about 200 micrometers, wherein the integrated passive device includes a fifth width in a seventh range of about 500 micrometers to about 4000 micrometers, and wherein the second portion of the dam includes a sixth width in an eighth range of about 5 micrometers to about 50 micrometers.

8. The semiconductor package assembly of claim 1, wherein the dam is formed in the interposer and partially embedded in a dielectric layer, the dielectric layer also including a component of a redistributed interconnect structure.

9. The semiconductor package assembly of claim 8, wherein the dam and the redistributed interconnect structure comprise a common material.

10. An intermediary layer, comprising: One or more dielectric layers; a redistributed interconnect structure formed in the one or more dielectric layers; A first plurality of bonding structures formed on a first side of the interposer and electrically connected to the redistribution interconnect structure, wherein the first plurality of bonding structures are configured to electrically connect an integrated passive device to the interposer; and a dam protruding from the first side of the interposer.

11. As in the intermediary layer of request item 10, it further includes: The integrated passive device is coupled to the first side of the intermediate layer and electrically connected to the first plurality of bonding structures; And a bottom filling material portion formed in a volume between the bulk passive device and the first side of the intermediate layer, wherein the dam is configured to constrain a spatial range of the bottom filling material portion.

12. The interposer of claim 10, wherein the dam is formed in the interposer and partially embedded in a dielectric layer, the dielectric layer also including a component of the redistributed interconnect structure.

13. The intermediate layer of claim 12, wherein the dam and the redistribution interconnection structure comprise a common material.

14. The intermediary layer of claim 10, wherein the dam is configured to form a boundary of a two-dimensional region on the first side of the intermediary layer when viewed in a plan view.

15. The intermediary layer of claim 14, wherein the dam is configured to form one of the following: a connected boundary surrounding a rectangular area on the first side of the intermediary layer when viewed in the plan view; and a disconnected boundary comprising a plurality of disconnected segments.

16. A method of forming a semiconductor package assembly, comprising: An interposer is formed by performing the following operations: forming a first dielectric layer on a carrier substrate; forming a dam and a first portion of a redistribution interconnect structure in the first dielectric layer; forming one or more additional dielectric layers and one or more corresponding additional portions of the redistribution interconnect structure; removing the carrier substrate to expose a first side of the interposer including a package-side dielectric layer; and removing a portion of the package-side dielectric layer to expose a first portion of the dam, such that the dam includes the first portion extending over the first side of the interposer and a second portion embedded below the first side of the interposer.

17. The method of forming a semiconductor package assembly as described in claim 16 further includes: A first plurality of bonding structures are formed on the redistributed interconnect structure, such that the first plurality of bonding structures are configured to protrude from the first side of the interposer layer; Electrically connecting an integrated passive device to the first plurality of bonding structures; and distributing a bottom filler portion such that the bottom filler portion is configured to be formed in a volume between the integrated passive device and the first side of the interlayer, wherein the dam is configured to constrain a spatial extent of the bottom filler portion.

18. The method of forming a semiconductor package assembly as claimed in claim 16, wherein forming the dam further comprises: A via is formed in the first dielectric layer; The dam is formed by depositing a conductive material in the through-hole.

19. The method of forming a semiconductor package assembly as claimed in claim 16, wherein forming the dam further comprises: The dam is configured to have a shape having a boundary of a two-dimensional region formed on the first side of the intermediate layer when viewed in a plan view, wherein the dam is configured to form one of: a connected boundary surrounding a rectangular region on the first side of the intermediate layer when viewed in a plan view; and a non-connected boundary comprising a plurality of non-connected segments.

20. The method of forming a semiconductor package assembly as described in claim 16 further includes: A second plurality of bonding structures are formed on the redistributed interconnect structure, such that the second plurality of bonding structures are configured to protrude from a second side of the interposer layer; And electrically bonding one or more semiconductor device dies to the second plurality of bonding structures.

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