Integrated circuit device and method of forming the same

Abstract

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Description

[Technical Field]

[0001] The present invention relates to integrated circuit devices, and more particularly to memory devices and methods of manufacturing the same. [Previous Technology]

[0002] Many modern electronic devices incorporate electronic memory. Electronic memory can be volatile or non-volatile. Non-volatile memory retains its stored data even when power is not supplied, while volatile memory loses its stored data when power is not supplied. Dynamic random-access memory (DRAM) is volatile memory and requires frequent refresh. Examples of non-volatile memory include resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), ferroelectric random-access memory (FeRAM), and phase-change memory (PCM). [Summary of the Invention]

[0003] Embodiments of the present invention provide an integrated circuit device, comprising a device including a ferroelectric layer, wherein the ferroelectric layer has less than 1 ppm of chlorine.

[0004] Embodiments of the present invention provide an integrated circuit device including a memory cell comprising a ferroelectric layer, wherein the memory cell has a leakage current and a time-dependent dielectric collapse rate, wherein the time-dependent dielectric collapse rate is defined as the initial value of the leakage current divided by the operating time during which the leakage current doubles from the initial value, and the time-dependent dielectric collapse rate is less than the amount by which the time-dependent dielectric collapse rate increases when 1 ppm of chlorine is added to the ferroelectric layer.

[0005] Embodiments of the present invention provide a method for forming an integrated circuit device, comprising forming a memory cell, the memory cell comprising a ferroelectric layer, wherein the step of forming the memory cell comprises forming the ferroelectric layer by deposition from a plurality of chlorine-free gaseous precursors.

Implementation Method

[0007] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0009] Various integrated circuit (IC) devices incorporate multiple layers of ferroelectric material. For example, ferroelectric memory uses ferroelectric layers for data storage. Data can be stored by preserving the polarization of electric dipoles within the ferroelectric layer. A first orientation of these electric dipoles can represent logic "1," and a second orientation can represent logic "0." Ferroelectric material can be used in various memory structures. In some embodiments, ferroelectric memory includes a ferroelectric layer disposed between two plates in a capacitor used to store data. For example, a 1T1C (one-transistor one-capacitor) memory architecture can use a ferroelectric capacitor. In some embodiments, the ferroelectric memory has a metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure, wherein the bottom electrode of the ferroelectric capacitor is coupled to the gate electrode of the field-effect transistor (FET). The gate electrode of the FET and the bottom electrode of the ferroelectric capacitor serve as a single floating gate. In some embodiments, the ferroelectric memory has a ferroelectric layer disposed between the gate electrode and the channel in the transistor structure. The ferroelectric field-effect transistor is an example disclosed herein.

[0010] Ideally, ferroelectric memory possesses long lifetime and high reliability. Memory lifetime is limited by the time-dependent dielectric breakdown rate (TDDB) and bias temperature instability (BTI). The TDDB manifests as an increase in leakage current over long periods of operation. Bias temperature instability may be related to charge trapping and manifests as a change in the threshold voltage during continuous operation. Bias temperature instability includes positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI). Because the causes and mechanisms of the TDDB and bias temperature instability are not yet fully understood, it is difficult to manage the occurrence of these instabilities in ferroelectric memory.

[0011] The inventors of this disclosure have determined that by removing chlorine residues from the ferroelectric layer and its surrounding structure, the time-dependent dielectric layer collapse rate (TDDB) and bias temperature instability (BTI) can be improved. The inventors of this disclosure have determined that as little as 1 ppm of chlorine in either the ferroelectric layer or its surrounding structure can cause the time-dependent dielectric layer collapse rate / bias temperature instability, and that this instability can be significantly mitigated by using less than 1 ppm of chlorine to produce and maintain the ferroelectric layer or its surrounding structure. In particular, using ferroelectric materials composed of HFxZr1-xO2 as an example, the time-dependent dielectric layer collapse rate / bias temperature instability caused by 1 ppm of chlorine has been observed. In the aforementioned formula, x ranges from 0 to 1. The aforementioned formula may include HfO2, HfZrO2, and ZrO2.

[0012] Generally, ferroelectric layers are produced by atomic layer deposition (ALD) using metal chloride precursors. The performance of ferroelectric layers is strongly affected by layer thickness. ALD allows for precise control of the film thickness. Metal chloride precursors have volatility and reaction rates that are very suitable for ALD processes. Ferroelectric memories may contain other metal-containing films, which are typically produced by ALD using metal chloride precursors. These films include a work function metal layer, electrodes, and an insulating layer. While not wishing to be bound by theory, it has been observed that even 1 ppm of fluorine in any of these films or in the metal electrodes of a ferroelectric memory device can lead to the development of fixed charge clusters, particularly at interfaces. These fixed charge clusters can contribute to time-dependent dielectric breakdown (TDDB) rates or bias temperature instability (BTI).

[0013] According to this disclosure, the ferroelectric layer of the ferroelectric memory cell has less than 1 ppm of chlorine. In some embodiments, the ferroelectric memory cell comprises other metal compound films, but has less than 1 ppm of chlorine. In some embodiments, the aforementioned other films comprise a work function metal layer. In some embodiments, the work function metal layer comprises an alloy of two metals. In some embodiments, the other films comprise two work function metal layers. In some embodiments, the two work function metal layers are located between the ferroelectric layer and the electrode. In some embodiments, the two work function metal layers are located on both sides of the ferroelectric layer. In some embodiments, the other films comprise an insulating layer. In some embodiments, the electrode of the ferroelectric memory cell has less than 1 ppm of chlorine. In some embodiments, all structures of the ferroelectric memory cell have less than 1 ppm of chlorine.

[0014] In some embodiments, the ferroelectric layer is produced from a gaseous precursor comprising a chlorine-free metal compound. In some embodiments, the work function metal layer is produced from a gaseous precursor comprising a chlorine-free metal compound. In some embodiments, the work function metal layer is produced from a gaseous precursor comprising a chlorine-free precursor of a first metal and a chlorine-free precursor of a second metal. In some embodiments, the insulating layer is produced from a gaseous precursor comprising a chlorine-free metal compound. Using a chlorine-free precursor removes chlorine residues.

[0015] In some embodiments, the chlorine-free precursor comprises a metal compound wherein the metal is directly bonded to oxygen (O), nitrogen (N), carbon (C), or a combination thereof. In some embodiments, the chlorine-free precursor comprises a metal compound wherein the metal is directly bonded to carbon. In some embodiments, the chlorine-free precursor comprises a metal compound wherein the metal is directly bonded to oxygen. In some embodiments, the chlorine-free precursor comprises a metal compound wherein the metal is directly bonded to only oxygen and / or carbon. In some embodiments, the chlorine-free precursor comprises a metal compound having a hydrocarbon functional group. In some embodiments, the chlorine-free precursor comprises a metal compound having a carbonyl functional group. In some embodiments, the chlorine-free precursor comprises a metal compound having a cyclopentadienyl complex. In some embodiments, the chlorine-free metal precursor comprises a metal compound having a nitrogen functional group. In some embodiments, the chlorine-free metal precursor comprises a metal compound having a hydrofluorocarbon functional group.

[0016] In some embodiments, the chlorine-free precursor comprises a metal compound in which the metal is directly bonded to nitrogen. In some embodiments, the chlorine-free precursor comprises a metal compound in which the metal is bonded to nitrogen only. Excellent results have been obtained using precursors in the form M(NR1R2)4, where M is zirconium (Zr), hafnium (Hf), or similar materials, and R1 and R2 are organic functional groups.

[0017] In some embodiments, the organic functional group is an alkanes, alkenes, alkynes, alcohols, amines, ethers, aldehydes, ketones, carboxylic acids, esters, amides, or similar organic functional groups. In some embodiments, the precursor comprises one or more of the following: zirconium(IV) tert-butoxide (Zr[OC(CH3)3]4 or ZTB); bis(methyl-η5-clyclopentadienyl)methoxymethylzirconium (Zr[CH3C5H4]2CH3OCH3, ZRCMMM, or ZrD-CO4); tetrakis(dimethylamino)zirconium(IV) (Zr[N(CH3)2]4 or TDMAZ); tetrakis(ethylmethylamido)zirconium(IV) (Zr[N(CH3)(C2H5)] 4 or TEMAZ); bis(methyl-η5-clyclopentadienyl)dimethylhafnium; Hf[CH3C5H4]2CH3OCH3, HFCMME, or HfD-CO2; bis(methyl-η5-clyclopentadienyl)methoxymethylhafnium; HfCH3OCH3[C5H4]2 or HfD-CO4; tetrakis(dimethylamino)hafnium(IV); Hf[N(CH3)2]4 or TDMAH; tetrakis(ethylmethylamido)hafnium(IV); Hf[N(CH3)(C2H 5)] 4 or TEMAH); or similar precursors.

[0018] The ferroelectric layer can be incorporated into any type of integrated circuit device. In some embodiments, the memory cell of the memory device includes the ferroelectric layer. The memory can be of any type. In some embodiments, the ferroelectric memory includes the ferroelectric layer in a transistor structure. In some embodiments, the transistor has a bottom gate. In some embodiments, the transistor has a top gate. In some embodiments, the transistor is located in a three-dimensional (3D) memory array. In some embodiments, the transistor has a metal-ferroelectric-semiconductor (MFS) structure. In some embodiments, the transistor has a metal-ferroelectric-insulator-semiconductor (MFIS) structure. In some embodiments, the ferroelectric memory includes the ferroelectric layer in a capacitor structure. In some embodiments, the memory is a ferroelectric random access memory (FeRAM) in which the ferroelectric capacitor is coupled to the drain region of a field-effect transistor (FET). In some embodiments, the memory has a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure in which the ferroelectric capacitor is coupled to the gate of the field-effect transistor.

[0019] Compared to an equivalent ferroelectric memory cell with only 1 ppm more chlorine in the ferroelectric layer, the ferroelectric memory cell disclosed herein exhibits a lower time-dependent dielectric collapse rate (TDDB rate) and a lower bias temperature instability (BTI) rate. The time-dependent dielectric collapse rate may not be well represented during short-term operation, but it is consistently judged to have better performance when considering longer-term operation, such as during periods when the leakage current doubles or during periods when the Weibull slope decreases. Therefore, for comparison, the time-dependent dielectric collapse rate can be defined as the initial value of the leakage current divided by the operating time during which the leakage current doubles from its initial value. Alternatively, the time-dependent dielectric collapse rate can be determined during periods when the Weibull slope decreases.

[0020] The ferroelectric layer of the ferroelectric memory cell disclosed herein can be formed from a chlorine-free precursor. The ferroelectric layer of a control ferroelectric memory cell can be formed by adding some chlorinated precursor to the process gas mixture. The control ferroelectric memory cell will have a greater time-dependent dielectric breakdown rate (TDDB) than the ferroelectric memory cell disclosed herein. In some embodiments, the time-dependent dielectric breakdown rate of the control memory cell having more than 1 ppm of chlorine in the ferroelectric layer is more than twice that of the memory cell disclosed herein. In some embodiments, the bias temperature instability (BTI) rate (defined as the rate at which the critical voltage changes during continuous operation) is half or less of that of the control memory cell.

[0021] Figure 1A illustrates an integrated circuit device 100A having a memory cell 101A according to some aspects of this disclosure. The memory cell 101A includes a ferroelectric layer 107A in a transistor structure. The transistor structure includes a gate electrode 105A, an alloy work function metal layer 121A, a second work function metal layer 123A, the ferroelectric layer 107A, an insulating layer 109A, a channel layer 111A, a source coupling 117A, and a drain coupling 113A. The ferroelectric layer 107A is located between the channel layer 111A and the gate electrode 105A. The insulating layer 109A is an optional film layer between the ferroelectric layer 107A and the channel layer 111A. The insulating layer 109A and the ferroelectric layer 107A are in direct contact at an interface 128A.

[0022] The gate electrode 105A, the alloy work function metal layer 121A, and the second work function metal layer 123A are located within the substrate 103A below the ferroelectric layer 107A. In this configuration, the gate electrode 105A is the bottom electrode. The source coupling 117A and the drain coupling 113A can be vias in the interlayer dielectric 115A. Each of the above structures has less than 1 ppm of chlorine.

[0023] The alloy work function metal layer 121A is located between the second work function metal layer 123A and the ferroelectric layer 107A. The second work function metal layer 123A is located between the gate electrode 105A and the alloy work function metal layer 121A. The alloy work function metal layer 121A and the ferroelectric layer 107A are in direct contact at interface 126A. The second work function metal layer 123A and the ferroelectric layer 107A are in direct contact at interface 124A. The gate electrode 105A and the ferroelectric layer 107A are in direct contact at interface 122A.

[0024] In some embodiments, the ferroelectric layer 107A is an HfZrO film. In some embodiments, the chemical formula of the ferroelectric layer 107A is HF xZr 1-xO 2, where x is in the range of 0 to 1. In some embodiments, the ferroelectric layer 107A is HF xZr 1-xO 2, where x is in the range of 0.1 to 0.9. In some embodiments, the ferroelectric layer 107A is HF 0.5Zr 0.5O 2. In some embodiments, the HFZrO in the ferroelectric layer 107A has a combination of more than 50% of the t phase (tetragonal), the o phase (orthorhombic), and the c phase (cubic), and less than 50% of the m phase (monoclinic). In some embodiments, the HFZrO is doped with ions with smaller radii that can increase 2Pr. The smaller radii include ions such as aluminum (Al) and silicon (Si). In some embodiments, HFZrO is doped with ions that have a larger radius, which can increase 2Pr. These larger radius ions include ions such as lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), thorium (Gd), and yttrium (Y). The aforementioned 2Pr is a measure of the switching polarization of the ferroelectric material. In some embodiments, the ferroelectric layer 107A has oxygen vacancies.

[0025] In some embodiments, the ferroelectric layer 107A is aluminum nitride (AlN) doped with scandium (Sc) or the like. The ferroelectric layer 107A may be replaced with other ferroelectric materials. Examples of other ferroelectric materials may include, but are not limited to, hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium thionium oxide (HfGdO), or similar ferroelectric materials.

[0026] The thickness of the ferroelectric layer 107A can be from 0.1 nanometers to 100 nanometers. In some embodiments, the thickness of the ferroelectric layer 107A is from 1 nanometer to 30 nanometers. If the ferroelectric layer 107A is too thin, it may not be able to provide sufficient critical voltage switching in the memory cell 101A. If the ferroelectric layer 107A is too thick, it may not have the required oxygen vacancy concentration. The ferroelectric layer 107A has a uniform thickness, a characteristic formed by an atomic layer deposition (ALD) process, and contains less than 1 ppm of chlorine. In some embodiments, the ferroelectric layer 107A does not contain chlorine.

[0027] The insulating layer 109A is a dielectric. In some embodiments, the insulating layer 109A has a thickness ranging from 0.1 nanometers to 10 nanometers. In some embodiments, the insulating layer 109A has a thickness ranging from 0.3 nanometers to 3 nanometers. If the insulating layer 109A is too thin, it may not function properly. If the insulating layer 109A is too thick, it may interfere with the operation of the memory cell 101A. The insulating layer 109A has a uniform thickness, a characteristic formed by an atomic layer deposition (ALD) process, and contains less than 1 ppm of chlorine.

[0028] The insulating layer 109A may comprise silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), lanthanum (La), strontium (Sr), thorium (Gd), scandium (Sc), calcium (Ca), compounds thereof, combinations thereof, or similar materials. In some of the foregoing embodiments, the insulating layer 109A comprises compounds of two or more metals. In some embodiments, the insulating layer 109A comprises hafnium oxide (HfO2). In some embodiments, the insulating layer 109A comprises compounds containing silicon and metals. In some embodiments, the insulating layer 109A comprises hafnium oxide (HfO2) and silicon (Si). The atomic ratio of silicon to hafnium may be 10% or more. In any of the foregoing embodiments, the insulating layer 109A may be chlorine-free.

[0029] Channel layer 111A is a semiconductor. In some embodiments, channel layer 111A is or comprises an oxide semiconductor. Oxide semiconductors suitable for channel layer 111A include, but are not limited to, zinc oxide (ZnO), magnesium oxide (MgO), thorium oxide (GdO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, or similar materials. In some embodiments, channel layer 111A is or comprises polysilicon, amorphous silicon, silicon germanium (SiGe), or similar materials. In some embodiments, channel layer 111A has a thickness ranging from 0.1 nanometers to 100 nanometers. In some embodiments, channel layer 111A has a thickness ranging from 2 nanometers to 30 nanometers. In some embodiments, channel layer 111A has a thickness ranging from 5 nanometers to 20 nanometers. In some of the foregoing embodiments, channel layer 111A comprises a metal compound and contains less than 1 ppm of chlorine. In some of the foregoing embodiments, channel layer 111A is a compound comprising two different metals and does not contain chlorine.

[0030] The source coupling 117A, drain coupling 113A, and gate electrode 105A can be formed of any suitable conductive material. Such suitable conductive materials may include doped polycrystalline silicon, graphene, metals, and similar materials. In some embodiments, the source coupling 117A, drain coupling 113A, and gate electrode 105A are formed of metal. Some examples of metals that can be used in the aforementioned components are tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), titanium (Ti), tellurium (Te), platinum (Pt), tantalum (Ta), combinations thereof, alloys thereof, or similar materials.

[0031] The source coupling 117A and drain coupling 113A may contain less than 1 ppm of chlorine. In some embodiments, the source coupling 117A and drain coupling 113A are alloys of two or more metals. In some of the foregoing embodiments, each source coupling 117A and drain coupling 113A is chlorine-free. The gate electrode 105A contains less than 1 ppm of chlorine. In some embodiments, the gate electrode 105A is an alloy of two or more metals. In some of the foregoing embodiments, the gate electrode 105A is chlorine-free.

[0032] The second work function metal layer 123A may be a metal compound. Some examples of materials that can be used for the second work function metal layer 123A are titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten nitride (W), tungsten carbide nitride (WCN), zirconium nitride (ZrN), hafnium nitride (HfN), ruthenium oxide (RuOx), and similar materials. The second work function metal layer 123A contains less than 1 ppm of chlorine. In some embodiments, the second work function metal layer 123A comprises an alloy of two or more metals. In some of the foregoing embodiments, the second work function metal layer 123A does not contain chlorine.

[0033] The alloy work function metal layer 121A comprises an alloy of two or more metals. In some embodiments, the alloy work function metal layer 121A comprises an alloy of three or more metals. In some embodiments, the alloy work function metal layer 121A comprises an alloy of four or more metals. The alloy work function metal layer 121A contains less than 1 ppm of chlorine. In some embodiments, the alloy work function metal layer 121A does not contain chlorine. The aforementioned metals may be derived from a cluster of metals including titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), zirconium (Zr), hafnium (Hf), ruthenium (Ru), nickel (Ni), manganese (Mn), palladium (Pd), iron (Fe), cobalt (Co), beryllium (Be), copper (Cu), barium (Ba), thorium (Th), calcium (Ca), strontium (Sr), silver (Ag), yttrium (Y), cerium (Ce), lanthanum (La), lithium (Li), cesium (Cs), and similar metals. The aforementioned metals may form compounds with nitrogen, carbon, oxygen, or similar materials. Specific examples include zirconium-cerium (Zr-Ce), tungsten-beryllium (W-Be), copper-barium (Cu-Ba), tungsten-lanthanum (W-La), tungsten-yttrium (WY), tungsten-zirconium (W-Zr), tungsten-calcium (W-Ca), tungsten-strontium (W-St), tungsten-lithium (W-Li), nickel-barium (Ni-Ba), nickel-cesium (Ni-Cs), molybdenum-thorium (Mo-Th), molybdenum-cesium (Mo-Cs), tantalum-cesium (Ta-Cs), tantalum-thorium (Ta-Th), titanium-cesium (Ti-Cs), silver-barium (Ag-Ba), combinations of other work function metals, and similar materials.

[0034] The interlayer dielectric 115A may be an undoped silicate glass (USG) or a similar material. In some embodiments, the interlayer dielectric 115A is a low-k dielectric. In some embodiments, the interlayer dielectric 115A is an extremely low-k dielectric. A low-k dielectric is a material having a dielectric constant lower than that of silica. Examples of low-k dielectrics include organosilicate glasses (OSG), such as carbon-doped silica, fluorine-doped silica (also known as fluorinated silica glass (FSG)), and low-k dielectrics of organic polymers. Examples of low-dielectric-constant dielectrics from organic polymers include polyarylene ethers, polyimide (PI), benzocyclobbutene, and amorphous polytetrafluoroethylene (PTFE). Ultra-low-dielectric-constant dielectrics are materials having a dielectric constant of about 2.1 or less. Ultra-low-dielectric-constant dielectrics can be formed by depositing a low-dielectric-constant dielectric material, giving it porosity or air-gaps, thereby resulting in a composite material including porosity and air-gaps with an effective dielectric constant of 2.1 or less. Interlayer dielectric 115A contains less than 1 ppm of chlorine. In some embodiments, interlayer dielectric 115A is chlorine-free.

[0035] The substrate 103A may be a die cut from a silicon wafer or the like. The substrate 103A may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 103A is or includes silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, germanium silicon, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium arsenide phosphide, combinations thereof, or similar materials. The substrate 103A may be or include a dielectric material. For example, the substrate 103A may be a dielectric substrate, or may include a dielectric layer located on a semiconductor substrate. The dielectric material may be an oxide, such as silicon oxide; a nitride, such as silicon nitride; a carbide, such as silicon carbide; a combination of the above, such as silicon oxynitride, silicon oxycarbonate, silicon carbonitride; similar materials; or any other suitable dielectric.

[0036] In memory cell 101A, a critical voltage exists on gate electrode 105A at which channel layer 111A begins to conduct between source coupling 117A and drain coupling 113A. This critical voltage can be used for write and erase operations by changing the polarization of the electric dipoles within ferroelectric layer 107A. A first orientation of these electric dipoles provides a first critical voltage representing logic "1", while a second orientation of these electric dipoles provides a second critical voltage representing logic "0".

[0037] A write operation of memory cell 101A may include setting the gate electrode 105A to a programmed voltage Vth, while grounding the source coupling 117A and the drain coupling 113A. Vth may be the highest possible threshold voltage of memory cell 101A. For an erase operation, the gate electrode 105A may be set to -Vth, while grounding the source coupling 117A and the drain coupling 113A. A read operation may include setting the gate electrode 105A to an intermediate voltage between a first threshold voltage and a second threshold voltage, such as ½Vth, setting the source coupling 117A to Vdd, grounding the drain coupling 113A, and determining whether the generated current is higher or lower than the threshold value. The operation of memory cell 101A includes combinations of read, write, and erase operations. Specific operating protocols may be set to determine the time-dependent dielectric collapse (TDDB) rate or the bias temperature instability (BTI) rate. In some embodiments, the operating protocol includes applying a constant voltage stress (CVS). To determine the rate of bias temperature instability, small gate voltage pulses can be applied to measure Vth while maintaining the voltage stress continuously.

[0038] Figure 1B illustrates an integrated circuit device 100B having a memory cell 101B, according to some other aspects of this disclosure. The memory cell 101B has a transistor structure, including a source region 118B, a drain region 104B, a channel 111B, a ferroelectric layer 107B, an insulating layer 109B, an alloy work function metal layer 121B, a second work function metal layer 123B, and a gate electrode 105B. The source region 118B, drain region 104B, and channel 111B are provided by a semiconductor portion of a substrate 103B. The source region 118B and drain region 104B have one doping type, and the channel 111B has the opposite doping type. A source coupling 117B is connected to the source region 118B. A drain coupling 113B is connected to the drain region 104B. Source coupling 117B and drain coupling 113B are vias in the interlayer dielectric 115B and can be connected to the metal interconnect structure formed above the substrate 103B. Gate electrode 105B is located above the ferroelectric layer 107B and the channel 111B. In this configuration, gate electrode 105B is the top gate.

[0039] The above description of gate electrode 105A applies to gate electrode 105B. The above description of alloy work function metal layer 121A applies to alloy work function metal layer 121B. The above description of second work function metal layer 123A applies to second work function metal layer 123B. The above description of ferroelectric layer 107A applies to ferroelectric layer 107B. The above description of insulating layer 109A applies to insulating layer 109B. The above description of substrate 103A applies to substrate 103B, provided that channel 111B is semiconductor. The above description of source coupling 117A applies to source coupling 117B. The above description of drain coupling 113A applies to drain coupling 113B.

[0040] Although the memory cell 101B has been described as a memory cell, the same material configuration can be used for related metal oxide semiconductor field-effect transistors (MOSFETs) with metal oxide semiconductor structures. While a different thickness may be more suitable for this application, the ferroelectric layer 107B with the same composition can be used as a high-k dielectric layer. As in memory cell applications, a low chlorine content is beneficial for achieving low time-dependent dielectric breakdown (TDDB).

[0041] Figure 2 illustrates an integrated circuit device 200 having a 1T1C memory device according to some aspects of this disclosure, which includes a transistor 227 and a ferroelectric capacitor 235. The ferroelectric capacitor 235 is contained in a ferroelectric layer 107C between a top electrode 237 and a bottom electrode 211. A first alloy work function metal layer 121C is located between the top electrode 237 and the ferroelectric layer 107C and is in direct contact with the ferroelectric layer 107C. A second alloy work function metal layer 121D is located between the bottom electrode 211 and the ferroelectric layer 107C, and is also in direct contact with the ferroelectric layer 107C.

[0042] A ferroelectric capacitor 235 is disposed in a metal interconnect 223 located above the semiconductor substrate 239. The metal interconnect 223 includes lines 231 and vias 233, which may be surrounded by an interlayer dielectric 115C. The ferroelectric capacitor 235 may be disposed between the third and fourth metal layers, the fourth and fifth metal layers, or any other adjacent pair of metal layers in the metal interconnect 223. The transistor 227 may include a gate 225 and a gate dielectric 229 disposed above a doped region 228 of the semiconductor substrate 239. The source / drain region 221 may be provided by other regions of the semiconductor substrate 239 having opposite doping types.

[0043] The ferroelectric capacitor 235 can serve as a memory cell by applying a suitable voltage to the word line (WL), bit line (BL), and source line (SL). If the ferroelectric layer 107C has a suitable thickness and a suitable operating mode, it will store data according to the polarization of the electric dipole. In this case, the ferroelectric capacitor 235 is a ferroelectric memory cell. If the ferroelectric layer 107C has a suitable thickness and a suitable operating mode, it will store data according to the charge on the capacitor. In this case, the ferroelectric capacitor 235 is a dynamic random access memory (DRAM) cell.

[0044] Ferroelectric layer 107C is a material having a compositional substitute as described for ferroelectric layer 107A. Similarly, interlayer dielectric 115C has a compositional substitute for interlayer dielectric 115A. The above description of alloy work function metal layer 121A applies to each of the first alloy work function metal layer 121C and the second alloy work function metal layer 121D.

[0045] Figures 3A, 3B, 3C, 4, 5, and 6 are schematic cross-sectional views illustrating a method for forming a memory unit according to the present disclosure. While Figures 3A, 3B, 3C, 4, 5, and 6 are described with reference to various embodiments of the method, it should be understood that the structures depicted in Figures 3A, 3B, 3C, 4, 5, and 6 are not limited to the described method but can be independent of it. Although Figures 3A, 3B, 3C, 4, 5, and 6 are described as a series of actions, it should be understood that the order of actions can be changed in other embodiments. Although Figures 3A, 3B, 3C, 4, 5, and 6 illustrate and describe a specific set of actions, some actions illustrated and / or described may be omitted in other embodiments. Furthermore, actions not illustrated and / or not described may be included in other embodiments. Although the methods described in Figures 3A, 3B, 3C, 4, 5 and 6 are for forming an integrated circuit device 100A, the above methods can be used to form other integrated circuit devices.

[0046] As shown in the cross-sectional schematic diagram 300 of Figure 3A, the above method can first form a mask 303 and use it to etch the trench 301 in the substrate 103A. The etching process can be dry etching. The mask 303 can be formed using an optical lithography process. After etching, the mask 303 can be stripped.

[0047] As illustrated in the cross-sectional schematic diagram 320 of Figure 3B, a gate electrode 105A, a second work function metal layer 123A, and an alloy work function metal layer 121A can be sequentially formed to fill the trench 301. The work function metal layer 121A is formed from a gaseous precursor by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a similar process, wherein the gaseous precursor is chlorine-free. The second work function metal layer 123A can be deposited by atomic layer deposition, chemical vapor deposition, physical vapor deposition (PVD), a similar process, or any other suitable process. In some embodiments, the second work function metal layer 123A is formed from a gaseous precursor by atomic layer deposition, chemical vapor deposition, or a similar process, wherein the gaseous precursor is chlorine-free. The gate electrode 105A can be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless electroplating, a similar process, or any other suitable material. In some embodiments, the gate electrode 105A is formed from a gaseous precursor by atomic layer deposition, chemical vapor deposition, or a similar process, wherein the gaseous precursor is chlorine-free. Processes using gaseous precursors are more suitable for forming alloys and other composite components. Compared to chemical vapor deposition, atomic layer deposition allows for more precise control of composition. Furthermore, atomic layer deposition also allows for precise control of film thickness.

[0048] As shown in the cross-sectional schematic diagram 340 of Figure 3C, planarization can be used to remove multiple portions of the gate electrode 105A, the second work function metal layer 123A, and the alloy work function metal layer 121A deposited outside the trench 301. The planarization process can be chemical mechanical polishing (CMP) or a similar process.

[0049] As illustrated in the cross-sectional schematic diagram 400 of Figure 4, the method may continue to form the ferroelectric layer 107A. The ferroelectric layer 107A is formed using a chlorine-free gaseous precursor by chemical vapor deposition (CVD), atomic layer deposition (ALD), or a similar process. In some embodiments, the ferroelectric layer 107A is formed by atomic layer deposition, as will be described more fully below. Atomic layer deposition provides precise control over the film thickness and also facilitates the adjustment of the addition of dopants, such as aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), thorium (Gd), yttrium (Y), and similar materials. When these dopants are included, they are provided by a chlorine-free gaseous precursor.

[0050] As illustrated in the cross-sectional schematic diagram 500 of Figure 5, the method may continue to form the insulating layer 109A and the channel layer 111A. The insulating layer 109A and the channel layer 111A may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), a combination thereof, or similar processes, or any other suitable one or more processes. In some embodiments, the aforementioned film layers are formed from chlorine-free precursors. In some embodiments, the insulating layer 109A is formed by atomic layer deposition (ALD). Atomic layer deposition allows for precise control of the thickness of the insulating layer. CVD and Atomic layer deposition processes are advantageous for forming insulating layers having silicon-metal composites, silicon-two-metal composites, or silicon-two-more-metal composites. Atomic layer deposition allows for the most accurate control of composition.

[0051] As illustrated in the cross-sectional schematic diagram 600 of Figure 6, the method may continue to form an interlayer dielectric 115A on the channel layer 111A. The interlayer dielectric 115A may be formed by chemical vapor deposition (CVD), liquid processing, such as a spin-on-glass process, or a similar process. In some embodiments, the interlayer dielectric 115A is an undoped silicate glass (USG) formed by chemical vapor deposition using silane (SiH4) or tetraethyl orthosilicate (TEOS).

[0052] As further illustrated in Figure 6, a photoresist mask 601 can be formed and used to etch trenches 603 in the interlayer dielectric 115A. Etching trenches 603 may include dry etching processes, such as plasma etching or any other suitable process. Trenches 603 can be filled with a conductive material through atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, electroless plating, similar processes, or any other suitable process, and then planarized to form the structure illustrated in Figure 1A. Planarization can be chemical mechanical polishing (CMP) or any other suitable process. In some embodiments, trenches 603 are filled from a gaseous precursor by atomic layer deposition, chemical vapor deposition, or a similar process, and the gaseous precursor is chlorine-free. The use of gaseous precursors and atomic layer deposition is particularly advantageous for precise control of the filling composition.

[0053] Figure 7 provides a schematic flow diagram illustrating the process 700 for forming an integrated circuit device as shown in this disclosure. Process 700 includes steps for forming the integrated circuit device 100A of Figure 1A, and also includes a method for forming a ferroelectric layer 107A, which can be used to form other ferroelectric layers in other embodiments of this disclosure. Although process 700 in Figure 7 is illustrated and described in this disclosure as a series of actions or events, it should be understood that the order of these illustrated actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events illustrated and / or described in this disclosure, some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all illustrated actions are required to be performed in one or more aspects or embodiments described in this disclosure, and one or more actions described in this disclosure may be performed in one or more separate actions and / or stages.

[0054] Process 700 can begin with action 701, etching trenches in the substrate. A cross-sectional schematic diagram 300 of Figure 3A is provided as an example.

[0055] Process 700 continues with operation 702, forming a bottom electrode; operation 703, depositing a second work function metal layer; and operation 704, depositing an alloy work function metal layer. A cross-sectional schematic diagram 320 in Figure 3B is provided as an example. The aforementioned film layer can be deposited in the trench formed in operation 701. The aforementioned film layer can be formed from a chlorine-free gaseous precursor.

[0056] Action 705 is chemical mechanical polishing (CMP). A cross-sectional schematic diagram 340 in Figure 3C is provided as an example.

[0057] Action 706 is to form a ferroelectric layer. A cross-sectional schematic diagram 400 of Figure 4 is provided as an example. It should be understood that the ferroelectric layer disclosed herein can be formed in different structures or at different stages of the process. Action 706 may include an atomic layer deposition (ALD) process, further illustrated by actions 711, 713, 715, 717, 719, 721, 723, and 725.

[0058] After forming the ferroelectric layer, process 700 may continue with operation 707, forming an insulating layer; and operation 708, forming a channel layer. A cross-sectional schematic diagram 500 in Figure 5 is provided as an example. Forming the insulating layer is optional. The insulating layer and the channel layer may be formed from a chlorine-free gaseous precursor.

[0059] Action 709 is to form the source and drain structure. A cross-sectional schematic diagram 600 in Figure 6 is provided as an example in conjunction with Figure 1A. The source and drain structure can be formed from a chlorine-free gaseous precursor.

[0060] Action 706, forming a ferroelectric layer, which may be atomic layer deposition (ALD). Atomic layer deposition involves periodically repeating a series of steps to uniformly deposit the ferroelectric layer at a controlled rate. As illustrated, the atomic layer deposition process may begin from action 711 by pulsing with water vapor or the like.

[0061] A pulse refers to the introduction of a reagent into the process gas stream within a finite time period. The process gas may contain an inert carrier, such as nitrogen or argon, which flows continuously through a chamber containing the substrate. The chamber may be continuously vented by a vacuum system. In some embodiments, the atomic layer deposition (ALD) process is performed at sub-atmospheric pressure. In some embodiments, the process is performed at a pressure of 50 torr or less. In some embodiments, the process is performed at a pressure ranging from about 1 to about 10 torr. In some embodiments, the process is performed at a pressure ranging from about 2 to about 5 torr. Low pressure is beneficial for maintaining the precursor in a gaseous state.

[0062] A layer of water vapor is formed on the surface of the substrate through absorption or adsorption. Water provides the oxygen source in the chemical reaction that forms the ferroelectric layer. Another suitable oxygen source that can replace water is, for example, O2, O3, or plasma O2 or plasma O3. The pulse continues until the film layer on the surface is formed. In some embodiments, the water pulse duration is 60 seconds or less. In some embodiments, the water pulse duration ranges from 1 second to 10 seconds.

[0063] After a film layer of water forms on the surface, the process can continue to step 713, purging the chamber. The chamber can be purged using a non-reactive gas. The non-reactive gas can be nitrogen. In some embodiments, purging lasts for 30 seconds or less. In some embodiments, purging lasts for 1 to 10 seconds. In some embodiments, purging lasts for 5 seconds or less.

[0064] The process can continue to operation 715, pulsating a chlorine-free zirconium precursor. The chlorine-free zirconium precursor is a zirconium compound that reacts with an oxygen source on the surface to form a zirconium-containing film. A precursor that is easily volatile under these process conditions is selected, whose deposition is limited only by the amount of oxygen source (e.g., water) present on the surface, and has an acceptable reaction rate. In some embodiments, the pulsed zirconium precursor lasts for 60 seconds or less. In some embodiments, the pulsed zirconium precursor lasts for 0.5 to 10 seconds. In some embodiments, the pulsed zirconium precursor lasts for about 1 to about 5 seconds.

[0065] In some embodiments, the zirconium precursor is a zirconium compound in which zirconium is directly bonded to carbon. Bis(methyl-n5-clyclopentadienyl)methoxymethylzirconium (Zr[CH3C5H4]2CH3OCH3 or ZRCMMM) is an example. In some embodiments, the zirconium precursor is a zirconium compound in which zirconium is directly bonded to oxygen. Zirconium(IV) tert-butoxide (Zr[OC(CH3)3]4 or ZTB) is an example. In some embodiments, the zirconium precursor is a zirconium compound in which zirconium is directly bonded to nitrogen. In some embodiments, the zirconium precursor has the form Zr(NR1R2)4, where R1 and R2 are organic functional groups. Tetrakis(dimethylamino)zirconium(IV); Zr[N(CH3)2]4 or TDMAZ) and tetrakis(ethylmethylamido)zirconium(IV); Zr[N(CH3)(C2H5)]4 or TEMAZ) are examples. In some embodiments, the zirconium precursor is one of the substances shown in the table below or an analogue thereof: bis(methyl-η5-cyclopentadienyl)methoxymethylzirconium Bis(methyl-eta-clyclopentadienyl)methoxymethylzirconium Zr[CH3C5H4]2CH3OCH3 Zirconium(IV) tert-butanol Zirconium(IV) tert-butoxide Zr[OC(CH3)3]4 Tetra(dimethylamino)zirconium(IV) Tetrakis(dimethylamino)zirconium(IV) Zr[N(CH3)2]4 Tetra(ethylmethylamino)zirconium (IV) Tetrakis(ethylmethylamido)zirconium(IV) Zr[N(CH3)(C2H5)]4 Bis(cyclopentadienyl)zirconium(IV) Bis(cyclopentadienyl)zirconium(IV) C 10 H 12 Zr bis(methyl-η5-cyclopentadienyl)methoxymethylzirconium Bis(methyl-eta-cyclopentadienyl)methoxymethylzirconium Zr(CH3C5H4)2CH3OCH3 Dimethylbis(pentamethylcyclopentadienyl)zirconium(IV) Dimethylbis(pentamethylcyclopentadienyl)zirconium(IV) C 22 H 36 Zr Tetra(dimethylamino)zirconium(IV) Tetrakis(dimethylamido)zirconium(IV) [(CH3)2N]4Zr Tetra(ethylmethylamino)zirconium (IV) Tetrakis(ethylmethylamido)zirconium(IV) Zr(NCH3C2H5)4 Zirconium dioxide (IV) (bis(2,4-pentanedione)) Zirconium(IV) dibutoxide(bis-2,4-pentanedionate) C 18 H 32 O6Zr Zirconium 2-ethylhexanoate (IV) Zirconium(IV) 2-ethylhexanoate Zr(C8H 15O2)4 Zirconium tetrakis(2,2,6,6-tetramethyl-3,5-heptanedione) Zirconium tetrakis(2,2,6,6-tetramethyl-3,5-heptanedionate) Zr(OCC(CH3)3CHCOC(CH3)3)4

[0066] Following action 715 is action 717, which involves another blow-through. This blow-through can be similar to the blow-through in action 713. Next is action 719, which involves another water pulse similar to action 711; and action 721, which involves yet another blow-through. Actions 719 and 721 can be similar to or the same as actions 711 and 713, and have the same description.

[0067] The process can continue to operation 723, pulsating a chlorine-free hafnium precursor. The chlorine-free hafnium precursor is a hafnium compound that reacts with an oxygen source on the surface to form a hafnium-containing film. A precursor that is easily volatile under these process conditions is selected, whose deposition is limited only by the amount of oxygen source (e.g., water) present on the surface, and has an acceptable reaction rate. In some embodiments, the pulsed hafnium precursor lasts for 60 seconds or less. In some embodiments, the pulsed hafnium precursor lasts for 0.5 to 10 seconds. In some embodiments, the pulsed hafnium precursor lasts for about 1 to about 5 seconds.

[0068] In some embodiments, the hafnium precursor is a hafnium compound in which hafnium is directly bonded to carbon. Bis(methyl-n5-clyclopentadienyl)dimethylhafnium (Hf[CH3C5H4]2CH3OCH3 or HfD-CO2) and bis(methyl-n5-clyclopentadienyl)methoxymethylhafnium (HfCH3OCH3[C5H4]2 or HfD-CO4) are examples. In some embodiments, the hafnium precursor is a hafnium compound in which hafnium is directly bonded to oxygen. In some embodiments, the hafnium precursor is a hafnium compound in which hafnium is directly bonded to nitrogen. In some embodiments, the hafnium precursor has the form Hf(NR1R2)4, wherein R1 and R2 are organic functional groups. Tetrakis(dimethylamino)hafnium(IV); Hf[N(CH3)2]4 or TDMAH) and tetrakis(ethylmethylamido)hafnium(IV); Hf[N(CH3)(C2H5)]4 or TEMAH are examples. In some embodiments, the hafnium precursor is one or more substances described in the following table, or analogues thereof: bis(methyl-n5-cyclopentadienyl)dimethylhafnium Bis(methyl-eta-clyclopentadienyl)dimethylhafnium Hf[CH3C5H4]2CH3OCH3 bis(methyl-η5-cyclopentadiene)methoxymethylhafnium Bis(methyl-eta-clyclopentadienyl)methoxymethylhafnium HfCH3OCH3[C5H4]2 Tetra(dimethylamino)hafnium(IV) Tetrakis(dimethylamino)hafnium(IV) Hf[N(CH3)2]4 Tetra(ethylmethylamino)hafnium(IV) Tetrakis(ethylmethylamido)hafnium(IV) Hf[N(CH3)(C2H5)]4 Dimethylbis(cyclopentadienyl)hafnium(IV) Dimethylbis(cyclopentadienyl)hafnium(IV) (C5H5)2Hf(CH3)2 Hafnium tert-butanol (IV) Hafnium(IV) tert-butoxide Hf[OC(CH3)3]4 Hafnium isopropanol Hafnium isopropoxide isopropanol C 12 H 28 HfO4 Tetra(diethylamino)hafnium(IV) Tetrakis(diethylamido)hafnium(IV) [(CH2CH3)2N]4Hf Tetra(dimethylamino)hafnium(IV) Tetrakis(dimethylamido)hafnium(IV) [(CH3)2N]4Hf Tetra(ethylmethylamino)hafnium(IV) Tetrakis(ethylmethylamido)hafnium(IV) [(CH3)(C2H5)N]4Hf

[0069] Following action 723 is action 725, which involves another cleaning process and repeating these steps until the ferroelectric layer has been established to the desired thickness. In the described process, the actions of incorporating zirconium into the ferroelectric layer are performed alternately with the actions of incorporating hafnium into the ferroelectric layer. Optionally, these actions may be performed in different proportions, or only the zirconium incorporation action may be used, or only the hafnium incorporation action may be used. In some embodiments, one layer is deposited at a frequency of 60 seconds or more. Selecting a suitable precursor allows the desired rate to be achieved.

[0070] In some embodiments, an additional precursor may be added to either the zirconium precursor or the hafnium precursor to provide metal ions. Examples of metal ions that can be provided by the additional precursor include aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), thorium (Gd), yttrium (Y), and similar metal ions. In some embodiments, the additional precursor is one of the substances shown in the table below or an analogue thereof: Tris(2,2,6,6-tetramethyl-3,5-heptanedione)aluminum Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) Al(OCC(CH3)3CHCOC(CH3)3)3 Triisobutylaluminum Triisobutylaluminum Al[(CH3)2CHCH2]3 Trimethylaluminum Trimethylaluminum Al(CH3)3 Tris(dimethylamino)aluminum(III) Tris(dimethylamido)aluminum(III) Al(N(CH3)2)3 (3-aminopropyl)triethoxysilane (3-Aminopropyl)triethoxysilane H2N(CH2)3Si(OC2H5)3 N-sec-butyl(trimethylsilyl)amine N-sec-Butyl(trimethylsilyl)amine C7H 19 NSi 1,3-Diethyl-1,1,3,3-Tetramethyldisilazane 1,3-Diethyl-1,1,3,3-tetramethyldisilazane C8H 23 NSi2 Dodecylcyclohexylsilane Dodecamethylcyclohexasilane (Si(CH3)2)6 Hexamethyldisilane Hexamethyldisilane (Si(CH3)3)2 Hexamethyldisilazane Hexamethyldisilazane (CH3)3SiNHSi(CH3)3 2,4,6,8,10-Pentamethylcyclopentasiloxane 2,4,6,8,10-Pentamethylcyclopentasiloxane (CH3SiHO)5 Pentamethyldisilane Pentamethyldisilane (CH3)3SiSi(CH3)2H Silicon tetrabromide Silicon tetrabromide SiBr4 Tetraethylsilane Tetraethylsilane Si(C2H5)4 2,4,6,8-Tetramethylcyclotetrasiloxane 2,4,6,8-Tetramethylcyclotetrasiloxane (HSiCH3O)4 1,1,2,2-Tetramethyldisilane 1,1,2,2-Tetramethyldisilane (CH3)2SiHSiH(CH3)2 Tetramethylsilane Tetramethylsilane Si(CH3)4 N,N′,N′′-Tri-tert-butylsilanetriamine N,N′,N′′-Tri-tert-butylsilanetriamine HSi(HNC(CH3)3)3 Tris(tert-butoxy)silanol Tris(tert-butoxy)silanol ((CH3)3CO)3SiOH Tris(tert-pentoxy)silanol Tris(tert-pentoxy)silanol (CH3CH2C(CH3)2O)3SiOH Tri[N,N-bis(trimethylsilyl)phenylamine]trimonium(III) Tris[N,N-Bis(trimethylsilyl)amide]gadolinium(III) Gd(N(Si(CH3)3)2)3 Tris(tetramethylcyclopentadienyl)thorium(III) Tris(tetramethylcyclopentadienyl)gadolinium(III) C 27 H 39 Gd Tri(isopropylcyclopentadienyl)hodox Tris(isopropylcyclopentadienyl)gadolinium C 24 H 33 Gd Triethylgallium Triethylgallium (CH3CH2)3Ga Trimethylgallium Ga(CH3)3 Tris(dimethylamino)gallium(III) Tris(dimethylamido)gallium(III) C 12 H 36 Ga2N6 Lanthanum isopropoxide (III) Lanthanum(III) isopropoxide C9H 21 LaO3 Tris[N,N-bis(trimethylsilyl)phenylamine]lanthanum(III) Tris[N,N-bis(trimethylsilyl)amide]lanthanum(III) La(N(Si(CH3)3)2)3 Tri(cyclopentadienyl)lanthanum(III) Tris(cyclopentadienyl)lanthanum(III) La(C5H5)3 Lanthanum (2,2,6,6-tetramethyl-3,5-heptadecanoic acid) Lanthanum (2,2,6,6-tetramethyl-3,5-heptanedionato) La(OCC(CH3)3CHCOC(CH3)3)3 Tris(tetramethylcyclopentadienyl)lanthanum(III) Tris(tetramethylcyclopentadienyl)lanthanum(III) C 27 H 39 La Tris[N,N-bis(trimethylsilyl)pyridine]yttrium Tris[N,N-bis(trimethylsilyl)amide]yttrium [[(CH3)3Si]2N]3Y Tris(butylcyclopentadienyl)yttrium(III) Tris(butylcyclopentadienyl)yttrium(III) Y(C5H4CH2(CH2)2CH3)3 Tris(cyclopentadienyl)yttrium(III) Tris(cyclopentadienyl)yttrium(III) Y(C5H5)3 2-Methoxyethoxyyttrium Yttrium 2-methoxyethoxide C9H 21 O6Y Tri-(isopropanol)yttrium(III) Yttrium(III) tris(isopropoxide) C9H 21 O3Y Tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)yttrium(III) Yttrium(III) tris(2,2,6,6-tetramethyl-3,5-heptanedionate) Y(OCC(CH3)3CHCOC(CH3)3)3

[0071] In some embodiments, the metal ion is aluminum (Al) or the like. In some embodiments, the metal ion is silicon (Si) or the like. In some embodiments, the metal ion is lanthanum (La) or the like. In some embodiments, the metal ion is thorium (Gd) or the like. In some embodiments, the metal ion is yttrium (Y) or the like. In some embodiments, an additional precursor comprises a metal ion directly bonded to oxygen (O), nitrogen (N), carbon (C), or a combination thereof. In some embodiments, an additional precursor comprises a metal ion directly bonded to carbon (C). In some embodiments, an additional precursor comprises a metal ion directly bonded to oxygen (O). In some embodiments, an additional precursor comprises a metal ion directly bonded to only oxygen (O) and / or carbon (C). In some embodiments, an additional precursor comprises a metal ion directly bonded to nitrogen (N).

[0072] Figures 8, 9, 10, 11, 12, and 13 illustrate a cross-sectional side view, representing another method of forming a memory unit according to this disclosure. While Figures 8, 9, 10, 11, 12, and 13 are described with reference to various embodiments of the method, it should be understood that the structures illustrated in Figures 8, 9, 10, 11, 12, and 13 are not limited to the above method but can be independent of it. Although Figures 8, 9, 10, 11, 12, and 13 are described as a series of actions, it should be understood that the order of actions can be changed in other embodiments. Although Figures 8, 9, 10, 11, 12, and 13 illustrate and describe a specific set of actions, some illustrated and / or described actions may be omitted in other embodiments. Furthermore, actions not illustrated and / or not described may be included in other embodiments. Although the methods described in Figures 8, 9, 10, 11, 12 and 13 are in the manner of forming an integrated circuit device 100B, the above methods can be used to form other integrated circuit devices.

[0073] As shown in the cross-sectional schematic diagram 800 of Figure 8, the above method can first form a memory cell stack 801 on the substrate 103B. The memory cell stack 801 may include an insulating layer 109B, a ferroelectric layer 107B, an alloy work function metal layer 121B, a second work function metal layer 123B, and a gate electrode 105B. The process options for forming the aforementioned film layers can be the same as the process options for forming the insulating layer 109A, the ferroelectric layer 107A, the alloy work function metal layer 121A, the second work function metal layer 123A, and the gate electrode 105A, respectively.

[0074] As illustrated in the cross-sectional schematic diagram 900 of Figure 9, a mask 901 can be formed and used to pattern the memory cells 101B from the memory cell stack 801. The mask 901 can be formed using optical lithography. Patterning may involve dry etching. After patterning, the mask 901 can be stripped off.

[0075] As shown in the cross-sectional schematic diagram 1000 of Figure 10, sidewall spacers 125 may be formed around the memory cell 101B. The formation of the sidewall spacers 125 may include deposited spacer material, such as silicon nitride (SiN) or the like, followed by etching.

[0076] As shown in the cross-sectional schematic diagram 1100 of Figure 11, the source region 118B and the drain region 104B can be doped in a self-aligned doping process using the sidewall spacer 125.

[0077] As shown in the cross-sectional schematic diagram 1200 of Figure 12, an interlayer dielectric 115B can be formed above and around the memory cell 101B. The process options for forming the interlayer dielectric 115B can be the same as those for forming the interlayer dielectric 115A.

[0078] As illustrated in the cross-sectional view 1300 of Figure 13, an optical lithography mask 1303 can be used to pattern openings 1301 in the interlayer dielectric 115B. Openings 1301 can be filled to form source couplers 117B and drain couplers 113B, as illustrated in Figure 1B. The process options for filling openings 1301 to form source couplers 117B and drain couplers 113B are the same as those for filling trenches 603 (see Figure 6) to form source couplers 117A and drain couplers 113A.

[0079] Figure 14 provides a schematic flow diagram illustrating the process 1400 for forming an integrated circuit device as shown in this disclosure. Process 1400 includes steps for forming the integrated circuit device 100B of Figure 1B. Although process 1400 of Figure 14 is illustrated and described in this disclosure as a series of actions or events, it should be understood that the order of these illustrated actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events illustrated and / or described in this disclosure, some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all illustrated actions are required to be performed in one or more aspects or embodiments described in this disclosure, and one or more actions described in this disclosure may be performed in one or more separate actions and / or stages.

[0080] Process 1400, from actions 1401, 1403, 1405, 1407 to 1409, forms a stack of memory cells as shown in the cross-sectional schematic diagram 800 of Figure 8. Action 1401 deposits an insulating layer, action 1403 deposits a ferroelectric layer, action 1405 deposits an alloy work function metal layer, action 1407 deposits a second work function metal layer, and action 1409 deposits a gate electrode. The aforementioned actions may be substantially the same as actions 707, 706, 704, 703, and 702 of process 700, respectively.

[0081] Action 1411: Pattern the stack of memory cells to define the memory cells. A cross-sectional view 900 in Figure 9 is provided as an example.

[0082] Action 1413 forms spacers around the memory cells. A cross-sectional view 1000 of Figure 10 is provided as an example.

[0083] Action 1415 places the source and drain regions adjacent to the memory cell. A cross-sectional schematic diagram 1100 in Figure 11 is provided as an example.

[0084] Action 1417 deposits interlayer dielectric material above and around the memory cell. A cross-sectional schematic diagram 1200 of Figure 12 is provided as an example.

[0085] Action 1419 forms an opening in the interlayer dielectric for the connection between the source and drain electrodes. A cross-sectional schematic diagram 1300 of Figure 13 is provided as an example.

[0086] Action 1421 fills the opening with a conductive material to form a source-drain connection. Action 1423 is chemical mechanical polishing (CMP). Figure 1B provides an example of the structure formed.

[0087] In some embodiments, titanium (Ti), titanium nitride (TiN), or some other titanium-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form titanium (Ti), titanium nitride (TiN), similar materials, or other titanium compounds include tetrakis(diethylamido)titanium(IV); [(C2H5)2N]4Ti), tetrakis(dimethylamido)titanium(IV); [(CH3)2N]4Ti), tetrakis(ethylmethylamido)titanium(IV); [(CH3C2H5)N]4Ti, and titanium(IV)diisopropoxidebis(2,2,6,6-tetramethyl-3,5-heptanedionate); Ti[OCC(CH3)3CHCOC(CH 3) 3] 2(OC 3H 7) 2), and similar non-chlorine gaseous precursors.

[0088] In some embodiments, molybdenum (Mo), molybdenum nitride (MoN), or some other molybdenum-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form molybdenum (Mo), molybdenum nitride (MoN), similar materials, or other molybdenum compounds include cyclopentadienyl molybdenum tricarbonyl dimer (C16H10Mo2O6), molybdenum hexacarbonyl (Mo(CO)6), and similar chlorine-free gaseous precursors.

[0089] In some embodiments, nickel (Ni) or nickel-containing compounds are formed from chlorine-free gaseous precursors. Examples that can be used to form chlorine-free gaseous precursors having nickel (Ni) or nickel compounds include bis(cyclopentadienyl)nickel(II); Ni(C5H5)2, bis(ethylcyclopentadienyl)nickel(II); Ni(C5H4C2H5)2, nickel(II)bis(2,2,6,6-tetramethyl-3,5-heptanedionate); Ni(OCC(CH3)3CHCOC(CH3)3)2, and similar chlorine-free gaseous precursors.

[0090] In some embodiments, aluminum (Al), aluminum nitride (AlN), or some other aluminum-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form aluminum (Al), aluminum nitride (AlN), similar materials, or other aluminum compounds include aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate); Al(OCC(CH 3) 3CHCOC(CH 3) 3), aluminum triisobutylaluminum; [(CH 3) 2CHCH 2] 3Al, aluminum trimethylaluminum; (CH 3) 3Al, aluminum tris(dimethylamido)aluminum(III); Al(N(CH 3) 2) 3, and similar chlorine-free gaseous precursors.

[0091] In some embodiments, copper (Cu) or a copper-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form copper (Cu) or a copper compound include copper bis(6,6,7,7,8,8,8-heptafluoro-2,2-dimethyl-3,5-octanedionate); Cu(OCC(CH 3) 3CHCOCF 2CF 2CF 3) 2, copper bis(2,2,6,6-tetramethyl-3,5-heptanedionate); Cu(OCC(CH 3) 3CHCOC(CH 3) 3) 2, and similar chlorine-free gaseous precursors.

[0092] In some embodiments, platinum (Pt) or a platinum-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form platinum (Pt) or a platinum compound include trimethyl(methylcyclopentadienyl)platinum(IV); (C5H4CH3Pt(CH3)3) and similar chlorine-free gaseous precursors.

[0093] In some embodiments, ruthenium (Ru) or a ruthenium-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form ruthenium (Ru) or a ruthenium compound include bis(cyclopentadienyl)ruthenium(II); C10H10Ru, bis(ethylcyclopentadienyl)ruthenium(II); C7H9RuC7H9, triruthenium dodecacarbonyl; Ru3(CO)12, and similar chlorine-free gaseous precursors.

[0094] In some embodiments, tantalum (Ta), tantalum nitride (TaN), or some other tantalum-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form tantalum (Ta), tantalum nitride (TaN), similar materials, or other tantalum compounds include penta(dimethylamino)tantalum (V) (Ta(N(CH3)2)5), tantalum (V) ethoxide (Ta(OC2H5)5), tris(diethylamido)(tert-butylimido)tantalum (V) (CH3)3CNTa(N(C2H5)2)3, tris(ethylmethylamido)(tert-butylimido)tantalum (V) (C13H33N4Ta), and similar chlorine-free gaseous precursors.

[0095] In some embodiments, tungsten (W), tungsten nitride (WN), tungsten carbide (WCN), or some other tungsten-containing compound is formed from a chlorine-free gaseous precursor. Examples of chlorine-free gaseous precursors that can be used to form tungsten (W), tungsten nitride (WN), tungsten carbide (WCN), similar materials, or other tungsten compounds include bis(tert-butylimino)bis(tert-butylamino)tungsten (C4H9NH)2W(C4H9N)2), bis(tert-butylimino)bis(dimethylamino)tungsten (VI) (C10H3NH)2W(C4H9N)2), and bis(cyclopentadienyl)tungsten (IV)dihydride (C10H3NH)2W( ... 12W), bis(isopropylcyclopentadienyl)tungsten(IV)dihydride (C 5H 4CH(CH 3) 2) 2WH 2), tetracarbonyl(1,5-cyclooctadiene)tungsten(O) (C 12H 12O 4W), hexacarbonyltungsten (W(CO) 6), and similar chlorine-free gaseous precursors.

[0096] In some embodiments, the chlorine-free gaseous metal precursor is a metal compound having hydrocarbon functional groups. Each example of a chlorine-free gaseous metal precursor described above is an example of a chlorine-free metal precursor having hydrocarbon functional groups.

[0097] In some embodiments, the chlorine-free gaseous metal precursor is a metal compound having a hydrocarbon functional group. Examples of chlorine-free gaseous metal precursors having hydrocarbon functional groups include cyclopentadienyl molybdenum tricarbonyl dimer (C 16H 10Mo 2O 6), molybdenum hexacarbonyl (Mo(CO) 6), triruthenium dodecacarbonyl (Ru 3(CO) 12), bis(isopropylcyclopentadienyl)tungsten(IV) dihydride ((C 5H 4CH(CH 3) 2) 2WH 2), tungsten hexacarbonyl (W(CO) 6), and similar chlorine-free gaseous metal precursors. The aforementioned compounds can exhibit exceptionally high deposition rates.

[0098] In some embodiments, the chlorine-free gaseous metal precursor is a cyclopentadiene complex. Examples of chlorine-free gaseous metal precursors that are cyclopentadienyl complexes include cyclopentadienyl molybdenum tricarbonyl dimer (C16H10Mo2O6), bis(cyclopentadienyl)nickel(II) (Ni(C5H5)2), bis(ethylcyclopentadienyl)nickel(II) (Ni(C5H4C2H5)2), trimethyl(methylcyclopentadienyl)platinum(IV) (C5H4CH3Pt(CH3)3), and bis(cyclopentadienyl)ruthenium(II) (C10H5) 10Ru), bis(ethylcyclopentadienyl)ruthenium(II); C 7H 9RuC 7H 9, bis(cyclopentadienyl)tungsten(IV)dihydride; C 10H 12W, bis(isopropylcyclopentadienyl)tungsten(IV)dihydride; (C 5H 4CH(CH 3) 2) 2WH 2, and similar chlorine-free cyclopentadiene complex gaseous precursors. Many different metals can be formed into cyclopentadiene complexes. Selecting cyclopentadiene complexes can improve the uniformity and predictability of deposition processes for forming films with various compositions. In some embodiments, the deposition process uses two cyclopentadiene complexes corresponding to two different metals.

[0099] In some embodiments, the chlorine-free gaseous metal precursor is a metal compound having a nitrogen functional group. Examples of chlorine-free gaseous metal precursors that are nitrogen-functionalized metal compounds include tetrakis(diethylamido)titanium(IV); [(C₂H₅)₂N]₄Ti, tetrakis(dimethylamido)titanium(IV); [(CH₃)₂N]₄Ti, tetrakis(ethylmethylamido)titanium(IV); [(CH₃C₂H₅)N]₄Ti, tris(dimethylamido)aluminum(III); Al(N(CH₃)₂)₃, and pentakis(dimethylamino)tantalum(V); Ta(N(CH₃)₂)₃. 5) Tantalum (V) ethoxide; Ta(OC 2H 5) 5) Tris(diethylamido)(tert-butylimido) tantalum (V); (CH 3) 3CNTa(N(C 2H 5) 2) 3) Tris(ethylmethylamido)(tert-butylimido) tantalum (V); C 13H 33N 4Ta, Bis(tert-butylimido)bis(tert-butylamino)tungsten; (C 4H 9NH) 2W(C 4H 9N) 2) Bis(tert-butylimino)bis(dimethylamino)tungsten (VI); ((CH3)3CN)2W(N(CH3)2)2), and similar chlorine-free gaseous metal precursors. The aforementioned compounds may be particularly useful in the formation of nitrogen-containing metal compounds.

[0100] Some aspects of this disclosure relate to integrated circuit devices comprising a ferroelectric layer having less than 1 ppm of chlorine. In some embodiments, the ferroelectric layer is HfxZr1-xO2, where 0 ≤ x ≤ 1. In some embodiments, the ferroelectric film is part of a memory cell. In some embodiments, a work function metal layer is in direct contact with the ferroelectric layer and has less than 1 ppm of chlorine. In some embodiments, the work function metal layer comprises an alloy of two different metals. In some embodiments, a second work function metal layer is also in direct contact with the ferroelectric layer and has less than 1 ppm of chlorine. In some embodiments, a gate electrode is also in direct contact with the ferroelectric layer and has less than 1 ppm of chlorine.

[0101] Some aspects of this disclosure relate to an integrated circuit device including a memory cell, the memory cell including a channel extending between a source and a drain, a gate electrode, and a ferroelectric layer located between the gate electrode and the channel. The memory cell has a leakage current and a time-dependent dielectric collapse (TDDB) rate. The time-dependent dielectric collapse rate is defined as the initial value of the leakage current divided by the operating time during which the leakage current doubles from the initial value. The time-dependent dielectric collapse rate is less than the increase in the time-dependent dielectric collapse rate when 1 ppm of chlorine is added to the ferroelectric layer.

[0102] Some aspects of this disclosure relate to methods for forming integrated circuit devices, which include forming a ferroelectric layer using a chlorine-free precursor by atomic layer deposition (ALD). In some embodiments, the chlorine-free precursor comprises a zirconium (Zr) precursor or a hafnium (Hf) precursor. In some embodiments, the method further comprises forming a work function metal layer from the chlorine-free gaseous precursor, wherein the work function metal layer is in direct contact with the ferroelectric layer. In some embodiments, the work function metal layer is an alloy work function metal layer. In some embodiments, the chlorine-free gaseous precursor comprises a metal compound having a hydrocarbon functional group. In some embodiments, the chlorine-free gaseous precursor comprises a metal compound having a carbonyl functional group. In some embodiments, the chlorine-free gaseous precursor comprises a metal compound having a nitrogen functional group. In some embodiments, the chlorine-free gaseous precursor comprises a metal in a cyclopentadiene complex.

[0103] Some aspects of this disclosure relate to an integrated circuit device comprising a ferroelectric layer having a chlorine content of less than 1 ppm. In some embodiments, the integrated circuit device further comprises a first work function metal layer in direct contact with the ferroelectric layer, wherein the first work function metal layer has a chlorine content of less than 1 ppm. In some embodiments, the first work function metal layer comprises an alloy of two metals. In some embodiments, the integrated circuit device further comprises a metal electrode and a second work function metal layer in direct contact with the first work function metal layer, the second work function metal layer being disposed between the first work function metal layer and the metal electrode, and the second work function metal layer having a chlorine content of less than 1 ppm. In some embodiments, the metal electrode is in direct contact with the ferroelectric layer, and the metal electrode has a chlorine content of less than 1 ppm. In some embodiments, the integrated circuit device further comprises a second work function metal layer in direct contact with the ferroelectric layer, the second work function metal layer having a chlorine content of less than 1 ppm, the ferroelectric layer being located between the first work function metal layer and the second work function metal layer. In some embodiments, the second work function metal layer comprises an alloy of two metals.

[0104] Some aspects of this disclosure relate to an integrated circuit device including a memory cell comprising a ferroelectric layer. The memory cell has a leakage current and a time-dependent dielectric collapse rate, the time-dependent dielectric collapse rate being defined as an initial value of the leakage current divided by the operating time during which the leakage current doubles from the initial value, and the time-dependent dielectric collapse rate being less than the amount by which the time-dependent dielectric collapse rate increases when 1 ppm of chlorine is added to the ferroelectric layer. In some embodiments, the memory cell further includes a gate electrode and a channel extending between a source and a drain electrode, and the ferroelectric layer being located between the gate electrode and the channel. In some embodiments, the integrated circuit device further includes a first work function metal layer in direct contact with the ferroelectric layer, the first work function metal layer being located between the ferroelectric layer and the gate electrode, and the first work function metal layer having less than 1 ppm of chlorine. In some embodiments, the first work function metal layer comprises an alloy of two metals. In some embodiments, the integrated circuit device further includes a second work function metal layer in direct contact with the first work function metal layer, the second work function metal layer being disposed between the first work function metal layer and the gate electrode, and the second work function metal layer having less than 1 ppm of chlorine. In some embodiments, the integrated circuit device further includes a bottom electrode and a top electrode, a ferroelectric layer being located between the bottom electrode and the top electrode, and the bottom electrode being coupled to the source region or drain region of the transistor. In some embodiments, the integrated circuit device further includes a first work function metal layer in direct contact with the ferroelectric layer, the first work function metal layer having less than 1 ppm of chlorine. In some embodiments, the first work function metal layer comprises an alloy of two metals.

[0105] Some aspects of this disclosure relate to a method of forming an integrated circuit device, including forming a memory cell comprising a ferroelectric layer, wherein the step of forming the memory cell includes depositing the ferroelectric layer from a plurality of chlorine-free gaseous precursors. In some embodiments, the step of forming the memory cell further includes depositing a work function metal layer from the chlorine-free gaseous precursors, and bringing the work function metal layer into direct contact with the ferroelectric layer. In some embodiments, the step of forming the memory cell further includes depositing electrodes of the memory cell from the chlorine-free gaseous precursors by atomic layer deposition. In some embodiments, the gaseous precursors comprise a metal compound having a carbonyl functional group. In some embodiments, the gaseous precursors comprise a metal in a cyclopentadiene complex.

[0106] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0006] The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention. Figure 1A is a cross-sectional side view schematic diagram of an integrated circuit device according to some aspects of this disclosure. Figure 1B is a cross-sectional side view schematic diagram of an integrated circuit device according to some other aspects of this disclosure. Figure 2 is a cross-sectional side view schematic diagram of an integrated circuit device according to some other aspects of this disclosure. Figures 3A, 3B, 3C, 4, 5, and 6 are illustrated, showing a series of cross-sectional side views, illustrating a method for forming an apparatus such as Figure 1A according to this disclosure. Figure 7 provides a flowchart illustrating a method for forming an integrated circuit device including a ferroelectric layer as shown in this disclosure. Figures 8, 9, 10, 11, 12, and 13 illustrate a series of cross-sectional side views illustrating a method for forming an apparatus such as that in Figure 1B according to this disclosure. Figure 14 provides a flowchart illustrating a method for forming an integrated circuit apparatus including a ferroelectric layer as shown in this disclosure.

Claims

1. An integrated circuit device, comprising: An apparatus comprising: a ferroelectric layer, wherein the ferroelectric layer has less than 1 ppm of chlorine.

2. The integrated circuit device as claimed in claim 1 further includes: A first work function metal layer is in direct contact with the ferroelectric layer, wherein the first work function metal layer has less than 1 ppm of chlorine.

3. The integrated circuit device as claimed in claim 2, wherein the first work function metal layer comprises: An alloy of two metals.

4. The integrated circuit device as claimed in claim 3 further includes: A metal electrode; And a second work function metal layer, wherein the second work function metal layer is in direct contact with the first work function metal layer, and the second work function metal layer is disposed between the first work function metal layer and the metal electrode, and the second work function metal layer has less than 1 ppm of chlorine.

5. An integrated circuit device as claimed in claim 4, wherein: The metal electrode is in direct contact with the ferroelectric layer, and the metal electrode has less than 1 ppm of chlorine.

6. The integrated circuit device as claimed in claim 2 further includes: A second work function metal layer is in direct contact with the ferroelectric layer, wherein the second work function metal layer has less than 1 ppm of chlorine, and the ferroelectric layer is located between the first work function metal layer and the second work function metal layer.

7. The integrated circuit device of claim 6, wherein the second work function metal layer comprises: An alloy of two metals.

8. An integrated circuit device, comprising: A memory cell includes: a ferroelectric layer, wherein the memory cell has a leakage current and a time-dependent dielectric breakdown (TDDB) rate, wherein the TDDB rate is defined as an initial value of the leakage current divided by an operating time in which the leakage current doubles from the initial value, and the TDDB rate is less than the amount by which the TDDB rate increases when 1 ppm of chlorine is added to the ferroelectric layer.

9. An integrated circuit device as claimed in item 8, wherein: The memory cell further includes: a gate electrode and a channel extending between a source electrode and a drain electrode, and the ferroelectric layer located between the gate electrode and the channel.

10. The integrated circuit device as claimed in claim 9 further includes: A first work function metal layer is in direct contact with the ferroelectric layer, wherein the first work function metal layer is located between the ferroelectric layer and the gate electrode, and the first work function metal layer has less than 1 ppm of chlorine.

11. The integrated circuit arrangement of claim 10, wherein the first work function metal layer comprises: An alloy of two metals.

12. The integrated circuit device as claimed in claim 11 further includes: A second work function metal layer, wherein the second work function metal layer is in direct contact with the first work function metal layer, and the second work function metal layer is disposed between the first work function metal layer and the gate electrode, and the second work function metal layer has less than 1 ppm of chlorine.

13. The integrated circuit device as claimed in claim 10 further includes: A bottom electrode and a top electrode, wherein the ferroelectric layer is located between the bottom electrode and the top electrode, and the bottom electrode is coupled to a source region or a drain region of a transistor.

14. The integrated circuit device as claimed in claim 8 further includes: A first work function metal layer is in direct contact with the ferroelectric layer, wherein the first work function metal layer has less than 1 ppm of chlorine.

15. The integrated circuit device of claim 14, wherein the first work function metal layer comprises: An alloy of two metals.

16. A method for forming an integrated circuit device, comprising: A memory cell is formed, the memory cell comprising: a ferroelectric layer, wherein the step of forming the memory cell comprises: forming the ferroelectric layer by deposition from a plurality of chlorine-free gaseous precursors.

17. A method for forming an integrated circuit device as claimed in claim 16, wherein: The steps for forming the memory cell further include: depositing a work function metal layer from the chlorine-free gaseous precursor; and bringing the work function metal layer into direct contact with the ferroelectric layer.

18. The method of forming an integrated circuit device as claimed in claim 16, wherein the step of forming the memory cell further includes: An electrode of the memory cell is formed by depositing the chlorine-free gaseous precursor using atomic layer deposition (ALD).

19. A method of forming an integrated circuit device as claimed in claim 16, wherein the gaseous precursor comprises: A monometallic compound having a carbonyl functional group.

20. A method of forming an integrated circuit device as claimed in claim 16, wherein the gaseous precursor comprises: A metal in a cyclopentadiene complex.

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