Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions

Abstract

Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.

Description

[Technical Field]

[0001] The embodiments disclosed herein belong to the field of integrated circuit structure and processing, specifically, a gate-all-around integrated circuit structure having a source or drain structure including a substrate connection portion, and a method for manufacturing a gate-all-around (GAA) integrated circuit structure having a source or drain structure including a substrate connection portion. [Previous Technology]

[0002] For decades, the shrinking of features in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Shrinking features to ever smaller sizes allows for increased density of functional units within the limited area of ​​a semiconductor wafer. For example, shrinking transistor size allows for the integration of a greater number of memory or logic devices on a single wafer, facilitating the manufacture of products with increased capacity. However, this drive for greater capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0003] In the fabrication of integrated circuit devices, as device dimensions continue to shrink, multi-gate transistors, such as three-gate transistors, are becoming more common. In conventional processes, three-gate transistors are typically fabricated on a bulk silicon substrate or a silicon-on-insulator substrate. In some cases, a bulk silicon substrate is a preferred choice because of its lower cost and because it allows for less complex three-gate processes. On the other hand, as microelectronic device dimensions shrink to below the 10-nanometer (nm) node, maintaining improved mobility and short-channel control poses challenges to device fabrication. The nanometer lines used to fabricate devices provide improved short-channel control.

[0004] However, shrinking multi-gate and nanowire transistors does not come without consequences. As the size of these fundamental components of microelectronic circuits decreases and the absolute number of fundamental components fabricated in a given area increases, the limitations on the lithography processes used to pattern these components become unavoidable. In particular, there may be trade-offs between the minimum size (critical size) of the features patterned in a semiconductor stack and the spacing between these features. [Summary of the Invention]

[0005] and

Implementation Method

[0018] This document describes a gate-all-around integrated circuit structure having a source or drain structure including a substrate connection portion, and a method for manufacturing a gate-all-around integrated circuit structure having a source or drain structure including a substrate connection portion. In the following description, numerous specific details, such as particular integration and material matching, are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

[0019] Certain terms may also be used in the following description for illustrative purposes only and are not intended to be limiting. For example, terms such as “up,” “down,” “above,” and “below” refer to directions referenced in the diagrams. Terms such as “front,” “back,” “rear,” and “side” indicate the orientation and / or position of a component portion within any reference frame that becomes clear through the reference text and the relevant diagrams describing the component under discussion. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0020] The embodiments described herein are applicable to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0021] The embodiments described herein are applicable to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, such as one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for wafer-to-package connections. During the manufacturing phase of BEOL, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processing, more than 10 metal layers may be added to the BEOL.

[0022] The embodiments described below are applicable to FEOL processing and structures, BEOL processing and structures, or FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme can be illustrated using an FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using a BEOL processing scenario, such a method can also be applied to FEOL processing.

[0023] One or more embodiments described herein are directed to epitaxial growth of a substrate connected to a gate-all-around (GAA) transistor. One or more embodiments described herein are directed to implanted surfactant catalysts for defect mitigation selective GAAs used in PMOS source or drain epitaxy. Embodiments include gate-all-around (GAA) integrated circuits or FinFET transistor architectures. It should be understood that, unless otherwise stated, nanowires mentioned herein may refer to nanowires, nanoribbons, or nanosheets.

[0024] In the first state sample, the implementation of epitaxial growth of the substrate connected to the gate-all-around (GAA) transistor is described.

[0025] For background purposes, conventional GAA transistors do not have epitaxial-to-substrate connections. This can result in poor epitaxial growth quality and a lack of channel strain due to epitaxy. The lack of proper substrate connections leads to poor epitaxial quality and the inability to apply any strain in the channels.

[0026] According to one or more embodiments of this disclosure, an additional etching process is performed prior to epitaxial growth to remove any residue / dielectric material under the epitaxial layer, ensuring a clean substrate for epitaxial growth. Bottom-up epitaxial growth chemistry can be used to develop substrate connections and provide good channel strain with minimal defects.

[0027] In one embodiment, TEM of the line-end of the gate cut on the channel and the epitaxial cut between the gates confirms a good epitaxial-to-substrate connection. Elemental analysis and SIMS characterization confirm the epitaxial growth profile. The absence of any seams or voids at the bottom of the epitaxial layer demonstrates the bottom-up epitaxial growth chemistry, indicating the implementation of the embodiments described herein. The gate cut on the channel showing a healthy epitaxial-to-substrate connection without any seams or voids at the bottom of the epitaxial layer indicates the implementation of the embodiments described herein.

[0028] As an exemplary structure, FIG1 shows a cross-sectional view of a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion according to an embodiment of the present disclosure. It should be understood that, more generally, the described source or drain structure may be adjacent to nanowire stacks, nanoribbon stacks, or fins.

[0029] Referring to FIG1, the integrated circuit structure 100 includes a substrate 102, such as a silicon substrate, having sub-fins 104 projecting therefrom. A plurality of nanowires 108, such as silicon nanowires, are located above the sub-fins 104. A dielectric cap 112, such as a silicon nitride cap, may be located above the plurality of nanowires 108. In another embodiment, the dielectric cap 112 is not included. Gate spacers, such as dielectric gate spacers 116A and internal spacers 116B, are also included in the integrated circuit structure 100.

[0030] Referring again to FIG1, epitaxial source or drain structures 124 are included at the ends of a plurality of nanowires 108. Each epitaxial source or drain structure 124 includes an upper portion 124B and a lower epitaxial extension 124A. In one embodiment, the upper portion 124B and the lower epitaxial extension 124A are continuous, as shown. In one embodiment, the lateral width of the upper portion 124B is greater than the lateral width of the lower epitaxial extension 124A, also as shown. In one embodiment, the lowermost surface of the lower epitaxial extension 124A is lower than the uppermost surface of the sub-fin 104, as shown.

[0031] Referring again to FIG1, gate structures are included on and around the plurality of nanowires 108. The gate structures may include a high-k gate dielectric layer 126 and a metal gate electrode 128. Additional features may include conductive contacts 130 and / or additional spacers or interlayer dielectric material 132. In one embodiment, the conductive contacts 130 are in direct contact with their counterparts in the upper portion 124B of the epitaxial source or drain structure 124, as shown.

[0032] Referring again to FIG1, according to an embodiment of the present disclosure, the integrated circuit structure 100 includes vertically arranged nanowires 108. Gate stacks 126 / 128 are above the vertically arranged nanowires 108. A first epitaxial source or drain structure (left 124) is at a first end of the vertically arranged nanowires 108. A second epitaxial source or drain structure (right 124) is at a second end of the vertically arranged nanowires 108. One or both of the first or second epitaxial source or drain structures 124 have an upper portion 124B and a lower epitaxial extension 124A.

[0033] In one embodiment, the upper portion 124B is continuous with the lower epitaxial extension 124A. In one embodiment, the lateral width of the upper portion 124B is greater than the lateral width of the lower epitaxial extension 124A. In one embodiment, the vertically arranged nanowires 108 are above the sub-fin 104. In such an embodiment, the lowermost surface of the lower epitaxial extension 124A is lower than the uppermost surface of the sub-fin 104.

[0034] In a broader sense, in one embodiment, the nanowire 108 is a silicon nanowire, a silicon-germanium nanowire, a germanium nanowire, or a germanium-tin nanowire. In one embodiment, the source or drain structure 124 is a silicon source or drain structure 124, a silicon-germanium source or drain structure 124, a germanium source or drain structure 124, or a germanium-tin source or drain structure 124. In a particular embodiment, the vertically arranged nanowire 108 comprises silicon, and the first and second epitaxial source or drain structures 124 comprise silicon and germanium. In another particular embodiment, the vertically arranged nanowire 108 comprises silicon and germanium, and the first and second epitaxial source or drain structures 124 comprise silicon and germanium.

[0035] As an exemplary processing flow, Figures 2A-2E show cross-sectional views illustrating various operations in a method of manufacturing a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion according to an embodiment of the present disclosure.

[0036] Referring to FIG2A, the initial structure 200 includes a substrate 202 having a silicon substrate thereon having fins 204. The fins 204 include a plurality of nanowire forming layers 206, such as silicon layers, and sacrificial material 208, such as silicon-germanium, alternating with the plurality of nanowire forming layers 206. A pseudo-gate structure 210, such as a polycrystalline silicon pseudo-gate structure, is located above the fins 204 and along the side of the fins 204 (the latter is indicated by dashed lines).

[0037] Referring to FIG2B, fin 204 is etched to form a plurality of nanowires 206A and patterned sacrificial material 208A between source or drain cavities 212. The stack of the plurality of nanowires 206A and patterned sacrificial material 208A can be formed over sub-fins (e.g., silicon sub-fins formed due to over-etching or epitaxial undercut etching of the substrate 202A to form the substrate 202A). Furthermore, as shown, a recess can be formed on either side of the sub-fin in the substrate 202A. As shown, a recessing process can be performed to make the patterned sacrificial material 208A recessed relative to the plurality of nanowires 206A. Gate spacers, such as silicon nitride spacers, can then be formed along the sidewalls of the pseudo-gate structure 210 and along the sidewalls of the recessed patterned sacrificial material 208A. A portion 214A of the gate spacer can be referred to as an external gate spacer, while a portion 214B of the gate spacer can be referred to as a cavity spacer or an internal spacer. In one embodiment, the gate spacer is formed in a recess in the substrate 202A on either side of the sub-fin, leaving dielectric material 216, as shown.

[0038] Referring to FIG2C, the dielectric material 216 in the recess of the substrate 202A is removed, for example, by anisotropic etching. The removal of the dielectric material 216 leaves an exposed recess 218 in the substrate 202A.

[0039] Referring again to FIG2D, epitaxial source or drain structures 220 are formed at the ends of a plurality of nanowires 206A. In one embodiment, each epitaxial source or drain structure 220 includes an upper and a lower epitaxial extension, as described above in conjunction with FIG1. ​​In one embodiment, the lower epitaxial extension is formed in a recess 218 in a substrate 202A, as shown.

[0040] Referring to Figure 2E, the pseudo-gate structure 210 is removed using a displacement gate process and a nanowire release process, followed by the removal of the patterned sacrificial material 208A. A permanent gate structure is then formed. As shown, the permanent gate structure may include a high-k gate dielectric layer 222 and a metal gate electrode 224. Additional processing of the resulting structure may include the formation of interlayer dielectric materials and / or conductive contacts.

[0041] In the second state, the implementation of an implanted surfactant catalyst for defect mitigation selective GAA used in PMOS source or drain epitaxy is described.

[0042] For background, for GAA transistors, source-drain epitaxy has multiple growth fronts supporting the epitaxy: exposed Si nanowires and sub-fins. Epitaxy growth is performed from broken nanowires grown on cavity spacers and merging to form defects. These defects need to be mitigated to allow the PMOS S / D to act as a source of compressive stress in the P-channel device and improve its performance. For example, the epitaxy growth processing parameters of the temperature can be adjusted to prefer growth on the (001) interface rather than the (110) interface. The growth processing parameters that prefer growth on (001) can result in a film with higher pMOS S / D resistivity or an undesirable facet shape that leads to short-circuit problems.

[0043] According to one or more embodiments of this disclosure, an surfactant catalyst is implanted before PMOS S / D epitaxy. Directional implantation affects the sub-fin surface rather than the nanowires, thereby catalyzing growth solely from the sub-fin surface. In one embodiment, since the implanted catalyst material is also a surfactant, it segregates to the surface during epitaxial growth and continues to catalyze the pressure-driven "bottom-up" SiGe growth seeded from the sub-fin surface. This results in higher stress in the p-channel device while still allowing for low resistivity pMOS S / D, thereby improving performance.

[0044] In one embodiment, even if most of the catalyst can remain on the top surface of the epitaxial layer, residual catalyst may also be present in the S / D-Si sub-fin connection and in the cavity and gate spacer embedded during implantation. APT and SIMS analysis of the source and drain can reveal the profile of the implanted species, which can be reverse engineered to understand the location and purpose of the implantation.

[0045] To provide further background, p-doped SiGe grows from multiple growth fronts: nanowires and daughter fins, which typically generate stress-relief defects when these growth fronts merge. In one embodiment, this can be avoided by catalytic growth solely from Si daughter fins, and the epitaxial growth starting from the daughter fins can coherently merge with the Si nanoribbons without leaving defects. Recovery of crystal damage after implantation can be achieved by annealing.

[0046] In one embodiment, the above-mentioned problem is addressed by implanting a surfactant species capable of catalyzing pEPI growth. Its surfactant properties are crucial, therefore a significant portion of the implanted dose crosses the epitaxial growth interface derived from the Si daughter fin, thereby allowing bottom-up growth to continue. In one embodiment, an annealing operation can be used to restore any damage to crystallinity caused by the implantation.

[0047] As an exemplary processing flow, Figures 3A-3H show cross-sectional views illustrating various operations in a method for manufacturing a surround-gate integrated circuit structure using an implanted surfactant catalyst according to an embodiment of the present disclosure. As an exemplary structure, Figure 4 shows cross-sectional views illustrating various surround-gate integrated circuit structures manufactured using an implanted surfactant catalyst according to an embodiment of the present disclosure.

[0048] Referring to FIG3A, the initial structure 300 includes a substrate 302, such as a silicon substrate. A plurality of nanowire forming layers 304, such as silicon layers, and a plurality of sacrificial material layers 306, such as silicon germanium, are located above the substrate 302.

[0049] Referring to FIG. 3B, the initial structure is etched to form a fin 308, which includes a nanowire forming layer 304A and a plurality of sacrificial material layers 306A, as well as sub-fins 303 that may be formed in a patterned substrate 302A. For example, a pseudo-gate structure 310 of polysilicon pseudo-gate structure is formed on the resulting structure (e.g., included in positions before and after the structure shown). Dielectric gate spacers 312 are formed along the sidewalls of the pseudo-gate structure 310.

[0050] Referring to FIG3C, fin 308 is etched to form fin 308A, each fin 308A including multiple nanowires 304B and patterned sacrificial material 306B, having a source or drain cavity between the patterned sub-fins 303 and the patterned substrate 302B.

[0051] Referring to FIG3D, a recessing process is performed to recess the patterned sacrificial material 306B relative to the plurality of nanowires 304B to form a patterned sacrificial material 306C. Then, cavity spacers or internal spacers 314 are formed along the side of the patterned sacrificial material 306C.

[0052] Referring to Figure 3E, in operation 320, the catalyst is implanted into the structure of Figure 3D.

[0053] Referring to FIG3F, a recessing process is performed to recess a plurality of nanowires 304B relative to the cavity spacer or internal spacer 314 to form a plurality of nanowires 304C.

[0054] Referring to Figure 3G, the epitaxial process begins and is driven from bottom to top by the implanted catalyst. In the initial formation stage, an initial epitaxial structure 322 is formed, on which residual implanted surfactant 323 may be present.

[0055] Referring to Figure 3H, the epitaxial process continues. In the subsequent formation stage, an epitaxial source or structure 322A is formed and may have residual implanted surfactant 323A thereon. In one embodiment, when growth is complete, the residual implanted surfactant 323A can be removed by etching. Annealing can also be performed to remove any defects.

[0056] Referring to FIG4, the pseudo-gate structure 310 is removed using a gate displacement process and a nanowire release process, and then the patterned sacrificial material 306C in FIG3H is removed. A permanent gate structure is then formed to provide an integrated circuit structure 400. As shown, the permanent gate structure may include a high-k gate dielectric layer 404 and a metal gate electrode 406. Additional processing of the resulting structure may include the formation of interlayer dielectric material and / or conductive contacts. Further processing of the resulting structure may include the formation of interlayer dielectric material 412 and / or conductive contacts 414 (which may include a barrier layer 416 and conductive filler 418).

[0057] As used throughout, a silicon layer can be used to describe a silicon material composed of a very large amount (if not all) of silicon. However, it should be understood that in practice, 100% pure Si may be difficult to form and may therefore contain very small percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition or may “contaminate” Si during post-deposition processing. Therefore, embodiments of silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or species (e.g., Ge, C, or Sn). It should be understood that silicon layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0058] As used throughout, a germanium layer can be used to describe a germanium material composed of a very large amount (if not all) of germanium. However, it should be understood that in practice, 100% pure Ge may be difficult to form, and therefore may contain very small percentages of silicon, carbon, or tin. Such impurities may be included as unavoidable impurities or components during Ge deposition, or may “contaminate” Ge during post-deposition processing. Therefore, embodiments of germanium layers described herein may include germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge atoms or species (e.g., carbon, silicon, or tin). It should be understood that germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0059] As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material consisting mostly of silicon and germanium, for example, at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In some embodiments, the silicon-germanium layer comprises about 60% germanium and about 40% silicon (Si 40Ge 60). In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises about 30% germanium and about 70% silicon (Si 70Ge 30). It should be understood that, in practice, 100% pure silicon-germanium (commonly referred to as SiGe) may be difficult to form and may therefore contain a very small percentage of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may "contaminate" SiGe during post-deposition processing. Therefore, the embodiments of silicon-germanium layers described herein may include silicon-germanium layers containing relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or species (e.g., carbon or tin). It should be understood that silicon-germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0060] As used throughout, a germanium-tin layer can be used to describe a germanium-tin material consisting primarily of germanium and tin, for example, at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of tin. In other embodiments, the amount of tin is greater than the amount of germanium. It should be understood that, in practice, 100% pure germanium-tin (commonly referred to as GeSn) may be difficult to form and may therefore contain a very small percentage of carbon or silicon. Such impurities may be included as unavoidable impurities or components during GeSn deposition, or may “contaminate” GeSn during diffusion during post-deposition processing. Therefore, the embodiments for germanium-tin layers described herein may contain relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Sn atoms or species (e.g., carbon or silicon). It should be understood that germanium-tin layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0061] In another embodiment, nanowire release processing can be performed by replacing gate trenches. Examples of such release processes are described below. Furthermore, in yet another embodiment, back-end (BE) interconnect scaling results in lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein can be implemented to achieve front and back interconnect integration of nanowire transistors. The embodiments described herein can provide a method for achieving relatively wide interconnect spacing. The result may be improved product performance and reduced patterning costs. Embodiments can be implemented to achieve robust functionality of scaled nanowires or nano-charged transistors with low power and high performance.

[0062] In another embodiment, in order to access the conductive contact structure of a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be fabricated using a back-side reveal fabrication method for the front structure. In some exemplary embodiments, the back-side reveal of the transistor or other device structure requires wafer-level back-side processing. Compared to conventional TSV-type techniques, the back-side reveal of the transistor as described herein can be performed at the density of device cells, even within sub-regions of the device. Furthermore, this back-side reveal of the transistor can be performed to substantially remove all donor substrates on which device layers are disposed during the front-side device processing. Therefore, the thickness of the semiconductor in the device cell may be only tens or hundreds of nanometers with the back-side reveal of the transistor, thus eliminating the need for micrometer-deep TSVs.

[0063] The exposure techniques described herein enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where "center" refers to any layer exposed from the back side in front-side fabrication and then reused in back-side fabrication. When relying primarily on front-side processing, processing both the front and exposed back sides of the device structure can address many challenges associated with manufacturing 3D ICs.

[0064] The method for exposing the back side of the transistor can be used, for example, to remove at least a portion of the carrier layer and interposer layer of the donor-substrate assembly. The process begins with the input donor-substrate assembly. Polishing (e.g., CMP) and / or wet or dry (e.g., plasma) etching processes are used to etch the thickness of the carrier layer in the donor-substrate. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0065] In some embodiments, the carrier layer is cleaved along a fracture surface substantially parallel to the interposer layer prior to the above operations. Cleaving or fracturing can be used to remove a large portion of the carrier layer as a bulk mass, reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cut by performing any blanket implantation known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer at a uniform target depth within the desired fracture surface. After such a cutting process, the thickness of the carrier layer remaining in the donor-host substrate assembly can be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a thicker carrier layer.

[0066] Next, the exposure of the interposer is detected. A point is detected to identify when the back surface of the donor substrate has advanced to near the device layer. Any endpoint detection technique known to be suitable for detecting the transition between the materials used for the carrier layer and the interposer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting changes in light absorption or emission of the back surface of the donor substrate during the polishing or etching process. In some other embodiments, the endpoint criteria are associated with changes in light absorption or emission of byproducts during the polishing or etching of the back surface of the donor substrate. For example, the absorbance or emission wavelength associated with carrier layer etching byproducts can vary depending on the different compositions of the carrier layer and the interposer. In other embodiments, the endpoint criteria are associated with changes in the mass of species in the byproducts of polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and changes in the mass of the substances can be associated with different compositions of the carrier layer and the interposer. In another exemplary embodiment, the endpoint criteria are associated with changes in friction between the back surface of the donor substrate and the polished surface in contact with the back surface of the donor substrate.

[0067] The detection of the interposer can be enhanced, wherein the removal process is selective relative to the interposer for the carrier layer, because the difference in etching rates between the carrier layer and the interposer can mitigate inhomogeneities in the carrier removal process. If the grinding, polishing, and / or etching operations remove the interposer at a rate sufficiently lower than that used to remove the carrier layer, detection may even be omitted. If no endpoint criterion is used, and if the thickness of the interposer is sufficient to achieve selective etching, the grinding, polishing, and / or etching operations for a predetermined fixed duration can be stopped at the interposer material. In some examples, the charge carrier etching rate:interposer etching rate is 3:1 to 10:1, or greater.

[0068] After exposing the interposer, at least a portion of the interposer can be removed. For example, one or more component layers of the interposer can be removed. For example, the thickness of the interposer can be uniformly removed by polishing. Alternatively, a certain thickness of the interposer can be removed by a photomask or blanket etching process. This process can employ the same polishing or etching process used to thin the carrier, or it can be a different process with different processing parameters. For example, in cases where the interposer provides an etching stop for the carrier removal process, the latter operation can employ a different polishing or etching process that favors the removal of the interposer rather than the removal of the device layer. In cases where the thickness of the interposer to be removed is less than a few hundred nanometers, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than the methods used to remove the carrier layer. For example, the CMP process employed can use a paste that provides very high selectivity (e.g., 100:1-300:1 or higher) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) around the device layer and is embedded within the interposer, for example, as electrical isolation between adjacent device regions.

[0069] For embodiments that expose the device layer by completely removing the interposer, the back-side processing may begin on the exposed back side of the device layer or on a specific device region therein. In some embodiments, the back-side device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the interposer and a device region (e.g., a source or drain region) previously fabricated in the device layer.

[0070] In some embodiments, the back face of the carrier layer, interposer, or device layer is recessed by wet etching and / or plasma etching. Such etching can be patterned etching or material-selective etching that imparts significant non-planarity or morphology to the back face surface of the device layer. As further described below, patterning can be within a device cell (i.e., "intra-cell") or across device cells (i.e., "inter-cell"). In some patterned etching embodiments, at least a portion of the thickness of the interposer is used as a hard photomask for patterning the back face device layer. Therefore, the photomask etching process can be performed prior to the etching of the corresponding mask's device layer.

[0071] The above processing scheme can produce a donor-substrate assembly including IC devices and / or exposed front metallization, the IC devices having a back side of an interposer, a back side of a device layer, and / or a back side of one or more semiconductor regions within the device layer. Further back side processing can then be performed on any of these exposed regions during downstream processing.

[0072] It should be understood that the structure generated by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device manufacturing, such as PMOS and / or NMOS device manufacturing. As an example of completing a device, FIG5 shows a cross-sectional view of a non-planar cubic circuit structure taken along the gate line according to an embodiment of the present disclosure.

[0073] Referring to FIG5, the semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including a protruding fin 504 and a sub-fin region 505) within a trench isolation region 506. In one embodiment, the non-planar active region is divided into nanolines (e.g., nanolines 504A and 504B) above the sub-fin region 505 instead of solid fins, as shown by dashed lines. In either case, for ease of illustration of the non-planar bulk circuit structure 500, the non-planar active region 504 is hereinafter referred to as the protruding fin. In one embodiment, the process involves using a processing scheme that provides an all-around gate integrated circuit structure having an epitaxial source or drain structure including a substrate interconnect portion.

[0074] Gate line 508 is disposed on the protrusion 504 of the nonplanar active region (including, if applicable, surrounding nanolines 504A and 504B) and a portion of the trench isolation region 506. As shown, gate line 508 includes gate electrode 550 and gate dielectric layer 552. In one embodiment, gate line 508 may also include dielectric capping layer 554. Together with overlying metal interconnect 560, gate contact 514 and overlying gate contact via 516 are also visible from this angle, all disposed in the interlayer dielectric stack or layer 570. Also viewed from the angle of FIG5, in one embodiment, gate contact 514 is disposed above trench isolation region 506, but not above nonplanar active region. In another embodiment, gate contact 514 is above nonplanar active region.

[0075] In one embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a fin FET device, a three-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 508 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0076] Also as shown in FIG. 5, in one embodiment, interface 580 exists between the protruding fin 504 and the sub-fin region 505. Interface 580 may be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin 504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid-state doped layer at the sub-fin location. In certain such embodiments, the width of each fin is less than 10 nanometers.

[0077] Although not depicted in FIG. 5, it should be understood that the source or drain region of the protruding fin 504 or its adjacent region is on either side of the gate line 508, i.e., entering and exiting the page. In one embodiment, the material of the protruding fin 504 at the source or drain location is removed and replaced with another semiconductor material, for example, by epitaxial deposition, to form a source or drain structure including a substrate connection portion. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 506, i.e., extending into the sub-fin region 505. According to embodiments of this disclosure, a more heavily doped sub-fin region, i.e., the doped portion of the fin below interface 580, suppresses source-to-drain leakage through that portion of the bulk semiconductor fin.

[0078] Referring again to FIG5, in one embodiment, the fins 504 / 505 (and possible nanowires 504A and 504B) are composed of a crystalline silicon-germanium layer, which may be doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, gallium or combinations thereof.

[0079] In one embodiment, the trench isolation region 506 and the trench isolation region (trench isolation structure or trench isolation layer) described throughout may be composed of a material suitable for final electrical isolation or contributing to a permanent gate structure, and an isolation active region (e.g., isolation fin active region) formed within the underlying body substrate. For example, in one embodiment, the trench isolation region 506 is composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0080] Gate line 508 may be composed of a gate electrode stack, which includes a gate dielectric layer 552 and a gate electrode layer 550. In one embodiment, the gate electrodes of the gate electrode stack are composed of metal gates and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of, but is not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer may include a natural oxide layer formed from the top layers of the substrate fin 504. In one embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of oxides of semiconductor materials. In one embodiment, the gate dielectric layer is composed of a top hafnium oxide and a bottom silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure, which includes a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0081] In one embodiment, the gate electrode is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-work function setting filler material formed above the metal work function setting layer. The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive filler layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will be able to form a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will be able to form an NMOS gate electrode with a power function between approximately 3.9 eV and approximately 4.2 eV. In some embodiments, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and excluding the sidewall portions substantially perpendicular to the top surface of the substrate. In further embodiments of this disclosure, the gate electrode may consist of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0082] The spacers associated with the gate electrode stack may be composed of materials suitable for final electrical isolation or that contribute to the isolation of the permanent gate structure from adjacent conductive contacts (e.g., self-aligned contacts). For example, in one embodiment, the spacers are composed of dielectric materials, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0083] The gate contact 514 and the overlying gate contact via 516 may be composed of a conductive material. In one embodiment, one or more contacts or vias may be composed of a metallic species. The metallic species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicate material).

[0084] In one embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 508, while eliminating lithography steps using extremely tight alignment budgets. In other embodiments, all contacts are face-to-face connected and not asymmetrical. In one such embodiment, the self-alignment method enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching in conventional implementations) to create contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with contact plug lithography operations. In one such embodiment, the method enables the elimination of the need for additional critical lithography operations for creating the contact pattern, as used in conventional methods. In one embodiment, the trench contact gate is not patterned separately but formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact gate is formed after gate grating patterning but before gate grating dicing.

[0085] In one embodiment, the provided structure 500 relates to a process for fabricating a gate stack structure 508 via a gate displacement process. In such an embodiment, a pseudo-gate material, such as a columnar material of polycrystalline silicon or silicon nitride, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, which is the opposite of that performed from an earlier process. In one embodiment, the pseudo-gate is removed by a dry etching or wet etching process. In one embodiment, the pseudo-gate is composed of polycrystalline silicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the pseudo-gate is composed of polycrystalline silicon or amorphous silicon and is removed by a wet etching process including the use of an aqueous solution of NH4OH or tetramethylammonium hydroxide. In one embodiment, the pseudo-gate is composed of silicon nitride and is removed by a wet etching process including an aqueous solution of phosphoric acid.

[0086] Referring again to FIG5, the configuration of the semiconductor structure or device 500 places the gate contact above the isolation region. This configuration can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode, which is formed above the active region, for example, above the fin 505, and in the same layer as the trench contact via.

[0087] It should be understood that not all of the above-described processing methods need to be practiced to fall within the spirit and scope of the embodiments disclosed herein. Furthermore, the processing methods described herein can be used to manufacture one or more semiconductor devices. The semiconductor device can be a transistor or similar device. For example, in one embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Furthermore, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a three-gate device, an independently accessible dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at the next 10-nanometer (10 nm) technology node.

[0088] In one embodiment, as used throughout this specification, the interlayer dielectric (ILD) material comprises or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed using conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0089] In one embodiment, as used throughout this description, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed of multiple layers including a conductive liner and a filler layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect. In one embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in this art as traces, wires, lines, metals, or simply interconnects.

[0090] In one embodiment, as used throughout this description, the hard photomask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard photomask, capping, or plug materials may be used in different regions to provide different growth or etching selectivity for each other and for the underlying dielectric and metal layers. In some embodiments, the hard photomask layer, capping layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard photomask, capping layer, or plug layer known in the art may be used. The hard photomask, capping layer, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0091] In one embodiment, as used throughout this description, lithography is performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV), and / or electron beam direct writing (EBDW) lithography. Positive or negative resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topographic mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular embodiment of this type, the topographic mask portion is a carbon hard mask (CHM) layer and the anti-reflective coating is a silicon ARC layer.

[0092] In another embodiment, one or more embodiments are directed to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may be directed to integrating multi-width (multi-Wsi) nanowires and nanoribbons within a SAGE architecture and separated by SAGE walls. In one embodiment, the nanowires / nanoribbons are integrated with multiple Wsi within a SAGE architecture portion of a front-end processing flow. This processing flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality for next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., a portion of the nanowire is removed and then source or drain (S / D) growth is performed) and may be or include substrate interconnect portions.

[0093] To provide further background, the advantages of the self-aligned gate end cap (SAGE) architecture may include achieving higher layout density, particularly reducing diffusion to the diffusion interval. For an illustrative comparison, Figure 6 shows cross-sectional views of a non-end cap architecture (left side (a)) and a self-aligned gate end cap (SAGE) architecture (right side (b)) taken through nanowires and fins, according to an embodiment of this disclosure.

[0094] Referring to the left side (a) of FIG6, the integrated circuit structure 600 includes a substrate 602 having a fin 604 protruding therefrom over an isolation structure 608 by an amount 606, the isolation structure 608 laterally surrounding the lower portion of the fin 604. As shown, the upper portion of the fin may include a relaxation buffer layer 622 and a defect modification layer 620. Corresponding nanowires 605 are above the fin 604. A gate structure can be formed above the integrated circuit structure 600 to manufacture a device. However, breaks in such a gate structure can be accommodated by increasing the spacing between the fin 604 / nanowire 605 pairs.

[0095] Conversely, referring to the right side (b) of FIG6, the integrated circuit structure 650 includes a substrate 652 having fins 654 protruding therefrom over an isolation structure 658 by an amount 656, the isolation structure 658 laterally surrounding the lower portion of the fins 654. As shown, the upper portion of the fins may include a relaxation buffer layer 672 and a defect modification layer 670. Corresponding nanowires 655 are above the fins 654. Isolation SAGE walls 660 (which may include hard photomasks, as shown) are included within the isolation structure 652 and between adjacent pairs of fins 654 / nanowires 655. The distance between the isolation SAGE walls 660 and the nearest pair of fins 654 / nanowires 655 defines a gate cap spacing 662. Gate structures may be formed above the integrated circuit structure 600, between the isolation SAGE walls, to manufacture a device. A break is applied in such a gate structure through the isolation SAGE walls. Because the isolation SAGE wall 660 is self-aligned, limitations from conventional methods can be minimized, allowing for more aggressive diffusion into the diffusion gap. Furthermore, since the gate structure includes breaks at all locations, the individual gate structure portions can be layered via local interconnects formed above the isolation SAGE wall 660. In one embodiment, as shown, each SAGE wall 660 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to embodiments of this disclosure, the fabrication process of the structure associated with FIG. 6 involves using a process scheme that provides a surround gate integrated circuit structure having epitaxial source or drain structures that may include substrate interconnect portions.

[0096] The self-aligned gate end cap (SAGE) processing scheme involves the formation of a gate / groove contact end cap that is self-aligned to the fins without requiring additional length to address mask misregistration. Therefore, embodiments can be implemented to enable a reduction in transistor layout area. The embodiments described herein may relate to the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate end cap (SAGE) wall.

[0097] In an exemplary processing scheme for a structure having SAGE walls that separate adjacent devices, FIG7 shows a cross-sectional view representing various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a surrounding gate device according to an embodiment of the present disclosure.

[0098] Referring to portion (a) of FIG7, the initial structure includes a nanoline patterned stack 704 above a substrate 702. A lithography patterned stack 706 is formed above the nanoline patterned stack 704. As shown, the nanoline patterned stack 704 includes alternating sacrificial layers 710 and nanoline layers 712, which may be located above a relaxation buffer layer 782 and a defect modification layer 780. A protective photomask 714 is located between the nanoline patterned stack 704 and the lithography patterned stack 706. In one embodiment, the lithography patterned stack 706 is a three-layer photomask consisting of a topology photomask portion 720, an antireflective coating (ARC) layer 722, and a photoresist layer 724. In a particular embodiment of this type, the topology photomask portion 720 is a carbon hard photomask (CHM) layer and the antireflective coating 722 is a silicon ARC layer.

[0099] Referring to part (b) of FIG7, the stacked photolithography pattern of part (a) is patterned and then etched to provide an etched structure including a patterned substrate 702 and a trench 730.

[0100] Referring to part (c) of FIG7, the structure of part (b) has an isolation layer 740 and a SAGE material 742 formed in the trench 730. The structure is then planarized to leave a patterned topographic mask layer 720' as the exposed upper layer.

[0101] Referring to part (d) of FIG7, the isolation layer 740 is recessed below the upper surface of the patterned substrate 702, for example, to define the protruding fins and provide a trench isolation structure 741 below the SAGE wall 742.

[0102] Referring to portion (e) of FIG7, the sacrificial layer 710 is removed at least in the channel region to release nanowires 712A and 712B. After forming the structure of portion (e) of FIG7, a gate stack can be formed around nanowires 712B or 712A, above the protruding fins of substrate 702, and between SAGE walls 742. In one embodiment, the remainder of the protective photomask 714 is removed before forming the gate stack. In another embodiment, the remainder of the protective photomask 714 is retained as an insulating fin cap as a product of the processing.

[0103] Referring again to portion (e) of Figure 7, it should be understood that a channel view is depicted, wherein the source or drain regions are located within and outside the page. In one embodiment, the width of the channel region including nanoline 712B is smaller than the width of the channel region including nanoline 712A. Therefore, in one embodiment, the integrated circuit structure includes multi-width (multi-Wsi) nanolines. Although the structures of 712B and 712A can be distinguished as nanolines and nanobands, respectively, both structures are generally referred to herein as nanolines. It should also be understood that references or descriptions of fin / nanoline pairs throughout may refer to a structure including fins and one or more overlapping nanolines (e.g., two overlapping nanolines are shown in Figure 7). According to embodiments of this disclosure, the fabrication process for the structure associated with Figure 7 involves a process scheme that provides a surround gate integrated circuit structure having an epitaxial source or drain structure that may include a substrate connection portion.

[0104] In one embodiment, as described throughout, the self-aligned gate end cap (SAGE) isolation structure may consist of one or more materials suitable for ultimately electrically isolating portions of the permanent gate structure from each other or facilitating the isolation of portions of the permanent gate structure from each other. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower layer of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper layer of a material with a higher dielectric constant (e.g., hafnium oxide).

[0105] To emphasize the exemplary integrated circuit structure having three vertically arranged nanowires, FIG8A shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. FIG8B shows a cross-sectional source or drain view of the nanowire-based integrated circuit structure of FIG8A taken along the a-a' axis. FIG8C shows a cross-sectional channel view of the nanowire-based integrated circuit structure of FIG8A taken along the b-b' axis.

[0106] Referring to FIG8A, the integrated circuit structure 800 includes one or more vertically stacked nanowires (groups 804) above a substrate 802. In one embodiment, as depicted, a relaxation buffer layer 802C, a defect modification layer 802B, and a lower substrate portion 802A are included in the substrate 802, as shown. For illustrative purposes, and to emphasize the nanowire portion, optional fins formed by the substrate 802 below the bottommost nanowire are not depicted. The embodiments herein pertain to single-wire and multi-wire devices. As an example, three nanowire-based devices having nanowires 804A, 804B, and 804C are shown for illustrative purposes. For ease of description, nanowire 804A is used as an example, and one of the nanowires is described in detail. It should be understood that, in describing the properties of a single nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire.

[0107] Each nanoline 804 includes a channel region 806 within the nanoline. The channel region 806 has a length (L). Referring to FIG8C, the channel region also has a perimeter (Pc) orthogonal to the length (L). Referring to FIG8A and 8C, a gate electrode stack 808 surrounds the entire perimeter (Pc) of each channel region 806. The gate electrode stack 808 includes a gate electrode together with a gate dielectric layer between the channel region 806 and the gate electrode (not shown). In one embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 808 without any interfacing material, such as the underlying substrate material or the upper channel fabrication material. Therefore, in embodiments having multiple nanolines 804, the channel regions 806 of the nanolines are also discrete relative to each other.

[0108] Referring simultaneously to Figures 8A and 8B, the integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810 / 812. This pair of non-discrete source or drain regions 810 / 812 is located on either side of a channel region 806 of a plurality of vertically stacked nanowires 804. Furthermore, this pair of non-discrete source or drain regions 810 / 812 is adjacent to the channel region 806 of the plurality of vertically stacked nanowires 804. In one such embodiment, not depicted in the figures, the pair of non-discrete source or drain regions 810 / 812 is directly perpendicularly adjacent to the channel region 806 because epitaxial growth occurs on and between portions of the nanowires extending beyond the channel region 806, wherein the ends of the nanowires are visible within the source or drain structure. In another embodiment, as shown in Figure 8A, the pair of non-discrete source or drain regions 810 / 812 is indirectly perpendicularly adjacent to the channel region 806 because they are formed at the ends of the nanowires rather than between the nanowires. In one embodiment, the non-discrete source or drain region 810 / 812 is a non-discrete source or drain region including a substrate connection portion.

[0109] In one embodiment, as shown, the source or drain regions 810 / 812 are non-discrete because there is no individual and discrete source or drain region for each channel region 806 of the nanoline 804. Therefore, in embodiments having multiple nanolines 804, the source or drain regions 810 / 812 of the nanoline are global or uniform source or drain regions, rather than being discrete for each nanoline. That is, the non-discrete source or drain regions 810 / 812 are global in the sense that a single uniform feature is used as the source or drain region of multiple (in this case, 3) nanolines 804, and more specifically, for more than one discrete channel region 806. In one embodiment, each of the pair of non-discrete source or drain regions 810 / 812 is approximately rectangular in shape when viewed from a cross-sectional angle orthogonal to the length of the discrete channel region 806, as shown in Figure 8B.

[0110] According to an embodiment of this disclosure, and as shown in Figures 8A and 8B, the integrated circuit structure 800 further includes a pair of contacts 814, each contact 814 on one of the pair of non-discrete source or drain regions 810 / 812. In one such embodiment, in the vertical direction, each contact 814 completely surrounds its respective non-discrete source or drain region 810 / 812. In another example, the entire periphery of the non-discrete source or drain region 810 / 812 may not be accessible for contact with the contact 814, so the contact 814 only partially surrounds the non-discrete source or drain region 810 / 812, as shown in Figure 8B. In a comparative embodiment not shown, the entire periphery of the non-discrete source or drain region 810 / 812, truncated along the a-a' axis, is surrounded by the contact 814.

[0111] Referring again to FIG8A, in one embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As shown, the outer portions of the pair of spacers 816 may overlap portions of the non-discrete source or drain regions 810 / 812, and an "embedded" portion of the non-discrete source or drain regions 810 / 812 is provided below the pair of spacers 816. Also as shown, the embedded portion of the non-discrete source or drain regions 810 / 812 may not extend below the entirety of the pair of spacers 816.

[0112] The substrate 802 may be composed of materials suitable for manufacturing integrated circuit structures. In one embodiment, the substrate 802 includes a lower body substrate composed of a single-crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or III-V compound semiconductor materials. The material of the upper insulating layer on the lower body substrate may be composed of materials including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. Therefore, the structure 800 may be made from an initial semiconductor-on-insulator substrate. Alternatively, the structure 800 may be formed directly from the body substrate and use localized oxidation to form electrically insulating portions instead of the aforementioned upper insulating layer. In another alternative embodiment, the structure 800 may be formed directly from the body substrate and use doping to form electrically isolated active regions thereon, such as nanowires. In such an embodiment, the first nanowire (i.e., adjacent to the substrate) is in the form of an Ω-type FET (omega-FET) structure.

[0113] In one embodiment, the nanowire 804 may be sized as a line or strip, as described below, and may have square or rounded corners. In one embodiment, the nanowire 804 is composed of a material such as, but not limited to, silicon, germanium, or combinations thereof. In such an embodiment, the nanowire is single-crystal. For example, for silicon nanowire 804, the single-crystal nanowire may be based on a (100) global orientation, for example, having a <100> plane in the z-direction. Other orientations may also be considered, as described below. In one embodiment, the size of the nanowire 804 is nanometer-scale when viewed from a cross-sectional perspective. For example, in a particular embodiment, the minimum size of the nanowire 804 is less than about 20 nanometers. In one embodiment, the nanowire 804 is composed of a strained material, particularly in the channel region 806.

[0114] Referring to Figure 8C, in one embodiment, each channel region 806 has a width (Wc) and a height (Hc), the width (Wc) and height (Hc) being approximately the same. That is, in both cases, the cross-sectional profile of the channel region 806 is square, or, if it is rounded, circular. In another embodiment, the width and height of the channel region need not be the same, such as in the case of the nanoribbons described throughout.

[0115] In one embodiment, as described throughout, the integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or a three-gate device having corresponding one or more overlapping nanowire structures. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body, with one or more discrete nanowire channel portions overlapping the three-dimensional body. In such an embodiment, the gate structure at least surrounds the top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0116] In one embodiment, as described throughout, the underlying substrate may be composed of a semiconductor material capable of withstanding the process and in which charge can migrate. In one embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on a different crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single-crystal substrate. The bulk substrate may alternatively be composed of a Group III-V material. In one embodiment, the bulk substrate is composed of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the body substrate is composed of a III-V group material, and the charge carrier dopant impurity atoms are such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0117] The embodiments disclosed herein can be used to manufacture a variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset assemblies, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide range of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptops, servers), cell phones, personal electronic devices, etc. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to memory, chipsets, etc., through one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0118] FIG9 illustrates a computing device 900 according to an embodiment of the present disclosure. The computing device 900 houses a board 902. The board 902 may include multiple components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some other embodiments, at least one communication chip 906 is also physically and electrically coupled to the board 902. In a further embodiment, the communication chip 906 is part of the processor 904.

[0119] Depending on its application, the computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, encryption processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, optical discs (CDs), digital versatile discs (DVDs), etc.).

[0120] The communication chip 906 implements wireless communication for transmitting data to and from the computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated device does not contain any wires, although they may not in some embodiments. The communication chip 906 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and above. The computing device 900 may include multiple communication chips 906. For example, the first communication chip 906 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, while the second communication chip 906 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0121] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. The integrated circuit die of the processor 904 may include one or more structures, such as a gate-all-around integrated circuit structure having a source or drain structure including a substrate interconnect portion constructed according to an embodiment of the present disclosure. The term "processor" may mean any device or part of a device that processes, for example, electronic data from a register and / or memory to convert the electronic data into other electronic data that can be stored in the register and / or memory.

[0122] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. The integrated circuit die of the communication chip 906 may include one or more structures, such as a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion constructed according to an embodiment of the present disclosure.

[0123] In a further embodiment, another component housed within the computing device 900 may include an integrated circuit die, which includes one or more structures, such as a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion constructed according to an embodiment of the present disclosure.

[0124] In various embodiments, the computing device 900 may be a laptop, lightweight laptop, notebook computer, ultra-thin laptop, smartphone, tablet computer, personal digital assistant (PDA), supercomputer, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, the computing device 900 may be any other electronic device for processing data.

[0125] FIG. 10 shows an interposer 1000 including one or more embodiments of the present disclosure. The interposer 1000 is an interposer substrate for bridging a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for example, an integrated circuit die. The second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 1000 is to extend connections to a wider spacing or to reroute connections to different connections. For example, the interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006, which may then be coupled to the second substrate 1004. In some embodiments, the first and second substrates 1002 / 1004 are attached to opposite sides of the interposer 1000. In other embodiments, the first and second substrates 1002 / 1004 are attached to the same side of the interposer 1000. And, in a further embodiment, three or more substrates are interconnected via the interposer 1000.

[0126] Intermediate layer 1000 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material or polymer material such as polyimide. In a further embodiment, intermediate layer 1000 may be formed of alternative rigid or flexible material, which may include the same material as described above for semiconductor substrates, such as silicon, germanium and other group III-V and group IV materials.

[0127] Intermediate layer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. Intermediate layer 1000 may also include embedded devices 1014, including passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on intermediate layer 1000. According to embodiments of this disclosure, the devices or processing methods disclosed herein can be used in the fabrication of intermediate layer 1000 or in the fabrication of components contained in intermediate layer 1000.

[0128] Therefore, the embodiments disclosed herein include a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion, and a method for manufacturing a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion.

[0129] The above description of illustrative embodiments of the present disclosure, including the content described in the abstract, is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications can be made within the scope of the present disclosure as will be recognized by those skilled in the art.

[0130] These modifications can be made to this disclosure based on the above detailed description. The terminology used in the following claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims. Rather, the scope of this disclosure will be determined entirely by the following claims, which will be interpreted in accordance with established principles of claim interpretation.

[0131] Exemplary Example 1: An integrated circuit structure includes vertically arranged nanowires. Gates are stacked above the vertically arranged nanowires. A first epitaxial source or drain structure is located at a first end of the vertically arranged nanowires. A second epitaxial source or drain structure is located at a second end of the vertically arranged nanowires. One or both of the first or second epitaxial source or drain structure have upper and lower epitaxial extensions.

[0132] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the upper part is continuous with the lower epitaxial extension.

[0133] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the lateral width of the upper part is greater than the lateral width of the lower epitaxial extension.

[0134] Example 4: Integrated circuit structure of Example 1, 2 or 3, wherein the vertically arranged nanowires are above the sub-fins.

[0135] Example 5: The integrated circuit structure of Example 4, wherein the lowermost surface of the lower epitaxial extension is lower than the uppermost surface of the sub-fin.

[0136] Example Embodiment 6: An integrated circuit structure includes a fin. Gates are stacked above the fin. A first epitaxial source or drain structure is located at a first end of the fin. A second epitaxial source or drain structure is located at a second end of the fin. One or both of the first or second epitaxial source or drain structures have upper and lower epitaxial extensions.

[0137] Example Embodiment 7: The integrated circuit structure of Example Embodiment 6, wherein the upper part is continuous with the lower epitaxial extension.

[0138] Example Embodiment 8: The integrated circuit structure of Example Embodiment 6 or 7, wherein the lateral width of the upper part is greater than the lateral width of the lower epitaxial extension.

[0139] Example 9: Integrated circuit structure of Example 6, 7 or 8, wherein the fin is above the sub-fin.

[0140] Example 10: The integrated circuit structure of Example 9, wherein the lowermost surface of the lower epitaxial extension is lower than the uppermost surface of the sub-fin.

[0141] Example Embodiment 11: A computing device includes a board and an assembly coupled to the board. The assembly includes an integrated circuit structure comprising vertically arranged nanowires. Gates are stacked above the vertically arranged nanowires. A first epitaxial source or drain structure is located at a first end of the vertically arranged nanowires. A second epitaxial source or drain structure is located at a second end of the vertically arranged nanowires. One or both of the first or second epitaxial source or drain structure have upper and lower epitaxial extensions.

[0142] Example 12: The computing device of Example 11 further includes memory coupled to the board.

[0143] Example 13: The computing device of Example 11 or 12 further includes a communication chip coupled to the board.

[0144] Example 14: The computing device of Example 11, 12 or 13 further includes a battery coupled to the plate.

[0145] Example 15: A computing device of Example 11, 12, 13 or 14, wherein the component is a packaged integrated circuit die.

[0146] Example Embodiment 16: A computing device includes a board and an assembly coupled to the board. The assembly includes an integrated circuit structure containing fins. Gates are stacked above the fins. A first epitaxial source or drain structure is located at a first end of the fin. A second epitaxial source or drain structure is located at a second end of the fin. One or both of the first or second epitaxial source or drain structures have upper and lower epitaxial extensions.

[0147] Example 17: The computing device of Example 16 further includes memory coupled to the board.

[0148] Example 18: The computing device of Example 16 or 17 further includes a communication chip coupled to the board.

[0149] Example 19: The computing device of Example 16, 17 or 18 further includes a battery coupled to the plate.

[0150] Example 20: A computing device of Example 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die. [Simplified Explanation of the Diagram]

[0006] [Figure 1] shows a cross-sectional view of a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion according to an embodiment of the present disclosure.

[0007] [Figures 2A-2E] show cross-sectional views illustrating various operations in a method of manufacturing a surround gate integrated circuit structure having a source or drain structure including a substrate connection portion, according to an embodiment of the present disclosure.

[0008] [Figures 3A-3H] show cross-sectional views illustrating various operations in a method for fabricating a surround gate integrated circuit structure using an implanted surfactant catalyst according to an embodiment of the present disclosure.

[0009] [Figure 4] shows a cross-sectional view illustrating various all-around gate integrated circuit structures manufactured using implanted surfactant catalysts according to embodiments of the present disclosure.

[0010] [Figure 5] shows a cross-sectional view of a non-planar cubic circuit structure according to an embodiment of the present disclosure, taken along the gate line.

[0011] [Figure 6] shows a cross-sectional view of a non-end cap architecture (left side (a)) and a slef-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure, taken through nanowires and fins.

[0012] [Figure 7] shows a cross-sectional view illustrating various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a surrounding gate device according to an embodiment of the present disclosure.

[0013] [Figure 8A] shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure.

[0014] [Figure 8B] shows a cross-sectional source or drain view along the a-a' axis of the nanowire-based integrated circuit structure of Figure 8A according to an embodiment of the present disclosure.

[0015] [Figure 8C] shows a cross-sectional channel view along the b-b' axis of the nanowire-based integrated circuit structure of Figure 8A according to an embodiment of the present disclosure.

[0016] [Figure 9] shows a computing device implemented according to one embodiment of the present disclosure.

[0017] [Figure 10] shows an intermediary layer including one or more embodiments of the present disclosure.

Claims

1. An integrated circuit structure comprising: vertically arranged nanowires; a gate stack above the vertically arranged nanowires; a first epitaxial source or drain structure at a first end of the vertically arranged nanowires; and a second epitaxial source or drain structure at a second end of the vertically arranged nanowires, wherein... One or both of the first or second epitaxial source or drain structures have an upper and a lower epitaxial extension.

2. As in request item 1, the integrated circuit structure, wherein, The upper part is continuous with the lower epitaxial extension.

3. As in request item 1 or 2, the integrated circuit structure, wherein, The lateral width of the upper part is greater than the lateral width of the lower epitaxial extension.

4. As in request item 1 or 2, the integrated circuit structure, wherein, These vertically arranged nanowires are above the fins.

5. As in request item 4, the integrated circuit structure, wherein, The lowest surface of the epitaxial extension is lower than the highest surface of the sub-fin.

6. An integrated circuit structure comprising: a fin; a gate stack above the fin; a first epitaxial source or drain structure at a first end of the fin; and a second epitaxial source or drain structure at a second end of the fin, wherein... One or both of the first or second epitaxial source or drain structures have an upper and a lower epitaxial extension.

7. As in request item 6, the integrated circuit structure, wherein, The upper part is continuous with the lower epitaxial extension.

8. As in request item 6 or 7, the integrated circuit structure, wherein, The lateral width of the upper part is greater than the lateral width of the lower epitaxial extension.

9. As in request item 6 or 7, the integrated circuit structure, wherein, The fin is located above the finlets.

10. The integrated circuit structure as described in claim 9, wherein, The lowest surface of the epitaxial extension is lower than the highest surface of the sub-fin.

11. A computing device comprising: a board; and a component coupled to the board, the component including an integrated circuit structure comprising: vertically arranged nanowires; a gate stack above the vertically arranged nanowires; a first epitaxial source or drain structure at a first end of the vertically arranged nanowires; and a second epitaxial source or drain structure at a second end of the vertically arranged nanowires, wherein... One or both of the first or second epitaxial source or drain structures have an upper and a lower epitaxial extension.

12. The computing device of claim 11 further includes: memory coupled to the board.

13. The computing device as claimed in claim 11 or 12 further includes: a communication chip coupled to the board.

14. The computing device as claimed in claim 11 or 12 further includes: a battery coupled to the plate.

15. The computing device as claimed in claim 11 or 12, wherein, This component is a packaged integrated circuit die.

16. A computing device comprising: a board; and a component coupled to the board, the component including an integrated circuit structure comprising: a fin; a gate stack above the fin; a first epitaxial source or drain structure at a first end of the fin; and a second epitaxial source or drain structure at a second end of the fin, wherein... One or both of the first or second epitaxial source or drain structures have an upper and a lower epitaxial extension.

17. The computing device of claim 16 further includes: memory coupled to the board.

18. The computing device of claim 16 or 17 further includes: a communication chip coupled to the board.

19. The computing device of claim 16 or 17 further includes: a battery coupled to the plate.

20. The computing device as claimed in claim 16 or 17, wherein, This component is a packaged integrated circuit die.

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