Parallel power conversion system and parallel controller thereof

Abstract

A parallel controller of a parallel power conversion system can connect power converters to a load and includes current-sharing circuit sections corresponding to the power converters. Each current-sharing circuit section includes a reference source, a current detecting and amplifying circuit, and a voltage control circuit that is connected to the reference source and the current detecting and amplifying circuit to control the corresponding power converter to adjust its output voltage by the voltage droop method via the negative sense port of the corresponding power converter. Therefore, the output currents of power converters become equal.

Description

[Technical Field]

[0001] This invention relates to a power converter technology, and more particularly to a parallel power conversion system and its parallel controller. [Previous Technology]

[0002] With industrial development and technological advancements, the demand for power supply is increasing. To improve output power, in addition to upgrading the components and functions of the power converter through circuit design, two power converters can be connected in parallel. This eliminates the need to redesign new products and allows for the direct acquisition of greater power.

[0003] However, if two power converters are directly connected in parallel, even if they are of the same specifications, uneven output current will occur. Over time, this will shorten the power supply's lifespan and reduce its reliability. Therefore, the parallel application of power converters has emerged.

[0004] Existing parallel applications of power converters involve connecting an active current sharing control chip externally to the output side of each power converter. Each active current sharing control chip feeds back to the positive sensing port (S+) of the corresponding power converter, and additional wiring is required to connect these active current sharing control chips to each other. However, this approach is not only difficult to wire and susceptible to interference, but also expensive. [Summary of the Invention]

[0005] Therefore, one of the objectives of the present invention is to provide a parallel power conversion system and its parallel controller, which can overcome the problems of difficult wiring, easy interference and high cost in the prior art.

[0006] The present invention provides a parallel controller for a parallel power conversion system according to an embodiment. The parallel power conversion system is adapted to electrically connect an input power supply to a load and further includes a plurality of power converters. The input side of each power converter is connected to the input power supply, and the output side of each power converter includes a first conversion output port, a second conversion output port, and a negative sensing port. Each first conversion output port is connected to a first load port of the load. The parallel controller includes: a power input port configured to be electrically connected to each of the first conversion output ports; a plurality of power output ports corresponding to the plurality of power converters, each power output port being configured to be electrically connected to the second conversion output port of the corresponding power converter; a plurality of load sensing ports corresponding to the plurality of power converters and configured to be electrically connected to a second load port of the load; a plurality of sensing output ports corresponding to the plurality of power converters, each sensing output port being configured to be electrically connected to the negative sensing port of the corresponding power converter; and a plurality of current sharing circuit blocks corresponding to the plurality of power converters, the plurality of power output ports, the plurality of load sensing ports, and the plurality of sensing output ports. Each current sharing circuit block includes: a reference source electrically connected to the power input port for adjusting the power from the power input port to provide a reference supply voltage via its reference output node; a current sensing amplifier circuit electrically connected to the corresponding power output port, the corresponding load sensing port, and the reference output node for detecting and amplifying the current from the corresponding load sensing port to output a sensing signal; and a voltage control circuit including: an error amplifier including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the error amplifier being electrically connected to the output terminal of the current sensing amplifier circuit to receive the sensing signal. The error amplifier has its second input terminal electrically connected to the reference output node to receive a reference input level. The error amplifier compares the detection signal with the reference input level to generate an error signal. The reference input level is obtained by voltage division of the reference supply voltage. A control switch includes a control terminal, an input terminal, and an output terminal. The control terminal of the control switch is electrically connected to the output terminal of the error amplifier. The input terminal of the control switch is electrically connected to the reference output node. The output terminal of the control switch is electrically connected to the corresponding sensing output port. The control switch determines the level of the corresponding sensing output port based on the error signal.

[0007] Optionally, the voltage control circuit further includes a voltage regulator, a capacitor, and a voltage divider circuit. The voltage regulator includes a first terminal, a second terminal, and a reference terminal. The first terminal and the reference terminal of the voltage regulator are short-circuited and electrically connected to the reference output node. The second terminal and the reference terminal of the voltage regulator are respectively connected to the opposite ends of the capacitor. The second input terminal of the error amplifier is electrically connected to the first terminal and the reference terminal of the voltage regulator through the voltage divider circuit.

[0008] Optionally, the voltage control circuit further includes an RC series circuit, the first end of which is connected to the output terminal of the control switch, the second end of which is connected to the first input terminal of the error amplifier, and the third end of which is connected to the output terminal of the error amplifier, with the second end between the first end and the third end.

[0009] Optionally, each of the reference sources includes a voltage regulator circuit, the input of which is connected to the power input port, and the output of which serves as the reference output node and is connected to the current detection amplifier circuit and the voltage control circuit. The voltage regulator circuit is used to stabilize the power from the power input port and to provide the reference supply voltage at the reference output node.

[0010] Optionally, each of the reference sources further includes a filter connected to the reference output node, the current detection amplifier circuit and the voltage control circuit, and used to filter out noise from the reference supply voltage.

[0011] Optionally, the current detection amplifier circuit includes a current detection circuit and a current amplifier circuit. The input and output terminals of the current detection circuit are electrically connected to the corresponding load detection port and the corresponding power output port, respectively. The current detection circuit is used to convert the current from the corresponding load detection port into a detection voltage. The current amplifier circuit is used to amplify the detection voltage and output the detection signal, and includes a current amplifier. The current amplifier includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the current amplifier is electrically connected to the output terminal of the current detection circuit and the reference output node. The second input terminal of the current amplifier is electrically connected to the input terminal of the current detection circuit. The output terminal of the current amplifier is fed back to the first input terminal of the current amplifier and electrically connected to the first input terminal of the error amplifier.

[0012] Optionally, each current sharing circuit block further includes an OR switch circuit, which is electrically connected to the power input port, the corresponding load detection port, the current detection amplifier circuit and the reference output node. The OR switch circuit is used to selectively connect the current detection amplifier circuit to the corresponding load detection port according to the detection signal and the reference supply voltage after voltage division, thereby selectively shutting down the current sharing circuit block.

[0013] Optionally, the switching circuit includes: a switching amplifier including a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the switching amplifier is electrically connected to the reference output node, and the second input terminal of the switching amplifier is electrically connected to the output terminal of the current sensing amplifier circuit; an optocoupler, wherein the input side of the optocoupler is electrically connected to the output terminal of the switching amplifier; a first switch including a driving terminal, an input terminal and an output terminal, wherein the driving terminal of the first switch is electrically connected to the output side of the optocoupler and the power input port, the input terminal of the first switch is electrically connected to the power input port, and the output terminal of the first switch is connected to the corresponding load sensing port; and two second switches, each second switch including a driving terminal, an input terminal and an output terminal, wherein the driving terminal of each second switch is connected to the input terminal of the first switch, the input terminal of each second switch is connected to the input terminal of the current sensing amplifier circuit, and the output terminal of each second switch is connected to the corresponding load sensing port.

[0014] Optionally, the parallel controller further includes a switch control block, comprising: a voltage regulator circuit electrically connected to the reference output node and the power input port; a hysteresis comparator circuit electrically connected to the voltage regulator circuit and the power input port, the hysteresis comparator circuit being configured to set a first quasi-threshold and a second quasi-threshold based on the power from the power input port, and comparing the output of the voltage regulator circuit with the first quasi-threshold and the second quasi-threshold to output a setting signal; a delay circuit electrically connected to the voltage regulator circuit, the hysteresis comparator circuit and the power input port, the delay circuit being configured to output a delayed output signal based on the setting signal and the output of the voltage regulator circuit; and a control switch circuit electrically connected to each of the OR switch circuits, the delay circuit and each of the load detection ports, and being configured to selectively connect each of the OR switch circuits electrically to the corresponding load detection port based on the delayed output signal.

[0015] In addition, according to one embodiment, the present invention provides a parallel power conversion system suitable for supplying power from an input power source to a load after conversion, and includes: a plurality of power converters; and the above-mentioned parallel controller for electrically connecting the plurality of power converters to the load.

Implementation Method

[0017] The parallel power conversion system provided by the present invention mainly utilizes the voltage droop method to ensure that the output current / voltage of multiple power converters can be supplied to the load end uniformly and stably. Although only a parallel power conversion system with two power converters is used as an example to illustrate the spirit of the present invention clearly and concisely, the parallel power conversion system of the present invention can also be applied to two or more power converters.

[0018] Referring to Figures 1 to 2B, the parallel power conversion system 1 provided by the present invention according to an embodiment mainly includes power converters 10_1 and 10_2 and a parallel controller 20. The input side of each power converter is electrically connected to an input power supply 2, and the output side of each power converter is electrically connected to the parallel controller 20 and a load 3.

[0019] The output side of each power converter includes a first conversion output port PC1, a second conversion output port PC2, a positive sensing port S1, and a negative sensing port S2. The load 3 includes a first load port L1 and a second load port L2. The first conversion output port PC1 of each power converter is electrically connected to the positive sensing port S1 and the first load port L1 of the load 3. In this embodiment, the first conversion output port PC1, the positive sensing port S1, and the first load port L1 are all positive terminals, and the second conversion output port PC2, the negative sensing port S2, and the second load port L2 are all negative terminals; however, the present invention is not limited thereto.

[0020] The parallel controller 20 includes a power input port CN1, power output ports CN2 and CN3, sensing output ports SO1 and SO2, and load sensing ports X1 and X2. Power input port CN1 is configured to be electrically connected to the first conversion output port PC1 of power converter 10_1 and the first load port L1 of load 3. Sensing output port SO1 is configured to be electrically connected to the negative sensing port S2 of power converter 10_1. Power output ports CN2 and CN3 are respectively configured to be electrically connected to the second conversion output port PC2 of power converters 10_1 and 10_2, and power output ports CN2 and CN3 are connected to ground. Sensing output ports SO1 and SO2 are respectively configured to be electrically connected to the negative sensing port S2 of power converters 10_1 and 10_2. Load sensing ports X1 and X2 are short-circuited and configured to be electrically connected to the second load port L2 of load 3. The number of power output ports, the number of sensing output ports, and the number of load sensing ports can be adjusted according to the number of power converters.

[0021] The parallel controller 20 includes, for example but not limited to, current sharing circuit blocks 21 and 22. Current sharing circuit blocks 21 and 22 correspond to power converters 10_1 and 10_2, respectively. The number of current sharing circuit blocks can be adjusted according to the number of power converters. Each current sharing circuit block includes a voltage regulator circuit 201, a current detection circuit 202, a current amplifier circuit 203, and a voltage control circuit 204.

[0022] Current sharing circuit blocks 21 and 22 are similar. To briefly illustrate the spirit of the present invention, current sharing circuit block 21 is described below.

[0023] The voltage regulator circuit 201 of the current sharing circuit block 21 includes, for example but not limited to, a switch Q1 (e.g., but not limited to, an NPN bipolar transistor (BJT)), a Zener diode ZD1, resistors R1-R3, and capacitors C1 and C2. The input terminal of switch Q1 (the emitter in the example of an NPN BJT) is connected to the power input port CN1 through resistor R1. The control terminal of switch Q1 (the base in the example of an NPN BJT) is connected to the power input port CN1 through resistors R2 and R3 connected in series. The opposite ends of capacitor C1 are respectively connected to the output terminal of switch Q1 (the collector in the example of an NPN BJT) and a common reference voltage terminal GND1 (or common reference voltage terminal GND2 in the current sharing circuit block 22 of FIG. 2B, and the voltage levels of the common reference voltage terminals GND1 and GND2 are, for example but not limited to, different). The first terminal (e.g., but not limited to, the cathode) and the second terminal (e.g., but not limited to, the anode) of the Zener diode ZD1 are respectively connected to the control terminal of switch Q1 and the common reference voltage terminal GND1. The opposite terminals of capacitor C2 are also connected to the control terminal of switch Q1 and the common reference voltage terminal GND1. In this way, the voltage regulator circuit 201 can stabilize the output voltage supplied from the first conversion output port PC1 to the power input port CN1, and adjust (e.g., but not limited to, step down) it to a reference supply voltage, which is then supplied to the downstream circuitry through the output terminal of switch Q1, which serves as a reference output node.

[0024] The current detection circuit 202 and the current amplification circuit 203 of the current sharing circuit block 21 together form a current detection amplification circuit.

[0025] The current sensing circuit 202 includes, for example but not limited to, at least one resistor (e.g., resistors R5 and R6). Resistors R5 and R6 are connected in parallel. The first terminal of resistors R5 and R6 (i.e., the output terminal of the current sensing circuit 202) is connected to the power output terminal CN2 (which is the power output terminal CN3 in the current sharing circuit block 22 of FIG. 2B). The second terminal of resistors R5 and R6 (i.e., the input terminal of the current sensing circuit 202 and the current sensing amplifier circuit) is connected to the load sensing port X1 (which is the load sensing port X2 in the current sharing circuit block 22 of FIG. 2B). In this way, the current from the second load port L2 of the load 3 can be detected and this current can be converted into a detection voltage (i.e., the voltage across resistors R5 and R6).

[0026] The current amplifier circuit 203 includes, for example but not limited to, an amplifier OP1 (i.e., a current amplifier), resistors R7-R14, capacitors C3-C5, and a rated voltage source V1, wherein the amplifier OP1 and resistors R7, R8, and R11-R14 together form a differential amplifier circuit. The rated voltage source V1 is, for example but not limited to, the amplifier power supply for amplifier OP1. The first input terminal of amplifier OP1 (e.g., but not limited to, the inverting input terminal) is connected to the first terminals of resistors R5 and R6 and the power output port CN1 through resistor R7. The second input terminal of amplifier OP1 (e.g., but not limited to, the non-inverting input terminal) is connected to the second terminals of resistors R5 and R6 and the load detection port X1 through resistor R8. The opposite ends of resistors R13 and R14 are respectively connected to the second input terminal of amplifier OP1 and the common reference voltage terminal GND1. The output terminal of amplifier OP1 (i.e., the output terminal of the current sensing amplifier circuit) is fed back to the first input terminal of amplifier OP1 through parallel resistors R11 and R12. The two opposite ends of capacitor C3 are connected to the output terminal of amplifier OP1 and the common reference voltage terminal GND1, respectively. In this way, amplifier OP1 can amplify and output the detection voltage on its input side to output a detection signal.

[0027] The voltage regulator circuit 201, resistors R9 and R10, capacitors C4 and C5, and the rated voltage source V1 can together form a reference source, for example, but not limited to, a voltage regulator filter circuit, wherein capacitors C4 and C5 and the rated voltage source V1 can form a filter. The output terminal of switch Q1 and the first terminals of capacitors C4 and C5 are connected (short-circuited) to a node N1. Node N1 is also connected to the first input terminal of amplifier OP1 through series resistors R9 and R10. The second terminals of capacitors C4 and C5 are connected to the common reference voltage terminal GND1. The positive and negative terminals of the rated voltage source V1 are connected to the first and second terminals of capacitors C4 and C5, respectively. In this way, the reference source can not only use the voltage regulator circuit 201 to stabilize the output current to provide a reference supply voltage, but also use the filter to filter out noise from the reference supply voltage.

[0028] The voltage control circuit 204 includes, for example but not limited to, an amplifier OP2 (i.e., an error amplifier), a switch Q2 (i.e., a control switch), a voltage regulator T1 (e.g., but not limited to, a TL431 adjustable parallel regulator), resistors R15 to R21, and capacitors C6 to C10 (e.g., but not limited to, NPN type BJTs).

[0029] The first terminal of resistor R16 is connected to node N1. The second terminal of resistor R16 and the first terminal of voltage regulator T1 (in the example of the TL431 adjustable parallel regulator, for example, but not limited to, the cathode) are connected (short-circuited) to the reference terminal at node N2. The first terminal of capacitor C7 is connected to the reference terminal of voltage regulator T1. The second terminal of capacitor C7 and the second terminal of voltage regulator T1 (in the example of the TL431 adjustable parallel regulator, for example, but not limited to, the anode) are connected to the common reference voltage terminal GND1. Resistor R16, voltage regulator T1, and capacitor C7 can be regarded as a voltage regulator circuit unit that can adjust (for example, but not limited to, step down) the reference supply voltage at node N1 to a precise reference input voltage for supply to subsequent circuits through node N2.

[0030] The first input terminal of amplifier OP2 (e.g., but not limited to, the inverting input terminal) is electrically connected to the output terminal of amplifier OP1 through resistor R15. The opposite ends of capacitor C6 are connected to the first input terminal of amplifier OP2 and the common reference voltage terminal GND1, respectively. The second input terminal of amplifier OP2 (e.g., but not limited to, the non-inverting input terminal) is electrically connected to node N2 through resistor R17. Resistors R18 and R19, and the first and second ends of capacitor C8 are connected to the second input terminal of amplifier OP2 and the common reference voltage terminal GND1, respectively. Resistors R17 to R19 form a voltage divider circuit, and node N2 can be used as the voltage divider node of this voltage divider circuit. The level of this voltage divider node can be used as the reference input level for the second input terminal of amplifier OP2. In this way, amplifier OP2 can compare the detected signal with the reference input level to output an error signal through its output terminal.

[0031] The control terminal of switch Q2 (the base in the example of an NPN BJT) is electrically connected to the output terminal of amplifier OP2 through resistor R20. The input terminal of switch Q2 (the emitter in the example of an NPN BJT) is connected to node N1. The first terminal of capacitor C9 is connected to the output terminal of amplifier OP2 and the first terminal of resistor S20. The second terminal of capacitor C9 is connected to the first terminal of resistor S21 and the first input terminal of amplifier OP2. The output terminal of switch Q2 (the collector in the example of an NPN BJT) is connected to the sensing output port SO1 (the sensing output port SO2 in block 22 of the current sharing circuit in Figure 2B), the first terminal of capacitor C10, and the second terminal of resistor R21. The second terminal of capacitor C10 is connected to the common reference voltage terminal GND1. Capacitor C9 and resistor S21 together form an RC series circuit, with the second terminal of resistor R21 serving as the first terminal of the RC series circuit, the node where capacitor C9 and resistor S21 are connected serving as the second terminal of the RC series circuit, and the first terminal of capacitor C9 serving as the third terminal of the RC series circuit.

[0032] When amplifier OP1 detects a high level of output current from load 3, the level of the detection signal at the output of amplifier OP1 rises, causing the level of the error signal at the output of amplifier OP2 to fall, resulting in a decrease in the level of the sensing signal at the output of switch Q2. Consequently, the power converter can correspondingly reduce its output voltage. This effectively achieves output current sharing. Furthermore, when the level of the detection signal at the output of amplifier OP1 falls, causing a lower voltage value on capacitor C10, the voltage level at the first input of amplifier OP2 will be lower than the voltage level at the second input of amplifier OP2. This causes switch Q2 to be turned on by the output voltage at the output of amplifier OP2, resulting in an increase in the voltage value on capacitor C10. Consequently, the power converter can correspondingly increase its output voltage, effectively achieving output current sharing.

[0033] Referring also to Figures 1 and 3A and 3B, according to another embodiment, the present invention provides a parallel controller 20. The current sharing circuit blocks 23 and 24 of the parallel controller 20 each include a voltage regulator circuit 201, a current detection circuit 202, a current amplifier circuit 203, a voltage control circuit 204, and an OR switch circuit 205. The voltage regulator circuit 201, current amplifier circuit 203, and voltage control circuit 204 in Figures 3A and 3B are the same as those in Figures 2A and 2B. The current detection circuit 202 in Figures 3A and 3B is similar to that in Figures 2A and 2B, except that resistors R5 and R6 are electrically connected to the corresponding load detection ports through the OR switch circuit 205.

[0034] To briefly illustrate the spirit of the present invention, the following description uses the current sharing circuit block 23 as an example.

[0035] Or the switching circuit 205 includes, for example but not limited to, an amplifier OP3 (i.e., a switching amplifier), an optocoupler OC, switches Q3-Q5 (e.g., but not limited to N-type metal-oxide-semiconductor field-effect transistors (NMOS)), Zener diodes ZD2 and ZD3, resistors R22-R28, and capacitors C11 and C12. The first input terminal of amplifier OP3 (e.g., but not limited to the inverting input terminal) is electrically connected to node N2 through resistor R22. The opposite ends of capacitor C12 and resistor R23 are respectively connected to the first input terminal of amplifier OP3 and the common reference voltage terminal GND1 (in the current sharing circuit block 24 of FIG3B, the common reference voltage terminal GND2). The second input terminal of amplifier OP3 (e.g., but not limited to the non-inverting input terminal) is connected to the output terminal of amplifier OP1 and is electrically connected to the common reference voltage terminal GND1 through capacitor C11.

[0036] The output terminal of amplifier OP3 is electrically connected to the positive terminal of the input side of optocoupler OC through resistor R24, and the cathode of the input side is connected to the common reference voltage terminal GND1. The first terminal of the output side of optocoupler OC (e.g., but not limited to the collector), the first terminal of ZD2 (e.g., but not limited to the cathode), and the second terminals of resistors R25 and R26 are connected to a node N3. The first terminal of resistor R25 is connected to the power input port CN1. The drive terminal (gate in the NMOS example) of switch Q3 (i.e., the first switch) is connected to node N3. The input terminal (drain in the NMOS example) of switch Q3 is electrically connected to the power input port CN1 through resistor R27. The drive terminals (gate in the NMOS example) of switches Q4 and Q5 (i.e., the second switches) are connected to the input terminal of switch Q3. The input terminals of switches Q4 and Q5 are connected and connected to the second terminals of resistors R5 and R6. Resistor R28 and the first terminal of Zener diode ZD3 are connected to the drive terminals of switches Q4 and Q5, respectively. The second terminal of the output side of optocoupler OC (e.g., but not limited to the emitter), the second terminal of Zener diode ZD2 (e.g., but not limited to the anode), the output terminals of switches Q3~Q5 (in the NMOS example, the output terminal is the source), and resistors R26 and R28 and the second terminal of Zener diode ZD3 are connected to load sensing port X1 (load sensing port X2 in current sharing circuit block 24 of Figure 3B).

[0037] When the individual power converter corresponding to the switching circuit 205 is operating normally, the current from the current detection amplifier circuit will pass through the light source of the optocoupler OC, causing the sensor of the optocoupler OC to be photosensitive and generate current, thereby turning off switch Q3 and turning on switches Q4 and Q5. Therefore, resistors R5 and R6 can be electrically connected to the corresponding load detection port. At this time, the voltage control circuit 204 can continue to perform current sharing. Conversely, when the individual power converter corresponding to the switching circuit 205 is unloaded or faulty, causing an output short circuit, no current is input to the optocoupler OC, causing switch Q3 to be turned on and switches Q4 and Q5 to be turned off, thereby turning off the unloaded or faulty power converter, while other normal power converters continue to operate.

[0038] Referring again to Figures 1 and 4A-4C, according to another embodiment, the present invention provides a parallel controller 20, wherein the voltage regulator circuit 201, current detection circuit 202, current amplification circuit 203, and voltage control circuit 204 of its current sharing circuit blocks 25 and 26 are the same as those of Figures 3A and 3B. The OR switch circuit 205 of Figures 4A and 4B is similar to that of Figures 3A and 3B, except that the second terminal of the output side of the optocoupler OC, the second terminals of the Zener diodes ZD2 and ZD3, the output terminals of switches Q3-Q5, and the second terminals of resistors R26 and R28 in Figures 4A and 4B are connected to the common reference voltage terminal GND3. The voltage levels of the common reference voltage terminals GND1, GND2, and GND3 are, for example, but not limited to, different.

[0039] The parallel controller 20 further includes a switch control block 27, which includes, for example but not limited to, a voltage regulator circuit 206, a hysteresis comparator circuit 207, a delay circuit 208 and a control switch circuit 209.

[0040] The voltage regulator circuit 206 includes, for example but not limited to, ZNER diodes ZD4 and ZD5, resistors R30-R32, capacitors C13-C14, and a rated voltage source V2. The first terminal of resistor R30 is connected to node N1. The second terminal of resistor R30, the first terminals of capacitors C13 and C14, the positive terminal of rated voltage source V2, the first terminal of ZNER diode ZD5 (e.g., but not limited to the cathode), and the first terminal of resistor R31 are connected to node N4. The second terminals of capacitors C13 and C14, the negative terminal of rated voltage source V2, and the second terminal of ZNER diode ZD5 (e.g., but not limited to the anode) are connected to the common reference voltage terminal GND3. The second terminal of resistor R31 is connected to the first terminal of ZNER diode ZD4 (e.g., but not limited to the anode) and the first terminal of resistor R32. The second terminal of ZNER diode ZD4 (e.g., but not limited to the cathode) and the second terminal of resistor R32 are connected to the power input port CN1.

[0041] Accordingly, the voltage regulator circuit 206 uses resistor R30 and Zener diode ZD5 to adjust the reference supply voltage at node N1 to the voltage level at node N4 (e.g., but not limited to 5V) and stabilize the voltage level at node N4; the voltage regulator circuit 206 also uses Zener diodes ZD4 and ZD5 and resistor R31 to stabilize the voltage at power input port CN1.

[0042] The hysteresis comparator circuit 207 includes, for example but not limited to, a voltage regulator T2 (e.g., but not limited to, a TL431 adjustable parallel regulator), a comparator OP4 (i.e., a hysteresis comparator), a Zener diode ZD6, diodes D1 and D2, resistors R33 to R39, and a capacitor C15. A rated voltage source V2 is, for example but not limited to, the comparator power supply for comparator OP4. The positive and negative terminals of the rated voltage source V2 are, for example but not limited to, connected (short-circuited) to node N4 and the common reference voltage terminal GND3, respectively. The first input terminal of comparator OP4 (e.g., but not limited to, the inverting input terminal) is electrically connected to node N4 through resistor R33. The first terminal of voltage regulator T2 (in the example of a TL431 adjustable parallel regulator, for example, but not limited to, the cathode), the reference terminal, and the first terminal of capacitor C15 are connected to the first input terminal of comparator OP4. The second terminal of the voltage regulator T2 (in the example of the TL431 adjustable parallel regulator, for example, but not limited to, the anode) and the second terminal of the capacitor C15 are connected (short-circuited) to the common reference voltage terminal GND3. In this way, the first terminal of the voltage regulator T2 can provide a precise reference input voltage (for example, but not limited to, 2.5V) to the first input terminal of the comparator OP4.

[0043] The first terminal of resistor R34 is connected to the power input port CN1. The second terminal of resistor R34, the first terminal of ZN diode ZD6 (e.g., but not limited to the cathode), the first terminal of resistor R35, and the second input terminal of comparator OP4 (e.g., but not limited to the inverting input terminal) are connected. The second terminal of ZN diode ZD6 (e.g., but not limited to the anode) and the second terminal of resistor R35 are connected (short-circuited) to the common reference voltage terminal GND3. The second input terminal of comparator OP4 is also electrically connected to the output terminal of comparator OP4 through resistor R36 and diode D1 connected in series.

[0044] The output of comparator OP4 is connected to node N4 through resistor R37 (i.e., the second resistor). The output of comparator OP4 is connected to the first end of resistor R39, and the second end of resistor R39 is connected to the output of comparator OP4 through diode D2 and resistor R38 connected in series.

[0045] Accordingly, comparator OP4 has a first threshold and a second threshold, and comparator OP4 can compare the signal from node N1 with the first threshold and the second threshold to output a setting signal through its output terminal. When the level of this signal is greater than the first threshold, the setting signal is at a high level. When the level of this signal is lower than the second threshold, the setting signal is at a low level. Specifically, when the voltage of the power input port CN1 starts to rise from 0V, the voltage of the second input terminal of comparator OP4 is lower than the voltage of the first input terminal of comparator OP4, so that the output terminal of comparator OP4 is at a low level, and therefore diode D1 is forward biased and turned on; at this time, resistors R35 and R36 are connected in parallel, and the voltage of the power input port CN1 will form a first voltage divider at the junction of resistor R34 and the parallel resistors R35 and R36 (i.e., the second input terminal of comparator OP4). Then, as the voltage at power input port CN1 continues to rise until the voltage at the second input terminal of comparator OP4 exceeds the voltage at the first input terminal of comparator OP4, the output of comparator OP4 becomes high, thus blocking diode D1 in reverse bias. At this time, the voltage at power input port CN1 forms a second voltage divider (i.e., the first threshold) at the junction of resistors R34 and R35 (i.e., the second input terminal of comparator OP4), and this second voltage divider is greater than the first voltage divider. When the voltage at power input port CN1 drops, it needs to drop even lower for the voltage at the second input terminal of comparator OP4 (i.e., the second threshold) to fall below the voltage at the first input terminal of comparator OP4, causing the output of comparator OP4 to become low. In this way, a voltage comparison hysteresis function is formed.

[0046] The delay circuit 208 includes, for example but not limited to, a comparator OP5 (i.e., a delay timing comparator), a Zener diode ZD7 (i.e., a second Zener diode), resistors R40~R41, and capacitors C16 and C17. The first input terminal of comparator OP5 (e.g., but not limited to, the inverting input terminal), the first input terminal of comparator OP4, and the first terminal of capacitor C16 (i.e., the second capacitor) are connected together. The second terminal of capacitor C16 is connected to the common reference voltage terminal GND3. The second input terminal of comparator OP5 (e.g., but not limited to, the non-inverting input terminal) is connected to the second terminal of resistor R39 and a series resistor R38 and diode D2. The opposite ends of resistor R40 and capacitor C17 are respectively connected to the second input terminal of comparator OP5 and the common reference voltage terminal GND3. The opposite ends of resistor R41 (i.e., the third resistor) are respectively connected to the power input port CN1 and the output terminal of comparator OP5. The first terminal of the ZD7 diode (e.g., but not limited to the cathode) is connected to the output of the comparator OP5, and the second terminal of the ZD7 diode is connected to the common reference voltage terminal GND3. In this way, the comparator OP5 can start timing and output a delayed output signal based on the level change of the set signal. When the set signal is at a high level, the delay circuit 208 starts timing, and when the timing reaches a preset time, the delayed output signal goes high.

[0047] The control switch circuit 209 includes, for example but not limited to, switches Q6-Q9 (i.e., power supply control switches), resistors R42-R43, and a capacitor C18. Switches Q6-Q9 are, for example but not limited to, NMOS. The drive terminals (gate terminals in the NMOS example) of switches Q6-Q9 are electrically connected to the output terminal of comparator OP5 through resistor R42. The opposite ends of resistor R43 and capacitor C18 are respectively connected to the drive terminals of each power supply control switch and the common reference voltage terminal GND3. The input terminals (drain terminals in the NMOS example) of switches Q6-Q9 are connected together, and the input terminals of switches Q7 and Q9 are connected to load detection ports X1 and X2, respectively. The output terminals (source terminals in the NMOS example) of switches Q6-Q9 are connected together and connected to the common reference voltage terminal GND3. In this way, the control switch circuit 209 can determine whether each load detection port is disconnected from the second load port L2 according to the level of the delayed output signal. When the delayed output signal is at a high level, switches Q6~Q9 are turned on, connecting each load detection port to the second load port L2.

[0048] Although the present invention has been disclosed above with reference to the foregoing embodiments, these embodiments are not intended to limit the present invention. Any modifications, refinements, and combinations of embodiments made without departing from the spirit and scope of the present invention are within the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the appended claims. [Simplified Explanation of the Diagram]

[0016] Other aspects and advantages of the invention will be discovered after studying the detailed description in conjunction with the following figures: Figure 1 is a circuit diagram of a parallel power conversion system according to an embodiment of the invention; Figures 2A and 2B are circuit diagrams of a parallel controller according to an embodiment of the invention; Figures 3A and 3B are circuit diagrams of a parallel controller according to another embodiment of the invention; and Figures 4A to 4C are circuit diagrams of a parallel controller according to yet another embodiment of the invention.

Claims

1. A parallel controller for a parallel power conversion system, the parallel power conversion system being adapted to electrically connect an input power supply to a load and further comprising a plurality of power converters, each power converter having an input side connected to the input power supply, each power converter having an output side including a first conversion output port, a second conversion output port, and a negative sensing port, each first conversion output port being connected to a first load port of the load, the parallel controller comprising: a power input port configured to be electrically connected to each of the first conversion output ports; a plurality of power output ports corresponding to the plurality of power converters, each power output port being configured to be electrically connected to the second conversion output port of the corresponding power converter; and a plurality of load sensing ports corresponding to the plurality of power converters and configured to be electrically connected to a second load port of the load; Multiple sensing output ports, corresponding to multiple power converters, each sensing output port being configured to be electrically connected to the negative sensing port of the corresponding power converter; and multiple current sharing circuit blocks, corresponding to the multiple power converters, the multiple power output ports, the multiple load sensing ports, and the multiple sensing output ports, each current sharing circuit block comprising: a reference source, electrically connected to the power input port, for adjusting the power from the power input port to provide a reference supply voltage via its reference output node; a current sensing amplifier circuit, electrically connected to the corresponding power output port, the corresponding load sensing port, and the reference output node, for detecting and amplifying the current from the corresponding load sensing port to output a detection signal; and a voltage control circuit, comprising: An error amplifier includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the error amplifier is electrically connected to the output terminal of a current sensing amplifier circuit to receive the detection signal. The second input terminal of the error amplifier is electrically connected to a reference output node to receive a reference input level. The error amplifier is used to compare the detection signal and the reference input level to generate an error signal. The reference input level is obtained by voltage division of the reference supply voltage. A control switch includes a control terminal, an input terminal, and an output terminal. The control terminal of the control switch is electrically connected to the output terminal of the error amplifier. The input terminal of the control switch is electrically connected to the reference output node. The output terminal of the control switch is electrically connected to a corresponding sensing output port. The control switch is used to determine the level of the corresponding sensing output port based on the error signal.

2. The parallel controller of the parallel power conversion system according to claim 1, wherein the voltage control circuit further includes a voltage regulator, a capacitor and a voltage divider circuit, the voltage regulator includes a first terminal, a second terminal and a reference terminal, the first terminal and the reference terminal of the voltage regulator are short-circuited and electrically connected to the reference output node, the second terminal and the reference terminal of the voltage regulator are respectively connected to the opposite ends of the capacitor, and the second input terminal of the error amplifier is electrically connected to the first terminal and the reference terminal of the voltage regulator through the voltage divider circuit.

3. The parallel controller of the parallel power conversion system according to claim 2, wherein the voltage control circuit further includes an RC series circuit, the first end of the RC series circuit being connected to the output terminal of the control switch, the second end of the RC series circuit being connected to the first input terminal of the error amplifier, the third end of the RC series circuit being connected to the output terminal of the error amplifier, and the second end of the RC series circuit being between the first end and the third end of the RC series circuit.

4. The parallel controller of the parallel power conversion system according to claim 1, wherein each reference source includes a voltage regulator circuit, the input of the voltage regulator circuit is connected to the power input port, the output of the voltage regulator circuit is connected as the reference output node to the current detection amplifier circuit and the voltage control circuit, the voltage regulator circuit is used to stabilize the power from the power input port, and provides the reference supply voltage at the reference output node.

5. The parallel controller of the parallel power conversion system according to claim 4, wherein each of the reference sources further includes a filter connected to the reference output node, the current sensing amplifier circuit and the voltage control circuit, and is used to filter out noise from the reference supply voltage.

6. A parallel controller for a parallel power conversion system according to claim 1, wherein the current sensing amplifier circuit includes a current sensing circuit and a current amplification circuit, the input and output terminals of the current sensing circuit being electrically connected to the corresponding load sensing port and the corresponding power output port, respectively, the current sensing circuit being used to convert the current from the corresponding load sensing port into a sensing voltage; and the current amplification circuit being used to amplify the sensing voltage and output the sensing signal, and including a current amplifier, the current amplifier including a first input terminal, a second input terminal and an output terminal, the first input terminal of the current amplifier being electrically connected to the output terminal of the current sensing circuit and the reference output node, the second input terminal of the current amplifier being electrically connected to the input terminal of the current sensing circuit, and the output terminal of the current amplifier being fed back to the first input terminal of the current amplifier and electrically connected to the first input terminal of the error amplifier.

7. The parallel controller of the parallel power conversion system according to claim 1, wherein each current sharing circuit block further includes an OR switch circuit electrically connected to the power input port, the corresponding load detection port, the current detection amplifier circuit and the reference output node, the OR switch circuit being used to selectively electrically connect the current detection amplifier circuit to the corresponding load detection port according to the detection signal and the reference supply voltage after voltage division, thereby selectively shutting down the current sharing circuit block.

8. The parallel controller for the parallel power conversion system according to claim 7, wherein the switching circuit comprises: a switching amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the switching amplifier being electrically connected to the reference output node, and the second input terminal of the switching amplifier being electrically connected to the output terminal of the current sensing amplifier circuit; and an optocoupler having its input side electrically connected to the output terminal of the switching amplifier. A first switch includes a driving terminal, an input terminal, and an output terminal. The driving terminal of the first switch is electrically connected to the output side of the optocoupler and the power input port. The input terminal of the first switch is electrically connected to the power input port. The output terminal of the first switch is connected to the corresponding load detection port. Two second switches, each including a driving terminal, an input terminal, and an output terminal, are also provided. The driving terminal of each second switch is connected to the input terminal of the first switch. The input terminal of each second switch is connected to the input terminal of the current detection amplifier circuit. The output terminal of each second switch is connected to the corresponding load detection port.

9. The parallel controller of the parallel power conversion system according to claim 7 further includes a switching control block, comprising: a voltage regulator circuit electrically connected to the reference output node and the power input port; a hysteresis comparator circuit electrically connected to the voltage regulator circuit and the power input port, the hysteresis comparator circuit being configured to set a first quasi-threshold and a second quasi-threshold based on power from the power input port, and comparing the output of the voltage regulator circuit with the first quasi-threshold and the second quasi-threshold to output a setting signal; a delay circuit electrically connected to the voltage regulator circuit, the hysteresis comparator circuit and the power input port, the delay circuit being configured to output a delayed output signal based on the setting signal and the output of the voltage regulator circuit; and a control switch circuit electrically connected to each of the OR switch circuits, the delay circuit and each of the load detection ports, and being configured to selectively connect each of the OR switch circuits electrically to the corresponding load detection port based on the delayed output signal.

10. A parallel power conversion system adapted to supply power from an input power source to a load after conversion, and comprising: a plurality of power converters; and a parallel controller as described in any one of claims 1 to 9 for electrically connecting the plurality of power converters to the load.

Images