System and methods for generating inference information on a revisable model on a storage device

Abstract

A system and related method, including memory and processing circuitry, which is to receive multiple weights from a host device to implement an instantiation of a model on the storage device. The instantiation of the model includes multiple weights, and each weight is determined using another instantiation of the model that was trained on the host device. The processing circuitry is then to generate inference information using the instantiation of the model implemented on the storage device. The processing circuitry is further to receive multiple updated weights from the host device and update the instantiation of the model based on the multiple updated weights to implement an updated instantiation of the model on the storage device. The processing circuitry is then to generate updated inference information on the storage device using the updated instantiation of the model based on at least one signal to be processed by the processing circuitry.

Description

[Technical Field]

[0001] This disclosure relates to a system and method for generating inference information on a storage device using a model based on at least one signal received from a host system. [Previous Technology]

[0002] and [Summary of the Invention]

[0003] According to this disclosure, a system and method are provided for generating inference information on a storage device (e.g., a solid-state drive (SSD) device) using a modifiable instantiation of a model based on at least one signal to be processed. The system and method disclosed herein enable an instantiation of the model on a host (e.g., a first instantiation of the model) to be trained by the host without communicating with the storage device, and then an instantiation of the model implemented on the storage device (e.g., a second instantiation of the model) to be updated. This allows the first instantiation of the model to be trained by a centralized host while at least one storage device is using an implemented instantiation of the model (e.g., the second instantiation of the model), and the model can be updated at any time by receiving updated data. When the storage device receives a signal to be processed, the storage device generates inference information based on at least one received signal using the instantiation of the model on the storage device. The system and method disclosed herein utilize the modifiable instantiation of the model on the storage device to enable a centralized host to maintain a trained instantiation of the model and then distribute updated weights to at least one storage device to implement the updated instantiation on the storage device. This system and method disclosed herein offloads the work of training the instantiation of the model from each storage device, allowing each storage device to focus on the execution of operations rather than firmware or system training, which will require only a minimal amount of bandwidth and power from each storage device. This improves the overall access efficiency and power consumption of the processing circuitry of the storage device (e.g., a solid-state drive).

[0004] In some embodiments, the system (e.g., a storage device) is provided with a memory and processing circuitry communicatively coupled to each other. In some embodiments, the system may be distributed between a storage device and another device separate from the storage device (e.g., a host, such as a storage controller device), wherein the host provides control circuitry to implement at least some of the functions described herein. In some embodiments, the processing circuitry receives updated weights from the host device. In some embodiments, the processing circuitry updates the instantiation of the model on the storage device according to the updated weights to implement an updated instantiation of the model on the storage device. The processing circuitry then uses the updated instantiation of the model to generate inference information on the storage device according to at least one signal to be processed.

Implementation Method

[0011] According to this disclosure, a system and method are proposed for generating inference information on a storage device (e.g., a solid-state drive (SSD) device) based on at least one signal to be processed, using a modifiable instantiation of a model (e.g., a neural network, a machine learning neural network, or any other suitable neural network with a training / learning architecture). An SSD device may implement a model to aid instruction execution, wherein the model is trained on the SSD device, and wherein operations processed by the SSD are used as training data. However, if the processing circuitry of the SSD is responsible for training the model, the processing circuitry has limited available bandwidth for processing instructions and for performing operations (e.g., reading and writing). Furthermore, in a system with more than one storage device, each storage device trains a separate instantiation of the model. In such a system, each SSD training its individual instantiation of the model further degrades the limited bandwidth of the system. This results in inefficiency of the processing circuitry of each storage device.

[0012] If the processing circuitry of the SSD device can offload the training of the model instantiation to another device (e.g., a host), the bandwidth available to each storage device will be improved. To improve the efficiency of the SSD device, the processing circuitry can implement an instantiation of the model based on a trained instantiation of the model on a host device to process the received signals. Therefore, the host is responsible for training an instantiation of the model and then transmitting updated data (e.g., weights for updating the model) to update the instantiation of the model on the storage device.

[0013] The processing circuit generates inference information on the storage device by using an instantiation of a model implemented on the storage device. Each instantiation of the model includes a plurality of weights, each of which is determined using another instantiation of the model trained on a host coupled to the storage device. At some point after the instantiation of the model is implemented on the storage device, the processing circuit may receive a plurality of updated weights from the host. Once the processing circuit receives the plurality of updated weights, it implements an updated instantiation of the model on the storage device based on the plurality of updated weights. When the processing circuit receives a signal to be processed, it generates updated inference information on the storage device using the updated instantiation of the model based on at least the received signal to be processed. In some embodiments, the processing circuit may continuously update the instantiation of the model on the storage device by receiving further updated weights from the host.

[0014] In some embodiments, the memory of the system disclosed herein may include any of the following memory densities: single-layer cell (SLC), multi-layer cell (MLC), three-layer cell (TLC), four-layer cell (QLC), five-layer cell (PLC), and any suitable memory density with more than five bits per memory cell.

[0015] For the purposes of brevity and clarity, the features of this disclosure are presented within the context of a storage device having processing circuitry and memory. However, the principles of this disclosure can be applied to any other suitable context, where inference information is generated on a storage device based on at least one signal to be processed using a modifiable instantiation of a model. A storage device may include processing circuitry and memory, and the processing circuitry and memory are communicatively coupled via a network bus or interface. In some embodiments, the processing circuitry receives signal-updated data (e.g., updated weights), which may be driven from a source outside the storage device (e.g., the host) on a network bus or interface, or may be sent from within the storage device (e.g., from memory).

[0016] In some embodiments, a processor of the processing circuit may be a highly parallelized processor capable of rapidly processing high-bandwidth incoming data. For example, the processing circuit may begin generating inference information for a signal to be processed before completing the generation of inference information for a previously received signal to be processed.

[0017] In some embodiments, the system and method disclosed herein may refer to a storage device system (e.g., an SSD storage system) that includes a storage device, such as a solid-state drive, which is communicatively coupled to the processing circuitry via a network bus or interface.

[0018] An SSD is a data storage device that uses integrated circuit components as memory to continuously store data. SSDs have no moving mechanical parts, a characteristic that distinguishes them from traditional electromechanical disks, such as hard disk drives (HDDs) or floppy disks, which contain rotating platters and movable read / write heads. Compared to electromechanical disks, SSDs are generally more resistant to physical shocks, operate quietly, have shorter access times, and lower latency.

[0019] Many types of SSDs utilize NAND-based flash memory, which retains data without power and incorporates a type of non-volatile storage technology. The Quality of Service (QoS) of an SSD can be related to the predictability of low latency and high consistency of input / output operations per second (IOPS) under read / write input / output (I / O) workloads. This means that the latency or I / O command completion time needs to be within a specified range without unexpected outliers. Processing volume or I / O rates may also need to be strictly monitored to avoid sudden drops in performance levels.

[0020] The subject matter of this disclosure can be better understood by referring to Figures 1-5.

[0021] FIG1 illustrates an example of a system 100 according to certain embodiments of the present disclosure, comprising a host device (e.g., host 108) and a storage device 102 having a processing circuitry 104 and memory 106. In some embodiments, the storage device 102 may be a solid-state storage device (e.g., a solid-state drive (SSD) device). In some embodiments, the processing circuitry 104 may include a processor or any suitable processing unit. In some embodiments, the memory 106 may be non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, the storage device 102 may additionally include a hard disk drive (HDD) device, or include a hard disk drive (HDD) device instead of an SSD. In some embodiments, the system 100 includes a host 108 that communicates with the storage device 102.

[0022] The host 108 includes a first instantiation 112 of the model, which may be implemented on the control circuitry of the host 108. In some embodiments, the control circuitry trains the first instantiation 112 of the model using analog signals. The first instantiation 112 of the model is used to determine weights (e.g., updated weights 110) based on training by the host 108. Each weight of a model contributes to a decision outcome or result based on an input (e.g., a received signal to be processed). Once the processing circuitry 104 receives the weights from the host 108, the processing circuitry 104 implements a second instantiation 114 of the model on the storage device 102. The processing circuitry 104 then uses the second instantiation 114 of the model on the storage device to generate inference information based on at least one signal to be processed. The second instantiation 114 of the model may be updated when the processing circuitry 104 receives updated weights 110 from the host 108. In some embodiments, the second instantiation 114 of the model can be updated at any time via any appropriate firmware update request to receive updated data (e.g., updated weights 110).

[0023] In some embodiments, the processing circuitry 104 is configured to generate inference information on the storage device using the second instantiation 114 of the model implemented on the storage device 102. In some embodiments, the second instantiation 114 of the model is implemented based on weights received from the host 108, which determines the weights by training the first instantiation 112 of the model. The processing circuitry further receives a plurality of updated weights from the host 108 and then updates the second instantiation 114 of the model based on the plurality of updated weights to implement an updated instantiation on the storage device 102. Once the second instantiation 114 of the model is updated to the updated instantiation of the model, the processing circuitry 104 then determines updated inference information on the storage device 102 using the updated instantiation of the model based on at least one pending signal. In some embodiments, the garbage collection request includes a destination memory address corresponding to destination data that may be outdated or invalid. In some embodiments, garbage collection requests and weights (e.g., updated weights 110) are sent to the processing circuitry 104 via a network bus or interface. In some embodiments, garbage collection requests and weights (e.g., updated weights 110) are sent from an external source (e.g., host 108). In some embodiments, the processing circuitry 104 receives signals (e.g., garbage collection requests and updated weights 110) from both internal and external sources of the storage device 102. A temporary memory (e.g., cache or queue) may also be located within the processing circuitry 104, configured to store any unresolved requests to be processed by the processing circuitry 104.

[0024] Furthermore, the storage device 102 includes memory 106. In some embodiments, memory 106 includes any or more of the following: a nonvolatile memory such as a phase-change memory (PCM), a PCM and switch (PCMS), a ferroelectric random access memory (FeRAM), or a ferroelectric transistor random access memory (FeTRAM), a memristor, a spin-transfer torque random access memory (STT-RAM), and a magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, memory 106 may include volatile memory in cache form. In some embodiments, memory 106 may include single-cell (SLC) memory, multi-cell (MLC) memory, three-cell (TLC) memory, four-cell (QLC) memory, five-cell (PLC) memory, or any other suitable memory having a memory density greater than 5 bits per memory cell. In some embodiments, processing circuitry 104 is communicatively coupled to memory 106 to store and access data for executing signals / requests. In some embodiments, a data bus between memory 106 and processing circuitry 104 provides a network bus for accessing or writing data to memory 106. In some embodiments, the processor or processing unit of processing circuitry 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor (also referred to herein as processing circuitry 104) may include any suitable software, hardware, or both for controlling memory 106 and processing circuitry 104. In some embodiments, storage device 102 may further include a multi-core processor. Memory 106 may also include hardware elements for non-transitory storage of instructions, commands, or requests.

[0025] The processing circuit 104 is configured to generate inference information on a storage device based on at least one signal to be processed, using a modifiable instantiation of a model, wherein the instantiation of the model is implemented on the storage device using weights received from a host device, and wherein another instantiation of the model has been trained on the host device. Furthermore, the processing circuit 104 can receive updated weights 110 from the host 108. The updated weights 110 are determined by using a first instantiation 112 of a model trained on the host 108. The updated weights 110 are used to implement a second instantiation 114 of the model on the storage device 102. Each weight of a model contributes to a decision outcome or result based on an input (e.g., a received signal to be processed). Once the processing circuit 104 receives the updated weights 110 from the host 108, the processing circuit 104 updates the second instantiation 114 of the model on the storage device 102. The processing circuit 104 then generates updated inference information on the storage device based on at least one signal to be processed, using the updated second instantiation of the model. These procedures enable an instantiation of the model on the host 108 (e.g., the first instantiation 112 of the model) to be trained by the host 108 without communicating with the storage device 102, and then update the instantiation of the model implemented on the storage device 102 (e.g., the second instantiation 114 of the model). This allows an instantiation of the model to be trained by a centralized host 108 while at least one storage device (e.g., storage device 102) is using an instantiation of an implementation of the model (e.g., the second instantiation 114 of the model), which can be updated at any time by receiving updated data (e.g., updated weights 110) through any appropriate firmware update request.

[0026] A storage device (e.g., an SSD device) may include one or more packages containing memory chips (e.g., containing memory 106), wherein each chip contains a storage cell. In some embodiments, the storage cells are organized into pages, and the pages are organized into blocks. Each storage cell may store one or more bits of information.

[0027] It will be understood that although the system 100 according to this disclosure describes one embodiment in which a storage device 102 is configured to have the function of generating inference information on a storage device based on a modifiable instantiation of a model according to at least one signal to be processed, any other suitable device may be implemented in a similar manner.

[0028] For clarity and brevity, and not for limitation, this disclosure is made in the context of generating inference information on a storage device based on at least one signal to be processed using a modifiable instantiation of a model, providing the features and functions disclosed herein. The program for generating inference information on a storage device based on at least one signal to be processed using a modifiable instantiation of a model can be configured by any suitable software, hardware, or both to implement such features and functions. Generating inference information on a storage device based on at least one signal to be processed using a modifiable instantiation of a model can be implemented at least partially in, for example, storage device 102 (e.g., as part of processing circuitry 104 or any other suitable device). For example, for a solid-state storage device (e.g., storage device 102), the generation of inference information on a storage device based on at least one signal to be processed using a modifiable instantiation of a model can be implemented in processing circuitry 104.

[0029] FIG2 shows an illustrative diagram of a system 200 according to certain embodiments of the present disclosure, which includes a host device 108 communicating with a plurality of storage devices (e.g., storage device_1 202, storage device_2 204, storage device_3 206, and storage device_N 208).

[0030] The host 108 includes a first instantiation 112 of the model, which can be implemented on the control circuitry of the host 108 and used for training. The host 108 is communicatively coupled to each of the storage devices (e.g., 202, 204, 206, and 208) via a network interface or data bus. Each other storage device (e.g., 202, 204, 206, and 208) has another instantiation of the model implemented on the individual storage device (e.g., a second instantiation 203 of the model, a third instantiation 205 of the model, a fourth instantiation 207 of the model, and an Nth instantiation 209 of the model). The host 108 is configured to train the first instantiation 112 of the model to determine updated weights 110, which are transmitted to each of the storage devices (e.g., storage device_1 202, storage device_2 204, storage device_3, and storage device_N 208) via the network interface or data bus. Once another storage device receives the updated weights 110 from the host 108, the individual storage device 102 uses the updated weights 110 to update the individual instantiation of the model. This system 200 enables a distributed system to have multiple storage devices with an instantiation of a model, wherein the instantiation of the model can be updated simultaneously.

[0031] Figure 3 illustrates an example of a host 108 training an instance of a model (e.g., a first instance 112 of the model) according to certain embodiments of the present disclosure. The host 108 includes control circuitry 302, a first instance 112 of the model implemented on the control circuitry 302, and a training module 304. The training module 304 is configured to transmit a simulated signal 306 to the first instance 112 of the model to train the first instance 112 of the model. The first instance 112 of the model generates a training result 308 based on the simulated signal 306 and transmits the training result 308 to the training module 304. In some embodiments, the training module 304 further compares the expected training result corresponding to the simulated signal 306 with the training result 308 generated by the first instance 112 of the model. The weights of the first instantiation 112 of the model can be adjusted based on a comparison of the training result 308 with the expected training result corresponding to the simulated signal 306. In some embodiments, the comparison of the training result 308 with the expected training result can also be used to determine the effectiveness of the first instantiation 112 of the model and whether the first instantiation of the model needs further training.

[0032] At any time, the control circuitry 302 of the host 108 may transmit updated weights 310 to the storage device 102. In some embodiments, the updated weights 310 are received by the processing circuitry 104 and used to implement the second instantiation 114 of the model. In some embodiments, the updated weights 310 are transmitted to the storage device 102 via a data bus or network interface that communicatively couples the host 108 to the storage device 102. In some embodiments, the first instantiation 112 of the model is trained by the control circuitry 302 without communicating with the storage device 102, and then the instantiation of the model implemented on the storage device 102 is updated (e.g., the second instantiation 114 of the model).

[0033] Figure 4 illustrates a flowchart 400 illustrating steps according to certain embodiments of the present disclosure, for generating inference information using an instantiation of a model on a storage device based on at least one signal, and updating the instantiation of the model on the storage device. In some embodiments, the referenced storage device, processing circuitry, memory, host, updated weights, first instantiation of the model, second instantiation of the model, control circuitry, training module, and simulated signal may be implemented as storage device 102, processing circuitry 104, memory 106, host 108, updated weights 110, first instantiation of the model 112, second instantiation of the model 114, control circuitry 302, training module 304, and simulated signal 306, respectively. In some embodiments, the procedure 400 may be modified, for example, by rearranging, changing, adding, and / or deleting steps.

[0034] In step 402, the processing circuitry generates inference information on the storage device using an instantiation of a model implemented on the storage device, wherein the instantiation of the model includes a plurality of weights, each of which is determined using another instantiation of the model trained on a host device coupled to the storage device. In some embodiments, the processing circuitry implements an instantiation of the model on the storage device using a plurality of weights received from the host (e.g., a second instantiation of the model). In some embodiments, the host includes control circuitry to train another instantiation of the model (e.g., a first instantiation of the model) using simulated signals, the simulated signals being similar to the expected signals that the processing circuitry will receive and process. Furthermore, the control circuitry of the host may include a training module to generate and transmit the simulated signals to the other instantiation of the model (e.g., the first instantiation of the model) and then compare the expected result of the simulated signals with the test result received from the other instantiation of the model (e.g., the first instantiation of the model). In some embodiments, the host trains the other instantiation of the model based on simulated signals when the host is not communicatively coupled to the storage device. The weights are determined by the host and transmitted to the processing circuitry of the storage device to implement the instantiation of the model (e.g., the second instantiation of the model). In some embodiments, the processing circuitry generates inference information using the implemented instantiation of the model based on at least one signal received by the processing circuitry. In some embodiments, the generated inference information includes a predicted operation to be performed by the processing circuitry based on at least one received signal. In some embodiments, the predicted operation may be any one of a workload detection operation, a hot operation, a storage device optimization operation, or a storage device arbitration operation. Once the inference information is generated on the storage device, the processing circuitry may receive multiple updated weights from the host device in step 404.

[0035] In step 404, the processing circuit receives multiple updated weights from the host device on the storage device. In some embodiments, the processing circuit receives the multiple updated weights from a firmware update request transmitted by the host. In some embodiments, the processing circuit receives the updated weights from a network interface or data bus that communicatively couples the storage device to the host. When the processing circuit of the storage device receives the multiple updated weights from the host device, the processing circuit then updates the instantiation of the model according to the multiple updated weights in step 406 to implement an updated instantiation of the model on the storage device.

[0036] In step 406, the processing circuit updates the instantiation of the model according to the plurality of updated weights to implement an updated instantiation of the model on the storage device. In some embodiments, the number of updated weights may be the same as the number of weights in an original instantiation of the model implemented on the storage device. Once the updated instantiation of the model is implemented on the storage device, in step 408, the processing circuit generates updated inference information on the storage device based on at least one signal to be processed, using the updated instantiation of the model.

[0037] In step 408, the processing circuit generates updated inference information on the storage device based on at least one signal to be processed, using the updated instantiation of the model. In some embodiments, the generated updated inference information is for a predictive operation to be performed by the processing circuit based on at least one signal. In some embodiments, given the same signal received by the processing circuit, the updated inference information generated using the updated instantiation of the model may be different from the inference information generated using a previous version of the model instantiation. In some embodiments, the updated instantiation of the model may be updated when the processing circuit receives any other updated weights from the host.

[0038] Figure 5 illustrates a flowchart of the steps of a subroutine according to certain embodiments of the present disclosure, used to generate inference information on the storage device using an instantiation of a model implemented on the storage device (e.g., as shown at 402 in Figure 4). In some embodiments, the referenced storage device, processing circuitry, memory, host, updated weights, first instantiation of the model, and second instantiation of the model may be implemented as storage device 102, processing circuitry 104, memory 106, host 108, updated weights 110, first instantiation of the model 112, and second instantiation of the model 114, respectively. In some embodiments, the subroutine 500 may be modified by, for example, rearranging, changing, adding, and / or deleting steps.

[0039] In step 502, the processing circuit determines a moving average from the at least one signal to be processed and generates inference information based on the determined moving average. In some embodiments, the moving average can be determined based on a preset number of signals received by the processing circuit. For example, an instantiation of a model implemented on the storage device can be used to generate inference information for workload detection. In this example, the processing circuit of the storage device can receive, for example, signals that are instructions or operations to be processed by the processing circuit, and then predict the expected instructions or operations based on a moving average over previously received signals. In some embodiments, the moving average is continuously adjusted based on the most recently received signals on the storage device.

[0040] Unless otherwise expressly indicated, the terms "an embodiment", "an embodiment", "multiple embodiments", "the embodiment", "the multiple embodiments", "one or more embodiments", "some embodiments", and "an embodiment" mean "one or more (but not all) embodiments".

[0041] Unless otherwise expressly indicated, the terms “comprising,” “including,” “having,” and variations thereof mean “including but not limited to.”

[0042] Unless otherwise expressly indicated, the list of items does not imply that any or all of the items are mutually exclusive.

[0043] Unless otherwise expressly indicated, the terms “a”, “an”, “one” and “the” mean “one or more”.

[0044] Unless otherwise expressly specified, the devices communicating with each other need not be in continuous communication with each other. Furthermore, the devices communicating with each other may communicate directly or indirectly through one or more intermediaries.

[0045] The description of an embodiment having several components that communicate with each other does not imply that all such components are necessary. Rather, various optional components are described to illustrate many possible embodiments. Furthermore, although program steps, method steps, algorithms, or the like may be described in a sequential order, such programs, methods, and algorithms may be configured to run in an alternative order. In other words, any sequence or order of steps that may be described does not necessarily indicate that the steps need to be performed in that order. The steps of the program described herein can be performed in any practically feasible order. Moreover, some steps may be performed simultaneously.

[0046] When a single device or article is described herein, it will be quite obvious that more than one device / article (whether or not they cooperate) can be used to replace the single device / article. Similarly, in cases where more than one device or article is described herein (whether or not they cooperate), it will be quite obvious that a single device / article can be used to replace the more than one device or article, or a different number of devices / articles can be used to replace the number of devices or programs shown. The function and / or feature of a device may alternatively be embodied by one or more other devices that are not explicitly stated to have such function / feature. Therefore, other embodiments do not need to include the device itself.

[0047] At least some of the operations depicted in the diagrams may represent events occurring in a certain order. In alternative embodiments, some operations may be performed, modified, or deleted in a different order. Furthermore, steps may be added to the logic described above, while still conforming to the embodiments. Furthermore, the operations described herein may occur sequentially, or some operations may be processed in parallel. Moreover, operations may be performed by a single processing unit or by distributed processing units.

[0048] The foregoing description of various embodiments has been presented for illustrative purposes. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible based on the teachings above. [Simplified Explanation of the Diagram]

[0005] The following description includes a discussion of illustrative diagrams illustrating embodiments of the present disclosure. These diagrams should be understood as illustrative and not restrictive. As used herein, references to one or more "embodiments" are to be understood as describing a particular feature, structure, and / or characteristic contained in at least one implementation. Therefore, phrases appearing herein, such as "in one embodiment" or "in an alternative embodiment," describe various embodiments and implementations and do not necessarily refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0006] [Figure 1] shows an illustrative diagram of an example of a system according to certain embodiments of the present disclosure, which includes a host device and a storage device having a processing circuit and memory;

[0007] [Figure 2] shows an illustrative diagram of an example of a system according to certain embodiments of the present disclosure, which includes a host device communicating with a plurality of storage devices;

[0008] [Figure 3] is an illustrative diagram showing an instance of a host device for training a model according to certain embodiments of the present disclosure;

[0009] [Figure 4] A flowchart illustrating illustrative steps according to certain embodiments of the present disclosure for generating inference information on a storage device based on at least one signal using an instantiation of a model, and updating the instantiation of the model on the storage device; and

[0010] [Figure 5] shows a flowchart illustrating the steps of a subroutine according to certain embodiments of the present disclosure, which is used to generate inference information on the storage device by means of an instantiation of a model implemented on the storage device as shown in Figure 4.

Claims

1. A method for processing at least one signal on a storage device, the method comprising: Inference information is generated on the storage device using an instantiation of a model implemented on the storage device, the instantiation of the model including a plurality of weights, wherein the plurality of weights are determined using another instantiation of the model already trained on a host device coupled to the storage device; the storage device receives a plurality of updated weights from the host device; The instantiation of the model is updated according to the plurality of updated weights to implement the updated instantiation of the model; and updated inference information is generated on the storage device using the updated instantiation of the model according to the at least one signal.

2. The method of claim 1, wherein the other instantiation of the model is trained on the host device based on simulated data when the host device is not communicatively coupled to the storage device.

3. The method of claim 2, wherein the data of the simulation used to train the model in the other instantiation is determined by the host device based on a subset of expected signals to be processed by the instantiation of the model on the storage device.

4. The method of request item 1, wherein the inference information includes predicted operations from a plurality of operations.

5. The method of claim 4, wherein the plurality of operations includes any one or more of the following: (a) workload detection operation, (b) thermal arbitration operation, (c) device power optimization operation, or (d) device bandwidth arbitration operation.

6. The method of claim 1, wherein generating inference information using the instantiation of the model on the storage device includes: Determining a moving average from the at least one signal, and wherein generating inference information includes generating inference information based on the moving average.

7. A storage device comprising: Memory; The processing circuitry includes: receiving a plurality of weights from a host device to instantiate a model on the storage device, wherein the instantiation of the model comprises a plurality of weights, each of which is determined using another instantiation of the model trained on the host device; generating inference information using the instantiation of the model implemented on the storage device; receiving a plurality of updated weights from the host device; updating the instantiation of the model based on the plurality of updated weights to implement an updated instantiation of the model; and generating updated inference information on the storage device using the updated instantiation of the model based on at least one signal to be processed.

8. The storage device as claimed in claim 7, wherein the other instantiation of the model is trained on the host device based on simulated data when the host device is not communicatively coupled to the storage device.

9. The storage device of claim 8, wherein the data of the simulation used to train the model in the other instantiation is determined by the host device based on a subset of expected signals to be processed by the instantiation of the model on the storage device.

10. The storage device as claimed in claim 7, wherein the inference information includes predicted operations from a plurality of operations.

11. The storage device of claim 10, wherein the plurality of operations includes any one or more of the following: (a) workload detection operation, (b) thermal arbitration operation, (c) device power optimization operation, or (d) device bandwidth arbitration operation.

12. The storage device of claim 7, wherein, in order to generate inference information using the instantiation of the model on the storage device, the processing circuitry is: determining a moving average from the at least one signal, and wherein generating inference information includes generating inference information based on the moving average.

13. A system comprising: Host, It includes: control circuitry coupled to a communication bus to: train a first instantiation of a model to provide inference output, wherein the first instantiation of the trained model includes a plurality of weights; transmit the plurality of weights to a storage device using the communication bus; transmit a plurality of updated weights to the storage device using the communication bus; and the storage device coupled to the communication bus, the storage device including: memory; and processing circuitry to: receive the plurality of weights; implement a second instantiation of the model on the storage device based on the plurality of weights; generate inference information using the second instantiation of the model based on at least one signal to be processed; receive a plurality of updated weights from the host; update the second instantiation of the model based on the plurality of updated weights to implement an updated second instantiation of the model; and generate updated inference information using the updated second instantiation of the model.

14. The system of claim 13, wherein the first instantiation of the trained model is performed on the host based on simulated data when the host is not communicatively coupled to the storage device.

15. The system of claim 14, wherein the simulated data used to train the first instantiation of the trained model is determined by the control circuitry based on a subset of expected signals to be processed by the second instantiation of the model.

16. The system of claim 14, wherein the control circuitry further: transmits the simulated data to the first instantiation of the model, receives training results from the first instantiation of the model, determines modified simulated data in response to a comparison of the training results with expected training results corresponding to the simulated data, and transmits the modified simulated data.

17. The system of request 13, wherein the inference information includes predictions of operations from a plurality of operations.

18. The system of claim 17, wherein the plurality of operations includes any one or more of the following: (a) workload detection operation, (b) thermal arbitration operation, (c) power optimization operation, or (d) device bandwidth arbitration operation.

19. The system of claim 13, wherein, in order to generate inference information using the instantiation of the trained model, the processing circuitry is: determining a moving average from the at least one signal, and wherein generating inference information includes generating inference information based on the moving average.

20. The system of claim 13, further comprising a plurality of storage devices, wherein the storage device is one of the plurality of storage devices, and each storage device is coupled to the host via the communication bus.

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