Semiconductor memory devices

Abstract

This invention can improve the integrated density of semiconductor memory devices. The semiconductor memory device of the embodiment includes: a first wiring layer and a plurality of second wiring layers of a first memory cell array, and a third wiring layer and a plurality of fourth wiring layers of a second memory cell array, which are arranged to overlap in this order in a first direction; a first contact that is connected to a stepped portion of one of the plurality of fourth wiring layers of the second memory cell array and extends in the first direction; a second contact that penetrates a bridging portion of the plurality of second wiring layers of the first memory cell array in the first direction; a third contact that is connected to a stepped portion of one of the plurality of second wiring layers of the first memory cell array and extends in the first direction; and first and second memory pillars that are arranged to penetrate the plurality of second and fourth wiring layers of the first and second memory cell arrays respectively in the first direction; and the first contact and the second contact are arranged at overlapping positions in the first direction and are electrically connected to each other.