Semiconductor package

Abstract

The semiconductor package includes a semiconductor chip; a first bonding layer including a first inner bonding layer and a first outer bonding layer sequentially stacked on the semiconductor chip along a vertical direction; first inner bonding pads accommodated in the first inner bonding layer on the bonding region of the substrate, and first inner align key patterns accommodated in the first inner bonding layer on the align key region of the substrate; first outer bonding pads accommodated in the first outer bonding layer on the bonding region of the substrate and first outer align key patterns accommodated in the first outer bonding layer on the bonding region of the substrate; a second bonding layer including a second outer bonding layer and a second inner bonding layer sequentially stacked on the first bonding layer along the vertical direction; and a second semiconductor chip disposed on the second bonding layer.