Overclocking simulation algorithm for heat dissipation module

Abstract

This invention relates to an overclocking simulation algorithm for heat dissipation modules, applied to the optimal prediction of overclocking / downclocking ratios and times for heat pipe and other heat dissipation modules. New-generation AIPC chips, in order to achieve higher computing performance, have built-in powerful overclocking capabilities. However, when paired with existing heat pipe cooling modules, the optimal combination of overclocking ratio and time is needed to maximize the computing performance of the built-in overclocking function. Higher overclocking ratios result in better performance, but the overclocking time must be shorter; the frequency must be reduced before reaching the chip's temperature limit to avoid exceeding the chip's temperature range. Therefore, by simulating the combination of parameters such as overclocking ratio, overclocking time, downclocking ratio, and downclocking time using mathematical equations, without exceeding the chip's temperature limits, development costs can be significantly reduced.

Description

[Technical Field]

[0001] This invention provides an overclocking simulation algorithm for a heat dissipation module. Targeting the overclocking capabilities unique to next-generation AI chips, and in conjunction with existing heat pipe cooling modules, the algorithm uses overclocking simulation to find the optimal combination of overclocking multiplier / duration and underclocking multiplier / duration to maintain the chip within its temperature limits and maximize its computing power. This overclocking simulation algorithm can predict the most effective optimized combination of overclocking / underclocking / duration before developing new models, utilizing the computer's firmware to control the chip's operating speed and maximize its computing performance. [Previous Technology]

[0002] Older generation computer chips do not have built-in overclocking capabilities. The chips will only operate at 100% of their heat output power. The heat dissipation capacity of the heat pipe cooling module is designed based on the 100% heat output of the chip. During operation, the temperature limit will never be exceeded, as shown in Figure 2. The computing power is already limited to 100%, and it is impossible to improve the computing performance. There is no need to use overclocking simulation algorithms. If the computing power is increased to 150%, the chip will stop operating due to overheating for a short period of time. Downclocking is the only way to continue operating. Therefore, the algorithm of this invention must be used. [Summary of the Invention]

[0003] The main purpose of this invention is that before the prototype sample of the new generation AIPC computer is made for testing, the computer's specifications and space limitations, as well as the heat dissipation performance of the heat pipe cooling module, can be determined by using an overclocking simulation algorithm to find the optimal combination of overclocking multiplier and time, so as to achieve a computing performance that is 20-30% higher than that of traditional chips with fixed operating frequencies.

[0004] Another objective of this invention is to shorten development time and reduce the cost of manufacturing prototypes. The traditional approach is to first manufacture a prototype, and then perform a second / third round of corrections and prototyping through actual testing. If an overclocking simulation algorithm is used, the parameters of the overclocking simulation algorithm can be changed without manufacturing a prototype until the optimal overclocking combination is achieved, and then a prototype can be manufactured.

[0005] Accordingly, the present invention is a specific overclocking simulation algorithm that reduces development costs and shortens research and development time. Through this algorithm, the computer industry can more quickly improve the computing performance of AIPC chips and enhance the competitiveness of products.

Implementation Method

[0006] Typically, customers will customize an overclocking power distribution diagram, as shown in the lower left of Figure 1. The customer wants to overclock from 40W to 60W by 150%, and the corresponding temperature curve will be a sawtooth temperature curve as shown in the lower right figure. However, the biggest problem is that the customer cannot determine which time t will not exceed the chip temperature limit if the overclocking time is 15 / 18 / 20 seconds. In this case, the overclocking simulation algorithm of the present invention can play a significant role.

[0007] To achieve the above objectives and effects, this invention first solves the basic analytical solution of the energy equation, such as equation (7), and then uses the actual operating conditions as boundary conditions to solve the equation that conforms to the physical phenomenon. For example, after the computer is turned on, it will enter the standby state, and the power consumed is represented by the proportion value denoted by rt0 (rt=1 represents 100%, rt will be >1 when overclocking, and rt will be <1 when downclocking). Then, based on equation (7), equation (0) is derived; the rt0 of the standby state should be <1 or 0.3-0.6, etc., as a reasonable state. The temperature rise equation of the first cycle of overclocking is derived with the temperature distribution of the standby state as the initial condition, and the result is equation (1). The power value rt1 needs to be >1 or 100%, and can be 1.5 / 2 / 2.5, etc., depending on the heat dissipation capacity of the heat dissipation module. The temperature drop equation of the first cycle of downclocking is derived with the temperature rise curve of the previous overclocking as the initial condition, equation (2). The power value rt2 must be <1, and can be set to 0.5 / 0.7 / 0.8 depending on the cooling rate requirement. The temperature rise equation for the second cycle of overclocking is derived from the cooling equation of the first cycle as the initial condition (3). The power value rt3 must be >1, and can be 1.5 / 2 / 2.5 depending on the heat dissipation capacity of the heat dissipation module. The temperature drop equation for the second cycle of downclocking is derived from the overclocking temperature rise curve of the first cycle as the initial condition (4). The power value rt4 must be <1, and can be set to 0.5 / 0.7 / 0.8 depending on the cooling rate requirement. The temperature rise equation for the third cycle of overclocking is derived from the cooling equation of the second cycle as the initial condition (5). The power value rt5 must be >1, and can be 1.5 / 2 / 2.5 depending on the heat dissipation capacity of the heat dissipation module. The temperature drop equation for the third cycle of frequency reduction is derived from the overclocking temperature rise curve of the previous second cycle as the initial condition (equation 6). The power value rt6 must be <1, and can be set to 0.5 / 0.7 / 0.8, etc., depending on the cooling rate requirement. Equations (0)-(6) are as follows.

[0008] Since each equation uses the previous equation as its initial condition, the end point of each overclocking equation is the starting point of the next downclocking equation, and vice versa. Figures 3(A)-3(F) show that the connection points of each equation are quite precise. Therefore, in the eight equations, regardless of the input overclocking multiplier / overclocking time / downclocking multiplier / downclocking time, it can be presented as a continuous equation, achieving the function of overclocking simulation. Figure 4 shows that different overclocking times can still be connected quite precisely. Using this algorithm, various customized overclocking simulators can be developed using Python or C++.

[0009] (0)

[0010] (1)

[0011] (2)

[0012] (3)

[0013] (4)

[0014] (5)

[0015] (6)

[0016] (7) Where, M means the ratio of convection intensity to thermal conductivity of the conductor, τ is the time variable / τ1-τ5 is the time constant, X is the position, X=0 is the position where the heat pipe contacts the chip, X=1 is the end position of the heat sink fin. Usually, the temperature change of the chip is the judgment benchmark, so in the above equations (0)-(6), the temperature change of X=0 is the focus of observation.

[0017] In the above equations (0)-(6), rt1 / rt3 / rt5 represent overclocking, so the multiplier must be >1 or 100%. When rt(n)=1, it is equivalent to the normal operating power of the chip. Usually, when rt1 / 3 / 5 can be 1.5, 2, or 2.5, although the computing power will continue to increase, the overclocking time will continue to decrease to prevent exceeding the chip's temperature limit. rt2 / rt4 / rt6 represent downclocking, so the multiplier must be <1. Usually, when rt2 / 4 / 6 can be 0.8, 0.7, or 0.6, the chip cooling rate will continue to increase, but the computing power will continue to decrease. Therefore, how to combine the overclocking / downclocking multipliers and the duration becomes the maximum utility of the overclocking simulation algorithm.

[0018] As can be seen from the above, the present invention is a specific overclocking simulation algorithm that reduces development costs and shortens research and development time. Through this algorithm, the computer industry can more quickly improve the computing performance of AIPC and enhance the competitiveness of products. [Simplified Explanation of the Diagram]

[0019] [Figure 1] is a schematic diagram of an embodiment of the present invention. [Figure 2] is a schematic diagram comparing the temperature curve of the AIPC of the present invention with that of a conventional PC. [Figure 3] shows that the algorithm of the present invention can seamlessly connect 7 equations, and the user can define the boundary conditions. [Figure 4] is a comparison diagram of the algorithm of the present invention, where the user can define different overclocking times.

Claims

1. An overclocking simulation algorithm for a heat dissipation module is a specific overclocking simulation algorithm that reduces development costs and shortens R&D time. Through this algorithm, the computer industry can more quickly improve the computing performance of AIPC and enhance the competitiveness of products. This overclocking simulation algorithm includes 7 equations, such as equations (0)-(6). The result of the previous term will become the initial condition for the derivation of the subsequent term, so that the 7 independent equations can be seamlessly connected into a single continuous equation, which becomes the core calculation program of the overclocking simulation algorithm. Users can use PYTHON or C++ programming language to customize development tools suitable for themselves to improve the computing performance of AIPC. The 7 independent equations are as follows: (0)(1)(2)(3)(4)(5)(6) Where, M means the ratio of convection intensity to thermal conductivity of the conductor, h is the thermal convection coefficient / k is the thermal conductivity coefficient / D is the characteristic diameter / L is the heat pipe length / rt0-6 is the overclocking and downclocking ratio, τ The time variable is / τ1-τ5 is the time constant, X is the position, X=0 is the position where the heat pipe contacts the chip, X=1 is the position of the end of the heat sink fin. Usually, the temperature change of the chip is the judgment benchmark, so in the above equations (0)-(6), the temperature change of X=0 is the focus of observation.

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