Circuit and method for data processing

Abstract

A circuit is provided. The circuit comprises a shared scale pre-process circuit, a first partial multiply-and-accumulate (MAC) circuit, a second partial MAC circuit and an accumulate circuit. The shared scale pre-process circuit comprises first adders configured to performs first additions between a plurality of shared scales of inputs and weights, in which the shared scale pre-process circuit generates a flag indicating a variance corresponding to results of the first additions. The first partial MAC circuit performs first mantissa alignments according to the flag for generating a first partial MAC result. The second partial MAC circuit performs second mantissa alignments according to the flag for generating a second partial MAC result. The accumulate circuit accumulates the first and second partial MAC results to generate a MAC result.

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